JP2000261033A - GaN-BASED SEMICONDUCTOR DEVICE - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent reaction of a Ti layer with a Si substrate in advance and to improve crystallinity of a GaN-based semiconductor layer, by interposing a heat-resistant layer between the Si substrate and the Ti layer and keeping state of separation for the Si substrate from the Ti layer at a forming temperature of the GaN-based semiconductor layer. SOLUTION: An Al layer 12 formed on a Si(111) face is grown epitaxially by a general-purpose evaporation method. A TiN layer 13n and Ti layer 4 are formed by a general-purpose reactive sputtering method. Thereafter, a Ti/TiN/Al/Si sample is moved from a sputtering unit into the chamber of a MOCVD unit. The chamber is evacuated, and then the sample is heated to 650 deg.C and held for five minutes. Thereafter, a buffer layer 15 made of AlGaN is grown at a growth temperature of 350 deg.C and is heated up to 1,000 deg.C to form an n-clad layer 15 and the like in accordance with a conventional method. Crystallinity of the GaN-based semiconductor layer formed in this manner is satisfactory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a GaN-based semiconductor device. More specifically, the present invention relates to improvement of an underlayer of a GaN-based semiconductor layer.

[0002]

2. Description of the Related Art It is known that a GaN-based semiconductor can be used, for example, as a blue light emitting device. In such a light emitting device, sapphire is generally used as a substrate.

[0003]

One of the problems to be solved in this sapphire substrate is as follows. That is, since the sapphire substrate is transparent, light of the light emitting element that is originally desired to be extracted from the upper surface of the element passes through the sapphire substrate on the lower surface of the element. Therefore, the light emitted by the light emitting element cannot be used effectively.

[0004] Sapphire substrates are also expensive. Further, since the sapphire substrate is an insulator, it is necessary to form an electrode on the same surface side, a part of the semiconductor layer must be etched, and the bonding step is accordingly performed in two steps.
Double. In addition, since both n and p electrodes are formed on the same surface side, there is a limitation in miniaturizing the element size, and there is also a problem of charge-up.

[0005] Further, use of a Si (silicon) substrate instead of a sapphire substrate is conceivable. However, according to the study of the present inventors, it is very difficult to grow a GaN-based semiconductor layer on a Si substrate. there were. As one of the causes,
There is a difference in the coefficient of thermal expansion between Si and GaN-based semiconductors. While the linear expansion coefficient of Si is 4.7 X 10-6 / K,
The linear expansion coefficient of aN is 5.59 X 10-6 / K,
The former is smaller than the latter. Therefore, when heating is performed when growing a GaN-based semiconductor layer, the Si substrate is elongated and Ga
The element is deformed such that the N-type semiconductor layer side is compressed. At this time, tensile stress occurs in the GaN-based semiconductor layer,
As a result, cracks may occur. In addition, even if cracks do not occur, the lattice is distorted. Therefore, G
The aN-based semiconductor element cannot exhibit its original function.

The present invention has been made in view of the above problems, and has as its object to provide a GaN-based semiconductor device having a novel configuration. Another object of the present invention is to provide a laminate having a novel structure, which is an intermediate of a GaN-based semiconductor device.

[0007]

The present inventors have proposed G
The present inventors have conducted intensive studies to find a new substrate suitable for growing an aN-based semiconductor layer. As a result, 9-29
In Japanese Patent No. 3465 (Applicant Reference Number 970152 / Attorney Reference Number P0060), the following items were conceived and disclosed. That is, in order to heteroepitaxially grow a GaN-based semiconductor on a substrate, it has been considered that the substrate must satisfy at least two of the following requirements. Good adhesion between the GaN-based semiconductor and the substrate The thermal expansion coefficient of the GaN-based semiconductor is close to that of the substrate The elastic modulus of the substrate is low The crystal structure of the substrate is the same as that of the GaN-based semiconductor | Lattice constant of substrate-Lattice constant of GaN-based semiconductor |
/ Lattice constant of GaN-based semiconductor ≦ 0.05 (that is, the difference between the lattice constant of the substrate and the lattice constant of the GaN-based semiconductor layer is ± 5% or less). At least three of the
More preferably, at least four, and most preferably, all five of the above requirements are satisfied.

As a material satisfying such a condition, some of the metal materials are noted in the above-mentioned Japanese Patent Application No. 9-293465. Ti is disclosed as one of them. According to the earlier application, the substrate only needs to satisfy the above requirements at least on its surface, that is, the surface in contact with the GaN-based semiconductor layer. Therefore, the base portion of the substrate can be formed of any material, and the surface portion of the substrate can be formed of a material satisfying the above requirements. As in the case of the sapphire substrate, A is applied between the semiconductor layer and the substrate.
AlaInbGa1-a-bN such as 1N or GaN
(Including a = 0, b = 0 and a = b = 0) can be interposed.

On the other hand, according to Japanese Patent Application No. 9-293463 (Applicant's reference number 970136 / Attorney's reference number P0057), a buffer layer for stress buffering is provided between the Si substrate and the GaN-based semiconductor layer. A semiconductor device having an interposed structure is disclosed. As a material constituting the buffer layer for stress buffering, Japanese Patent Application No. 9-293465 has focused on several metal materials, and disclosed Ti as one of them. That is, a semiconductor element having a configuration in which a Ti layer is formed on a Si substrate and a GaN-based semiconductor layer is formed thereon is disclosed.

When a Si substrate is used, it is preferable that such a Ti layer be used as an underlayer of a GaN-based semiconductor layer as disclosed in Japanese Patent Application No. 10-287485 (Applicant's reference number:
98112, agent reference number: P0105). The present inventor has proposed that T
Further studies have been made on a technique of laminating an i-layer and using this as a base layer to grow a GaN-based semiconductor layer thereon. As a result, they have found that when the substrate made of Ti / Si is exposed to an environment of 700 ° C. or more, the morphology of the surface of the Ti layer and its crystallinity are reduced. This is considered to be because Ti and Si react at such a temperature. Normally, a GaN-based semiconductor layer has a temperature of 1000 ° C.
Since the growth is performed at the temperature before and after, there is a possibility that the reaction between the Ti and Si adversely affects the crystallinity of the GaN-based semiconductor layer.

The present invention solves such a problem found by the present inventor, and has the following configuration. That is, a Si substrate, a Ti layer formed on the substrate, a GaN-based semiconductor layer formed on the Ti layer, and both interposed between the substrate and the Ti layer. A GaN-based semiconductor device, comprising: a heat-resistant layer to be separated; and a heat-resistant layer that maintains a separation state between the substrate and the Ti layer at a molding temperature of the GaN-based semiconductor layer.

According to the semiconductor device of the present invention thus configured, since the heat-resistant layer is interposed between the Ti layer and the Si substrate, the reaction between the Ti layer and the Si substrate is prevented beforehand and surely. You. As a result, the crystallinity of the GaN-based semiconductor layer is improved. An element including a GaN-based semiconductor layer having favorable crystallinity performs a suitable operation.

(Si Substrate) In the above, it is preferable that the (111) plane is used for the Si substrate, and a heat-resistant layer or the like is grown thereon in order.

(Heat-Resistant Layer) The heat-resistant layer is not particularly limited as long as it maintains the separated state of the Si substrate and the Ti layer under the forming temperature of the GaN-based semiconductor layer. For example, Ti, A
l, silicides such as Co and Ni, refractory metals such as Ta and Mo, and metal nitrides such as TiN, ZrN, HfN and tantalum nitride can be used. In the above, silicide is formed by forming a film of each metal on a Si substrate and performing heat treatment. Refractory metals and metal nitrides are plasma C
VD, thermal CVD, optical CVD, MOCVD and other CVD (C
chemical Vapor Deposition
n), P for sputtering, reactive sputtering, laser ablation, ion plating, vapor deposition, ECR, etc.
VD (Physical Vapor Deposi)
)). The thickness of the heat-resistant layer is
There is no particular limitation as long as the materials of the substrate and the Ti layer can be prevented from reacting. For example, when TiN is used for the heat-resistant layer, its thickness is set to 50 to 10000 °.

This heat-resistant layer is preferably made of a conductive material. Since the Si substrate and the Ti layer also have conductivity, electrodes can be formed on both surfaces of the semiconductor element, and the problem of charge-up can be easily solved by grounding the substrate.

When TiN is used for the heat-resistant layer, an Al layer or an Ag layer is preferably interposed between the Si substrate and the TiN. The thickness of these layers is not particularly limited, but is set to 50 to 250 °. The Al and Ag layers are formed, for example, by vapor deposition or sputtering.

(Ti layer) The Ti layer is also described by CVD or PVD.
And the like. According to the study of the present inventors, when the thickness of the Ti layer exceeds approximately 250 °, peeling of the Ti layer may occur. Therefore, the thickness of the Ti layer is preferably set to 250 ° or less. However, T
When the i-layer is made thin, the buffering function expected from the Ti layer, that is, the buffering function for internal stress due to the difference in thermal expansion coefficient between the Si substrate and the GaN-based semiconductor may not be sufficiently exhibited. is there. Therefore, in the present invention, the heat-resistant layer and the Ti
Layers (thickness of 250 ° or less) are repeatedly laminated so that each Ti layer bears the above-mentioned buffering action. Thereby, while reliably preventing peeling of the Ti layer, the buffering action of the Ti layer can be ensured, and cracks and strains can be prevented from entering the GaN-based semiconductor layer. The number of repetitions of the heat-resistant layer and the Ti layer is not particularly limited, but is, for example, 2 to 10.

After forming the Ti layer in this manner, the Ti layer
It is preferable to heat-treat the layer / heat-resistant layer / Si substrate. The heat treatment temperature is 600 to 1200 ° C, preferably 800 to 1
200 ° C. The atmosphere for the heat treatment is under vacuum or under hydrogen flow.

It is preferable to interpose a buffer layer between the Ti layer and the GaN-based semiconductor layer. Preferably _{Al a Ga 1-a N (} a = 0.85~0.95) the buffer layer, more _{preferably, Al a Ga 1-a N} (a nearly 0.9) is.

(GaN-based semiconductor layer) Here, the GaN-based semiconductor is a group III nitride semiconductor.
l _X Ga _Y In _1-XY N (0 ≦ X ≦ 1, 0 ≦ Y ≦
1, 0 ≦ X + Y ≦ 1). Further, it may contain an arbitrary dopant. The method of forming the GaN-based semiconductor layer is not particularly limited, but is formed by, for example, a well-known metalorganic compound vapor deposition method (hereinafter, referred to as “MOCVD method”). Also, it can be formed by a well-known molecular beam crystal growth method (MBE method).

As is well known, the light emitting element and the light receiving element have a structure in which the light emitting layer is sandwiched between GaN-based semiconductor layers (cladding layers) of different conductivity types, and the light emitting layer has a super lattice structure, a double hetero structure, or the like. Is adopted. An electronic device represented by an FET structure can also be formed of a GaN-based semiconductor. Thus, the GaN formed on the Ti layer
In the system semiconductor layer, a plurality of layers interact with each other to achieve a desired function.

(Test Example) Hereinafter, test examples will be described. Test Example 1 Layer thickness TiN 3000 Al 100 Si substrate (111) 300 μm Al layer on (111) plane of Si substrate (film thickness: about 100 °)
Is deposited. X-ray diffraction (φ (PHI) scan) after titanium nitride (thickness: about 3000 °) was formed on this Al layer by reactive sputtering and heated to 950 ° C. for 5 minutes in a vacuum. Is shown in FIG. A 4-axis single crystal diffractometer (product name: X-pert) manufactured by Philips was used as an X-ray diffractometer (the same applies to the following test examples).
Journal of Electroni for φ (PHI) scan
c Materials, Vol. 25, No. 11, pp. 1740-1747, 1996. In the φ (PHI) scan, a peak corresponding to the crystal plane is obtained when the sample is rotated by 360 degrees. It is considered that the larger the value on the vertical axis in FIG. 1, the better the crystal is obtained. If the crystallinity of TiN is good, the crystallinity of the Ti layer grown thereon, and hence Ga
It is considered that the crystallinity of the N-based semiconductor layer is also improved. From the results shown in FIG. 1, it can be seen that the crystallinity of the TiN crystal manufactured as described above is preferable.

Test Example 2 Layer thickness TiN 3000ＮAg 100Å Si substrate (111) 300 μm FIG. 2 shows φ (PHI) when Test Example 1 was replaced with an Ag layer (film thickness: about 100Å). This is the result of the scan. Also in this case, a TiN layer having good crystallinity was obtained.

Test Example 3 Layer Thickness Ti 15000ÅTiN 5000ÅAl 100ÅSi substrate (111) 300 μm FIG. 3 shows a case where Ti is grown on TiN of Test Example 1 (thickness: about 5000５), and a crystal of this Ti is formed. It is the result of φ (PHI) scan for evaluating the performance. A good Ti layer was obtained.

Test Example 4 Layer Thickness TiN 3000 Ti 1000ÅTiN 100ÅAl 100ÅSi substrate (111) 300 μm In this test example, the thickness of the first TiN layer in Test Example 1 was set to 100Å, and then the thickness of the TiÅ layer and the thickness of 1000Å were increased to 300Å.
A second TiN layer of 0 ° was continuously formed by a reactive sputtering method. FIG. 4 shows the result of a φ (PHI) scan for evaluating the crystallinity of the TiN layer. Also in this case, a TiN layer having good crystallinity was obtained.

Test Example 5 Layer thickness TiN (100 °) / Ti (250 °) repetition (number of repetitions: 10) TiN 3000 {Al 100} Si substrate (111) 300 μm In this test example, the first TiN layer in test example 1 was used. The thickness is 3000Å, then 250 そ の 後 Ti layer and 100１００
Ｔｉ TiN layers were alternately formed 10 times. Each Ti
The N layer and the Ti layer were continuously formed by a reactive sputtering method. FIG. 5 shows the evaluation of the crystallinity of the TiN layer by φ (P
HI) The result of the scan. Also in this case, a TiN layer having good crystallinity was obtained.

Test Example 6 Layer thickness TiN (600 °) / Ti (50 °) repetition (number of repetitions: 4) TiN 600 {Al 100} Si substrate (111) 300 μm In this test example, the first TiN layer in Test Example 1 was used. The thickness was set to 600 °, and thereafter, a 50 ° Ti layer and a 600 ° TiN layer were alternately formed four times. Each TiN layer and Ti layer were continuously formed by a reactive sputtering method. FIG. 6 shows φ (PHI) in which the crystallinity of the TiN layer was evaluated.
This is the result of the scan. Also in this case, good crystalline Ti
An N layer was obtained.

Test Example 7 Layer thickness Ti 15000 {Al silicide 100} Si substrate (111) 300 μm Al layer on (111) plane of Si substrate (film thickness: about 100 °)
Is deposited at room temperature. And this is 950 under vacuum environment
At 5 ° C. for 5 minutes, Al and Si are positively reacted to form a reaction layer. Thereafter, a Ti layer (film thickness: 15000 °) was formed by sputtering. FIG. 7 shows the Ti layer (15
9 shows the results of a φ (PHI) scan for evaluating the crystallinity of 000 °). In this case, a Ti layer having good crystallinity was obtained.

Test Example 8 Layer Thickness Ti 15000 {Ti silicide 50} Si substrate (111) 300 μm A Ti layer (thickness: about 50 °) is deposited on the (111) plane of a Si substrate at room temperature. Then, put this in a vacuum environment at 950 ° C,
Heat for 5 minutes to make Ti and Si react positively,
A silicide layer is formed. After that, the Ti
A layer (film thickness: 15000 °) was formed. FIG. 8 shows the results of a φ (PHI) scan for evaluating the crystallinity of the Ti layer (15000 °). In this case, six peaks can be clearly confirmed. Therefore, it can be seen that the crystallinity of the Ti layer is good.

Test Example 9 Layer thickness Ti 15000 {Co silicide 100} Si substrate (111) 300 μm Co layer on (111) plane of Si substrate (film thickness: about 100 °)
Is deposited at room temperature. And this is vacuum environment, 600
C. for 5 minutes to positively react Co and Si to form a Co silicide layer. Thereafter, a Ti layer (film thickness: 15000 °) was formed by sputtering. FIG. 9 shows the T
φ (PHI) for evaluating the crystallinity of the i-layer (15000 °)
This is the result of the scan. In this case, since six peaks can be determined, single crystal growth of the Ti layer can be confirmed.

Test Example 10 Layer thickness Ti 15000 {Ni silicide 100} Si substrate (111) 300 μm Ni layer (film thickness: about 100) on the (111) plane of the Si substrate
Is deposited at room temperature. And this is 800 under vacuum environment
At 5 ° C. for 5 minutes, Ni and Si are positively reacted to form a Ni silicide layer. Thereafter, a Ti layer (film thickness: 15000 °) was formed by sputtering. FIG. 10 shows φ (PH) for evaluating the crystallinity of the Ti layer (15000 °).
I) The result of the scan. In this case, since six peaks can be determined, single crystal growth of the Ti layer can be confirmed.

Test Example 11 Layer thickness TiN 10000 {Al silicide 100} Si substrate (111) 300 μm Al layer on (111) plane of Si substrate (film thickness: about 100 °)
Is deposited at room temperature. And this is 950 under vacuum environment
At 5 ° C. for 5 minutes, Al and Si are positively reacted to form an Al silicide layer. Thereafter, a TiN layer (film thickness: 10000 °) was formed by sputtering. FIG. 11 shows φ (P) obtained by evaluating the crystallinity of the TiN layer (10000 °).
HI) The result of the scan. In this case, a TiN layer having good crystallinity was obtained.

Test Example 12 Layer Thickness TiN 10,000 {Ti silicide 50} Si substrate (111) 300 μm A Ti layer (thickness: about 50 °) is deposited on the (111) plane of a Si substrate at room temperature. Then, this is placed in a vacuum environment at 950 ° C.
Heat for 5 minutes to make Ti and Si react positively,
A silicide layer is formed. After that, the Ti
An N layer (film thickness: 10000 °) was formed. Looking at the φ (PHI) scan for evaluating the crystallinity of the TiN layer (10000 °), six peaks can be clearly confirmed. Therefore, it can be seen that the TiN layer is growing as a single crystal.

Test Example 13 Layer Thickness TiN 3000 a-plane of sapphire substrate 300 μm TiN (3000Å) is formed on the a-plane of a sapphire substrate by a reactive sputtering method. X-ray diffraction (φ (PH
FIG. 12 shows the results of (I) scan). From the results shown in FIG. 12, it can be seen that preferable crystalline TiN is also formed on the sapphire substrate. Similarly, preferable crystalline TiN is formed on the c-plane sapphire substrate. In addition, 80
By performing a high-temperature heat treatment at 0 ° C. or higher, the crystallinity of TiN is significantly improved. Ti can be further formed on the TiN, and a GaN-based semiconductor layer can be formed thereon. The laminate of Ti / TiN can be repeated.
In this case, the number of repetitions and the thickness of each layer are not particularly limited.

Test Example 14 Layer thickness TiN 3000Ｎ GaN 400 μm AlN buffer layer 160Å Sapphire a-plane 300 μm TiN (3000Å) is formed on GaN by reactive sputtering. FIG. 13 shows the result of X-ray diffraction (φ (PHI) scan). From the results of FIG.
It can be seen that preferred crystalline TiN is also formed thereon.

Test Example 15 Layer Thickness Ti 15000ÅTiN 3000ÅGaN 400 μm AlN buffer layer 160 フ ァ イ Sapphire a-plane 300 μm Ti is further grown on TiN of the sample of Test Example 15 (before heat treatment) by sputtering. X-ray diffraction (φ
(PHI) scan) is shown in FIG. From the results in FIG. 14, it is understood that the Ti layer formed on TiN / GaN has a preferable crystallinity.

Next, an embodiment of the present invention will be described.

(First Embodiment) This embodiment is a light emitting diode 10, and the structure is shown in FIG.

The specifications of each layer are as follows. Layer: Composition: Dopant (thickness) P-cladding layer 18: p-GaN: Mg (0.3 μm) Emitting layer 17: Superlattice structure Quantum well layer: In _0.15 Ga _0.85 N (35 °) Barrier layer: GaN (35 °) Number of repetitions of quantum well layer and barrier layer: 1 to 10 n cladding layer 16: n-GaN: Si (4 μm) buffer layer 15: Al _0.9 Ga _0.1 N (150 °) Ti layer 14: Ti Crystal (250 mm) TiN layer 13: TiN crystal (3000 mm) Al layer 12: Al (100 mm) Substrate 11: Si (111) (300 μm)

The n-cladding layer 16 can have a two-layer structure including a low electron concentration n− layer on the light emitting layer 17 side and a high electron concentration n + layer on the buffer layer 15 side. The light emitting layer 17 is not limited to the superlattice structure, but may be a single hetero type, a double hetero type, a homo junction type, or the like. A wide band gap A doped with an acceptor such as magnesium between the light emitting layer 17 and the p cladding layer 18
_{l X In Y Ga 1-X} -Y N ( including _{X = 0, Y = 0,} X = Y = 0)
Layers can be interposed. This is to prevent electrons injected into the light emitting layer 17 from diffusing into the p clad layer 18. The p-cladding layer 18 may have a two-layer structure including a low hole concentration p− layer on the light emitting layer 17 side and a high hole concentration p + layer on the electrode side.

In the light emitting diode 10 of the embodiment, Ti
The illuminant structure above the layer 14 has a well-known structure, and therefore, a well-known method can be adopted for the formation method. The details will be described below. The Al layer 12 formed on the Si (111) surface is epitaxially grown by a general-purpose deposition method. TiN
The layer 13 and the Ti layer 14 are formed by a general reactive sputtering method. Then, Ti / TiN / Al / Si
The sample is transferred from the sputtering apparatus into the chamber of the MOCVD apparatus. The chamber is evacuated (2 × 10
⁻³ Pa), and in this state, the sample is heated to 650 ° C. and maintained for 5 minutes. This process improves the flatness of Ti.

Thereafter, at a growth temperature of 350 ° C., the AlGaN
A buffer layer 15 made of
The temperature is raised to the n-cladding layer 16 and thereafter by the usual method (MOCVD
Method). In this growth method, ammonia gas and an alkyl compound gas of a group III element, for example, trimethylgallium (TMG), trimethylaluminum (TMA) or trimethylindium (TMI) are supplied onto a substrate heated to an appropriate temperature. Thermal decomposition reaction,
Thus, a desired crystal is grown on the substrate. The crystallinity of the GaN-based semiconductor layer of the present embodiment thus formed is preferable.

The translucent electrode 19 is a thin film containing gold.
The cladding layer 18 is laminated so as to cover substantially the entire upper surface. The p-electrode 9 is also made of a material containing gold, and is formed on the translucent electrode 19 by vapor deposition. Note that the Si substrate layer 11 becomes an n-electrode. Then, a wire is bonded at the desired position.

(Second Embodiment) FIG. 16 shows a semiconductor device according to a second embodiment of the present invention. The semiconductor element of this embodiment is a light emitting diode 20. The same elements as those in FIG. 16 are denoted by the same reference numerals, and description thereof will be omitted. The specifications of each layer are as follows. Layer: Composition: Dopant (thickness) n-cladding layer 28: n-GaN: Si (0.3 μm) Light-emitting layer 17: superlattice structure Quantum well layer: In _0.15 Ga _0.85 N (35 °) Barrier layer: GaN (35 °) Number of repetitions of quantum well layer and barrier layer: 1 to 10 p cladding layer 26: p-GaN: Mg (4 μm) buffer layer 15: Al _0.9 Ga _0.1 N (150 °) Ti layer 14 b: Ti Crystal (250 °) TiN layer 13b: TiN crystal (100 °) Ti layer 14a: Ti crystal (250 °) TiN layer 13a: TiN crystal (100 °) Al layer 12: Al (100 °) Substrate 11: Si (111) (300 μm)

As described above, in this embodiment, Ti / T
A stacked body of iN is repeatedly formed. The number of repetitions of the Ti / TiN laminate is not particularly limited. The thickness of each layer is not particularly limited, but the thickness of the Ti layer is preferably 250 ° or less from the viewpoint of reliably preventing peeling. The manufacturing method of this embodiment is the same as that of the first embodiment.

In this embodiment, p
The light emitting diode 20 is formed by sequentially growing the clad layer 26, the light emitting layer 17, and the n clad layer 28. In the case of this element 20, the n-cladding layer 28 having a low resistance value is the uppermost surface, so that the translucent electrode here (see reference numeral 19 in FIG. 15)
Can be omitted. Reference numeral 30 in the figure denotes an n-electrode. The Si substrate 11 can be used as it is as a p-electrode.

The element to which the present invention is applied is not limited to the light emitting diode described above, but can be applied to an electronic device having an FET structure in addition to an optical element such as a light receiving diode and a laser diode. The present invention is also applicable to a laminate as an intermediate of these elements.

The present invention is not limited to the description of the above-described embodiments and examples, and includes various modifications that can be made by those skilled in the art without departing from the scope of the claims.

The following is disclosed below: (11) Si substrate and T substrate formed on the substrate
an i-layer, a GaN-based semiconductor layer formed on the Ti layer, and a heat-resistant layer interposed between the substrate and the Ti layer for separating the two, and forming the GaN-based semiconductor layer. A laminate comprising: a heat-resistant layer that maintains a separation state between the substrate and the Ti layer at a temperature. (12) The laminate according to (11), wherein the heat-resistant layer is a silicide, a high-melting metal, or a metal nitride. (13) The silicide is Ti silicide, Al silicide, Co silicide or Ni silicide, the refractory metal is Ta or Mo, and the metal nitride is TiN, ZrN, HfN or tantalum nitride. (12). (14) The laminate according to any one of (11) to (13), wherein the heat-resistant layer is formed on a (111) plane of the substrate. (15) The laminate according to any one of (11) to (14), wherein the Ti layer and the heat-resistant layer are repeatedly laminated. (16) The thickness of the Ti layer is 10 to 250 °,
The laminate according to (15), wherein (17) a substrate, a layer formed by repeating a Ti layer and a heat-resistant layer formed on the substrate, and a GaN-based semiconductor layer formed on the repeated layer; The layered body, wherein the layer has a melting point substantially higher than a forming temperature of the GaN-based semiconductor layer. (18) The thickness of the Ti layer is 10 to 250 °,
The laminate according to (17), wherein:

[Brief description of the drawings]

FIG. 1 shows the results of a φ (PHI) scan of Test Example 1.

FIG. 2 shows the results of a φ (PHI) scan of Test Example 2.

FIG. 3 shows the results of a φ (PHI) scan of Test Example 3.

FIG. 4 shows the results of a φ (PHI) scan of Test Example 4.

FIG. 5 shows the results of a φ (PHI) scan of Test Example 5.

FIG. 6 shows the results of a φ (PHI) scan of Test Example 6.

FIG. 7 shows the results of a φ (PHI) scan of Test Example 7.

FIG. 8 shows the results of a φ (PHI) scan of Test Example 8.

FIG. 9 shows the results of a φ (PHI) scan of Test Example 9.

FIG. 10 shows the results of a φ (PHI) scan of Test Example 10.

FIG. 11 shows the results of a φ (PHI) scan of Test Example 11.

FIG. 12 shows the results of a φ (PHI) scan of Test Example 13.

FIG. 13 shows the results of a φ (PHI) scan of Test Example 14.

FIG. 14 shows the results of a φ (PHI) scan of Test Example 15.

FIG. 15 shows a configuration of the light emitting diode of the first embodiment.

FIG. 16 illustrates a configuration of a light emitting diode according to a second embodiment. 10, 20 	 light emitting diode 11 substrate 13 heat resistant layer 14 Ti layer 15 	 buffer layer 16, 26 cladding layer 17 light emitting layer 18, 28 cladding layer 19 translucent electrode 20 	 light emitting diode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/812 (72) Inventor Toshiaki Chiyo 1 Kasugamachi, Kasuga-cho, Nishikasugai-gun, Aichi 1 No. 1 Nagahata Toyoda Gosei Co., Ltd. (72) Inventor Shizuyo Nori 1 Ogatachi Nagahata, Kasuga-cho, Nishi-Kasugai-gun, Aichi F-term (reference) 5F041 AA40 CA04 CA05 CA23 CA33 CA34 CA40 CA46 CA65 CA66 CA67 5F045 AA04 AB14 AB17 AB18 AB30 AB31 AB31 AC08 AC12 AD07 AD14 AF03 AF13 CA10 CA12 CA13 DA53 DA54 5F049 MA01 MB07 NA13 PA04 PA07 SS03 SS07 SS09 WA03 5F073 AA73 AA74 CA07 CB04 CB05 CB07 DA05 DA06 DA07 EA07 5F102 GB01 GC01 GD01 GJ03 GK08 GK09 GL04 GR01

Claims (8)

[Claims] 1. A substrate made of Si, a Ti layer formed on the substrate, a GaN-based semiconductor layer formed on the Ti layer, and interposed between the substrate and the Ti layer. A GaN-based semiconductor device, comprising: a heat-resistant layer that separates the two from each other, the heat-resistant layer maintaining a separation state between the substrate and the Ti layer at a molding temperature of the GaN-based semiconductor layer. 2. The semiconductor device according to claim 1, wherein said heat-resistant layer is made of a silicide, a refractory metal or a metal nitride. 3. The silicide is Ti silicide, Al
3. The semiconductor device according to claim 2, wherein the refractory metal is Ta or Mo, and the metal nitride is TiN, ZrN, HfN, or tantalum nitride. 4. . 4. The semiconductor device according to claim 1, wherein the heat-resistant layer is formed on a (111) plane of the substrate. 5. The semiconductor device according to claim 1, wherein said Ti layer and said heat-resistant layer are repeatedly laminated. 6. The semiconductor device according to claim 5, wherein the thickness of the Ti layer is 10 to 250 °. 7. A substrate, a layer formed by repeating a Ti layer and a heat-resistant layer formed on the substrate, a GaN-based semiconductor layer formed on the repetitive layer,
Wherein the heat-resistant layer has a melting point substantially higher than the forming temperature of the GaN-based semiconductor layer. 8. The semiconductor device according to claim 7, wherein said Ti layer has a thickness of 10 to 250 °.