JP2000260997A - Manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the boundary surface between a crystalline semiconductor film and a gate insulation film flat and clean, in a thin-film transistor provided with a crystalline semiconductor film made mainly of silicon as an active layer. SOLUTION: A crystalline semiconductor film (polycrystalline silicon film) 2 having a uneven surface is formed on a glass substrate 1 by the annealing method and, is treated by a plasma using a mixed gas containing an SiF4 gas and an H2 gas, and while the lamination of silicon films and etching are performed at the same time, the surface of the crystalline semiconductor film 2 is flattened to make a flattened (polycrystalline silicon) film 3. A gate insulating film 5 is formed thereon. Therefore, a flat and clean boundary surface can be formed and a thin-film transistor that has less variation in characteristics or less scattering of carriers on the boundary surface is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor using a crystalline semiconductor film mainly composed of silicon for a channel layer.

[0002]

2. Description of the Related Art In recent years, in an active matrix type liquid crystal display device, a demand for a large screen and a high definition has been increased, and a characteristic improvement of a thin film transistor as a switching element has been demanded.

Conventionally, an amorphous silicon film has been used as an active layer of a thin film transistor. However, an amorphous silicon film having a low mobility has a limitation in increasing the screen size and definition of a liquid crystal display device. Attempts have been made to use a polycrystalline silicon film having higher mobility than the film as an active layer.

Since the formation of a polycrystalline silicon film on a glass substrate requires a process temperature of 600 ° C. or lower, an amorphous silicon film formed by low-pressure CVD or plasma CVD is converted into polysilicon by annealing. And an indirect method of reforming.
As a method of the annealing treatment, a temperature of about 600 ° C.
There are a solid layer growth method in which heat treatment is performed for 4 hours or more, and a laser annealing method in which melt crystallization is performed by irradiating a laser beam. The laser annealing method has attracted attention from the viewpoint of process temperature and throughput.

A method of manufacturing a thin film transistor using a polycrystalline silicon film as an active layer will be described with reference to FIG. As a conventional method of manufacturing a thin film transistor, first, an amorphous silicon film is formed on a glass substrate 1 on which a base film (not shown) is formed by plasma CVD using monosilane or the like as a raw material.
After the hydrogen in the amorphous silicon film is desorbed by a heat treatment at about 450 ° C., the polycrystal is formed by a laser annealing method using an excimer laser or the like as shown in FIG. A silicon film 2 is formed.

Next, as shown in FIG. 5B, after the polycrystalline silicon film 2 is patterned into an island shape, a gate insulating film 5 is formed by a plasma CVD method or a normal pressure CVD method.

Subsequently, aluminum (Al), tantalum (T
After the gate electrode 6 is formed using a metal such as a), phosphorus (P),
An impurity such as boron (B) is implanted to form a polycrystalline silicon film 2.
Source / drain regions are formed therein.

Finally, an interlayer insulating film 7 is formed by a plasma CVD method or a normal pressure CVD method, and after opening contact holes to source / drain regions, a source electrode 8 and a drain electrode 9 are formed by a metal such as aluminum. Thus, a thin film transistor as shown in FIG.

[0009]

In a thin film transistor in which a polycrystalline silicon film formed by a laser annealing method is used as an active layer, a polycrystalline silicon film having excellent crystallinity can be obtained by reducing the thickness of an amorphous silicon film as a precursor to 100 nm or less. A silicon film can be obtained. However, in such a case, it has been clarified that irregularities of several tens nm are formed on the film surface as shown in FIG.

In a top gate type thin film transistor, since this unevenness is formed at the interface between the semiconductor and the gate insulating film, that is, at the channel region, it causes variations in transistor characteristics and limits the performance. Therefore, it is necessary to flatten the surface of the semiconductor thin film. However, when the thickness of the semiconductor is reduced by the planarization process, the variation in crystallinity and thickness greatly affects the variation in the thin film transistor. Therefore, it is necessary to minimize the decrease in film thickness due to the planarization.

As a method of flattening the surface of the thin film, an etch-back method of forming a coating film such as a resist on the surface of the thin film and performing flattening by etching the film or a mechanical chemical polishing method ( Although there is a CMP method or the like, the planarization is performed while shaving the thin film, so that the thickness of the semiconductor is significantly reduced. Therefore, it is difficult to flatten a thin film having a thickness of 100 nm or less with good controllability.

A plasma treatment for simultaneously performing film formation and etching is effective for flattening a thin film. However, when a gas containing carbon, nitrogen, or the like is used as a raw material gas at this time, these impurities are added to the semiconductor surface. This results in the formation of a film that includes a thin film transistor, which has another effect on the characteristics of the thin film transistor, such as a change in threshold voltage due to impurity levels. Therefore, a step of removing the film containing these impurities is further required.

An object of the present invention is to solve the above problems and to provide a method of manufacturing a thin film transistor in which the interface between a thin crystalline silicon film formed by a laser annealing method and a gate insulating film is clean and flat.

[0014]

In order to solve the above-mentioned object, a method of manufacturing a thin film transistor according to the present invention comprises a step of forming a crystalline semiconductor film mainly composed of silicon, and a step of forming a surface of the crystalline semiconductor film. In a method for manufacturing a thin film transistor, comprising: a flattening step for flattening; and a step of forming an insulating film on a surface of the crystalline semiconductor film, the flattening step includes a process in which halogenated silane and a gas for supplying hydrogen atoms are mixed at least. Is a plasma treatment process using the gas, specifically, a mixed gas of SiF ₄ gas and H ₂ gas, and the polycrystalline silicon film deposition with SiH _x radicals and the etching with fluorine radicals have irregularities on the surface of the polycrystalline silicon film. Is a plasma treatment that occurs simultaneously.

In the flattening step of the present invention, a silicon film is sequentially deposited from a concave portion on the surface of the polycrystalline silicon film by plasma treatment, and fluorine radicals are preferentially supplied to convex portions having a small radius of curvature. Etching proceeds rapidly. As a result, the film formation is made redundant in the concave portions and the etching is made redundant in the convex portions, so that the surface of the polycrystalline silicon film is finally flattened.

In the present invention, the film deposited on the surface of the polycrystalline silicon film in the planarization step is a polycrystalline silicon film of the same quality, and the next step of forming an insulating film without removing the film is performed. By performing this in the same vacuum as the planarization step, a cleaner interface between the semiconductor and the gate insulating film can be formed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, polycrystalline silicon having irregularities
The process of flattening the film surface will be described. Halogenated silane
Gas that is at least mixed with
, More specifically, SiF_FourGas and H_TwoGas mixing
In a gas-based plasma, complex gas-phase reactions can occur.
Fruit, F, SiH_x, SiH_xF_y, SiF_yLike
Various particles are produced.

When the fluorine radicals reach the surface of the polycrystalline silicon film, the silicon on the film surface reacts with the fluorine radicals to form volatile SiF _{4 and} the etching of the polycrystalline silicon film proceeds. At this time, since the fluorine radicals are intensively supplied to a region having a small radius of curvature, the etching proceeds fastest on the convex portion on the surface of the polycrystalline silicon film. When the SiH _x radicals reach the surface of the polycrystalline silicon film, they diffuse on the surface and combine with the silicon in the film, and the deposition of the silicon film proceeds. Since this film deposition occurs sequentially from the concave portions, the film formation is performed in the concave portions and the etching is redundant in the convex portions, and the surface of the polycrystalline silicon film is finally flattened.

The amount of change in the thickness of the polycrystalline silicon film is determined by the supply amount of fluorine radicals and SiH _x radicals to the film surface. If the supply amount of fluorine radicals is large, the etching amount increases and the film thickness decreases. Conversely, SiH _x
If the supply amount of radicals is large, the film deposition amount increases, and the film thickness increases. FIG. 4 shows the dependency of the film thickness change amount on the change of the SiF ₄ partial pressure ratio with respect to the total pressure. Thus, it can be seen that as the SiF ₄ partial pressure increases, the amount of generated fluorine radicals increases and the film thickness decreases. Also,
The surface unevenness at this time was about 20 nm before and after the treatment, but the surface unevenness was flattened to ₂ to 5 nm except when the SiF ₄ partial pressure was 100%, that is, when H ₂ was not mixed. I was

When a polycrystalline silicon film is formed by using a laser annealing method, the thickness of the amorphous silicon film serving as a precursor is set to 100 nm or less, preferably 50 nm or less.
By setting the thickness to about nm, a polycrystalline silicon film having excellent crystallinity is formed. In the case of manufacturing a thin film transistor by flattening the surface of the polycrystalline silicon film, it is desired that the thickness is not reduced in the flattening step. This is because, when the polycrystalline silicon film thickness decreases, the resistance of the contact region with the electrode increases, and the film thickness variation largely reflects the transistor characteristic variation.

(Embodiment 1) The present embodiment relates to a method of manufacturing a thin film transistor in which the thickness of a polycrystalline silicon film is not reduced by a planarization step. Hereinafter, a method for manufacturing a thin film transistor in this embodiment will be described with reference to FIGS. First, a silicon oxide film (not shown) is formed on a glass substrate 1 as a base film by plasma CVD to a thickness of 200 nm.
It is formed using a method. Furthermore, by the plasma CVD method,
An amorphous silicon film is formed to a thickness of 50 nm.
After a heat treatment at 450 ° C.
As shown in (a), the polycrystalline silicon film 2 is formed by irradiating an excimer laser.

However, although the polycrystalline silicon film formed by such a laser annealing method has excellent crystallinity, irregularities of several tens nm are formed on the surface thereof. In the present embodiment, surface irregularities of about 20 nm were formed. Then, subsequently, the surface of the polycrystalline silicon film is planarized by plasma processing using SiF ₄ gas and H ₂ gas as raw materials.

In this embodiment, the partial pressure ratio of SiF ₄ is 50%, the total pressure is 0.2 Torr, and the discharge power is 100%.
W, plasma processing at a substrate temperature of 350 ° C. is performed. The SiH _x radicals generated in the plasma diffuse on the surface of the polycrystalline silicon film, and a polycrystalline silicon film is formed in a concave portion on the surface. Further, since the etching by the fluorine radical proceeds at the convex portion at the highest speed, the unevenness on the surface of the polycrystalline silicon film is finally flattened as shown in FIG. Under the flattening conditions in this embodiment, the film formation is superior to the etching, so that the polycrystalline silicon film thickness after the flattening is 6 times.
The surface roughness of this polycrystalline silicon film is about 2 nm. In addition, since the film deposited on the surface in this embodiment is a polycrystalline silicon film, there is no need for a step of removing the film deposited on the surface after planarization.

Next, as shown in FIG. 1C, the planarized polycrystalline silicon film 3 is patterned into an island shape, and a silicon oxide film is formed thereon as a gate insulating film 5 to a thickness of 100 nm by plasma. It is formed using a CVD method.

Further, after forming tantalum to a thickness of 300 nm on the surface of the gate insulating film 5 by sputtering, it is patterned to form a gate electrode 6, and using the gate electrode as a mask, as shown in FIG. Source/
Impurity ions are implanted to form a drain region. In this embodiment mode, phosphorus ions are implanted in order to manufacture an N-channel thin film transistor.

Next, as shown in FIG. 1E, an interlayer insulating film 7 is formed.
Then, a silicon oxide film is formed to a thickness of 500 nm by a normal pressure CVD method, and the impurities implanted in the step shown in FIG. Then, a contact hole to the source / drain region is opened, and the source electrode 8 and the drain electrode 9 are made of a material containing aluminum as a main component.
To form Through the above steps, a thin film transistor is manufactured.

[0027] Thin film tiger manufactured by the present embodiment
The transistor has a channel region where the carriers conduct
Flatness reduces characteristic variations of thin film transistors
Reduced and carrier scattering or trapping
Can be suppressed, so that the characteristics themselves are also improved.

[0028] In the present embodiment, the flattening step
S, which is a fluoride, as a source gas for the plasma treatment
iF_FourAnd hydrogen were used, but this was converted to chloride (SiH_TwoC
l_Two, SiCl_FourEtc.) and hydrogen have the same effect.
Can be In this case, chlorine radicals cause
Pitching proceeds. Also, in the present embodiment,
Although the film thickness increased due to the supporting process, the plasma conditions changed.
It is possible to control the film thickness change by changing
You.

(Embodiment 2) This embodiment relates to a method of manufacturing a thin film transistor in which a planarization step and a gate insulating film forming step are performed in the same vacuum. A method for manufacturing a thin film transistor in this embodiment will be described with reference to FIGS. The process up to the step of forming the polycrystalline silicon film 2 shown in FIG. 2A is the same as that of the first embodiment. A silicon oxide film (not shown) is formed as a base film on the glass substrate 1 by plasma CVD to a thickness of 200 nm. After forming using the plasma C
An amorphous silicon film is formed to a thickness of 50 nm by the VD method. Then, after a heat treatment at 450 ° C., the surface of the amorphous silicon film is irradiated with excimer laser to form a polycrystalline silicon film 2 having a surface roughness of about 20 nm.

[0030] In the present embodiment, from the flattening step
Vacuum apparatus as shown in FIG. 3 until the gate insulating film forming step
Done by Each chamber of this device is evacuated (not shown)
Equipment is installed and each chamber can be evacuated independently.
You. The arrows in the figure indicate the movement of the substrate, and are set in the load chamber 11.
The loaded substrate is evacuated to a vacuum state in the load chamber 11.
Then, the wafer is transferred to the flattening chamber 12 via the transfer chamber 10. flat
The substrate flattened in the carrier chamber 12 is again transported in a vacuum state.
After being transferred to the insulating film forming chamber 13 through the chamber 10, the surface coating film is formed.
After forming an insulating film as
It is taken out.

FIG. 2B shows a state where the polycrystalline silicon film 2 is flattened and the surface coating film 4 is formed in the same vacuum. As a method of flattening, a SiF ₄ partial pressure ratio of 60%,
Total pressure 0.2 Torr, discharge power 100 W, substrate temperature 35
Plasma treatment at 0 ° C. is performed. Thereby, the surface irregularities are flattened to about 2 nm, and the polycrystalline silicon film thickness hardly changes. The substrate whose surface is flattened is transferred to the insulating film forming chamber 13 in a vacuum, and a silicon oxide film is deposited to a thickness of 20 nm by a plasma CVD method, and then taken out of the unloading chamber 14. By forming an insulating film on the surface of the polycrystalline silicon film and exposing it to a gate insulating film or a part thereof without exposing the surface of the polycrystalline silicon film to the atmosphere,
A more clean polycrystalline silicon film and a gate insulating film interface can be formed.

Next, as shown in FIG. 2C, the polycrystalline silicon film 3 and the surface coating film 4 are patterned into an island shape, and a silicon oxide film 8 as a gate insulating film 5 is formed thereon.
It is formed to a thickness of 0 nm by using a plasma CVD method. At this time, since the silicon oxide film has already been formed to a thickness of 20 nm on the surface of the polycrystalline silicon film, the gate insulating film thickness on the channel is 100 nm.

In the present embodiment, the surface coating film 4 formed after planarization and the gate insulating film 5 formed after patterning the polycrystalline silicon film are made of the same silicon oxide film. It may be an insulating film. The surface coating film 4 formed after the planarization is not a CVD deposited film, but a polycrystalline silicon film 3 using a plasma oxidation method or the like.
May be oxidized at a low temperature.

[0034] Sputtering is also applied to the gate insulating film surface.
Tantalum was formed to a thickness of 300 nm by the
Then, patterning is performed to form a gate electrode 6, and the gate electrode 6 is formed.
Using the pole 6 as a mask, as shown in FIG.
Impurity ions are implanted to form the drain region.
U. In this embodiment, an N-channel thin film transistor is used.
In order to manufacture a star, phosphorus ions are implanted.

Next, as shown in FIG.
A silicon oxide film is formed to a thickness of 500 nm by a normal pressure CVD method, and the impurity implanted in the step shown in FIG. Then, a contact hole to the source / drain region is opened, and a source electrode 8 and a drain electrode 9 are formed using a material containing aluminum as a main component. Through the above steps, a thin film transistor is manufactured.

In the thin film transistor manufactured according to this embodiment, the surface of the channel region through which carriers are conducted is flat and clean, so that variations in the characteristics of the thin film transistor can be reduced, and scattering and trapping of carriers can be prevented. Since it can be suppressed, the characteristics themselves are also improved.

[0037] In the present embodiment, the flattening step
S, which is a fluoride, as a source gas for the plasma treatment
iF_FourAnd hydrogen were used, but this was converted to chloride (SiH_TwoC
l_Two, SiCl_FourEtc.) and hydrogen have the same effect.
Can be In this case, chlorine radicals cause
Pitching proceeds. Also, in the present embodiment,
The thickness of the polycrystalline silicon film does not change due to the supporting process
Conditions were used, but changing the plasma conditions
It is possible to control the thickness change.

[0038]

As described above, according to the method for manufacturing a thin film transistor of the present invention, a crystalline semiconductor film having excellent crystallinity and a flat and clean surface can be obtained, so that the interface between the crystalline semiconductor and the gate insulating film can be obtained. The condition can be improved. As a result, a thin film transistor having small characteristic variations and small carrier scattering in the channel region is manufactured.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a thin film transistor in Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram of a thin film transistor manufacturing process in Embodiment 2 of the present invention.

FIG. 3 is a schematic diagram of a vacuum device used in Embodiment 2 of the present invention.

FIG. 4 is a diagram showing the dependency of the amount of change in polycrystalline silicon film thickness due to planarization on the SiF ₄ partial pressure.

FIG. 5 is an explanatory view of a conventional thin film transistor manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Polycrystalline silicon film 3 Planarized polycrystalline silicon film 4 Surface coating film 5 Gate insulating film 6 Gate electrode 7 Interlayer insulating film 8 Source electrode 9 Drain electrode 10 Transport chamber 11 Load chamber 12 Flattening chamber 13 Insulation film formation room 14 Unload room

Continued on front page F-term (reference)

Claims (6)

[Claims] A step of forming a crystalline semiconductor film mainly composed of silicon; a step of flattening a surface of the crystalline semiconductor film; and a step of forming an insulating film on the surface of the crystalline semiconductor film. A method of manufacturing a thin film transistor, characterized in that the thickness of the crystalline semiconductor film is not reduced by the flattening step. 2. A step of forming a crystalline semiconductor film mainly composed of silicon, a step of flattening a surface of the crystalline semiconductor film, and a step of forming an insulating film on the surface of the crystalline semiconductor film. Wherein the step of forming an insulating film on the surface of the crystalline semiconductor film is performed continuously in the same vacuum as the flattening step. . 3. A step of forming a crystalline semiconductor film mainly composed of silicon, a step of flattening a surface of the crystalline semiconductor film, and a step of forming an insulating film on a surface of the crystalline semiconductor film. In the method of manufacturing a thin film transistor, the flattening step comprises flattening a convex portion on the surface of the crystalline semiconductor film while forming a polycrystalline silicon film in a concave portion on the surface of the crystalline semiconductor film. A method for manufacturing a thin film transistor, which is characterized in that: 4. The plasma processing step according to claim 1, wherein the flattening step is a plasma processing step using a gas in which at least a halogenated silane and a gas for supplying hydrogen atoms are mixed. Method for manufacturing thin film transistor. 5. The method according to claim 1, wherein the halogenated silane is SiF ₄ , Si
5. The method according to claim 4, wherein the method is one of Cl ₄ and SiH ₂ Cl ₂ . 6. The semiconductor device according to claim 1, wherein said crystalline semiconductor film mainly composed of silicon is a polycrystalline silicon film having a thickness of 10 nm or less, and is polycrystallized by irradiating a laser beam. Item 4. A method for manufacturing a thin film transistor according to any one of items 3.