JP2000259132A - Shift register circuit and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a shift register circuit which stably operates without extremely increasing the driving capability of an external IC by eliminating an unstable state at the time of powered ON. SOLUTION: This shift register circuit 1 is equipped with latch circuits LATA and LATB which are connected in series and transfer pulse signals ST in order, a clock line CLKL which transmits a clock signal CLK and switch circuits ASW which electrically connect and disconnect the clock line CLKL and latch circuits LATA and LATB. When the shift register circuit 1 is powered ON, at least one of the switch circuits ASW electrically disconnects at least one of the latch circuits LATA and LATB from the clock line CLKL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit for transferring a digital signal in synchronization with the rise and fall of a clock signal, and more particularly to a shift register circuit for locally inputting a clock signal. The present invention relates to a shift register circuit in which a load on a clock signal line is reduced, an operation margin is improved and power consumption is reduced, and an image display device in which the shift register circuit is applied to a data signal line driving circuit or a scanning signal line driving circuit. .

[0002]

2. Description of the Related Art As a conventional liquid crystal display device, a liquid crystal display device of an active matrix drive system (hereinafter referred to as an active matrix drive type liquid crystal display device) is known.

FIG. 18 is a diagram showing an active matrix drive type liquid crystal display device 100.

[0004] The active matrix driving type liquid crystal display device 100 shown in FIG. 18 includes a pixel array ARY, a scanning signal line driving circuit GD, and a data signal line driving circuit SD.

The pixel array ARY includes a plurality of scanning signal lines G
L, and a plurality of data signal lines SL crossing the plurality of scanning signal lines GL. Two adjacent scanning signal lines G
Pixels PIX are arranged in a matrix at a portion surrounded by L and two adjacent data signal lines SL. The data signal line driving circuit SD samples the input video signal DAT in synchronization with a timing signal such as a clock signal CKS, amplifies the sampled video signal DAT as necessary, and outputs the amplified signal to the data signal line SL. I do.

The scanning signal line driving circuit GD synchronizes with a timing signal such as a clock signal CKG, etc.
Are sequentially selected, and the opening and closing of the switching element in the pixel PIX is controlled, whereby the video signal (data) output to the data signal line SL is written to the pixel PIX.
The pixel PIX functions to hold data written in the pixel PIX.

FIG. 19 is a diagram showing details of the pixel PIX shown in FIG.

The pixel PIX has a field effect transistor SW as a switching element and a pixel capacitor CI (liquid crystal capacitor C).
L and an auxiliary capacitance CS added as necessary).

The field effect transistor SW has a drain,
It has a source and a gate. Hereinafter, one of the drain and the source is called a first electrode, and the other of the drain and the source is called a second electrode.

The first electrode of the field effect transistor SW is connected to the data signal line SL,
Is connected to one end a of the pixel capacitor CI. The gate of the field effect transistor SW is connected to the scanning signal line GL. The other end b of the liquid crystal capacitor CL is connected to all pixels P
IX are connected to a common electrode line. Liquid crystal capacitance C
The transmittance or reflectance of the liquid crystal is modulated by the voltage applied to L, and an image is displayed.

In a conventional active matrix type liquid crystal display device, an amorphous silicon thin film formed on a transparent substrate such as glass is used as a material of the pixel transistor SW. Further, the scanning signal line driving circuit GD and the data signal line driving circuit SD in the conventional active matrix type liquid crystal display device are each configured by an external integrated circuit (IC).

However, in recent years, due to demands such as improvement in driving power of a pixel transistor accompanying a large screen, reduction in mounting cost of a driving IC, and reliability in mounting, a pixel is monolithically formed using a polycrystalline silicon thin film. An array and a drive circuit are formed.

In order to increase the screen size and reduce the cost of the liquid crystal display device, an element such as a field effect transistor is formed on a glass substrate at a process temperature equal to or lower than the glass strain point (about 600 ° C.). Has been attempted.

FIG. 20 is a diagram showing an active matrix type liquid crystal display device 200.

In the active matrix type liquid crystal display device 200 shown in FIG. 20, a pixel array ARY, a scanning signal line driving circuit GD, and a data signal line driving circuit SD are mounted on an insulating substrate SUB. Circuit GD
And a data signal line drive circuit SD, a timing signal generation circuit CTL and a power supply voltage generation circuit VGE, respectively.
N is connected.

The data signal line driving circuit SD outputs the video signal D
Receive AT etc. In FIG. 20, a path through which the video signal DAT or the like in the data signal line driving circuit SD is transmitted is indicated by a broken line.

The scanning signal line driving circuit GD outputs the pulse signal G
Receive PS etc. In FIG. 20, a path through which the pulse signal GPS or the like in the scanning signal line driving circuit GD is transmitted is indicated by a broken line.

As a data signal line driving circuit, a data signal line driving circuit of a dot sequential driving method and a data signal line driving circuit of a line sequential driving method are known due to a difference in a method of writing a video signal to a video signal line. . In a polycrystalline silicon TFT panel in which a data signal line driving circuit is integrated, a data signal line driving circuit of a point-sequential driving method is often used because of a simple configuration of the data signal line driving circuit.

The structure of a frequently used dot-sequential driving data signal line driving circuit will be described below with reference to FIG.

FIG. 21 is a diagram showing a data signal line drive circuit SD of a dot sequential drive system.

In the dot sequential driving method, a plurality of latch circuits L
Shift register circuit S composed of ATA and LATB
The sampling switch AS is opened and closed in synchronization with an output pulse output from each stage (each latch circuit) of the FC. By opening and closing the sampling switch AS, the video signal DAT input to the video signal line is written to the data signal line SL.

As shown in FIG. 21, a buffer circuit BFC1 is located between the shift register circuit SFC and the sampling switch AS. The buffer circuit BFC1 takes in the pulse signal output from the shift register circuit SFC, holds and amplifies the pulse signal, and generates an inverted signal of the pulse signal as necessary.

FIG. 2 shows the configuration of the scanning signal line driving circuit.
2 will be described.

FIG. 22 is a diagram showing the scanning signal line driving circuit GD. The scanning signal line driving circuit GD shown in FIG. 22 includes a shift register circuit SFC including a plurality of latch circuits LATA and LATB, and a buffer circuit BFC2.

The scanning signal line driving circuit GD shown in FIG.
By amplifying output pulse signals (as required, logical operation results with other signals) output from each stage (each latch circuit) of the shift register circuit SFC including a plurality of latch circuits LATA and LATB. , And outputs the amplified output pulse signal as a scanning signal.

As described above, the data signal line driving circuit S
In each of the driving circuits D and the scanning signal line driving circuit GD, a shift register circuit SFC for sequentially transferring pulse signals is used.

FIG. 23 is a diagram showing the shift register circuit SFC. As shown in FIG.
ATA and LATB are alternately connected in series.

FIG. 24 is a diagram showing a clock signal CLK input to the shift register circuit SFC shown in FIG. Note that the clock signal / CLK whose phase is inverted from that of the clock signal CLK is also input to the shift register circuit SFC illustrated in FIG.

FIG. 25 is a diagram showing a latch circuit LATA constituting the shift register circuit SFC, and FIG.
Latch circuit LAT forming shift register circuit SFC
FIG.

The latch circuits LATA and LATB are composed of one inverter and two clocked inverters CICA and CICA.
ICB, two clocked inverters C
Clock signals CLK and / CLK having opposite phases are input to ICA and CICB, respectively.

FIG. 27 shows a clocked inverter CICA.
FIG. 28 is a diagram showing a clocked inverter CI.
It is a figure showing CB. For example, in clocked inverter CICA shown in FIG. 27, when clock signal CLK is at a high level, an inverted signal of the signal input to input terminal IN of clocked inverter CICA is output from output terminal OUT of clocked inverter CICA. You. In the clocked inverter CICB shown in FIG. 28,
When the clock signal CLK is at the low level, an inverted signal of the signal input to the input terminal IN of the clocked inverter CICB is output from the output terminal O of the clocked inverter CICB.
Output from UT.

When a shift register circuit or a latch circuit is described in this specification and this drawing, clock signals having phases opposite to each other are input to these circuits, and therefore, clock signals having phases opposite to each other are input to the circuits. In some cases, description will be made using only one clock signal CLK.

[0033]

In the shift register circuit SFC shown in FIG. 23, clock signals CLK and / C
Since LK is input to all the latch circuits LATA and LATB, the load capacitance of the clock signal lines CLKL and / CLKL becomes extremely large. As a result, in order to drive the clock signal lines CLKL and / CLKL, it is necessary to use an external IC (e.g., a controller IC) having a large driving capability, which increases the manufacturing cost of the liquid crystal display device and increases the cost of the liquid crystal display device. Power consumption increases.

Japanese Unexamined Patent Publication No. Hei 3-147598 discloses that in order to reduce the load capacitance of a clock signal line, only when the output of each stage (latch circuit) of a shift register circuit is significant (active state), the latch circuit is activated. A configuration is disclosed in which a clock signal is input to a.

Specifically, whether the clock signal line is connected to or disconnected from each latch circuit is controlled by an output signal of each latch circuit (or a sum signal of output signals of a plurality of adjacent latch circuits).

However, in such a configuration, when the power is turned on, the state (voltage level) of the internal node of the shift register circuit is indefinite (it can be in any state). Occasionally, all the internal nodes of the shift register circuit may be activated. This state continues until a signal corresponding to the inactive state is scanned through all stages of the shift register circuit (initialization of the shift register circuit).

In this state, since the clock signal has been input to all the latch circuits, the load capacitance of the clock signal line is in the normal state (the state in which one pulse signal is scanned in the shift register circuit). (When the number of latch circuits to which the clock signal is input is one to several).

Therefore, when there is no sufficient driving capability (when the external IC is optimized for a small load capacity), the clock signal line cannot be driven within a predetermined time, and the shift is not performed. There is a possibility that the register circuit cannot operate.

Therefore, the external IC for supplying the clock signal needs to have the ability to drive even if it has such a large load capacity. However, in the normal state, the load capacity is small, and the drive capacity corresponding to the load capacity is small. Is unnecessary. That is, an external IC having a large driving capability is required only for initializing the shift register circuit when the power is turned on, which is an obstacle to further reducing costs and power consumption. .

The present invention has been made to solve such a problem of the prior art. In a shift register circuit in which a load on a clock signal line is reduced by locally inputting a clock signal, the present invention is applied to a shift register circuit. It is an object of the present invention to provide a shift register circuit that operates normally even in a device such as an image display device, and that the shift register circuit is provided as a part of a driver circuit, thereby realizing low power consumption and low cost. .

[0041]

A shift register circuit according to the present invention includes a plurality of latch circuits connected in series and sequentially transferring a pulse signal, a clock line transmitting a clock signal, the clock line and the plurality of clock lines. A plurality of switch circuits for electrically connecting or disconnecting a latch circuit; and when power is supplied to the shift register circuit, at least one of the plurality of switch circuits includes: At least one of the plurality of latch circuits
And the clock line is electrically disconnected, thereby achieving the above object.

Another shift register circuit of the present invention includes a plurality of latch circuits connected in series and sequentially transferring a pulse signal, a clock line transmitting a clock signal, and the clock line and the plurality of latch circuits. A shift register circuit comprising: a plurality of switch circuits that are electrically connected or disconnected, wherein at least one of the plurality of switch circuits is connected to at least one of the plurality of latch circuits and a clock line at regular time intervals. Are electrically disconnected, thereby achieving the above object.

The potential of the nodes of the plurality of latch circuits is
The plurality of switch circuits change according to the transmitted pulse signal, and each of the plurality of switch circuits electrically connects or disconnects the corresponding latch circuit and a clock line according to a potential of a node of the corresponding latch circuit. A period during which the pulse signal is transferred from a first latch circuit to a last latch circuit of the plurality of latch circuits;
Preferably, the frequency of the clock signal is lower than the frequency of the clock signal during a normal period.

[0044] The frequency of the clock signal during the at least a part of the period may be gradually increased.

[0045] The frequency of the clock signal in at least a part of the period may be 1/2 to 1/16 of the clock signal in the normal period.

Each of the plurality of latch circuits may include an initialization circuit that receives an initialization signal from the outside and initializes an internal node according to the initialization signal.

The amplitude of the clock signal may be smaller than the amplitude of a power supply voltage of the shift register circuit.

[0048] The shift register circuit may have a buffer circuit for supplying a clock signal received from the outside to the plurality of latch circuits.

The amplitude of the clock signal received from the outside by the shift register circuit is different from the amplitude of the clock signal supplied to the plurality of latch circuits, and the amplitude of the clock signal received by the shift register circuit changes. A level shift circuit may be provided.

A plurality of pixels provided in a matrix,
An active matrix type comprising: a data signal line for supplying video data to be written to one of the plurality of pixels; and a scanning signal line for controlling writing of the video data to one of the plurality of pixels. An image display device,
It is preferable that a scanning signal line driving circuit that outputs a pulse signal to the scanning signal line in synchronization with a timing signal includes the shift register circuit or another shift register circuit of the present invention.

A plurality of pixels provided in a matrix,
An active matrix type comprising: a data signal line for supplying video data to be written to one of the plurality of pixels; and a scanning signal line for controlling writing of the video data to one of the plurality of pixels. An image display device,
A data signal line driving circuit that outputs the video data to the data signal line in synchronization with a timing signal,
It is preferable that the semiconductor device include the shift register circuit or the other shift register circuit.

The data signal line drive circuit may initialize a potential level of each internal node of each of the plurality of latch circuits of the shift register circuit in synchronization with a vertical synchronization signal.

[0053] At least one of the data signal line driving circuit and the scanning signal line driving circuit may be formed on the same substrate as the plurality of pixels.

At least the active element of the data signal line drive circuit may be a polycrystalline silicon thin film transistor.

The active element is formed on a glass substrate by 600
It may be formed by a process at a temperature of not more than ° C.

The operation will be described below.

In the shift register circuit of the present invention,
In a configuration in which a clock signal is selectively input only to a latch circuit in an active state and a latch circuit in the vicinity thereof, the potential levels of internal nodes of all the latch circuits are initialized when power is turned on. Since the internal node of the shift register circuit becomes indefinite only when the power is turned on, by performing initialization only when the power is turned on, there is no possibility that the operation during the normal operation period will be adversely affected. With such a configuration, the load capacitance of the clock signal line is reduced, and the external IC that supplies the clock signal has:
In particular, since a large driving capability is not required, the cost and power consumption of the external IC can be reduced.

In another shift register circuit according to the present invention, in a configuration in which a clock signal is selectively input only to a latch circuit in an active state and a latch circuit in the vicinity thereof, all of the latches are provided at regular intervals. In such a configuration in which the potential level of the internal node of the circuit is initialized, an appropriate timing signal in the system can be used and the inside of the shift register circuit can be initialized in synchronization with this. There is no need to input or generate a signal for initialization. In addition, with such a configuration, the load capacity of the clock signal line is reduced and the external IC for supplying the clock signal does not require a particularly large driving capability, so that the cost and power consumption of the external IC can be reduced. Is achieved.

In the shift register circuit or the other shift register circuit, at least for a period longer than a period in which the pulse signal is transferred to all the stages of the latch circuit,
The internal node of the latch circuit is initialized by reducing the frequency of the clock signal from a normal frequency. In such a configuration, the shift register circuit can be initialized only by changing the timing (frequency) of the clock signal input from the outside, and there is no need to newly add a circuit for initialization. .

In the shift register circuit or the other shift register circuit, the frequency of the clock signal for the initialization is gradually increased. In such a configuration, the initialization time can be reduced, so that other operations are not hindered or restricted.

In the shift register circuit or the other shift register circuit, the lowest frequency of the reduced clock signal is な い し to 1 of a normal frequency.
/ 16. At such a frequency, the period of operation at a low frequency is not so long, so that it is easy to minimize the influence on other operations. In particular, a frequency that is an integer fraction of the original frequency can be easily obtained by dividing the frequency of a normal clock signal.

In the shift register circuit or the other shift register circuit, an internal node initialization circuit is provided in each of the latch circuits, and an internal initialization signal is input from the external to the internal node initialization circuit. Initializing. In such a configuration, since all the latch circuits can be initialized at the same time, the initialization time is reduced, and there is little possibility that other operations will be adversely affected.

In the shift register circuit or the other shift register circuit, the amplitude of the clock signal is smaller than the power supply voltage of the shift register circuit. In such a configuration, the element size of the latch circuit to which the clock signal is input is increased, and the load capacity is also increased.

The shift register circuit or the other shift register circuit has a buffer circuit for supplying a clock signal input from the outside to each of the latch circuits. In such a configuration, only one of the clock signals can be input from the outside and an inverted signal thereof can be generated internally, which is effective in reducing the number of terminals and simplifying the external IC. Further, since the size (drive capability) of the buffer circuit is determined by the load capacitance of the clock signal line, the size of the buffer circuit can be reduced by reducing the effective load.

In the shift register circuit or the other shift register circuit, the amplitude of the clock signal supplied from the outside and the amplitude of the clock signal supplied to each of the latch circuits are different, and the clock signal supplied from the outside is different. Has a level shift circuit for changing the amplitude of the signal. In such a configuration, the size (driving capability) of the level shift circuit or the buffer circuit at the subsequent stage
Is determined by the load capacitance of the clock signal line,
By reducing the effective load, the size of the level shift circuit or the buffer circuit can be reduced. In addition, by providing the level shift circuit, the voltage level of the input signal can be made lower than the drive voltage of the shift register circuit, so that an external level shift IC can be eliminated and external consumption can be reduced. Power can be reduced.

A plurality of pixels provided in a matrix,
In an active matrix image display device including a plurality of data signal lines for supplying video data to be written to the pixel and a plurality of scanning signal lines for controlling writing of the video data to the pixel, the active matrix type image display device is synchronized with a timing signal. A scanning signal line driving circuit that outputs a pulse signal to the scanning signal line includes any one of the shift register circuits.
In such a configuration, for the above-described reason, normal operation of the shift register circuit can be realized while suppressing the driving ability of the external IC that drives the clock signal line input to the scanning signal line driving circuit. Therefore, a high-quality image display device having low cost and low power consumption can be realized.

A data signal line drive circuit for outputting a video signal to the data signal line in synchronization with a timing signal includes any one of the shift register circuits. In such a configuration, an external IC for driving a clock signal line input to the data signal line driving circuit is provided for the above-described reason.
Since the normal operation of the shift register circuit can be realized while suppressing the driving capability of the device, a high-quality image display device having low cost and low power consumption can be realized. In particular, since the data signal line driving circuit is a portion having the highest operating frequency in the image display device, the effect of reducing the load capacitance of the clock signal line is great.

In synchronization with the vertical synchronizing signal, the potential levels of the internal nodes of all the latch circuits of the shift register circuit constituting the data signal line driving circuit are initialized. In such a configuration, a vertical synchronizing signal or a start signal of the scanning signal line driving circuit generated thereby can be used as a signal for initialization, so that there is no need to add a new signal.

An active element constituting at least the data signal line driving circuit is a polycrystalline silicon thin film transistor. When a transistor is formed by using a polycrystalline silicon thin film in this way, extremely high driving characteristics can be obtained as compared with an amorphous silicon thin film transistor used in a conventional active matrix liquid crystal display device.
In addition to the effect, the pixel and the signal line driving circuit,
There is a merit that it can be easily formed on the same substrate. Therefore, the effects of reducing the manufacturing cost and the mounting cost and increasing the non-defective mounting rate can be expected. In addition, since a polycrystalline silicon thin film transistor has a driving force that is about one to two orders of magnitude smaller than a single crystal silicon transistor, when a scanning signal line driving circuit and a data signal line driving circuit are formed using the same, Needs to be increased in size. As a result, the load capacity of the clock signal line also increases, and the present configuration, in which the above effects can be expected, is highly effective. Furthermore, when a level shift circuit and a buffer circuit for a clock signal line are configured by using this,
Since the driving force is small, the effect of performing initialization for reducing the load capacity is large.

The active element is formed on a glass substrate by 600
It is formed by a process at a temperature of ℃ or less. Thus, 60
When a polycrystalline silicon thin film transistor is formed at a process temperature of 0 ° C. or lower, glass having a low strain point but inexpensive and easy to increase in size can be used as a substrate. There is an advantage that a large-sized image display device can be manufactured at low cost.

[0071]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a shift register circuit 1 in Embodiment 1.

The shift register circuit 1 shown in FIG. 1 includes a plurality of latch circuits LATA, LATB, and a plurality of OR circuits O.
R, and a plurality of switches ASW. An example of the latch circuit LAT is shown in FIG.
An example of B is shown in FIG. Note that the first latch circuit of the shift register circuit 1 shown in FIG.
Or a latch circuit LATB, but is determined by an input clock signal.

Whether or not clock signals CLK and / CLK are input to latch circuits LATA and LATB is controlled by OR circuit OR and switch ASW. For example, the OR circuit OR belonging to a certain unit 2 receives a signal output from a latch circuit preceding the latch circuit belonging to a certain unit 2 and a signal output from a latch circuit belonging to a certain unit 2, and receives the signals. Calculate the logical sum of these signals. Based on the calculated signal,
When the switch ASW belonging to a certain unit 2 becomes conductive, the clock signals CLK and / CLK are input to the latch circuits belonging to the certain unit 2.

That is, the clock signal is input to the latch circuit only when at least one of the latch circuit preceding the latch circuit belonging to the certain unit 2 and the latch circuit belonging to the certain unit 2 is in the active state. With the above-described configuration, most of the input capacitance of the latch circuit is disconnected from the clock signal lines CLKL and / CLKL. Therefore, the clock signal line CLK of the shift register circuit 1
The capacitances of L and / CLKL are extremely small as compared with the shift register circuit SFC shown in FIG. For this reason, the shift register circuit 1 can use a clock signal supply IC having a small driving ability.

However, when the power is turned on, the state (potential level) of the internal nodes of the latch circuits LATA and LATB is undefined. That is, the latch circuit LAT
A, the state of the internal node of LATB may be any state.

Therefore, the latch circuits LATA, LATB
All or most nodes may become active. All latch circuits LATA, LA
When the node of TB becomes active, the clock signal lines CLKL and / CLKL are connected to all the latch circuits LATA,
Connected to LATB. All latch circuits LATA, L
The load capacitance of the clock signal lines CLKL and / CLKL in the state where the node of the ATB becomes active is much larger than that in the other states.

When all the nodes of the latch circuits LATA and LATB become active, there is a possibility that a clock signal supply IC having a driving force enough to perform a normal operation cannot drive the shift register circuit.

FIG. 2 is a diagram showing an example of the clock signal CLK input to the shift register circuit and a clock signal CLKint inside the shift register circuit.

In the state where all the nodes of the latch circuits LATA and LATB are active, the load capacitance of the clock signal lines CLKL and / CLKL is large.
Clock signal CLK inside the shift register circuit shown in FIG.
Int has a duller waveform than the clock signal CLK input to the shift register circuit. For this reason, a sufficient amplitude for driving the shift register circuit cannot be secured. As a result, the shift register circuit does not operate. In other words, the levels of the internal nodes of the latch circuits LATA and LATB do not change. Therefore, clock signal line CLK
The load capacitances of L and / CLKL continue to take large values, and the shift register circuit cannot start operation.

However, the clock signal lines CLKL, / CL
When the load capacity of KL is large, the clock signal line CLK
If a clock signal supply IC having the ability to drive L and / CLKL is used, the shift register circuit operates. FIG. 3 is a diagram illustrating an example of the clock signal CLK input to the shift register circuit and a clock signal CLKint inside the shift register circuit when a clock signal supply IC having a large driving capability is used.

Such a large driving capability is unnecessary in a normal operation state, and only increases power consumption. Further, a clock signal supply IC having a large driving capability has a disadvantage that the cost is naturally high.

Even if a clock signal supply IC having a small driving ability is used, as shown in FIG. 4, the frequency of the clock signal CLK during the initialization operation period is made lower than the frequency of the clock signal CLK during the normal operation period. In addition, it is possible to solve the problem that a sufficient amplitude is not secured for driving the shift register circuit. The initialization operation period refers to a period in which a predetermined time has elapsed since the power was turned on. The normal operation period means a period other than the initialization operation period.

FIG. 5 is a diagram showing an example of the clock signal CLK and an example of the clock signal CLKint in the shift register circuit during the initialization operation period and the normal operation period. As shown in FIG. 5, the clock signal line CL
The clock signal C depends on the load capacitance of KL and / CLKL.
Although the rise of LKint is not agile, the shift register circuit operates normally because the clock signal CLKint is equal to or higher than a predetermined level (threshold).

The shift register circuit enters the initialization operation period and reduces the clock frequency for a certain period. Therefore, even if all the latch circuits LATA and LATB are active, as the initialization of the shift register circuit 1 proceeds, the latch circuits LATA and LATB are disconnected from the clock signal lines CLKL and / CLKL one after another from the first stage. . Therefore, the clock signal lines CLKL, / C
The load capacity of LKL gradually decreases.

The clock signal C at power-on
The frequency of LK, / CLK is the clock signal line CL
Although it is determined by how much the load capacitance of KL and / CLKL increases, generally, it should be about 1/2 to 1/16 of the clock signals CLK and / CLK during the normal operation period.

Although the frequency of the clock signal for initialization shown in FIGS. 4 and 5 is constant, the frequency of the clock signal for initialization is not necessarily required to be constant. For example, the frequency of the clock signal for initialization may gradually change.

FIG. 6 shows a clock signal CLK at power-on.
Is a diagram showing a clock signal whose frequency is lower than the frequency of the clock signal CLK at the end of the initialization period. For example, the clock frequency at power-on is set to 1/8 of the clock signal CLK in the normal operation period, the frequency of the clock signal CLK is gradually increased, and the clock frequency when the initialization is completed is set to the normal operation period. At the frequency of the clock signal CLK.

For example, all the latch circuits LATA, L
Even if ATB is active, shift register circuit 1
, The latch circuits LAT, LAT
B indicates the clock signal lines CLKL and / CL sequentially from the first stage.
KL, the clock signal lines CLKL,
/ CLKL gradually decreases in load capacity. For this reason,
Even if the frequency is increased, it is possible to drive sufficiently. By gradually increasing the frequency of the clock signals CLK and / CLK, the initialization period required for the initialization can be shortened. The frequency of the clock signal is
It may be increased continuously or discontinuously every few clocks.

(Embodiment 2) FIG. 7 is a diagram showing another clock signal for driving the shift register circuit 1. In FIG.

In the clock signal shown in FIG. 7, the frequency of the clock signal decreases for a certain period in synchronization with an arbitrary pulse signal PLS input at a certain period. Therefore, the shift register circuit 1 can be initialized at regular intervals. The shift register circuit 1 operates normally even if a clock signal supply IC having a small driving ability is used. Note that the certain period may be a period of one frame of a certain video.

(Embodiment 3) FIGS. 8 and 9 are diagrams showing another configuration example of the latch circuits LATA and LATB of the shift register circuit 1. FIG.

In the latch circuit shown in FIGS. 8 and 9, the internal node of the latch circuit is forcibly reset. For example, the signal output from the latch circuit goes low by reset.

FIGS. 10 and 11 are diagrams showing the clock signal CLK and the reset signal RST when the latch circuit shown in FIGS. 8 and 9 is used.

In the example of the signal waveform shown in FIG. 10, reset signal RST is input to latch circuits shown in FIGS. 8 and 9 only when power is turned on, and internal nodes of those latch circuits are initialized.

In the example of the signal waveform shown in FIG. 11, in synchronization with a certain pulse signal PLS inputted at a constant period,
Reset signal RST is input to the latch circuits shown in FIGS. 8 and 9, and the internal nodes of those latch circuits are initialized.

As described above, by initializing the shift register circuit 1, a normal operation of the shift register circuit 1 can be realized even if a clock signal supply IC having a small driving ability is used.

Note that the fixed period may be a period of one frame of a certain video.

(Embodiment 4) FIGS. 12 and 13 are diagrams showing still another configuration example of the latch circuits LATA and LATB of the shift register circuit 1. FIG.

Latch circuit LA shown in FIGS. 12 and 13
TA and LATB have transistors M1 to M8, respectively.

The clock signal input to shift register circuit 1 having the latch circuit shown in FIGS. 12 and 13 may be the clock signal shown in FIG. 4 or FIG.

Latch circuit LA shown in FIGS. 12 and 13
TA and LATB have a level shift function. Latch circuits LATA, L shown in FIGS. 12 and 13
Even if a clock signal having an amplitude smaller than that of the power supply voltage VCC is input to the ATB, the latch circuits LATA and LATB shown in FIGS. 12 and 13 output signals having the amplitude of the power supply voltage VCC.

For example, when the power supply voltage of latch circuits LATA and LATB shown in FIGS. 12 and 13 is 0V / 15V, even if the amplitude of the clock signal line is 0V / 5V, a signal having an amplitude of 0V / 15V is generated. 12 and 13
Are output from the latch circuits LATA and LATB shown in FIG.

Latch circuit LA shown in FIGS. 12 and 13
In TA and LATB, it is necessary to reduce the on-resistance of the current path on the ground (GND) side. for that purpose,
The size (channel width) of the transistors M4 and M6 to which the clock signal is input must be increased.

Therefore, the input capacitance of the latch circuit as viewed from the clock signal line becomes extremely large. Therefore, the shift register circuit of the present invention greatly reduces the effect of reducing the signal line capacitance due to the configuration in which the clock signal is locally input. large.

Further, when all the latch circuits are connected to the clock signal line when the power is turned on, the effect of the increase in the load capacity becomes extremely large, so that the effectiveness of the initialization of the above-described shift register circuit becomes very large.

(Fifth Embodiment) FIG. 14 is a diagram showing a shift register circuit 10 according to a fifth embodiment.

The shift register circuit 10 shown in FIG.
A plurality of latch circuits LATA, LATB, a plurality of OR circuits OR, a plurality of switches ASW, and a buffer circuit 1
1 is provided. In FIG. 14, only the signal CLKext, which is one phase of the clock signal, is externally input to the shift register circuit 10, and the clock signals CLK and / CLK are supplied to the shift register circuit via the buffer circuit 11. The buffer circuit 11 has at least one inverter circuit INV. Note that the buffer circuit 11 shown in FIG. 14 has three inverter circuits INV.

The shift register circuit 10 is the buffer circuit 1
With 1, the number of signal lines externally connected to the shift register circuit 10 can be reduced.

(Sixth Embodiment) FIG. 15 is a diagram showing a shift register circuit 20 according to a sixth embodiment.

The shift register circuit 20 shown in FIG.
Plural latch circuits LATA, LATB, plural OR circuits OR, plural switches ASW, level shift circuit LS
And a buffer circuit 21. Buffer circuit 2
1 has at least one inverter circuit INV.

In shift register circuit 20, external clock signals CLKext and / CLKex externally input are provided.
The amplitude of t is smaller than the amplitude of clock signals CLK and / CLK input to shift register circuit 1 shown in FIG. External clock signal CLKex input from outside
t and / CLKext are supplied to the latch circuits LATA and LAT via the level shift circuit LS and the buffer circuit 21, respectively.
B.

In the shift register circuit 20, since the amplitude of the clock signal input from the outside can be reduced, an external level shifter IC becomes unnecessary, and
Low power consumption is achieved.

(Embodiment 7) In the image display device shown in FIG. 18, it is preferable that at least one of the data signal line driving circuit SD and the scanning signal line driving circuit GD has the shift register circuit 1 shown in FIG. . Alternatively, in the image display device illustrated in FIG. 18, at least one of the data signal line driver circuit SD and the scanning signal line driver circuit GD preferably includes the shift register circuit 10 illustrated in FIG. Alternatively, in the image display device illustrated in FIG. 18, it is preferable that at least one of the data signal line driving circuit SD and the scanning signal line driving circuit GD includes the shift register circuit 20 illustrated in FIG.

Since the image display device shown in FIG. 18 includes at least one of the shift register circuit 1, the shift register circuit 10, and the shift register circuit 20, power consumption of a supply system for supplying a clock signal is reduced. It becomes possible.

Generally, a data signal line driving circuit is driven at a frequency several hundred times to a thousand times or more as compared with a scanning signal line driving circuit. Therefore, in the data signal line driving circuit,
The effect of the present invention is greater than that of the present invention in a scanning signal line driving circuit. In addition,
It goes without saying that the present invention is useful even when the present invention is implemented in a scanning signal line driving circuit.

The vertical synchronizing signal of the image display device (or the start pulse of the scanning signal line driving circuit) is input at a cycle of the frame frequency (normally 60 Hz).
Using this as a synchronization signal, the shift register circuit can be initialized at regular intervals. If the signal is used, there is no need to input a signal for specifying the initialization time from outside the image display device.

(Embodiment 8) In an image display device, forming a data signal line driving circuit and a scanning signal line driving circuit on the same substrate as a pixel (in a monolithic manner) means that these components are separately configured and mounted. Rather than reducing the manufacturing cost and mounting cost of the image display device,
It is also effective in improving reliability.

In the image display device shown in FIG.
X, the data signal line driving circuit SD, and the scanning signal line driving circuit GD are formed on the same substrate SUB (driver monolithic structure), and the image display device shown in FIG. It is driven by a signal and a drive power supply from an external power supply circuit VGEN.

In the above-described configuration, the data signal line driving circuit SD and the scanning signal line driving circuit GD are widely arranged in a region having substantially the same length as the screen (display region), and therefore, a clock signal or the like is not provided. The wiring length is extremely long.

Therefore, the load capacity of the clock signal line and the like becomes extremely large, so that the effect of reducing the load capacity of the clock signal line by locally inputting the clock signal also increases.

That is, in the eighth embodiment, at least one of the data signal line driving circuit SD and the scanning signal line driving circuit GD of the image display device shown in FIG. 20 has the shift register circuit 1 shown in FIG. 20. At least one of the data signal line driving circuit SD and the scanning signal line driving circuit GD of the image display device shown in FIG. 20 has the shift register circuit 10 shown in FIG.
It is preferable that at least one of the data signal line driving circuit SD and the scanning signal line driving circuit GD of the image display device shown in FIG. 0 has the shift register circuit 20 shown in FIG.

FIG. 16 is a diagram showing a structural example of a polycrystalline silicon thin film transistor included in the shift register circuit of the eighth embodiment.

The polycrystalline silicon thin film transistor shown in FIG. 16 has an insulating substrate 31, a silicon oxide film 32, a metal wiring 33, a source region 34, a drain region 35, a silicon thin film 36, a silicon oxide film 37, a gate electrode 38, and a silicon oxide film. A membrane 39 is provided.

The polycrystalline silicon thin film transistor shown in FIG. 16 has a forward stagger (top gate) structure using a polycrystalline silicon thin film on an insulating substrate as an active layer.
The present embodiment is not limited to this, and may have another structure such as an inverted stagger structure.

By using the polycrystalline silicon thin film transistor shown in FIG. 16, a scanning signal line driving circuit and a data signal line driving circuit having practical driving capabilities are formed on the same substrate as the pixel array in almost the same manufacturing steps. can do.

Further, since the polycrystalline silicon thin film transistor has a driving ability smaller by one or two digits than that of a single crystal silicon transistor (MOS transistor), the size of the transistor constituting the shift register circuit is increased. Required, and as a result, the input load capacity tends to increase. Therefore, the effect of reducing the load capacitance of the clock signal line by locally inputting the clock signal is also increased.

A manufacturing process for forming a polycrystalline silicon thin film transistor included in the shift register circuit according to the eighth embodiment will be briefly described below with reference to FIG.

FIG. 17A shows a glass substrate.

FIG. 17B shows an amorphous silicon thin film deposited on the glass substrate shown in FIG. 17A.

FIG. 17C shows a polycrystalline silicon thin film formed by irradiating the amorphous silicon thin film shown in FIG. 17B with an excimer laser.

FIG. 17D is a view showing a substrate in which the polycrystalline silicon thin film shown in FIG. 17C is patterned into a desired shape.

FIG. 17E shows a substrate in which a gate insulating film made of silicon dioxide is formed on the substrate shown in FIG. 17D.

FIG. 17F shows a substrate in which the gate electrode of the thin film transistor is formed of aluminum or the like on the substrate shown in FIG. 17E.

FIGS. 17G and 17H show the impurity (n)
FIG. 3 is a diagram showing a substrate in which phosphorus (a boron is implanted into a p-type region and boron is implanted into a p-type region) and a source region and a drain region of a thin film transistor are formed.

FIG. 17I shows a substrate in which an interlayer insulating film made of silicon dioxide or silicon nitride is deposited on the substrate shown in FIG. 17H.

FIG. 17 (j) is a diagram showing a state where a contact hole is opened in the interlayer insulating film shown in FIG. 17 (i).

FIG. 17 (k) is a view showing a state in which a metal wiring such as aluminum is formed in the contact hole shown in FIG. 17 (j).

The substrate shown in FIG.
17 (j) to obtain a polycrystalline silicon thin film transistor shown in FIG. 17 (k).

Since the maximum temperature of the process shown in FIGS. 17A to 17K is 600 ° C. during the formation of the gate insulating film, a high heat-resistant glass such as 1737 glass manufactured by Corning Incorporated in the United States can be used.

In the liquid crystal display device, a transparent electrode (in the case of a transmissive liquid crystal display device) and a reflective electrode (in the case of a reflective liquid crystal display device) are further formed via another interlayer insulating film. .

Here, in the manufacturing process as shown in FIG.
By forming a polycrystalline silicon thin film transistor at a temperature of 600 degrees Celsius or less, a low-cost and large-area glass substrate can be used, so that the cost and the area of the image display device can be reduced.

Although some embodiments of the present invention have been described, the present invention is not limited to these embodiments, and the same applies to other configurations such as combinations of the above embodiments.

The shift register circuit of the present invention is used in various fields, but here, an example applied to an image display device, especially a liquid crystal display device has been described. However, the present invention is not limited to this, and can be used in other fields for the same purpose.

[0145]

The shift register circuit according to the present invention comprises a plurality of latch circuits connected in series and sequentially transferring a pulse signal, a clock line transmitting a clock signal, the clock line and the plurality of latch circuits. A plurality of switch circuits that are electrically connected or disconnected. When power is applied to the shift register circuit, at least one of the plurality of switch circuits electrically disconnects at least one of the plurality of latch circuits from a clock line.

For this reason, the shift register circuit of the present invention has a smaller effective load capacity of the clock signal line than the conventional shift register circuit. Since an external IC for supplying a clock signal does not require a particularly large driving capability,
The cost and power consumption of the external IC can be reduced.

Another shift register circuit according to the present invention includes a plurality of latch circuits connected in series and sequentially transferring a pulse signal, a clock line transmitting a clock signal, and the clock line and the plurality of latch circuits. A plurality of switch circuits that are electrically connected or disconnected. At regular time intervals, at least one of the plurality of switch circuits is
At least one of the plurality of latch circuits is electrically disconnected from a clock line.

For this reason, the other shift register circuit of the present invention has a smaller effective load capacity of the clock signal line than the conventional shift register circuit. Since the external IC for supplying the clock signal does not require a particularly large driving capability, the cost and power consumption of the external IC can be reduced.

An image display device according to the present invention includes a plurality of pixels provided in a matrix, a data signal line for supplying video data to be written to one of the plurality of pixels, and a plurality of pixels of the video data. And a scanning signal line for controlling writing to one of the pixels. A data signal line driving circuit that outputs the video data to the data signal line in synchronization with a timing signal includes the shift register circuit or another shift register circuit.

Therefore, the image display device of the present invention has a smaller effective load capacity of the clock signal line than the conventional image display device. Since the external IC for supplying the clock signal does not require a particularly large driving capability, the cost and power consumption of the external IC can be reduced.

In another image display device of the present invention, at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed on the same substrate as the plurality of pixels.

For this reason, another image display device of the present invention
It can be manufactured at a lower cost than a conventional image display device. Further, other image display devices of the present invention consume less power than conventional image display devices.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a shift register circuit 1 according to a first embodiment.

FIG. 2 is a diagram illustrating an example of a clock signal CLK input to a shift register circuit and a clock signal CLKint inside the shift register circuit.

FIG. 3 is a diagram illustrating an example of a clock signal CLK input to a shift register circuit and a clock signal CLKint inside the shift register circuit when a clock signal supply IC having a large driving ability is used.

FIG. 4 is a diagram showing a clock signal CLK received by the shift register circuit 1;

FIG. 5 illustrates an initialization operation period and a normal operation period.
FIG. 3 is a diagram illustrating an example of a clock signal CLK and an example of a clock signal CLKint inside a shift register circuit.

FIG. 6 shows the frequency of the clock signal CLK when the power is turned on.
FIG. 4 is a diagram showing a clock signal lower than the frequency of the clock signal CLK at the end of the initialization period.

FIG. 7 is a diagram showing another clock signal for driving the shift register circuit 1;

FIG. 8 shows a latch circuit LATA of the shift register circuit 1,
It is a figure showing other examples of composition of LATB.

FIG. 9 illustrates a latch circuit LATA of the shift register circuit 1,
It is a figure showing other examples of composition of LATB.

FIG. 10 is a diagram showing signals of a clock signal CLK and a reset signal RST when the latch circuits shown in FIGS. 8 and 9 are used.

11 is a diagram showing signals of a clock signal CLK and a reset signal RST when the latch circuits shown in FIGS. 8 and 9 are used.

FIG. 12 shows a latch circuit LAT of the shift register circuit 1.
FIG. 11 is a diagram illustrating still another example of the configuration of A and LATB.

FIG. 13 shows a latch circuit LAT of the shift register circuit 1.
FIG. 11 is a diagram illustrating still another example of the configuration of A and LATB.

FIG. 14 is a diagram illustrating a shift register circuit 10 according to a fifth embodiment.
FIG.

FIG. 15 shows a shift register circuit 20 according to the sixth embodiment.
FIG.

FIG. 16 is a diagram illustrating a structural example of a polycrystalline silicon thin film transistor included in a shift register circuit according to an eighth embodiment.

17A is a view showing a glass substrate, and FIG.
FIG. 3A is a diagram showing an amorphous silicon thin film deposited on a glass substrate shown in FIG. 3A, and FIG. 3C is a diagram showing a polycrystalline film formed by irradiating the amorphous silicon thin film shown in FIG. It is a figure which shows a silicon thin film, (d) is a figure which shows the board | substrate in which the polycrystalline silicon thin film shown in (c) was patterned into a desired shape, (e) is a figure which shows a carbon dioxide It is a figure which shows the board | substrate which formed the gate insulating film which consists of silicon, (f) is a figure which shows the board | substrate which formed the gate electrode of the thin film transistor from aluminum etc. on the board | substrate shown in (e), (H) is an impurity (n)
FIG. 3 is a view showing a substrate in which phosphorus is implanted into a mold region and boron is implanted into a p-type region, and a source region and a drain region of a thin film transistor are formed. FIG. It is a figure which shows the board | substrate on which the interlayer insulation film which consists of silicon nitride etc. was deposited, (j) is a figure which shows the state in which the contact hole was opened in the interlayer insulation film shown in (i), (k) is ( FIG. 11 is a diagram showing a state in which metal wiring such as aluminum is formed in the contact hole shown in j).

FIG. 18 is a diagram showing an active matrix drive type liquid crystal display device 100.

FIG. 19 is a diagram showing details of a pixel PIX shown in FIG. 18;

FIG. 20 shows an active matrix type liquid crystal display device 20
FIG.

FIG. 21 is a data signal line driving circuit SD of a dot sequential driving method.
FIG.

FIG. 22 is a diagram illustrating a scanning signal line driving circuit GD of a dot sequential driving method.

FIG. 23 is a diagram illustrating a shift register circuit SFC.

24 is a diagram illustrating a clock signal CLK input to the shift register circuit SFC illustrated in FIG.

FIG. 25 is a diagram showing a latch circuit LATA forming the shift register circuit SFC.

FIG. 26 is a diagram illustrating a latch circuit LATB included in the shift register circuit SFC.

FIG. 27 is a diagram showing a clocked inverter CICA.

FIG. 28 is a diagram showing a clocked inverter CICB.

[Explanation of symbols]

 1, 10, 20 shift register circuit 2 units LATA, LATB latch circuit ST start signal OR OR circuit ASW, AS analog switch (transfer gate) CLK, / CLK clock signal VCC power supply voltage PLS pulse signal RST reset signal IN, / IN Input signal OUT, / OUT Output signal SCK, GCK Clock signal SSP, GSP Start signal GPS pulse signal DAT Video signal SL Data signal line GL Scan signal line SD Data signal line drive circuit GD Scan signal line drive circuit ARY Pixel array PIX Pixel CL Liquid crystal capacitance CS Auxiliary capacitance SW Pixel switch (transistor) CTL Timing signal generation circuit VSH, VGH Power supply terminal VSL, VGL Ground terminal COM Common electrode terminal VGEN Power supply voltage generation circuit SUB Insulation Board CLKint Internal clock signal CLKext External clock signal INV Inverter circuit (inverting circuit) LS Level shifter circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Shigeto Yoshida 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 2H093 NA16 NA42 NC22 NC26 NC34 ND39 ND54 NE07 5C006 AC09 AF67 BB15 BB16 BC03 BC13 BC20 BF03 BF04 BF11 BF26 BF46 FA47 FA52 5C080 AA10 BB05 DD24 DD26 DD27 FF11 JJ02 JJ03 JJ04 JJ06

Claims (15)

[Claims] A plurality of latch circuits connected in series and sequentially transferring a pulse signal; a clock line transmitting a clock signal; and electrically connecting or disconnecting the clock line and the plurality of latch circuits. A shift register circuit comprising: a plurality of switch circuits, wherein when power is supplied to the shift register circuit, at least one of the plurality of switch circuits includes at least one of the plurality of latch circuits, a clock line, Shift register circuit that electrically disconnects. 2. A plurality of latch circuits connected in series and sequentially transferring a pulse signal; a clock line transmitting a clock signal; and electrically connecting or disconnecting the clock line and the plurality of latch circuits. A shift register circuit comprising: a plurality of switch circuits, wherein at least one of the plurality of switch circuits
One is a shift register circuit that electrically disconnects at least one of the plurality of latch circuits from a clock line. 3. The potential of a node of the plurality of latch circuits changes in response to the transmitted pulse signal, and each of the plurality of switch circuits responds to a potential of a corresponding node of the latch circuit. Electrically connecting or disconnecting a corresponding latch circuit and a clock line, at least a part of a period during which the pulse signal is transferred from a first latch circuit to a last latch circuit of the plurality of latch circuits, 3. The shift register circuit according to claim 1, wherein a frequency of the clock signal is lower than a frequency of the clock signal in a normal period. 4. The shift register circuit according to claim 3, wherein the frequency of the clock signal in the at least one part of the period gradually increases. 5. The shift register circuit according to claim 3, wherein a frequency of the clock signal in the at least a part of the period is 1/2 to 1/16 of the clock signal in the normal period. 6. The latch circuit according to claim 1, wherein each of the plurality of latch circuits has an initialization circuit that receives an initialization signal from the outside and initializes an internal node according to the initialization signal.
Or the shift register circuit according to 2. 7. The amplitude of the clock signal is smaller than the amplitude of a power supply voltage of the shift register circuit.
Or the shift register circuit according to 2. 8. The shift register circuit according to claim 1, wherein the shift register circuit has a buffer circuit that supplies a clock signal received from outside to the plurality of latch circuits. 9. An amplitude of a clock signal received from the outside by the shift register circuit is different from an amplitude of a clock signal supplied to the plurality of latch circuits, and the amplitude of the clock signal received by the shift register circuit is different. 2. A level shift circuit for changing the threshold voltage.
Or the shift register circuit according to 2. 10. A plurality of pixels provided in a matrix, a data signal line for supplying video data to be written to one of the plurality of pixels, and a video signal to one of the plurality of pixels. A scanning signal line driving circuit that outputs a pulse signal to the scanning signal line in synchronization with a timing signal, wherein the scanning signal line driving circuit outputs a pulse signal to the scanning signal line in synchronization with a timing signal. 9. An image display device comprising the shift register circuit according to any one of 9. 11. A plurality of pixels provided in a matrix, a data signal line for supplying video data to be written to one of the plurality of pixels, and one of the plurality of pixels of the video data A scanning signal line for controlling writing of data, wherein the data signal line driving circuit outputs the video data to the data signal line in synchronization with a timing signal. ~
9. An image display device comprising the shift register circuit according to any one of 9. 12. The data signal line drive circuit according to claim 11, wherein said data signal line drive circuit initializes a potential level of an internal node of each of said plurality of latch circuits of said shift register circuit in synchronization with a vertical synchronization signal. Image display device. 13. The device according to claim 10, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed on the same substrate as the plurality of pixels.
2. The image display device according to 1. 14. The image display device according to claim 13, wherein at least the active element of the data signal line drive circuit is a polycrystalline silicon thin film transistor. 15. The method according to claim 15, wherein the active element is formed on a glass substrate.
The image display device according to claim 14, wherein the image display device is formed by a process at a temperature of 00 ° C. or lower.