JP2000307415A - Logic circuit and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make low power consumption compatible with realization of a low voltage interface without causing any defect on the standpoint of display by adopting a smaller level for amplitude of part of input signals than a voltage of a drive power supply of a CMOS logic circuit and incorporating a voltage booster function to the logic circuit. SOLUTION: The power supply voltage is 15 V and amplitude of an input signal IN2 and the input signal /IN2 are also 15 V, while the amplitude of an input signal IN1 and the input signal /IN1 are 5 V. Furthermore, since a gate electrode of a P-channel transistor(TR) M1 is connected to a drain electrode of a P-channel TR M2 and the gate electrode of the P-channel TR M2 is connected to the drain electrode of the P-channel TR M1, the TRs M1, M2 configure a latch circuit. On the other hand, the input signal IN1 and /IN1, and IN2 and /IN2 are respectively given to circuit parts CIR1, CIR2 consisting of n-channel TR. The configuration of the CIR1, CIR2 is similar to the configuration of a conventional CMOS logic circuit. Thus, no current flows every time the level of the input signal is switched but the current flows only when the output signal is inverted, resulting in reducing the current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit for performing a logical operation on an input signal, and in particular, can perform a normal logical operation even on an input signal whose amplitude is smaller than a power supply voltage of the circuit. It relates to a logic circuit.

[0002]

2. Description of the Related Art An active matrix drive type liquid crystal display device is known as one of image display devices. Conventionally, this liquid crystal display device has a pixel array, a scanning signal line driving circuit GD, and a data signal line driving circuit S as shown in FIG.
D. The pixel array includes a large number of scanning signal lines GL and a large number of data signal lines SL that intersect with each other, and a pixel PIX is provided in a portion surrounded by two adjacent scanning signal lines GL and two adjacent data signal lines SL. Are provided in a matrix.

[0003] The data signal line drive circuit SD functions to sample the input video signal DAT in synchronization with a timing signal such as a clock signal CKS, amplify it if necessary, and write it to each data signal line SL. The scanning signal line driving circuit GD sequentially selects the scanning signal lines GL in synchronization with a timing signal such as a clock signal CKG, and controls the opening and closing of the switching element in the pixel PIX to write the data to each data signal line SL. The video signal is written to each pixel PIX, and also functions to hold the data written to each pixel PIX.

As shown in FIG. 24, each pixel PIX in FIG. 23 is composed of a field effect transistor SW as a switching element and a pixel capacitor (consisting of a liquid crystal capacitor CL and an auxiliary capacitor CS added as necessary).
In FIG. 24, a transistor S which is a switching element
The data signal line SL and one electrode of the pixel capacitance are connected via the drain and source of W, the gate of the transistor SW is connected to the scanning signal line GL, and the other electrode of the pixel capacitance is shared by all the pixels. It is connected to the electrode wire. Then, the transmittance or reflectance of the liquid crystal is modulated by the voltage applied to each liquid crystal capacitor CL, and the modulated liquid crystal is used for display.

Next, a method of writing a video signal to a data signal line will be described. As a driving method of the data signal line, there are a dot sequential driving method and a line sequential driving method. Here, only the dot sequential driving method will be described.

FIG. 39 shows an example of a data signal line driving circuit. In the point-sequential driving method, as shown in FIG. 39, the video signal input to the video signal line DAT is written to the data signal line SL by opening and closing the sampling circuit AS in synchronization with the output pulse of each stage of the shift register.

More specifically, an overlap signal of the output signals N of two adjacent latch circuits SR is amplified by a buffer circuit including a plurality of inverter circuits, and an inverted signal is generated as necessary. To be sampling signals S and / S. The sampling circuit (analog switch) AW is opened and closed using the sampling signal to supply video data from the video signal line DAT to the data signal line SL.

FIG. 40 shows an example of a scanning signal line driving circuit.
As shown in FIG. 40, an output signal of an adjacent latch circuit SR is overlapped by a NAND circuit, and a desired pulse width is obtained by overlapping this with an external pulse width control signal GPS.

In recent years, in order to reduce the size, increase the resolution, and reduce the mounting cost of a liquid crystal display device, a pixel array for controlling display and a drive circuit for driving the pixel array are integrally formed on the same substrate. Technology is attracting attention. In such a liquid crystal display device integrated with a driving circuit, a transparent substrate needs to be used as a substrate when a transmission type liquid crystal display device that is currently most widely used is configured. Therefore, a pixel array and a driving circuit are required. In many cases, a polycrystalline silicon thin film transistor that can be formed on a quartz substrate or a glass substrate is used as an active element to be formed.

[0010]

In the above-described conventional image display device, as shown in FIGS. 39 and 40, a power supply of a driving circuit such as clock signals CKS and CKG, start signals SPS and SPG is supplied to a shift register circuit. A signal having the same amplitude as the voltage was directly input from the outside.

By the way, the polycrystalline silicon thin film transistor used in the above-mentioned liquid crystal display device integrated with a driving circuit has inferior transistor characteristics as compared with a single crystal silicon transistor. In particular, at present, the absolute value of the threshold voltage is as high as 1 to 6 V, and therefore the driving power supply voltage has to be increased to 10 to 20 V at present.

At this time, it is necessary to simultaneously increase the amplitude of a clock signal or the like input from the outside. In this case, the power consumption of an external circuit (a control circuit for generating a clock signal or the like) is greatly increased. In addition to the above, the influence of the unnecessary radiation from the signal line becomes large.

To solve this problem, it has been conventionally proposed to mount a signal booster circuit (level shifter) on the drive circuit side of the liquid crystal display device to reduce the voltage of the input / output interface. FIG. 41 shows a configuration example of a scanning signal line driving circuit for realizing a low-voltage interface. 41, a clock signal CLK, start signals SPS and SPG, and a pulse signal G input from outside
PS has a smaller amplitude than the drive circuit. These signals are
First, the voltage is input to a level shifter circuit (boost circuit) LS and boosted to the power supply voltage of the drive circuit, and then supplied to the drive circuit. Note that a similar configuration is also possible on the data signal line drive circuit side. 42 and 43 show configuration examples of a conventional level shifter circuit LS, which are generally used in LSI. In an actual liquid crystal display device, an external signal line (GPS or the like) extends in the longitudinal direction of the drive circuit region, so that the load due to the signal line is extremely large. Therefore, in order to drive a signal line with a large load at a high frequency, it is necessary to provide a large buffer circuit after the level shifter circuit, thereby significantly increasing power consumption and reducing the reliability of the drive circuit. .

The present invention has been made to solve such a problem of the prior art. By incorporating a boosting function, a low-voltage interface and low power consumption can be achieved without causing display problems. Logical operation circuit,
Another object of the present invention is to provide an image display device having low power consumption and high display quality by using the same.

[0015]

According to a first aspect of the present invention, there is provided a CMOS circuit for performing a logical operation based on a plurality of input signals. At least partially has an amplitude C
It is characterized in that it is smaller than the driving power supply of the MOS logic circuit.

A logic circuit according to a second aspect of the present invention is the logic circuit according to the first aspect, wherein each of the two current paths includes a circuit portion formed of an n-channel transistor and a p-channel transistor. A circuit portion is provided, and in one of the channel portions composed of channel type transistors, a circuit portion composed of an n-channel type transistor of a CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit is provided in one current path. A circuit having the same configuration as that of the circuit portion including the p-channel transistor of the CMOS logic circuit that outputs the same logical operation result as the logic circuit is provided on the other current path. In the circuit portion composed of the other channel-type transistor, the transistors provided in the two current paths are respectively provided. The gate electrode of Njisuta has been characterized by being connected to each other with the drain electrode of one another.

According to a third aspect of the present invention, there is provided the logic circuit according to the first aspect, wherein the logic circuit includes a circuit portion including an n-channel transistor and a p-channel transistor in each of two current paths. A circuit portion composed of a transistor is provided. In one of the circuit portions composed of the channel-type transistors, one of the current paths has a C that outputs a logical operation result similar to that of the logic circuit.
A circuit having the same configuration as that of the circuit portion including the n-channel transistor of the MOS logic circuit is provided, and the other current path is a CM that outputs the same logical operation result as the logic circuit.
A circuit having the same configuration as the circuit portion including the p-channel transistor of the OS logic circuit is provided. In the circuit portion including the other channel type transistor of the logic circuit, at least one of the input signals is provided in each of the two current paths. A transistor whose section is input to the gate electrode is provided, and on each power supply side of the two current paths,
A transistor is provided in which gate electrodes are connected to the output portions of the other current paths.

According to a fourth aspect of the present invention, there is provided the logic circuit according to the first aspect, wherein each of the two current paths includes a circuit portion including an n-channel transistor and a p-channel transistor. A circuit portion composed of a transistor is provided. In one of the circuit portions composed of the channel-type transistors, one of the current paths has a C that outputs a logical operation result similar to that of the logic circuit.
A circuit having the same configuration as that of the circuit portion including the n-channel transistor of the MOS logic circuit is provided, and the other current path is a CM that outputs the same logical operation result as the logic circuit.
A circuit having the same configuration as the circuit portion including the p-channel transistor of the OS logic circuit is provided. In the circuit portion including the other channel type transistor of the logic circuit, the same logical operation result as that of the logic circuit is supplied to one current path. A circuit having the same configuration as a circuit portion including a p-channel transistor of a CMOS logic circuit for outputting is provided, and a transistor on which at least a part of an input signal is input to a gate electrode is provided on the other current path. N of a CMOS logic circuit that outputs the same logical operation result as the circuit
A circuit having the same configuration as the circuit portion including the channel-type transistor is provided, and a transistor whose gate electrode is connected to the output of the other current path is provided on each power supply side of the two current paths. It is characterized by:

According to a fifth aspect of the present invention, there is provided a logic circuit according to the first to fourth aspects, wherein a signal having a smaller amplitude among the plurality of input signals is one channel type. In the circuit portion, the signal is input to the power supply side of the transistors connected in series.

A logic circuit according to a sixth aspect of the present invention is the logic circuit according to any one of the first to fifth aspects, wherein each of the source electrodes is connected to the first electrode potential, and the other is a gate. A first transistor and a second transistor each having an electrode connected to a corresponding drain electrode and connected to a first output terminal and a second output terminal, respectively;
A third transistor having a gate electrode connected to the first input terminal and a drain electrode connected to the second output terminal;
A fourth transistor having a gate electrode connected to the second input terminal, a drain electrode connected to the source electrode of the third transistor, and a source electrode connected to the second power supply potential; A fifth transistor connected to the input terminal, a drain electrode connected to the first output terminal, a source electrode connected to the second power supply potential, a gate electrode connected to the fourth input terminal, and a drain electrode Is connected to the first output terminal, and a sixth transistor whose source electrode is connected to the second power supply potential. The signals input to the first input terminal and the third input terminal are The signals input to the second input terminal and the fourth input terminal have opposite phases, and the first transistor and the second transistor have different channel types from the other transistors. It is characterized by a transistor.

According to a seventh aspect of the present invention, in the logic circuit according to any one of the first to fifth aspects, the respective source electrodes are connected to the first electrode potential, and the respective gates are connected. A first transistor and a second transistor each having an electrode connected to a corresponding drain electrode and connected to a first output terminal and a second output terminal, respectively;
A third transistor having a gate electrode connected to the first input terminal and a drain electrode connected to the second output terminal;
A fourth transistor having a gate electrode connected to the second input terminal, a drain electrode connected to the source electrode of the third transistor, and a source electrode connected to the second power supply potential; A fifth transistor connected to the input terminal, the drain electrode connected to the second output terminal, the source electrode connected to the second power supply potential, the gate electrode connected to the fourth input terminal, and the source electrode Are connected to a second power supply potential, a seventh transistor whose gate electrode is connected to a fifth input terminal, the source electrode is connected to the second power supply potential, and the gate electrode is An eighth transistor connected to an input terminal of the sixth transistor, a drain electrode connected to the first output terminal, and a source electrode connected to drain electrodes of the sixth transistor and the seventh transistor; Comprising, a signal input to the first input terminal and a fourth input terminal is the inverse phase to each other, the second
The signals input to the third input terminal and the fifth input terminal are opposite in phase to each other, and the signals input to the third input terminal and the sixth input terminal are opposite in phase to each other. And the second transistor is a channel-type transistor which is different from the other transistors.

The logic circuit according to claim 8 of the present invention is the logic circuit according to any one of claims 1 to 5, wherein each of the source electrodes is connected to the first electrode potential and each of the gates is connected to each other. A first transistor and a second transistor each having an electrode connected to a corresponding drain electrode and connected to a first output terminal and a second output terminal, respectively;
A third transistor having a gate electrode connected to the first input terminal and a drain electrode connected to the second output terminal;
A fourth transistor having a gate electrode connected to the second input terminal, a drain electrode connected to the source electrode of the third transistor, and a source electrode connected to the second power supply potential; A fifth transistor connected to the input terminal, the drain electrode connected to the second output terminal, the source electrode connected to the second power supply potential, and the gate electrode connected to the fourth input terminal; Are connected to the first output terminal, a seventh transistor whose gate electrode is connected to the fifth input terminal, the drain electrode is connected to the first output terminal, and the gate electrode is The sixth input terminal is connected to the input terminal of the sixth transistor, the drain electrode is connected to the source electrodes of the sixth transistor and the seventh transistor, and the source electrode is connected to the second power supply potential.
Wherein the signals input to the first input terminal and the fourth input terminal have opposite phases, and the signals input to the second input terminal and the fifth input terminal are:
The signals input to the third input terminal and the sixth input terminal have opposite phases to each other, and the first transistor and the second transistor have different channel types from the other transistors. It is a transistor.

A logic circuit according to a ninth aspect of the present invention is the logic circuit according to any one of the first to fifth aspects, wherein the source electrodes are connected to the first electrode potential, and the gate electrodes are connected to the first electrode potential. A first transistor and a second transistor connected to the first output terminal and the second output terminal, respectively, a gate electrode is connected to the first input terminal, and a source electrode is connected to a drain electrode of the first transistor. Connected
A third transistor having a drain electrode connected to the second output terminal, a gate electrode connected to the second input terminal,
A fourth electrode having a source electrode connected to the drain electrode of the second transistor and a drain electrode connected to the first output terminal;
And a fifth transistor having a gate electrode connected to the third input terminal and a drain electrode connected to the second output terminal.
A sixth transistor whose gate electrode is connected to the first input terminal, whose source electrode is connected to the second power supply potential, and whose drain electrode is connected to the source electrode of the fifth transistor; Is connected to the fourth input terminal, a seventh transistor whose source electrode is connected to the second power supply potential, and whose drain electrode is connected to the first output terminal, and whose gate electrode is connected to the second input terminal A seventh transistor having a drain electrode connected to the first output terminal, a gate electrode connected to the second input terminal, a source electrode connected to the second power supply potential,
An eighth transistor having a drain electrode connected to the first output terminal, wherein signals input to the first input terminal and the second input terminal are in opposite phases to each other, and the third input terminal And the signals input to the fourth input terminal are opposite in phase to each other, and the first to fourth transistors are channel-type transistors different from the other transistors.

A logic circuit according to a tenth aspect of the present invention is the logic circuit according to any one of the first to fifth aspects, wherein the respective source electrodes are connected to the first electrode potential, and the gate electrode is connected to the first electrode potential. A first transistor and a second transistor connected to the first output terminal and the second output terminal, respectively, a gate electrode is connected to the first input terminal, and a source electrode is connected to a drain electrode of the first transistor. Connected
A third transistor having a drain electrode connected to the second output terminal, a gate electrode connected to the second input terminal,
A fourth transistor having a source electrode connected to the drain electrode of the first transistor and a drain electrode connected to the second output terminal;
And a fifth transistor having a gate electrode connected to the third input terminal and a source electrode connected to the drain electrode of the second transistor, and a fourth transistor having a gate electrode connected to the fourth input terminal.
A sixth transistor whose source electrode is connected to the drain electrode of the fifth transistor, whose drain electrode is connected to the first output terminal, and whose gate electrode is connected to the fifth input terminal. A seventh transistor having a drain electrode connected to the second output terminal, a gate electrode connected to the second input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the seventh transistor. An eighth transistor connected to the source electrode of the first transistor, a gate electrode connected to the sixth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the first output terminal. And a tenth transistor having a gate electrode connected to the fourth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the first output terminal. And the signals input to the first input terminal and the third input terminal have opposite phases, and the signals input to the second input terminal and the fourth input terminal have opposite phases. And the first to sixth transistors are channel-type transistors different from the other transistors.

In the logic circuit according to claim 11 of the present invention, in the logic circuit according to any one of claims 1 to 5, each of the source electrodes is connected to the first electrode potential, and the gate electrode is connected to the other. A first transistor and a second transistor connected to the first output terminal and the second output terminal, respectively, a gate electrode is connected to the first input terminal, and a source electrode is connected to a drain electrode of the first transistor. Connected
A third transistor having a drain electrode connected to the second output terminal, a gate electrode connected to the second input terminal,
A fourth electrode having a source electrode connected to the drain electrode of the second transistor and a drain electrode connected to the first output terminal;
And a fifth transistor having a gate electrode connected to the third input terminal and a drain electrode connected to the second output terminal.
A sixth transistor whose gate electrode is connected to the first input terminal, whose source electrode is connected to the second power supply potential, and whose drain electrode is connected to the source electrode of the fifth transistor; Is connected to the fourth input terminal, a seventh transistor whose source electrode is connected to the second power supply potential, and whose drain electrode is connected to the second output terminal, and whose gate electrode is connected to the fifth input terminal. An eighth transistor having a drain electrode connected to the first output terminal, a gate electrode connected to the second input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the eighth output terminal. A ninth transistor connected to the source electrode of the transistor, a gate electrode connected to the sixth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the eighth transistor; And a tenth transistor connected to the source electrode of the star, the signals input to the first input terminal and the second input terminal are in opposite phases to each other, and the third input terminal and the sixth input terminal The signals input to the input terminals have opposite phases, the signals input to the fourth input terminal and the fifth input terminal have opposite phases, and the first to fourth transistors have other phases. It is a channel-type transistor which is different from a transistor.

According to a twelfth aspect of the present invention, in the logic circuit according to any one of the first to fifth aspects, each of the source electrodes is connected to the first electrode potential, and the other is connected to the gate electrode. A first transistor and a second transistor connected to the first output terminal and the second output terminal, respectively, a gate electrode is connected to the first input terminal, and a source electrode is connected to a drain electrode of the first transistor. A third transistor connected, a fourth electrode having a gate electrode connected to the second input terminal, a source electrode connected to the drain electrode of the third transistor, and a drain electrode connected to the second output terminal; A fifth transistor in which the transistor and the gate electrode are connected to the third input terminal, the source electrode is connected to the drain electrode of the third transistor, and the drain electrode is connected to the second output terminal And a transistor, a gate electrode 4
A sixth transistor having a source electrode connected to the drain electrode of the second transistor, a drain electrode connected to the first output terminal, and a gate electrode connected to the fifth input terminal. A seventh transistor having a source electrode connected to the drain electrode of the second transistor, a gate electrode connected to the sixth input terminal, a source electrode connected to the drain electrode of the seventh transistor,
An eighth transistor having a drain electrode connected to the first output terminal, a gate electrode connected to the seventh input terminal,
A ninth transistor having a drain electrode connected to the second output terminal, a gate electrode connected to the eighth input terminal,
The source electrode is connected to the second power supply potential, and the drain electrode is connected to the source electrode of the ninth transistor.
And an eleventh transistor having a gate electrode connected to the ninth input terminal, a source electrode connected to the second power supply potential, a drain electrode connected to the second output terminal, and a gate electrode connected to the ninth input terminal. A twelfth transistor having a drain electrode connected to the first output terminal, a gate electrode connected to the eleventh input terminal, a source electrode connected to the second power supply potential, A thirteenth transistor having a drain electrode connected to the source electrode of the twelfth transistor, a gate electrode connected to the twelfth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the twelfth transistor; And a fourteenth transistor connected to the source electrode of the transistor, wherein the signals input to the first input terminal and the fourth input terminal have opposite phases to each other, and The signals input to the input terminal and the sixth input terminal have phases opposite to each other, and the signals input to the third input terminal and the fifth input terminal have phases opposite to each other. Is characterized by being a channel transistor different from other transistors.

A logic circuit according to a thirteenth aspect of the present invention is the logic circuit according to any one of the first to twelfth aspects, wherein at least a part of the input signal is transferred for controlling the input of the signal. It is characterized in that it is inputted through a transistor for use.

A logic circuit according to a fourteenth aspect of the present invention is the logic circuit according to any one of the first to thirteenth aspects, wherein the gate electrode of the transistor whose signal input is controlled by the transfer transistor is connected to one of the gate electrodes. Between the power supply potential
A malfunction preventing transistor is connected, and a gate electrode of the malfunction preventing transistor is connected to a power supply potential different from a power supply potential.

A logic circuit according to a fifteenth aspect of the present invention is the logic circuit according to any one of the first to thirteenth aspects, wherein the gate electrode of the transistor whose signal input is controlled by the transfer transistor is connected to one of the gate electrodes. Between the power supply potential
A malfunction preventing transistor is connected, and a signal having a phase opposite to that of the transfer transistor is input to a gate electrode of the malfunction preventing transistor.

A logic circuit according to a sixteenth aspect of the present invention is the logic circuit according to any one of the first to fifteenth aspects, wherein one of the input signals is input to the gate electrode of the transfer transistor. It is characterized by that.

The image display device according to the seventeenth aspect of the present invention is arranged in a matrix by being surrounded by a plurality of data signal lines arranged in a column direction and a plurality of scanning signal lines arranged in a row direction. A plurality of pixels, a data signal line driving circuit for supplying video data to the data signal line, and a scanning signal line driving circuit for supplying a scanning signal to the scanning signal line; At least one of the scanning signal line driving circuits includes the logic circuit according to any one of claims 1 to 16.

The image display device according to claim 18 of the present invention is the image display device according to claim 17,
A logic circuit for receiving an output pulse of a shift register circuit constituting a data signal line driving circuit and a pulse width control signal input from the outside as an input signal, and generating an output signal having a pulse width smaller than the output pulse. It is a logic circuit according to any one of 1 to 16.

The image display device according to claim 19 of the present invention is the image display device according to claim 17,
A logic circuit for generating, as input signals, an output pulse of a shift register circuit constituting a scanning signal line driving circuit and a pulse width control signal input from the outside, and generating an output signal having a pulse width smaller than the output pulse. It is a logic circuit according to any one of 1 to 16.

According to a twentieth aspect of the present invention, there is provided an image display apparatus comprising:
An output pulse of a shift register circuit included in a scanning signal line driver circuit and one of a plurality of externally input control signals are used as input signals, and signals are simultaneously output to different combinations of shift register circuits. At least a part of the logic circuit for the above is a logic circuit according to any one of claims 1 to 15.

According to a twenty-first aspect of the present invention, in the image display device according to any one of the eighteenth to twentieth aspects, a logic constituting a data signal line driving circuit and a scanning signal line driving circuit is provided. The circuit is a logic circuit in which an output signal of the shift register is input to a gate electrode of a transfer transistor.

The image display device according to claim 22 of the present invention is the image display device according to any one of claims 17 to 21, wherein at least one of the data signal line drive circuit and the scanning signal line drive circuit is provided. , On the same substrate as the pixels.

The image display device according to a twenty-third aspect of the present invention is the image display device according to the twenty-second aspect,
The data signal line driving circuit, the scanning signal line driving circuit, and the active element forming the pixel are polycrystalline silicon thin film transistors.

The image display device according to a twenty-fourth aspect of the present invention is the image display device according to the twenty-third aspect,
The active element is formed by a process at about 600 ° C. or less.

The present invention has been made in view of the above-mentioned problems of the prior art, and provides a logic circuit capable of reducing power consumption of a driving circuit and an image display device using the same.

According to the logic circuit of the present invention, there is provided a CMOS logic circuit which performs a logical operation based on a plurality of input signals, wherein at least a part of the input signals has an amplitude of
It is made smaller than the driving power supply of the logic circuit. As a result, the amplitude of the input signal can be reduced even when it is necessary to increase the output amplitude of the logic circuit or when the logic circuit does not operate properly unless the drive voltage is increased to a certain degree or more. The load on an external circuit for generating a signal is reduced, and power consumption can be reduced. Further, according to the logic circuit of the present invention, a circuit is provided in each of the two current paths, the circuit being composed of any one of a circuit part composed of an n-channel transistor and a circuit part composed of a p-channel transistor. In one part, one of the current paths includes n of a CMOS logic circuit that outputs a similar logical operation result.
A circuit having the same configuration as the circuit portion including the channel type transistor is provided, and a circuit having the same configuration as the circuit portion including the p-channel type transistor of the CMOS logic circuit that outputs a similar logical operation result is provided on the other current path. In the circuit portion composed of the other channel type transistor, the gate electrodes of the transistors provided in the two current paths are connected to each other's drain electrodes. Thus, a logic operation circuit can be configured with a circuit portion including one channel transistor. In the circuit portion composed of the other channel-type transistor, the gate electrode and the drain electrode of the transistor are connected to each other to form a feedback loop, so that the through current can be suppressed and the internal state can be kept stable. it can.

Thus, it is possible to make the amplitude of the input signal smaller than the amplitude of the output pulse signal, that is, the power supply voltage of the logic circuit. Therefore, according to the logic circuit of the present invention, the current does not flow every time the level of the input signal is switched, and the current flows only when the output signal is inverted.
There is almost no increase in power consumption.

According to the logic circuit of the present invention, the number of transistors is slightly smaller than that of the conventional CMOS logic circuit.
The level shift function and the logical operation function can be made compatible with an extremely small number of elements.

Further, according to the logic circuit of the present invention, at any timing during operation, there is only one current path, and the internal delay operates with a delay corresponding to one stage of the logic gate. It can be operated at extremely high speed.

According to the logic circuit of the present invention, the signal having the smaller amplitude among the plurality of input signals is supplied to the power supply side of the serially connected transistors in one channel type circuit portion. Made to be input. Thus, a signal with a small amplitude is input to the transistor on the power supply potential side, so that the transistor operates sufficiently, so that a stable operation and a high-speed operation of the logic circuit can be realized. Among a plurality of transistors connected in series, the potential difference between the source electrode of each transistor and the power supply potential is lower in the transistor on the power supply potential side. Since the driving force of a transistor is determined by the potential difference between its gate electrode and source electrode, it is desirable to input a small-amplitude signal to the transistor on the power supply potential side.

According to the logic circuit of the present invention, in the above-described configuration of the logic circuit, the third and fourth transistors are arranged in series on one current path side in one channel type circuit portion, and 5th and 6th on the current path side of
Are arranged in parallel. And the third
And the signals input to the fifth and fifth transistors have opposite phases, and the signals input to the fourth and sixth transistors have opposite phases. As a result, in addition to the above-described effects, the number of transistors constituting the logic circuit is as small as six.
A logical NOT product circuit with a very small circuit scale can be configured. This logic circuit can also function as a logical NOR circuit by exchanging the input signal and the inverted input signal.

According to the logic circuit of the present invention, in the configuration of the logic circuit described above, the fifth transistor is connected in parallel to the third and fourth transistors arranged in series on one current path side. Provided in series with the fifth and sixth transistors arranged in parallel on the other current path side,
An eighth transistor is provided on the second output terminal side.
The signals input to the third and sixth transistors have opposite phases, the signals input to the fourth and seventh transistors have opposite phases, and the signals input to the fifth and eighth transistors have opposite phases. I made it. Thus, in addition to the above-described effects, the number of transistors constituting the logic circuit is as small as eight, so that a logical product-logical NOR circuit having a very small circuit scale can be configured. This logic circuit can also function as a logical sum-logical NOT product circuit by exchanging the input signal and the inverted input signal.

According to the logic circuit of the present invention, in the configuration of the logic circuit described above, the fifth transistor is connected in parallel to the third and fourth transistors arranged in series on one current path side. Provided in series with the fifth and sixth transistors arranged in parallel on the other current path side,
In addition, an eighth transistor is provided on the second power supply potential side.
The signals input to the third and sixth transistors have opposite phases, the signals input to the fourth and seventh transistors have opposite phases, and the signals input to the fifth and eighth transistors have opposite phases. I made it. Thus, in addition to the above-described effects, the number of transistors constituting the logic circuit is as small as eight, so that a logical product-logical NOR circuit having a very small circuit scale can be configured. This logic circuit can also function as a logical sum-logical NOT product circuit by exchanging the input signal and the inverted input signal.

Further, according to the logic circuit of the present invention, when the first power supply potential is on the high power supply side, a p-channel transistor for inputting an input signal or an inverted signal of the input signal to the gate electrode is added. By this, these p
When the channel type transistor operates such that the output node or the inverted output node is at a low level (ground potential),
Since it functions to limit the current from the power supply potential side, the operation margin can be increased.

According to the logic circuit of the present invention, at least a part of the input signal is input through the transfer transistor for controlling the input of the signal. This has the advantage that the capacitive load on the input signal line is reduced because the logic circuit is disconnected from the input signal line when no signal is needed. Therefore, the attenuation and waveform distortion of the input signal are reduced, the operation margin of the logic circuit is increased, and power consumption for driving the input signal line can be reduced.

According to the logic circuit of the present invention, the transistor is connected between the gate electrode of the transistor whose signal input is controlled by the transfer transistor and one power supply potential, and the gate electrode of the transistor is different. It was connected to the power supply potential. As a result, the signal input portion is always supplied with the power supply potential via this transistor, so that even when the signal input portion is electrically disconnected from the input signal line, it is possible to maintain a stable state without malfunction. In addition, there is an advantage that the capacitive load on the input signal line is reduced. However, at this time, the driving force of the transistor needs to be sufficiently smaller than that of the transfer transistor for transferring the input signal.

According to the logic circuit of the present invention, the transistor is connected between the gate electrode of the transistor whose signal input is controlled by the transfer transistor and one of the power supply potentials, and transferred to the gate electrode of the transistor. A signal having a phase opposite to that of the transistor for input is input. Accordingly, the signal input portion is electrically connected to the input signal line only during a period in which signal input is required and before and after the signal input portion, and is electrically disconnected from the input signal line in other periods. This makes it possible to maintain a stable state without performing the operation and to reduce the capacitive load on the input signal line. In this case, since the signal input unit is electrically connected to only one of the paths, the driving force of the transistor does not need to be sufficiently smaller than that of the transfer transistor that transfers the input signal.

Further, according to the logic circuit of the present invention, one of the input signals is input to the gate electrode of the transfer transistor and used as a control signal. Thus, the number of signal lines and terminals for control signals can be reduced.

Further, according to the image display device of the present invention, in the image display device, at least one of the scanning signal line driving circuit and the data signal line driving circuit for supplying a signal to the scanning signal line and the data signal line is provided with the above-mentioned signal. Any one of the logic circuits is provided. Thus, low power consumption of the image display device can be expected. That is, since the amplitude of the input signal can be made smaller than the driving voltage, the power consumption of the external circuit for signal generation can be reduced. In general, a large through current flows in a logic operation circuit when a signal is switched. However, according to the present invention, a through current flows only when an output signal is switched, not when an input signal is switched, so that power consumption is extremely small. can do.

According to the image display device of the present invention, the output pulse of the shift register circuit forming the data signal line drive circuit and the pulse width control signal input from the outside are used as input signals, and Any of the above-described logic circuits is used to generate an output signal with a small pulse width. Thus, low power consumption of the image display device can be expected. That is, since the amplitude of the input signal can be made smaller than the drive voltage, the power consumption of the external circuit for signal generation can be reduced. In general, a large through current flows in a logic operation circuit when a signal is switched. However, according to the present invention, a through current flows only when an output signal is switched, not when an input signal is switched, so that power consumption is extremely small. can do.
In addition, since an output signal having a pulse width smaller than that of the output signal of the shift register circuit is generated, a video signal is sampled on a data signal line based on the output signal.
It is expected that the sampling overlap between adjacent pixels is eliminated and the display quality is improved.

Further, according to the image display device of the present invention, the output pulse of the shift register circuit constituting the scanning signal line driving circuit and the pulse width control signal input from the outside are used as input signals, and Any of the above-described logic circuits is used to generate an output signal with a small pulse width. Thus, low power consumption of the image display device can be expected. That is, since the amplitude of the input signal can be made smaller than the drive voltage, the power consumption of the external circuit for signal generation can be reduced. In general, a large through current flows in a logic operation circuit when a signal is switched. However, according to the present invention, a through current flows only when an output signal is switched, not when an input signal is switched, so that power consumption is extremely small. can do. In addition, since an output signal having a pulse width smaller than that of the output signal of the shift register circuit is generated, by writing a video signal to a pixel based on this output signal, the scanning signals between adjacent horizontal lines do not overlap in time. The display quality can be expected to improve.

According to the image display device of the present invention, the output pulse of the shift register circuit forming the scanning signal line driving circuit and one of a plurality of externally input control signals are used as input signals. Any one of the above-described logic circuits is used to simultaneously output signals to different combinations of shift register circuits. Thus, low power consumption of the image display device can be expected. That is, since the amplitude of the input signal can be made smaller than the drive voltage, the power consumption of the external circuit for signal generation can be reduced. In general, a logical operation circuit is
Although a large through current flows when the signal is switched, according to the present invention, the through current flows only when the output signal is switched, not when the input signal is switched, so that the power consumption can be extremely reduced. In addition, since the timing of the output signal can be changed by a plurality of control signals input from the outside, it is possible to activate a plurality of scanning signal lines at the same time. It is also possible to change the combination. Therefore, it is possible to realize two horizontal line misalignment scans effective for displaying an NTSC image in an image display device of the VGA specification, for example.

According to the image display device of the present invention, at least one of the data signal line driving circuit and the scanning signal line driving circuit having any one of the above logic circuits is formed on the same substrate as the pixels. I did it. Accordingly, since the data signal line driving circuit and the scanning signal line driving circuit are widely distributed in the side direction of the image display device, the wiring such as the input signal line becomes longer and the wiring capacitance becomes larger. Since the signal amplitude can be reduced, an increase in the load of an external circuit for generating an input signal or the like can be suppressed. In such a structure, a pixel for performing display and a data signal line driving circuit and a scanning signal line driving circuit for driving the pixel can be manufactured over the same substrate in the same step. It can be expected that manufacturing costs and mounting costs will be reduced, and that the percentage of non-defective products will increase.

Further, according to the image display device of the present invention, a data signal line drive circuit provided with any one of the above logic circuits,
Active elements forming a scanning signal line driving circuit and a pixel,
It was constituted by a polycrystalline silicon thin film transistor. As a result, there is an advantage that characteristics with extremely high driving force can be obtained as compared with an amorphous silicon thin film transistor used in a conventional active matrix type liquid crystal display device.

Further, a polycrystalline silicon thin film transistor has a driving force of one unit as compared with a single crystal silicon transistor.
In order to drive a wiring having a large load using a conventional level shifter circuit, it is necessary to use an extremely large buffer circuit immediately after the level shifter circuit. Since a circuit is unnecessary, low power consumption can be achieved.

Further, according to the image display device of the present invention, the active element is formed by a process at about 600 ° C. or less. This makes it possible to use a glass substrate that has a low strain point temperature, is inexpensive, and can easily be made large in size. In addition to the above-described effects, a large-sized image display device can be used. This has the advantage that it can be manufactured at low cost.

[0061]

(Embodiment 1) Embodiments of a logic circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a logic circuit according to the present invention. In FIG. 1, the driving voltage of the logic circuit is 1
5V, the amplitude of the input signals IN2 and / IN2 is 15V, whereas the amplitude of the input signals IN1 and / IN1 is 5V.
It is.

As described above, in the logic circuit according to the present invention, by inputting an input signal of a voltage lower than the drive voltage, it is possible to suppress power consumption of the input signal line.

In FIG. 1, the amplitudes of the input signals IN2 and / IN2 and the amplitudes of the input signals IN1 and / IN1 are different. For example, both may be 5V. This is the same in the following embodiments.

In the drawings shown hereinafter, some of the signals require an inverted signal, but may not be shown.

FIGS. 2 and 3 are diagrams showing the basic configuration of a logic circuit according to the present invention. In FIG. 2, the power supply voltage is 1
5V, and the amplitude of the input signals IN2 and / IN2 is also 15
While the amplitude of the input signals IN1 and / IN1 is 5V.

The gate electrodes and the drain electrodes of the p-channel transistors M1 and M2 are alternately connected to each other to form a latch circuit. on the other hand,
The input signals IN1 and / IN1, IN2 and / IN2 are
These are input to the n-channel transistors CIR1 and CIR2, respectively. Here, CIR1 and CI
The configuration of R2 has the same configuration as a general CMOS logic circuit. That is, CIR1 is a CMOS that outputs the same logical operation result as the logic circuit of the present embodiment.
CIR2 has the same configuration as the circuit portion composed of n-channel transistors of the logic circuit, and CIR2 has the same configuration as the circuit portion composed of p-channel transistors of the CMOS logic circuit that outputs the same logical operation result as the logic circuit of the present embodiment. It is.

FIG. 3 is a diagram showing an example in which the channel type of the transistor in FIG. 2 is reversed. In FIG. 3, the power supply voltage is 15 V, and the input signals IN2 and / or
While the amplitude of IN2 is also 15V, the input signal IN1
And / IN1 has an amplitude of 5V. However, the input signal IN
The absolute values of 1 and / IN1 are different from the example shown in FIG.

The gate electrodes and the drain electrodes of the n-channel transistors M1 and M2 are connected alternately to form a latch circuit. on the other hand,
The input signals IN1 and / IN1, IN2 and / IN2 are
These are input to the n-channel transistors CIR1 and CIR2, respectively. Here, CIR1 and CI
The configuration of R2 has a connection similar to that of a general CMOS logic circuit. That is, CIR1 is a CM that outputs the same logical operation result as the logic circuit of the present embodiment.
The CIR2 has the same configuration as the circuit portion including the p-channel type transistor of the OS logic circuit, and the CIR2 is the same as the circuit portion including the n-channel type transistor of the CMOS logic circuit which outputs the same logic operation result as the logic circuit of the present embodiment. Configuration.

FIGS. 4 and 5 are diagrams showing another configuration of the logic circuit according to the present invention. p-channel transistor M
In transistors 1 and M2, transistors M3 and M4 are connected between their respective drain electrodes and output terminals, and the gate electrodes of transistors M3 and M4 are connected to input terminals.

On the other hand, the input signals IN1 and / IN1, IN
2 and / IN2 are input to portions CIR1 and CIR2 of the n-channel transistor, respectively. Here, the configuration of CIR1 and CIR2 is a general CMOS.
It has a configuration similar to that of a logic circuit. That is,
CIR1 has the same configuration as a circuit portion composed of n-channel transistors of a CMOS logic circuit that outputs the same logical operation result as the logic circuit of the present embodiment.
Has the same configuration as a circuit portion composed of p-channel transistors of a CMOS logic circuit that outputs the same logical operation result as the logic circuit of the present embodiment.

FIGS. 6 and 7 show another configuration of the logic circuit according to the present invention. CIR1 and CIR2 are constituted by n-channel transistors, and CIR3 and CIR
Reference numeral 4 denotes a p-channel transistor. Here, the configuration of CIR1, CIR2, CIR3 and CIR4 has the same configuration as a general CMOS logic circuit. That is, CIR1 and CIR4 are CMOs that output the same logical operation result as the logic circuit of the present embodiment.
It has the same configuration as the circuit portion of the S logic circuit composed of n-channel transistors, and CIR2 and CIR3 output the same logical operation result as the logic circuit of the present embodiment.
It has the same configuration as the circuit portion composed of p-channel transistors of the MOS logic circuit. The p-channel transistors M1 and M2 are provided on the power supply side of each current path, and have their gate electrodes connected to the output terminals of the other current paths.

In the following description of the embodiment, a circuit diagram corresponding to the basic configuration shown in FIG. 2 is mainly shown. However, as shown in FIG. 3, the configuration is such that the channel types of the transistors are interchanged. Needless to say, this may be done.

(Embodiment 2) Next, a specific embodiment of the logic circuit of the present invention will be described with reference to the drawings.
FIG. 8 is a circuit diagram showing a specific configuration example of the logic circuit according to the present invention. This circuit has a function of a logical NOT product (NAND) circuit. However, depending on how to take an input signal and an output signal, in addition to a NAND circuit, a logical NOR (NOR) circuit and a logical product (AND) are provided. ) Circuit, logical sum (O
R) It can be any of the circuits. That is, if the input signals are IN1 and IN2 and the output signal is / OUT, a logical NOT product circuit is provided, and the input signals are / IN1 and / I
If N2 is set and the output signal is set to OUT, a logical NOR circuit is formed. When the input signals are set to IN1 and IN2 and the output signal is set to OUT, an AND circuit is formed, and the input signal is set to / I
When N1 and / IN2 are set and the output signal is set to / OUT, an OR circuit is formed.

In the structure shown in FIG. 8, the p-channel transistors M1 and M2 have their gate electrodes and drain electrodes connected to each other to form a latch circuit. On the other hand, the input signals IN1 and / IN1, IN
2 and / IN2 are input to the portion of the n-channel transistor. More specifically, the input portions of the input signals IN1 and IN2 are the n-channel transistor portion of the conventional NAND circuit shown in FIG. 35 (or the p-channel transistor portion of the conventional NOR circuit shown in FIG. 36). And the input signals / IN1 and / IN
The input section 2 has the same configuration as the p-channel transistor portion of the conventional NAND circuit shown in FIG. 35 (or the n-channel transistor portion of the conventional NOR circuit shown in FIG. 36).

In the configuration shown in FIG. 8, the input signal IN2 having the smaller amplitude is input to the transistor M4 on the side closer to the ground power supply GND. However, it is not always necessary to input the input signal IN2 to the side closer to the ground power supply. Logically operates normally even if the signal is input to the transistor M3 on the far side. This is the same in other embodiments. However, the potential at the connection point between the transistor M3 and the transistor M4 may be higher than the ground potential by the resistance of the transistor M4. In this case, the voltage substantially applied to the gate of the transistor M3 decreases. Since the driving force also decreases, it is preferable to input a signal having a small input amplitude to the side closer to the ground potential because the operation margin is increased.

In the above-described embodiment, the case where the number of input signals is two (excluding the inverted signal) is shown.
A similar configuration is possible even in the case of more than one.

(Embodiment 3) Next, another embodiment of the logic circuit of the present invention will be described with reference to the drawings. FIG.
FIG. 10 is a circuit diagram showing another specific configuration example of the logic circuit according to the present invention.

This circuit uses a logical product-logical negative sum (AND-
NOR) circuit, but depending on how to take the input signal and the output signal, in addition to the AND-NOR circuit, a logical sum-logical NOT product (OR-NAND) circuit, a logical product-logical sum (AND-OR) circuit and logical sum-logical product (OR-AND) circuit.
That is, if the input signals are IN1, IN2, and IN3, and the output signal is / OUT, a logical product-logical NOR circuit is provided, and the input signals are set to / IN1, / IN2, and / IN3.
Assuming that the output signal is OUT, the circuit becomes a logical sum-logical NOT product circuit. When the input signals are IN1, IN2 and IN3 and the output signal is OUT, a logical product-OR circuit is obtained. When the input signals are / IN1, / IN2 and / IN3 and the output signal is / OUT, the logical sum is obtained. -It becomes an AND circuit.

In the configuration shown in FIGS. 9 and 10, p
The gate electrodes and the drain electrodes of the channel transistors M1 and M2 are alternately connected to each other to form a latch circuit. On the other hand, the input signals IN1 and / or
IN1, IN2 and / IN2, IN3 and / IN3 are
The signal is input to an n-channel transistor. More specifically, the input portions of the input signals IN1, IN2, and IN3 are connected to the n-side of the conventional AND-NOR circuit shown in FIG.
It has a configuration similar to that of a channel transistor portion (or a p-channel transistor portion of the conventional OR-NAND circuit shown in FIG. 38), and the input signals / IN1, / I
The input section of N2 and / IN3 is a conventional AN shown in FIG.
The configuration is the same as that of the p-channel transistor portion of the D-NOR circuit (or the n-channel transistor portion of the conventional OR-NAND circuit shown in FIG. 38).

FIG. 9 shows input signals IN1 and / IN
1 is input to the transistor on the side closer to the ground potential, which is a configuration suitable for the case where the amplitudes of the input signals IN2 and / IN2 are small. On the other hand, in FIG. 10, the input signal / IN3 is input to the transistor on the side closer to the ground potential, which is a configuration suitable when the amplitude of the input signals IN3 and / IN3 is small.

(Embodiment 4) Next, another embodiment of the logic circuit of the present invention will be described with reference to the drawings. FIG.
FIGS. 1, 12, and 13 are circuit diagrams showing specific examples of the configuration of the logic circuit according to the present invention. The circuit shown in FIG.
Although it has the function of a logical NOT product (NAND) circuit, depending on how to take input signals and output signals, NAND
In addition to the circuit, a logical NOR (NOR) circuit and a logical product (A
ND) circuit and OR (OR) circuit. That is, when the input signals are IN1 and IN2 and the output signal is / OUT, a logical NOT circuit is obtained. When the input signals are / IN1 and / IN2 and the output signal is OUT, a logical NOR circuit is obtained. Further, the input signal is set to IN1.
If the output signal is / IN2 and the output signal is / OUT, the input signal is / IN1 and / IN2, and the output signal is / OUT.

In the configuration shown in FIG. 11, transistors M3 and M4 are connected between the drain electrodes of p-channel transistors M1 and M2 and the output terminal, respectively, and the gate electrodes of transistors M3 and M4 are connected to the input terminals, respectively. Connected to signals IN2 and / IN2.
On the other hand, the input signals IN1 and / IN1, IN2 and / IN
2 is input to the portion of the n-channel transistor. Specifically, the input portions of the input signals IN1 and IN2 are connected to the portion of the n-channel transistor of the conventional NAND circuit shown in FIG. 35 (or the conventional N-channel transistor shown in FIG. 36).
It has the same configuration as the p-channel transistor portion of the OR circuit, and the input portions of the input signals / IN1 and / IN2 are connected to the p-channel transistor portion of the conventional NAND circuit shown in FIG. 35 (or FIG. 36). Conventional NOR shown
(A part of an n-channel transistor of the circuit).

The circuit shown in FIG. 12 has the function of an AND-NOR circuit.
Depending on how the input signal and output signal are taken, AND-NO
In addition to the R circuit, a logical OR-logical NOT product (OR-NAN)
D) circuit, AND-OR (AND-OR) circuit, OR-OR (OR-AND) circuit. That is, the input signals are IN1, IN2 and IN3.
If the output signal is / OUT, a logical product-logical NOR circuit is provided, and the input signals are / IN1, / IN2 and / I
If N3 is set and the output signal is set to OUT, a logical sum-logical NOT product circuit is obtained. If the input signals are IN1, IN2, and IN3 and the output signal is OUT, a logical product-OR circuit is provided, and the input signals are / IN1, / IN2, and / I.
If N3 is set and the output signal is set to / OUT, a logical OR-AND circuit is obtained.

In the configuration shown in FIG. 12, transistors M3 and M4 are connected between the drain electrodes and output terminals of p-channel transistors M1 and M2, respectively. The gate electrodes of transistors M3 and M4 are
They are connected to input signals IN1 and / IN1, respectively.

On the other hand, the input signals IN1 and / IN1, IN
2 and / IN2, IN3 and / IN3 are input to the portion of the n-channel transistor. Specifically, the input portions of the input signals IN1, IN2, and IN3 are connected to the n-channel transistor portion of the conventional AND-NOR circuit shown in FIG. 37 (or the conventional OR-NOR circuit shown in FIG. 38).
And the input signals / IN1, / IN2 and / I
The input portion of N3 is a portion of the p-channel transistor of the conventional AND-NOR circuit shown in FIG. 37 (or FIG. 38).
Of the conventional OR-NAND circuit shown in FIG.

FIG. 12 shows input signals IN1 and / I
N1 is input to the transistor on the side closer to the ground potential, which is a configuration suitable for the case where the amplitudes of the input signals IN2 and / IN2 are small.

In the structure shown in FIG. 13, transistors M3, M4 and M4 are connected between the drain terminals of p-channel transistors M1 and M2 and the output terminal, respectively.
5 and M6 are connected, and transistors M3 and M6 are connected.
4 are provided with input signals IN1 and IN2, respectively.
, And the gate electrodes of the transistors M5 and M6 are connected to the input signals / IN1 and / IN2, respectively.

The input signals IN2, IN3 and / IN1, /
The input section of IN2 is a conventional AND-NOR shown in FIG.
The n-channel transistor portion of the circuit (or FIG.
6 is the same as that of the conventional OR-NAND circuit shown in FIG.
1, IN2 and / IN2, / IN3 are shown in FIG.
36 shows a portion of a p-channel transistor of a conventional AND-NOR circuit shown in FIG.
The configuration is the same as that of the n-channel transistor of the ND circuit).

(Embodiment 5) Next, another embodiment of the logic circuit of the present invention will be described with reference to the drawings. FIG.
FIG. 4 is a circuit diagram showing a specific configuration example of the logic circuit according to the present invention.

In the configuration shown in FIG. 14, transistors M3, M4 and M5, M5 are connected between the drain terminals of p-channel transistors M1 and M2 and the output terminal, respectively.
6, M7 and M8 are connected and the transistor M
3, M4 and M5 have their respective input signals I
N1, IN2 and IN3, the transistor M
6, M7 and M8 have their respective input signals /
They are connected to IN1, / IN2 and / IN3.

Input signals IN4, IN5, IN6 and / I
The input portions of N1, / IN2, and / IN3 are n-channel transistor portions of the conventional AND-NOR circuit shown in FIG. 37 (or p-channel transistor portions of the conventional OR-NAND circuit shown in FIG. 38). And input signals IN1, IN2, IN3 and / IN4, /
The input section of IN5 and / IN6 is a conventional AN shown in FIG.
The configuration is the same as that of the p-channel transistor portion of the D-NOR circuit (or the n-channel transistor portion of the conventional OR-NAND circuit shown in FIG. 38).

(Embodiment 6) Next, another embodiment of the logic circuit of the present invention will be described with reference to the drawings. FIG.
5, FIG. 16, FIG. 17, and FIG. 18 show the NAN shown in FIG.
FIG. 19 is a circuit diagram showing a modified example of the D circuit.
0, 21 and 22 are circuit diagrams showing modified examples of the NAND circuit shown in FIG.

In FIG. 15, the input signals IN2 and / IN2 in FIG.
8, and is input to transistors M4 and M6.

The control signal CRL is input to the gate electrodes of the transfer transistors M7 and M8, and the transfer transistors are opened (connected) for a required period (a period during which the output may be switched). , The load on the signal lines for the input signals IN2 and / IN2 can be reduced. For example, when the pulse width of the input signal IN2 is smaller than the pulse width of the input signal IN1 (input signal IN2
Is included in the pulse of the input signal IN1), the input signal IN1 may be used as the above-described control signal CRL. This is the same for the examples of FIGS.

In FIG. 16, in addition to the configuration of FIG. 15, transistors M4 and M6 to which input signals IN2 and / IN2 are input, and transfer transistors M7 and M8
, Ground transistors M9 and M10 are arranged.

The ground transistors M9 and M10 are
This is a malfunction preventing means for preventing the transfer transistors M7 and M8 from being electrically floating and malfunctioning when the transfer transistors M7 and M8 are disconnected. Since the ground transistors M9 and M10 are always connected, when the control signal CRL is active, the input signals IN2 and //
It is necessary to reduce the driving force so that IN2 is prioritized. In the configuration shown in FIG. 16, the ground transistors M9 and M10 as malfunction preventing means may be resistors.

In FIG. 17, in addition to the configuration of FIG. 15, transistors M4 and M6 to which input signals IN2 and / IN2 are input, and transfer transistors M7 and M8
The ground transistors M9 and M10 are arranged between the gates, and their gate electrodes receive an inverted signal / CRL of a control signal input to the transfer transistor.

The ground transistors M9 and M10 are
As in the example of FIG. 16, the transfer transistors M7 and M8
This is to prevent the device from becoming electrically floating and malfunctioning when the device becomes disconnected. At this time, the ground transistors M9 and M10 are connected to the ground potential only when the transfer transistor is in a non-connected state, so that the potential of the signal input section does not drop regardless of the driving force of the transistors.

In FIG. 18, in the configuration of FIG. 17, the signal IN1 input to the transistor M3 is input to the gate electrode of the transfer transistor M7.

By using one of the input signals as a control signal for the transfer transistor, the number of terminals can be reduced.

Although not described, in the configurations shown in FIGS. 19, 20, 21 and 22, transfer transistors are indicated by M9 and M10, and ground transistors are indicated by M11 and M12. . These configurations have the same functions and effects as those of FIGS. 15, 16, 17, and 18.

(Embodiment 7) Next, an embodiment of the image display device of the present invention will be described with reference to the drawings. FIG.
3 and FIG. 24 are views showing a configuration example of the image display device according to the present invention.

The configuration in FIG. 23 is the same as that of the conventional image display device, and includes a pixel array ARY including pixels PIX arranged in a matrix, a scanning signal line driving circuit (gate driver) GD, and a data signal An active matrix type liquid crystal display device including a line drive circuit (data driver) SD, at least one of the data signal line drive circuit SD and the scanning signal line drive circuit has the above-described logic circuit. . The configuration example of the pixel PIX portion is as shown in FIG.

In a liquid crystal display device as an image display device, a relatively high driving voltage of 10 to 20 V is required to drive a liquid crystal element. Therefore, a driving circuit may be driven at a voltage close to this. General. On the other hand, since the signal input to the image display device is generated by an IC, it is usually 3.3 to 5 V. Therefore, during this time, some kind of voltage conversion circuit (level shift circuit) is used. However, according to the present invention, as described above, since the logic circuit in the drive circuit has the level shift function, the level shifter is separately provided. Good image display can be realized without adding a circuit.

FIG. 25 is a diagram showing a configuration example of a data signal line driving circuit used in the image display device according to the present invention. FIGS. 26 and 28 are scanning signal lines used in the image display device according to the present invention. FIG. 3 is a diagram illustrating a configuration example of a drive circuit.

In the configuration example of the data signal line drive circuit shown in FIG. 25, the data signal line drive circuit is driven by a power supply voltage of 15 V, but the amplitude of the input signal PCS is 5 V. This can be realized by employing the above-described logic circuit in the logical NOT product circuit LS_NAND to which the input signal PCS is input.

FIG. 29 shows the signal waveform at this time. Thus, a signal O having a smaller pulse width than the output signal N of the shift register circuit can be generated.

The amplitude of the clock signal CKS is also 5 V. This can be realized by using a shift register circuit constituted by a latch circuit as shown in FIG. The amplitude of the start signal SPS is 15
Although it is set to V, this can be boosted from 5 V using the conventional level shifter circuit shown in FIGS. By combining these, all the input signals of the data signal line driving circuit driven at a voltage of 15 V can have a 5 V amplitude.

In the configuration example of the scanning signal line driving circuit shown in FIG. 26, the scanning signal line driving circuit is driven by a power supply voltage of 15 V, but the amplitude of the input signal PCG is 5 V. This can be realized by employing the above-described logic circuit for the logical NOR circuit LS_NOR to which the input signal PCG is input.

FIG. 30 shows the signal waveform at this time. Thus, a signal O having a smaller pulse width than the output signal N of the shift register circuit can be generated.

The amplitude of the clock signal CKG is also 5 V. This can be realized by using a shift register circuit constituted by a latch circuit as shown in FIG. The amplitude of the start signal SPG is 15
Although it is set to V, this can be boosted from 5 V using the conventional level shifter circuit shown in FIGS. By combining these, all the input signals of the scanning signal line driving circuit driven at a voltage of 15 V
V amplitude.

In the configuration example of the scanning signal line driving circuit shown in FIG. 28, the scanning signal line driving circuit is driven by a power supply voltage of 15 V, but the amplitude of the input signals FR1 and FR2 is 5V. This can be realized by employing the above-described logic circuit for the logical NOR circuit LS_NOR to which the input signals FR1 and FR2 are input.

FIG. 31 shows the signal waveform at this time. As shown in FIG. 31, it is possible to change the combination of signal outputs according to the signal levels of the input signals FR1 and FR2, so that two horizontal line misalignment scanning can be realized. Further, the amplitude of the clock signal CKG is also 5 V, which can be realized by using a shift register circuit constituted by a latch circuit as shown in FIG. Although the amplitude of the start signal SPG is set to 15 V, it can be boosted from 5 V using the conventional level shifter circuit shown in FIGS. By combining these, all the input signals of the scanning signal line driving circuit driven at a voltage of 15 V
It can be amplitude. Here, as an example of a logic circuit and an image display device which are target technologies of the present invention, a liquid crystal display device and a logic operation circuit forming a data signal line driving circuit and a scanning signal line driving circuit thereof will be described. However,
The present invention is not limited to this, and is effective for other image display devices and other logical operation circuits.

Embodiment 8 Next, another embodiment of the image display device according to the present invention will be described with reference to the drawings.
FIG. 32 is a diagram showing another configuration example of the image display device according to the present invention.

In the image display device shown in FIG. 32, the pixel PIX, the data signal line driving circuit SD, and the scanning signal line driving circuit GD are formed on the same substrate SUB (driver monolithic structure), and It is driven by a signal from the control circuit CTL and a drive power supply from the external power supply circuit VGEN.

In such a configuration, the data signal line driving circuit and the scanning signal line driving circuit are provided on the screen (display area).
The wirings for input signals and the like are extremely long because they are widely distributed in the same length of area. Therefore, the load capacitance of the input signal wiring and the like becomes extremely large, and the effect of reducing the power consumption by reducing the signal amplitude is great.

Further, by forming the data signal line driving circuit and the scanning signal line driving circuit (monolithically) on the same substrate as the pixels, the manufacturing cost and the mounting cost of the driving circuit are reduced as compared with the case of separately configuring and mounting. Can be reduced, and the reliability can be improved.

FIG. 33 is a view showing a structural example of a polycrystalline silicon thin film transistor constituting an image display device according to the present invention.

The polycrystalline silicon thin film transistor shown in FIG. 33 has a forward stagger (top gate) structure using a polycrystalline silicon thin film on an insulating substrate as an active layer.
The present invention is not limited to this, and may have another structure such as an inverted stagger structure.

By using the polycrystalline silicon thin film transistor as described above, a scanning signal line driving circuit and a data signal line driving circuit having practical driving capabilities are formed on the same substrate as the pixel array in almost the same manufacturing steps. can do.

FIG. 34 is an example of a structural sectional view showing a manufacturing process of a polycrystalline silicon thin film transistor constituting an image display device according to the present invention.

Hereinafter, a manufacturing process for forming a polycrystalline silicon thin film transistor at a temperature of about 600 ° C. or less will be briefly described. FIG. 34 is a diagram illustrating an example of a manufacturing process of a thin film transistor included in the image display device according to the present invention. FIGS. 34A to 34K are cross-sectional views in each step.

In FIG. 34, first, an amorphous silicon thin film (b) deposited on a glass substrate (a) is irradiated with an excimer laser to form a polycrystalline silicon thin film (c). Next, the polycrystalline silicon thin film is patterned into a desired shape (d), and a gate insulating film made of silicon dioxide is formed (e). Further, after the gate electrode of the thin film transistor is formed of aluminum or the like (f), impurities (phosphorus in the n-type region and boron in the p-type region) are implanted into the source / drain regions of the thin film transistor (g, h). Thereafter, an interlayer insulating film made of silicon dioxide or silicon nitride is deposited (i), a contact hole is opened (j), and a metal wiring such as aluminum is formed.
In this step, the maximum temperature of the process is 600 ° C. during the formation of the gate insulating film.
High heat-resistant glass such as 737 glass can be used.

In the liquid crystal display device,
Further, a transparent electrode (in the case of a transmissive liquid crystal display device) and a reflective electrode (in the case of a reflective liquid crystal display device) are formed via another interlayer insulating film.

Here, in the manufacturing process as shown in FIG.
Polycrystalline silicon thin film transistor is approximately 600 ° C
By forming the glass substrate in the following manner, an inexpensive and large-sized glass substrate can be used, so that the cost and the area of the image display device can be reduced.

As described above, the logic circuit of the present invention and the case where this logic circuit is applied to an image display device have been described in detail with reference to various embodiments. Even if the polarity of the constituent transistors, the polarity of the power supply and the signal, and the like are reversed, the logic circuit is established and the same effects as described in the embodiment can be expected. There is no particular limitation on the number of input signals to the logic circuit. Further, it is needless to say that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention and without impairing the initial operation and effect.

[0127]

As described above, the present invention provides a logic circuit capable of reducing the power consumption of a driving circuit and an image display device using the same.

According to the logic circuit of the present invention, since the amplitude of an external input signal can be made smaller than the drive voltage, the load on the external circuit can be reduced.

Further, in the image display device employing the logic circuit of the present invention in the signal line driving circuit, the amplitude of the input logic signal can be reduced, so that the display quality of the image is not reduced. , External controller IC
Can be lightened.

In particular, when a scanning signal line driving circuit and a data signal line driving circuit are formed on the same substrate as a pixel by using a polycrystalline silicon thin film transistor, the driving power of the polycrystalline silicon thin film transistor is higher than that of a single crystal silicon transistor. Despite the small size, the scanning signal line driving circuit and the data signal line driving circuit are widely distributed in the side direction of the image display device, so that the load on the input signal lines is large. Therefore, there is a concern about display failure and increase in power consumption due to them, so that the advantage of employing the logic circuit of the present invention becomes extremely large.

As described above, the present invention realizes low power consumption of an image display device, and an image display device which is indispensable to the information society in the future, especially, a liquid crystal display device integrated with a driving circuit or the like. This has a significant effect on improving the performance and added value of the mounted portable device and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a logic circuit according to the present invention.

FIG. 3 is a block diagram showing another configuration example of the logic circuit according to the present invention.

FIG. 4 is a block diagram showing another configuration example of the logic circuit according to the present invention.

FIG. 5 is a block diagram showing another configuration example of the logic circuit according to the present invention.

FIG. 6 is a block diagram showing another configuration example of the logic circuit according to the present invention.

FIG. 7 is a block diagram showing another configuration example of the logic circuit according to the present invention.

FIG. 8 is a circuit diagram showing a specific example of a logic circuit according to the present invention.

FIG. 9 is a circuit diagram showing another specific example of the logic circuit according to the present invention.

FIG. 10 is a circuit diagram showing another specific example of the logic circuit according to the present invention.

FIG. 11 is a circuit diagram showing another specific example of the logic circuit according to the present invention.

FIG. 12 is a circuit diagram showing another specific example of the logic circuit according to the present invention.

FIG. 13 is a circuit diagram showing another specific example of the logic circuit according to the present invention.

FIG. 14 is a circuit diagram showing another specific example of the logic circuit according to the present invention.

FIG. 15 is a circuit diagram showing a modification of the logic circuit according to the present invention.

FIG. 16 is a circuit diagram showing another modified example of the logic circuit according to the present invention.

FIG. 17 is a circuit diagram showing another modification of the logic circuit according to the present invention.

FIG. 18 is a circuit diagram showing another modification of the logic circuit according to the present invention.

FIG. 19 is a circuit diagram showing another modification of the logic circuit according to the present invention.

FIG. 20 is a circuit diagram showing another modified example of the logic circuit according to the present invention.

FIG. 21 is a circuit diagram showing another modification of the logic circuit according to the present invention.

FIG. 22 is a circuit diagram showing another modified example of the logic circuit according to the present invention.

FIG. 23 is a block diagram illustrating a configuration example of an image display device according to the present invention.

FIG. 24 is a diagram showing an example of the internal structure of a pixel in the image display device according to the present invention.

FIG. 25 is a diagram illustrating a configuration example of a data signal line driving circuit in the image display device according to the present invention.

FIG. 26 is a diagram illustrating a configuration example of a scanning signal line driving circuit in the image display device according to the present invention.

FIG. 27 is a diagram illustrating a configuration example of a latch circuit used in a drive circuit of an image display device according to the present invention.

FIG. 28 is a diagram showing another configuration example of the scanning signal line driving circuit in the image display device according to the present invention.

FIG. 29 is a diagram illustrating an example of a signal waveform of a data signal line driving circuit in the image display device according to the present invention.

FIG. 30 is a diagram illustrating an example of a signal waveform of a scanning signal line driving circuit in the image display device according to the present invention.

FIG. 31 is a diagram illustrating an example of a signal waveform of a scanning signal line driving circuit in the image display device according to the present invention.

FIG. 32 is a block diagram showing another configuration example of the image display device according to the present invention.

FIG. 33 is a diagram showing an example of a cross-sectional structure of a polycrystalline silicon thin film transistor constituting an image display device according to the present invention.

FIG. 34 is a diagram illustrating an example of a manufacturing process of a polycrystalline silicon thin film transistor constituting the image display device according to the present invention.

FIG. 35 is a circuit diagram showing a configuration of a logical NOT product circuit in a conventional CMOS circuit.

FIG. 36 is a circuit diagram showing a configuration of a logical NOR circuit in a conventional CMOS circuit.

FIG. 37 is a circuit diagram showing a configuration of a logical product-logical NOR circuit in a conventional CMOS circuit.

FIG. 38 is a circuit diagram showing a configuration of a logical sum-logical NOT product circuit in a conventional CMOS circuit.

FIG. 39 is a circuit diagram showing a configuration example of a conventional data signal line drive circuit.

FIG. 40 is a circuit diagram showing a configuration example of a conventional scanning signal line driving circuit.

FIG. 41 is a circuit diagram showing another configuration example of a conventional scanning signal line driving circuit.

FIG. 42 is a circuit diagram showing a configuration example of a conventional level shift circuit.

FIG. 43 is a circuit diagram showing another configuration example of a conventional level shift circuit.

[Explanation of symbols]

 IN1, / IN1 input signal OUT, / OUT output signal CK, / CK, CKS, CKG clock signal SPS, SPG start signal PCS, PCG pulse width control signal FR1, FR2 frame switching signal DAT video signal LS_NAND level shifter NAND LS_NOR level shifter NOR LS_SR Level shifter / latch SR Latch circuit AS Analog switch SL Data signal line GL Scan signal line SD Data signal line drive circuit (data driver) GD Scan signal line drive circuit (gate driver) PIX Pixel ARY Pixel array GPS Pulse signal CL Liquid crystal capacity CS Auxiliary capacitance SW Pixel switch (transistor) VSH, VGH Power supply terminal VSL, VGL Ground terminal LS Level shifter circuit VGEN Power supply circuit CTL Timing Road, the control circuit SUB board COM common terminal

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasuka Kaise 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 2H093 NC09 NC11 NC34 ND38 ND39 5C058 AA08 BA01 BA26 5J056 AA03 BB17 CC21 DD13 DD29 EE03 EE11 FF09 FF10 KK01

Claims (24)

[Claims] 1. A CMOS logic circuit that performs a logical operation based on a plurality of input signals, wherein at least a part of the input signals has an amplitude smaller than a driving power supply of the CMOS logic circuit. Logic circuit. 2. The logic circuit according to claim 1, wherein a circuit portion including an n-channel transistor and a circuit portion including a p-channel transistor are provided in each of two current paths, and a circuit portion including one of the channel transistors is provided. In one of the current paths, a circuit having the same configuration as a circuit portion including an n-channel transistor of a CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit is provided. A circuit having the same configuration as a circuit portion including a p-channel transistor of a CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit is provided. The gate electrodes of the transistors provided in the current paths respectively Logic circuit according to claim 1, characterized in that connected to each other. 3. The logic circuit according to claim 1, wherein a circuit portion including an n-channel transistor and a circuit portion including a p-channel transistor are provided in each of two current paths, and a circuit portion including one of the channel transistors is provided. In one of the current paths, a circuit having the same configuration as a circuit portion including an n-channel transistor of a CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit is provided. A circuit having the same configuration as a circuit portion including a p-channel transistor of a CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit is provided. In each of the current paths, at least a portion of the input signal is gated. A transistor for inputting to a pole is provided, and a transistor whose gate electrode is connected to an output of the other current path is provided on each power supply side of the two current paths. The logic circuit according to claim 1. 4. The logic circuit according to claim 1, wherein each of the two current paths includes a circuit portion including an n-channel transistor and a circuit portion including a p-channel transistor, and the circuit portion includes one of the channel transistors. In one of the current paths, a circuit having the same configuration as a circuit portion including an n-channel transistor of a CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit is provided. A circuit having the same configuration as a circuit portion including a p-channel transistor of a CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit is provided. A CMOS logic circuit that outputs a logical operation result similar to that of the logic circuit to the current path. A circuit having the same configuration as a circuit portion including a p-channel transistor of the path is provided; a transistor in which at least a part of an input signal is input to a gate electrode is provided in the other current path;
CMOS that outputs the same logical operation result as the above logic circuit
A circuit provided with a circuit having the same configuration as a circuit portion composed of an n-channel transistor of a logic circuit, and having a gate electrode connected to the output of the other current path on each power supply side of the two current paths; The logic circuit according to claim 1, further comprising: 5. A signal having a smaller amplitude among the plurality of input signals is inputted to a power supply side of transistors connected in series in the one channel type circuit portion. The logic circuit according to claim 1, wherein 6. A mutual source electrode is connected to a first electrode potential, a mutual gate electrode is connected to a counterpart drain electrode, and connected to a first output terminal and a second output terminal, respectively. A first transistor and a second transistor, a third transistor having a gate electrode connected to the first input terminal and a drain electrode connected to the second output terminal, and a gate electrode connected to the second input terminal. A fourth transistor having a drain electrode connected to a source electrode of the third transistor, a source electrode connected to a second power supply potential, a gate electrode connected to a third input terminal, and a drain electrode Is connected to the first output terminal, a fifth transistor having a source electrode connected to the second power supply potential, a gate electrode connected to the fourth input terminal, and a drain electrode A sixth transistor connected to the first output terminal and having a source electrode connected to the second power supply potential; a signal input to the first input terminal and the third input terminal Have opposite phases, the signals input to the second input terminal and the fourth input terminal have opposite phases, and the first transistor and the second transistor are other transistors The logic circuit according to claim 1, wherein the logic circuit is a transistor of a channel type different from the transistor. 7. A mutual source electrode is connected to a first electrode potential, a mutual gate electrode is connected to a counterpart drain electrode, and connected to a first output terminal and a second output terminal, respectively. A first transistor, a second transistor, a third transistor having a gate electrode connected to the first input terminal and a drain electrode connected to the second output terminal, and a gate electrode connected to the second input terminal. A fourth transistor having a drain electrode connected to the source electrode of the third transistor, a source electrode connected to the second power supply potential, a gate electrode connected to the third input terminal, and a drain connected to the third input terminal. A fifth transistor having an electrode connected to the second output terminal and a source electrode connected to the second power supply potential; a gate electrode connected to the fourth input terminal; A sixth transistor having a gate electrode connected to a fifth input terminal, a seventh transistor having a source electrode connected to the second power supply potential, and a gate electrode having a gate electrode connected to the fifth input terminal. Is connected to a sixth input terminal, a drain electrode is connected to the first output terminal, a source electrode is connected to the drain electrode of the sixth transistor and the seventh transistor, an eighth transistor, Wherein the signals input to the first input terminal and the fourth input terminal have opposite phases, and the signals input to the second input terminal and the fifth input terminal The signals input to the third input terminal and the sixth input terminal are out of phase with each other, and the first transistor and the second transistor are connected to other transistors. Logic circuit according to any one of claims 1 to 5, characterized in that the motor is a transistor of a different channel type. 8. A mutual source electrode is connected to a first electrode potential, a mutual gate electrode is connected to a counterpart drain electrode, and connected to a first output terminal and a second output terminal, respectively. A first transistor, a second transistor, a third transistor having a gate electrode connected to the first input terminal and a drain electrode connected to the second output terminal, and a gate electrode connected to the second input terminal. A fourth transistor having a drain electrode connected to the source electrode of the third transistor, a source electrode connected to the second power supply potential, a gate electrode connected to the third input terminal, and a drain connected to the third input terminal. A fifth transistor having an electrode connected to the second output terminal and a source electrode connected to the second power supply potential; a gate electrode connected to the fourth input terminal; A sixth transistor having a pole connected to the first output terminal; a seventh transistor having a gate electrode connected to the fifth input terminal and a drain electrode connected to the first output terminal; An eighth transistor having an electrode connected to the sixth input terminal, a drain electrode connected to the source electrodes of the sixth transistor and the seventh transistor, and a source electrode connected to the second power supply potential; The signals input to the first input terminal and the fourth input terminal are in opposite phases to each other, and the signals input to the second input terminal and the fifth input terminal are: The signals input to the third input terminal and the sixth input terminal have opposite phases to each other, and the first transistor and the second transistor are connected to the other transistors. Logic circuit according to any one of claims 1 to 5, characterized in that the static is a transistor of a different channel type. 9. A mutual source electrode is connected to a first electrode potential, and gate electrodes are respectively connected to a first output terminal and a second output terminal.
A first transistor and a second transistor connected to an output terminal of the first transistor; a gate electrode connected to the first input terminal; a source electrode connected to a drain electrode of the first transistor; A third transistor connected to the second output terminal; a gate electrode connected to the second input terminal; a source electrode connected to the drain electrode of the second transistor; and a drain electrode connected to the first output terminal. A fifth transistor having a gate electrode connected to the third input terminal, a drain electrode connected to the second output terminal, and a gate electrode connected to the first input terminal. A sixth transistor having a source electrode connected to the second power supply potential, and a drain electrode connected to the source electrode of the fifth transistor; A seventh transistor having a gate electrode connected to the fourth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the first output terminal; A seventh transistor having a drain electrode connected to the first output terminal, a gate electrode connected to the second input terminal, and a source electrode connected to the second input terminal. An eighth transistor having a drain electrode connected to the first output terminal;
And the signals input to the first input terminal and the second input terminal have opposite phases, and the signals input to the third input terminal and the fourth input terminal The logic circuit according to any one of claims 1 to 5, wherein the first to fourth transistors have opposite phases and are channel-type transistors different from other transistors. 10. A first transistor and a second transistor each having a source electrode connected to a first electrode potential and a gate electrode connected to a first output terminal and a second output terminal, respectively.
A third transistor having a gate electrode connected to the first input terminal, a source electrode connected to the drain electrode of the first transistor, and a drain electrode connected to the second output terminal; A fourth transistor having a gate electrode connected to the second input terminal, a source electrode connected to the drain electrode of the first transistor, and a drain electrode connected to the second output terminal; A fifth transistor having a source electrode connected to the drain electrode of the second transistor, a gate electrode connected to the fourth input terminal, and a source electrode connected to the fifth transistor. A sixth transistor connected to a drain electrode, the drain electrode connected to the first output terminal, and a gate electrode connected to a fifth input terminal A seventh transistor having a drain electrode connected to the second output terminal, a gate electrode connected to the second input terminal, a source electrode connected to a second power supply potential, and a drain electrode connected to the second output terminal. An eighth transistor connected to the source electrode of the seventh transistor, a gate electrode connected to the sixth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the first output terminal. A ninth transistor connected to a terminal, a gate electrode connected to the fourth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the first output terminal. And a tenth transistor, wherein signals input to the first input terminal and the third input terminal are out of phase with each other, and input to the second input terminal and the fourth input terminal. 6. The signal according to claim 1, wherein the signals to be output have opposite phases to each other, and the first to sixth transistors are channel-type transistors different from other transistors. Logic circuit. 11. A first transistor and a second transistor each having a source electrode connected to a first electrode potential and a gate electrode connected to a first output terminal and a second output terminal, respectively.
A third transistor having a gate electrode connected to the first input terminal, a source electrode connected to the drain electrode of the first transistor, and a drain electrode connected to the second output terminal; A fourth transistor having a gate electrode connected to the second input terminal, a source electrode connected to the drain electrode of the second transistor, and a drain electrode connected to the first output terminal; A fifth transistor having a drain electrode connected to the second output terminal, a gate electrode connected to the first input terminal, and a source electrode connected to the second power supply potential. A sixth transistor having a drain electrode connected to the source electrode of the fifth transistor; a gate electrode connected to the fourth input terminal; A seventh transistor connected to the second power supply potential and having a drain electrode connected to the second output terminal; a gate electrode connected to a fifth input terminal; and a drain electrode connected to the first output terminal. An eighth transistor connected to the second input terminal, a gate electrode connected to the second input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to a source electrode of the eighth transistor. A ninth transistor having a gate electrode connected to a sixth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to a source electrode of the eighth transistor. And a transistor, wherein signals input to the first input terminal and the second input terminal have opposite phases to each other, and are input to the third input terminal and the sixth input terminal. The signals input to the fourth input terminal and the signal input to the fifth input terminal have opposite phases, and the first to fourth transistors are other transistors. The logic circuit according to claim 1, wherein the logic circuit is a transistor of a channel type different from the transistor. 12. A first transistor and a second transistor each having a source electrode connected to a first electrode potential and a gate electrode connected to a first output terminal and a second output terminal, respectively.
A third transistor having a gate electrode connected to the first input terminal and a source electrode connected to the drain electrode of the first transistor; a gate electrode connected to the second input terminal; A fourth transistor having an electrode connected to a drain electrode of the third transistor, a drain electrode connected to the second output terminal, a gate electrode connected to a third input terminal, and a source electrode connected to the third input terminal; A fifth transistor having a drain electrode connected to the second output terminal, a fifth electrode connected to the second output terminal, a gate electrode connected to the fourth input terminal, and a source electrode connected to the second transistor. A sixth transistor connected to a drain electrode, the drain electrode being connected to the first output terminal, and a gate electrode connected to a fifth input terminal A seventh transistor having a source electrode connected to a drain electrode of the second transistor; a gate electrode connected to a sixth input terminal; a source electrode connected to a drain electrode of the seventh transistor; An eighth transistor having a drain electrode connected to the first output terminal; a ninth transistor having a gate electrode connected to the seventh input terminal and a drain electrode connected to the second output terminal; A tenth transistor having a gate electrode connected to the eighth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to the source electrode of the ninth transistor; An eleventh transistor connected to an input terminal of the first transistor, a source electrode connected to the second power supply potential, and a drain electrode connected to the second output terminal; A twelfth transistor having a gate electrode connected to the tenth input terminal and a drain electrode connected to the first output terminal; a gate electrode connected to the eleventh input terminal; and a source electrode connected to the second input terminal. And a drain electrode connected to the source electrode of the twelfth transistor.
A transistor having a gate electrode connected to a twelfth input terminal, a source electrode connected to the second power supply potential, and a drain electrode connected to a source electrode of the twelfth transistor.
Wherein the signals input to the first input terminal and the fourth input terminal have opposite phases to each other, and are input to the second input terminal and the sixth input terminal. The signals have opposite phases, the signals input to the third input terminal and the fifth input terminal have opposite phases, and the first to eighth transistors are different from other transistors. 6. The logic circuit according to claim 1, wherein transistors are transistors of different channel types. 13. The logic circuit according to claim 1, wherein at least a part of the input signal is input via a transfer transistor for controlling input of the signal. 14. A malfunction preventing transistor is connected between a gate electrode of a transistor whose signal input is controlled by the transfer transistor and one power supply potential, and the gate electrode of the malfunction preventing transistor is connected to the power supply. 14. The logic circuit according to claim 1, wherein the logic circuit is connected to a power supply potential different from the potential. 15. A malfunction preventing transistor is connected between a gate electrode of a transistor whose signal input is controlled by the transfer transistor and one power supply potential, and the gate electrode of the malfunction preventing transistor has 14. The logic circuit according to claim 1, wherein a signal having a phase opposite to that of the transfer transistor is input. 16. The logic circuit according to claim 1, wherein one of the input signals is input to a gate electrode of the transfer transistor. 17. A plurality of pixels arranged in a matrix surrounded by a plurality of data signal lines arranged in a column direction and a plurality of scanning signal lines arranged in a row direction, and video data supplied to the data signal lines. A data signal line driving circuit, and a scanning signal line driving circuit for supplying a scanning signal to the scanning signal line, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit includes: An image display device comprising the logic circuit according to claim 1. 18. An output signal of a shift register circuit constituting the data signal line drive circuit and a pulse width control signal input from the outside are used as input signals, and an output signal having a pulse width smaller than the output pulse is generated. 18. The image display device according to claim 17, wherein the logic circuit is a logic circuit according to any one of claims 1 to 16. 19. An output pulse of a shift register circuit constituting the scanning signal line driving circuit and a pulse width control signal input from the outside are used as input signals, and an output signal having a pulse width smaller than the output pulse is generated. 18. The image display device according to claim 17, wherein the logic circuit is a logic circuit according to any one of claims 1 to 16. 20. An output pulse of a shift register circuit constituting the scanning signal line drive circuit and one of a plurality of control signals input from the outside are used as input signals, and a different combination of shift register circuits is used. , At least a part of the logic circuit for outputting the signal simultaneously,
An image display device according to claim 17, wherein the image display device is the logic circuit according to any one of claims 1 to 16. 21. A logic circuit constituting the data signal line driving circuit and the scanning signal line driving circuit, wherein a logic circuit in which an output signal of the shift register is input to a gate electrode of the transfer transistor. The image display device according to any one of claims 18 to 20, wherein 22. The device according to claim 17, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed on the same substrate as the pixels. Image display device. 23. The image display device according to claim 22, wherein the data signal line driving circuit, the scanning signal line driving circuit, and the active element forming the pixel are polycrystalline silicon thin film transistors. 24. The image display device according to claim 23, wherein the active element is formed by a process at about 600 ° C. or lower.