JP2000253564A - Power supply control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To high accurately control a current flowing in a load, when power source voltage is changed. SOLUTION: Voltage applied to a lamp L1 and voltage applied to a reference resistor Rr2 are monitored by a comparator CMP2, to detect changes of power source voltage, a drive signal always commanding an on-condition is given to a semiconductor chip 110 from a CPU 10 when the power source voltage is preset voltage or less, and a current is always supplied to the lamp L1 by placing a lamp driving FET of the semiconductor chip 110 always in an on- condition. While an intermittent current is allowed to flow in the lamp L1 by giving a PWM signal to the semiconductor chip 110 from the CPU 10 in accordance with a signal from the comparator CMP2, when the power source voltage exceeds the preset voltage, and an averaged current flowing in the lamp L1 is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply control device, and more particularly to a power supply control device suitable for controlling a value of a current supplied to a load such as a lamp in accordance with a power supply voltage.

[0002]

2. Description of the Related Art Conventionally, as a power supply device for controlling the current of a lamp, for example, the one shown in FIG. 6 is known. This power supply control device includes a CPU (microcomputer) 1, resistors 2, 3, an FET driver 4 with a booster circuit, an FET 5, and a power source 7. The FET 5 is connected in series with a lamp 6 serving as a load. Is connected to the power supply circuit connecting the plus terminal of the power supply and the ground indicating the reference potential. The CPU 1 takes in the voltage divided by the resistors 2 and 3 through the built-in A / D converter, monitors the power supply voltage according to the divided voltage, and when the power supply voltage is lower than the set voltage. A driving signal indicating an always-on state is output to the FET driver 4, and the FET 5 is always turned on so that a constant current flows through the lamp 6. On the other hand, when the power supply voltage exceeds the set voltage, CP
U1 outputs a PWM signal to the FET driver 4,
5 is turned on / off according to the PWM signal, and the lamp 6 is turned on.
To reduce the average current flowing through. Thereby, the life of the lamp 6 can be extended.

[0003]

However, in the prior art, the voltage divided by the resistors 2 and 3 is monitored to monitor the fluctuation of the power supply voltage.
In this case, the correlation with the current flowing through the lamp tends to shift, and the lamp current cannot be accurately controlled. CPU1
Requires an A / D converter, which complicates the system.

It is an object of the present invention to provide a power supply control device capable of controlling a current flowing to a load with high accuracy when a power supply voltage changes.

[0005]

In order to achieve the above object, the present invention provides a driving means for outputting a drive signal for commanding an always-on state or a drive signal for commanding an intermittent on-state, a load and a power supply. First switching means inserted into a power supply circuit to be connected and closed by turning on the power supply circuit by the drive signal; and an undercurrent determination reference for receiving a current from the power supply and generating an undercurrent determination reference voltage. A resistor, an auxiliary switching means inserted into an auxiliary shunt circuit connecting the power supply and the undercurrent determination reference resistor, and turned on by the drive signal to close the auxiliary shunt circuit; and an output of the first switching means. A voltage is compared with the undercurrent determination reference voltage, and when a difference between the two voltages deviates from an allowable value, a drive signal indicating an intermittent ON state is output to the drive means. It is obtained by constituting the power supply control apparatus and a drive command means for commanding.

In configuring the power supply control device, the power supply control device can be applied to a device intended for a lamp as a load.

Further, the present invention provides a driving means for outputting a driving signal for commanding an always-on state or a driving signal for commanding an intermittent on-state, and a driving signal inserted into a power supply circuit for connecting a load to a power supply. A first switching unit that conducts and closes the power supply circuit, an undercurrent determination reference resistor that receives a current from the power supply to generate an undercurrent determination reference voltage, and receives a current from the power supply. A reference resistor for generating a reference voltage, a second switching means inserted in a shunt circuit connecting the power supply and the reference resistor and conducting by the drive signal to close the shunt circuit; and the power supply and the undercurrent. Third switching means inserted into an auxiliary shunt circuit connecting the reference shunt to the judgment and connected by the drive signal to close the auxiliary shunt circuit; and the first switch. The output voltage of the driving means is compared with the reference voltage for judging the undercurrent, and when the difference between the two voltages deviates from an allowable value, the driving means is instructed to output a drive signal indicating an intermittent ON state. A power supply control device comprising a drive command means.

In configuring each of the power supply control devices, the following elements can be added.

A latch command means for monitoring a state of the first switching means and outputting a latch command signal when the first switching means repeats conduction / non-conduction for a set number of times according to a state of the load; In response to a latch command signal, the first switching means is provided with a non-conducting state, and interrupting latch means for latching the non-conducting state.

According to the above-mentioned means, a change in the power supply voltage is monitored from the difference between the output voltage of the first switching means and the reference voltage for judging the undercurrent, and when the difference between the two voltages is at an allowable value, the power supply is monitored. Assuming that the voltage is at the set voltage, the first switching means is turned on in accordance with the drive signal indicating the always-on state, so that a current is constantly supplied to a load, for example, a lamp, while the output voltage of the first switching means is too low. When the difference from the reference voltage for current determination deviates from the allowable value, it is determined that the power supply voltage has become higher than the set voltage, and a drive signal for commanding an intermittent ON / OFF state, for example, a PWM signal is supplied to the first switching means. In this case, the first switching means is switched to reduce the average current flowing through the load, so that the fluctuation of the load is detected with high accuracy and the current flowing through the load is reduced. Gosuru can.

When the load is short-circuited and the first switching means repeats conduction / non-conduction for a set number of times or more, a latch command signal is generated, and the first switching means is latched in a non-conduction state according to the latch command signal. Therefore, the switching means and other circuit elements can be protected. Further, when the power supply voltage increases, the average current flowing through the load can be reduced, so that the life of the load, for example, a lamp can be extended.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, a basic configuration and a basic operation of a switching device having a current oscillation type interruption function to which the present invention is applied will be described.

As shown in FIG. 1, a switching device having a current oscillation type interruption function is a semiconductor integrated circuit (power I) in which various circuit elements are integrated on a semiconductor chip 110.
C), and the power supply terminal T1 is connected to the output voltage V
B (for example, +12 volts), the ground terminal T2 is grounded, and the output terminal T3 is connected to the load 102.

On the semiconductor chip 110, as a semiconductor element (power device) having a thermal cutoff function, n
The channel thermal FET QA is integrated. The thermal FET QA has a drain electrode connected to a power supply 101 via a drain terminal D and a power supply terminal T1, and a source electrode connected to a load 10 via a source terminal S and an output terminal T3.
2, the gate electrode is connected to the gate terminal TG, the resistor RG
Are connected to the drive circuit 111 via the. This thermal FET QA is inserted into a power supply circuit connecting the power supply 101 and the load 102, and is turned on in response to a drive signal (on-pulse signal) input to the gate terminal TG to close the power supply circuit. As switching means. Further, n-channel FETs QB and QC are integrated as reference devices in parallel with the thermal FET QA.

The FET QB has a drain electrode connected to a power supply 101 via a drain terminal D and a power supply terminal T1, a source electrode connected to a first reference resistor Rr1 via an output terminal T4, and a gate electrode connected to a gate terminal TG. Through the resistor R
Connected to G. The FET QC has a drain electrode connected to the power supply 101 via a drain terminal D and a power supply terminal T1, a source electrode connected to a second reference resistor Rr2 via an output terminal T5, and a gate electrode connected via a gate terminal TG. It is connected to a resistor RG. The FET QB is configured as second switching means that is turned on by a drive signal (on-pulse signal) input to the gate terminal TG to close a shunt circuit connecting the power supply terminal T1 and the first reference resistor Rr1. The FET QC is turned on by a drive signal (on-pulse signal) input to the gate terminal TG, and serves as third switching means (auxiliary switching means) for closing an auxiliary shunt circuit connecting the power supply terminal T1 and the second reference resistor Rr2. It is configured.

As the FETs QA, QB, and QC, for example, a power MOSFET having a DMOS structure, a VMOS structure, or a UMOS structure, and a MOSF having a similar structure to these.
ET can be used, and MOS composite devices such as EST and MCT, and other insulated gate power devices such as IGBT can be used. If the gate is always used with a reverse bias, the junction type FE
T, junction type SIT, SI thyristor, or the like can also be used. Further, FETs QA and Q used for a power IC
As B and QC, either an n-channel type or a p-channel type can be used.

Also, thermal FETs QA, QB, QC
Is configured using, for example, a power device having a multi-channel structure in which a plurality of unit cells (unit cells) are connected in parallel, and each FET is arranged adjacently. The current capacity of the FETs QB and QC is set smaller than the current capacity of the FET QA. This setting is
It is adjusted by the number of unit cells connected in parallel that constitute ETQB and QC. For example, the number of unit cells of the FET QA is configured to be 1000 with respect to the number of unit cells of the FET QB being 1. The ratio of the channel width W between the FET QB and the FET QA is, for example, 1: 1000.

Further, the source terminal S of the FET QA is connected to the plus input terminals of the comparators CMP1 and CMP2, the source electrode of the FET QC is connected to the minus input terminal of the comparator CMP1, and the source electrode of the FET QC is connected to the comparator CMP2. Connected to negative input terminal. Comparator CM
The output terminal of P1 is connected to the drive circuit 111, and the output terminal of the comparator CMP2 is connected via the output terminal T6 of the semiconductor chip 110 to the undercurrent detection, lamp disconnection detection, and abnormality detection unit 501 that performs open detection. .
The source terminal S of the FET QA is connected to the drive circuit 111 via a Zener diode ZD1, and the Zener diode ZD1 is connected to the FET QA and the FET QA.
B, 1 between gate terminal TG and source terminal S of FETQC
The voltage is maintained at 2 volts, and when an overvoltage is applied to the gate terminal TG, the overvoltage is bypassed.

On the other hand, the power supply enable section 302 and the masking circuit 30
3. The ON / OFF counting circuit 304, the charge pump circuit 305, and the cutoff latch circuit 306 are integrated, the power enable unit 302 is connected to the terminal T7, and the masking circuit 303 is connected to the capacitor C11 via the terminal T8. , The ON / OFF counting circuit 304 is connected to the capacitor C12 via the terminal T9, the drive circuit 111 is connected to the switch SW1 and the resistor R11 via the input terminal T10, and the cutoff latch circuit 306 is connected via the output terminal T11. An output unit (diagnosis result output unit) 502 is connected.

As shown in FIG. 2, the drive circuit 111 includes a source transistor Q5 and a sink transistor Q6, and responds to a signal by operating the switch SW1 or a signal from the comparator CMP1 to connect the source transistor Q5 and the sink transistor Q5. As a semiconductor element for turning on / off the transistor Q6, for example, a semiconductor element forming an inverter circuit is provided, and the transistors Q5 and Q6 are connected in series.
The collector of the source transistor Q5 is connected to the terminal of the potential VP, and the emitter is connected to the gate terminal TG via the resistor RG. The collector of the sink transistor Q6 is connected to the gate terminal TG via the resistor RG,
The emitter is connected to the ground potential (GND). The terminal of the potential VP is connected to the charge pump circuit 305, and the potential VP of this terminal is
5 is higher than the power supply 101, for example, when the voltage of the power supply 101 is 12V, 12V + 1
It is set to 0V.

When the switch SW1 is turned on and the input terminal T10 is grounded via the switch SW1, the drive circuit 111 turns on the source transistor Q5 in response to a command signal from the input terminal T10, and turns on the output terminal. (The connection point between the transistor Q5 and the transistor Q6) is configured as a driving unit that outputs a high-level driving signal (on-pulse signal). On the other hand, when the switch SW1 is opened, the voltage of the power supply 101 is applied to the input terminal T10 via the resistor R11.
6 is turned on, and the level of the output terminal (the connection point between the transistor Q5 and the transistor Q6) is changed to a low level. Note that the driving circuit 111 is a CMOS FE instead of a bipolar transistor.
It is also possible to configure using T.

When a drive signal (on-pulse signal) from the drive circuit 111 having the above configuration is input to the gate terminal TG, the FETs QA, QB, and QC conduct, and the voltage between the drain and source electrodes of each FET becomes the voltage shown in FIG. 2V
It falls below. At this time, when the load 102 is in a normal state, while the drive signal is output from the drive circuit 111, the voltage between the drain and source electrodes of each FET is maintained at 2 V or less, and the drain current 705 of the FET QA becomes constant.

On the other hand, when the load 102 is short-circuited, the load 10
2, a large current may flow, and the load 102 and the FET QA may be damaged.

Therefore, a configuration is adopted in which the source voltages of the FETs QA and QB are monitored by the comparator CMP1, and when the voltages of both are abnormal, the driving circuit 111 forcibly stops the output of the driving signal.

That is, the source voltage of the FET QA is input to the plus input terminal of the comparator CMP1, and the source voltage of the FET QB is input to the minus input terminal. The comparator CMP1 having a hysteresis characteristic compares the voltages input to the plus input terminal and the minus input terminal, and when the source voltage of the FET QA substantially matches the source voltage of the FET QB, or when the source voltage of the FET QA When the source voltage of the FET QA is higher than the reference voltage (FET QB
Out of the allowable value by the source voltage of
When a large current flows through the load 102 and the source voltage of the FET QA becomes lower than the reference voltage generated by the first reference resistor Rr1, it is determined that an abnormal current has flowed through the FET QA, and a low-level signal is output. 111. The driving circuit 111 includes a comparator CMP1
When a "H" level signal is input from the controller, the output of the drive signal is enabled, but when an "L" level signal is input, the output of the drive signal is forcibly stopped. ing. That is, the comparator CMP1
Are configured as drive stop means.

Similarly, in the comparator CMP2, the source voltage of the FET QC is input to the plus input terminal, and the source voltage of the FET QC is input to the minus terminal. Then, the comparator CMP2 compares the voltages input to the plus input terminal and the minus input terminal, and when the source voltage of the FET QC and the source voltage of the FET QC substantially match, or when the source voltage of the FET QC exceeds the source voltage of the FET QC. Is also low,
When an output signal of “L” level is output and the source voltage of the FET QC deviates from the allowable value based on the reference voltage for judging undercurrent (source voltage of the FET QC), for example, the load 102
Due to disconnection or the like, a current much smaller than usual flows through the load 102, and the FET QA
When the source voltage becomes higher, it is determined that an abnormal current has flowed through the FET QA, and an "H" level signal is output to the drive circuit 111. As described above, the comparator CMP2 is configured as an abnormality determination unit that outputs the determination result of the presence or absence of the abnormality to the abnormality detection unit 501.

On the other hand, when the FET QA transitions from the on state to the off state, the transistor Q6 is turned on, and the diode D1 is turned on. As a result, the resistance R1,
A current flows through the path of the diode D1 and the comparator CM
The potential of the plus input terminal of P1 is lower than when the drive circuit 111 is performing on-control. Therefore, immediately after the transition to the off state, FE is maintained until a small specific drain-source voltage difference occurs, that is, until the source voltage of the FET QA becomes substantially equal to the source voltage of the FET QB.
TQA is kept off.

However, when the FET QA is turned off due to a short circuit in the wiring, the drain current increases due to the short circuit in the wiring, and the FET QA passes through the pinch-off region, for example, in the triode characteristic region. The state transits to the off state through the operation state of. As a result, after the elapse of a certain time, the potential of the plus input terminal of the comparator CMP1 increases, the output level of the comparator CMP1 changes from "L" level to "H" level, and the FET QA transitions to the ON state again. As shown in FIG. 3, the periodic transition of the drain-source voltage 703 of the FET QA at the time of an abnormality such as a short circuit of the load 102 is continued while the switch SW1 is closed. As a result, the drain current 707 of the FET QA fluctuates periodically. FET QA drain
The transition cycle of the source-to-source voltage 703 is determined by a time constant based on wiring inductance and wiring resistance, the capacitance of the FET QA, and the like.

Then, the number of times that the FET QA is turned on and off is counted, and when the counted value reaches the set value, the FET QA
A is forcibly shut off and this shut off state is maintained.

More specifically, an ON / OFF counting circuit 304 is used as a circuit for counting the ON / OFF state of the FET QA.
And a cutoff latch circuit 306 are provided.

As shown in FIG. 2, the ON / OFF counting circuit 304 includes bipolar transistors Q41, Q42, Q
43, n-channel FET Q44, diodes D41, D
42, D43, Zener diode ZD41, resistor R4
1 to R46.

The cathode side of the Zener diode ZD41 is connected to the source terminal S of the FET QA. When the voltage of the source terminal S is in a normal state, the transistor Q
A forward bias voltage is applied to the base of the transistor 43, and the transistor Q43 is on. Therefore, the transistor Q
42 is also in the ON state. On the other hand, since the base of the transistor Q41 is connected to the output terminal of the drive circuit 111 via the resistor R41 and the diode D42, when the transistor Q5 is on, that is, when the FET QA is on, the transistor Q41 is off. is there.

On the other hand, when the transistor Q6 is turned on, that is, when the FET QA is turned off, the diode D42 is grounded via the transistor Q6, so that the transistor Q41 is turned on. Transistor Q
When the switch 41 is turned on, the current from the power supply 101 is supplied to the capacitor C1 via the transistors Q41 and Q42 and the resistor R44.
2 and the capacitor C12 is charged.

Next, when the transistor Q5 changes from off to on, the transistor Q41 turns off, and the electric charge charged in the capacitor C12 is discharged via the resistor R46. Thereafter, when the transistor Q6 is turned on again and the transistor Q41 is turned on, the capacitor C12 is further charged.

In the process of repeating such an on / off operation, the electric charge stored in the capacitor C12 causes the FET to charge.
When the gate voltage of Q44 exceeds the threshold, FET Q4
4 turns on and the diode D42 conducts. As a result, both ends of the temperature sensor 121 are short-circuited via the diode D43, and a latch command signal is output to the cutoff latch circuit 306. That is, the ON / OFF counting circuit 304 is configured as a latch command unit. The time until the ON / OFF count reaches the set value is
It can be adjusted by the time constant of the resistor R46 and the capacitor C12.

The cut-off latch circuit 306 includes an n-channel FE
It comprises TQS, Q11, Q12, Q13, Q14, a temperature sensor 121, and resistors R31 to R35,
The drain electrode of the FET QS is the gate terminal T of the FET QA.
G, and the source electrode is connected to the source terminal S of the FET QA.
It is connected to the. The temperature sensor 121 is configured by connecting four diodes in series.
When the temperature of 10 exceeds the set temperature, the voltage at both ends is lower than the set voltage. That is, the voltage across the temperature sensor 121 is F
The threshold value is set higher than the threshold value between the source and gate electrodes of the ETQ11, and the FET Q11 is always kept on. When the FET Q11 is on,
FET Q14 is off, FET Q13 is on, FET
Q12 and the FET QS are kept off.

On the other hand, the FET Q44 is turned on, and both ends of the temperature sensor 121 are short-circuited via the diode D43, or the temperature of the semiconductor chip 110 exceeds the set temperature and the voltage across the temperature sensor 121 becomes lower than the set voltage. If it drops, the FET Q11 turns off from on and the FET Q14 turns on. When the FET Q14 turns on, the FET Q13 turns on and the FET QS
Is turned on, and F is applied between the source and gate electrodes of the FET QA.
A short circuit occurs due to ETQS, and FET QA is turned off. This short-circuit state is caused by the FET Q1 constituting the latch circuit.
2, latched by Q13. That is, the cutoff latch circuit 306 turns ON / OFF of the ON / OFF counting circuit 304.
When the number of OFF times reaches a set value, or when the temperature sensor 121 detects that the temperature of the semiconductor chip 110 has exceeded the set temperature, the FET QA is turned off and the non-conductive state is set. It is configured as a breaking latch means for latching.

Next, this embodiment will be described with reference to FIG.

In the present embodiment, the switching device having the current oscillation type interruption function described above is constituted as a main element, and a lamp L1 is connected as a load to the output terminal T3 of the semiconductor chip 110.

That is, in this embodiment, the lamp L1 is used as the load of the FET QA, and the lamp L1 is connected to the output terminal T3.
When the output terminal of the CPU (microcomputer) 10 is connected to the input terminal T10 instead of the switch SW1 and the resistor R11, and the input terminal of the CPU 10 is connected to the output terminal T6, CPU
10 outputs a drive signal for commanding an always-on state to the drive circuit 111, and outputs a drive signal for commanding an intermittent on-state, for example, a PWM signal as a drive signal to the drive circuit 111 when the power supply voltage exceeds a set voltage. The other configuration is the same as that of FIG.

More specifically, the reference resistor Rr2 is connected to the terminal T5 as a reference resistor for judging an undercurrent, and a reference voltage for judging an undercurrent is generated from the reference resistor Rr2. The reference resistor Rr2 is connected to the source of an FET QC as an auxiliary switching means or a third switching means. The FET QC is inserted into an auxiliary shunt circuit connecting the power supply 101 and the reference resistor Rr2, and is driven by a drive signal from the drive circuit 111. It is configured to conduct and close the auxiliary shunt circuit.

On the other hand, the comparator CMP2 is connected to the FET Q
The output voltage of A is compared with the terminal voltage of the reference resistor Rr2, that is, the reference voltage for judging the undercurrent, and when the difference between the two voltages is at an allowable value, for example, as shown in FIG. If it is smaller than this, an "L" signal is output to the CPU 10. Then C
The PU 10 outputs a drive signal indicating a constantly ON state as the drive signal 111.

On the other hand, when the difference between the output voltage of the FET QA and the reference voltage for judging undercurrent deviates from the allowable value, that is, as the power supply voltage rises, the reference voltage for judging undercurrent becomes linear as indicated by a broken line. When the voltage applied to the lamp L1 changes as shown by the solid line and the reference voltage for judging the undercurrent becomes larger than the output voltage of the FET QA, the power supply voltage is increased to the set voltage. V
As a result, the comparator CMP2 outputs an “H” level signal. Thereby, CPU1
From 0, a PWM signal is output to the drive circuit 111 as a drive signal for commanding the intermittent ON state. That is,
In the present embodiment, the CMP 2 is configured as a drive command unit, and the CPU 10 configures a drive unit together with the drive circuit 111.

When the power supply voltage exceeds the set voltage V0, the FET QA is turned on and off in accordance with the PWM signal, and the average current flowing through the lamp L1 can be reduced.
The life of the lamp L1 can be extended.

According to this embodiment, the fluctuation of the power supply voltage is
Since the monitoring is performed based on the difference between the output voltage of the FET QA and the reference voltage for judging the undercurrent, it can be determined with high accuracy whether the power supply voltage has exceeded the set voltage and the power supply voltage has exceeded the set voltage. At times, the average current flowing through the lamp can be reduced to extend the life of the lamp L1.

[0046]

As described above, according to the present invention,
A change in the power supply voltage is monitored based on a difference between the output voltage of the first switching means and the reference voltage for judging an undercurrent, and when the difference between the two voltages is at an allowable value, the power supply voltage is determined to be at the set voltage and is always on. The first switching means is turned on in accordance with the drive signal indicating the state, and a current is constantly supplied to the load (lamp). On the other hand, the difference between the output voltage of the first switching means and the reference voltage for judging undercurrent is an allowable value. If the power supply voltage is higher than the set voltage,
A drive signal (PWM signal) for instructing the intermittent ON / OFF state is given to the first switching means to control the switching of the first switching means so as to reduce the average current flowing through the load. The current flowing to the load can be controlled by accurately detecting the current.

[Brief description of the drawings]

FIG. 1 is a block diagram of a switching device having a current oscillation type interruption function, which is a basis of the present invention.

FIG. 2 is a main part circuit configuration diagram of the switching device shown in FIG. 1;

FIG. 3 is a waveform chart for explaining the operation of the switching device shown in FIG. 1;

FIG. 4 is a circuit configuration diagram of a power supply control device according to an embodiment of the present invention.

FIG. 5 is a characteristic diagram showing a relationship between voltage and current.

FIG. 6 is a circuit configuration diagram of a conventional power supply control device.

[Explanation of symbols]

 Reference Signs List 10 CPU 110 Semiconductor chip 111 Drive circuit 304 ON / OF counting circuit 305 Charge pump circuit 306 Cut-off latch circuit QA, QB, QC n-channel FET Rr1 First reference resistor Rr2 Second reference resistor CMP1, CMP2, CMP3 Comparator

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 3K073 AA12 AA50 AA87 AA92 AA93 BA00 BA01 BA09 CA01 CF16 CF18 CG02 CG06 CG13 CG45 CJ14 CJ19 5G004 AA04 AB02 BA03 BA04 DA02 DA04 DC01 DC04 DC14 EA01 FA01 GA02

Claims (4)

[Claims] 1. A driving means for outputting a drive signal for commanding an always-on state or a drive signal for commanding an intermittent on-state, and being inserted into a power supply circuit connecting a load and a power supply, being turned on by the drive signal to become conductive. A first switching means for closing a power supply circuit, an undercurrent determination reference resistor receiving a current supplied from the power supply to generate an undercurrent determination reference voltage, and connecting the power supply and the undercurrent determination reference resistor; An auxiliary switching means that is inserted into an auxiliary shunt circuit and closes the auxiliary shunt circuit by conducting with the drive signal, and compares the output voltage of the first switching means with the reference current for undercurrent determination and compares A power supply control unit comprising: a drive commanding unit that instructs the drive unit to output a drive signal indicating an intermittent ON state when the voltage difference deviates from an allowable value. Place. 2. A driving means for outputting a drive signal for instructing an always-on state or a drive signal for instructing an intermittent on-state, and being inserted into a power supply circuit connecting a lamp and a power supply, being turned on by the drive signal to become conductive. A first switching means for closing a power supply circuit, an undercurrent determination reference resistor receiving a current supplied from the power supply to generate an undercurrent determination reference voltage, and connecting the power supply and the undercurrent determination reference resistor; Auxiliary switching means inserted in an auxiliary shunt circuit to conduct by the drive signal and close the auxiliary shunt circuit;
The output voltage of the first switching means is compared with the reference voltage for judging the undercurrent, and when the difference between the two voltages deviates from an allowable value, the drive signal indicating the ON state which is intermittent to the drive means. A power supply control device comprising: a drive command means for commanding an output. 3. A drive means for outputting a drive signal for instructing an always-on state or a drive signal for instructing an intermittent on-state, and said drive means is inserted into a power supply circuit connecting a load and a power supply and becomes conductive by said drive signal. First switching means for closing a power supply circuit, an undercurrent determination reference resistor for generating an undercurrent determination reference voltage upon receiving a current from the power supply, and generating a reference voltage upon receiving a current from the power supply A second switching means inserted in a shunt circuit connecting the power supply and the reference resistor to conduct by the drive signal to close the shunt circuit; and the power supply and the undercurrent determination reference resistor. A third switching means inserted in an auxiliary shunting circuit connecting the first and second shunting circuits to close the auxiliary shunting circuit by conduction by the drive signal; and an output of the first switching means. Commanding means for comparing the voltage and the undercurrent determination reference voltage, and instructing the driving means to output a drive signal indicating an intermittent ON state when the difference between the two voltages deviates from an allowable value; and A power supply control device comprising: 4. A latch command means for monitoring a state of the first switching means and outputting a latch command signal when the first switching means repeats conducting / non-conducting a set number of times according to a state of the load. 4. A power supply control device according to claim 1, further comprising: a cut-off latch means for turning off the first switching means in response to the latch command signal and latching the non-conduction state. .