JP2000253089A - Digital costas loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a quick carrier recovery with a comparatively simple circuit. SOLUTION: A phase difference detection circuit 12 detects a phase difference of an output of a complex multiplier circuit 11. A loop filter 13 filters the detected phase difference and gives the result to an NCO 15. The NCO 15 adjusts the sine data and cosine data fed to the complex multiplier circuit 11 on the basis of the phase difference supplied from the loop filter 13 and whose high frequency component is cut off. On the other hand, the phase difference detected by the phase difference detection circuit 12 is also fed to a phase error generating circuit 14. The phase error generating circuit 14 generates actively a phase difference that is changing sequentially when the phase difference is large and gives it to the NCO 15. Thus, when the phase difference is large, the sin data and the cosine data are largely changed independently of a characteristic of the loop filter 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital Costas loop circuit for removing a carrier from a digital received signal, and more particularly to a circuit for realizing a quick carrier reproducing operation.

[0002]

2. Description of the Related Art FIG. 3 shows a general configuration of a front end section in a digital receiver including a digital Costas loop circuit. Such a digital receiver is used for receiving digital television satellite broadcasts and the like.

In a front end section of a digital receiver, a signal received by an antenna 31
2 down-converts to an arbitrary intermediate frequency signal (IF signal). Next, orthogonal detection is performed by the orthogonal detection circuit 33,
Analog I signal baseband _(I A), to obtain a Q signal _{(Q A).} The analog I signal and Q signal are AD
The digital I signal _(I D) by the converter 34, is converted into a Q signal _{(Q D)} is input to the Nyquist filter 35. The Nyquist filter 35 performs a filtering process for removing unnecessary high-frequency components and preventing intersymbol interference.

Here, a quadrature signal is generated by a quadrature detection circuit 33.
When generating minutes, synchronous detection of perfect carrier is not performed.
Baseband analog I and Q signals and data
A carrier component remains in the digital I signal and Q signal. this
Digital Costa to remove residual carrier components
This digital costa has a sloop circuit 36.
The data from which residual carrier components have been removed by the loop circuit
Digital I 'signal (I' _D), Q 'signal (Q'_D) Got
It is.

[0005] The digital Costas loop circuit 36 is composed of I '
The phase difference component is detected from the signal and the Q ′ signal, and the detected phase difference component is supplied to the loop filter 363. The loop filter 363 is a sufficiently low-pass filter, and removes a high-pass component of the supplied phase difference component. The output of the loop filter 363 is supplied to the NCO 364, and this NCO
364 is based on the output of the loop filter 363,
A control signal す for canceling out residual carrier components in the I ′ signal and the Q ′ signal is generated and output. SIN, COSR
The OM 365 receives the control signal 入 力 as an input and supplies the complex multiplication circuit 361 with sin and cos data values corresponding to the address value.

The complex multiplication circuit 361 performs an operation of I ′ = I × cosΘ−Q × sinΘ Q ′ = I × sinΘ + Q × cosΘ to obtain digital I ′ and Q ′ signals from which residual carrier components have been removed. Can be

In this way, even if perfect synchronous detection is not performed in the quadrature detection circuit 33, the remaining carrier component can be removed by the digital Costas loop circuit, and the received digital data can be demodulated. Can be.

[0008]

In the digital Costas loop circuit 36, the NCO is controlled by the output of the loop filter.
Generates the control signal Θ. In order to stably perform this control, it is necessary to sufficiently suppress a change in signal in the loop filter. For this reason, when the carrier is not sufficiently regenerated and the residual carrier component is large, there is a problem that it takes time to lock the carrier. Further, if the time until the carrier lock is reduced, stable control cannot be performed, so that there is a problem that it is difficult to design a loop filter.

[0009] As one of the conventional examples, NCO364
It has been proposed that a register which can be controlled by an external controller or the like is provided therein, and that the register is operated by software from the external controller to bring the control signal 近 closer to a desired value. However, in this circuit, there is a problem that input / output of a signal for the software control is required from an external controller and software control is newly required.

An object of the present invention is to provide a digital Costas loop circuit which can realize a quick carrier reproducing operation with a relatively simple circuit.

[0011]

According to the present invention, there is provided a phase difference detecting circuit for detecting a residual carrier component as a phase difference component from I and Q signals including a residual carrier component, and a phase difference component from the phase difference detecting circuit. A control signal conversion circuit for converting into a control signal for removing the residual carrier component, and a complex multiplication circuit for removing the residual carrier component by complexly multiplying the control signal by I and Q signals including the residual carrier component. In the digital Costas loop circuit provided, based on the phase difference component detected by the phase difference detection circuit, an error generation circuit that supplies a phase difference that actively changes to the control signal conversion circuit and changes the control signal. Features.

As described above, in addition to the conventional digital Costas loop circuit, the provision of a phase error generating circuit for actively providing a phase difference provides a quick carrier reproducing operation. This makes it possible to realize a quick carrier reproduction operation.

The error generating circuit includes a lock determining circuit that determines whether the control signal has a predetermined accuracy based on the phase difference component detected by the phase difference detecting circuit. A phase error generating circuit that actively generates a phase difference that fluctuates when it is determined to be locked.

Thus, when the phase difference is small, the control signal can be changed only when necessary without causing a large change in the control signal.

Further, the phase difference detection circuit has a loop filter for smoothing the detected phase difference component, and a detection circuit for detecting a change in the output of the loop filter. Preferably, the output of the phase error generating circuit at the time of locking is changed to change the control signal.

As described above, the output of the loop filter is biased,
When the lock is about to be released, the reference of the control signal can be shifted, and the lock can be prevented from being released.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a digital Costas loop circuit according to the present embodiment. As shown in FIG, I signal which is the output of the Nyquist filter _(I D), Q signal _{(Q D)} is input to the complex multiplier circuit 11. This complex multiplication circuit 11 performs complex multiplication based on the control signal Θ to remove residual carrier components, as in the conventional example of FIG.
An I ′ signal (I ′ _D ) and a Q ′ signal (Q ′ _D ) are obtained. The phase difference detection circuit 12 detects a phase difference from the I ′ signal and the Q ′ signal, and supplies this to the NCO 15 via the loop filter 13. The NCO 15 generates a control signal Θ for removing the residual carrier component based on the phase difference supplied from the loop filter 13 from which the high frequency has been cut. Next, this control signal Θ is supplied to the ROM 16 and
Sin data from SINROM and COSROM
Read s data. Then, the complex multiplication circuit 11
A complex operation similar to that of the above-described conventional example is performed on the n data and the cos data to obtain the I ′ signal and the Q ′ signal from which the residual carrier component has been removed.

For example, when digital data is QPSK modulated, a phase difference as shown in FIG. 4 occurs. That is, when synchronous detection of a complete carrier is performed by the orthogonal detection circuit, the phase tan ⁻¹ (Q ′ / I ′) of data obtained from the I ′ signal and the Q ′ signal is the same as that of A, B, C, and D. It should be located at four points. However, if synchronous detection of a complete carrier is not performed and a carrier component remains in the I ′ signal and the Q ′ signal, a phase shift occurs, and the signals are located at points a, b, c, and d. Therefore, this phase difference is detected by the phase difference detection circuit 12 and output as phase difference data.

The phase difference data detected by the phase difference detection circuit 12 is supplied to a phase error generation circuit 14. The phase error generation circuit 14 determines that the carrier is in an unlocked state when the detected phase difference is sufficiently large, and in this case, supplies a signal for actively changing the phase difference to the NCO 15. Thus, control signal Θ output from NCO 15 is sequentially changed in a predetermined manner. Therefore, even if the phase difference output from the loop filter 13 does not change much, the control signal Θ can be changed appropriately and a large phase error can be eliminated at an early stage. On the other hand, when the carrier is determined to be in the locked state, the control signal Θ is controlled by the output from the loop filter 13, and stable control can be performed.

FIG. 2 shows a more specific configuration of the circuit of the present invention. In the present embodiment, the phase error generation circuit 14 includes a phase error generation counter 141, a timing counter 142, and a lock determination circuit 143.
The NCO 15 includes a phase error fine adjustment circuit 151 and a loop filter output counter 152.

In the phase error generating circuit 14, the phase difference input from the phase difference detecting circuit 12 approaches 0 when the carrier approaches the locked state. Therefore, when the phase difference data from the phase difference detection circuit 12 is a value far apart from 0, the lock determination circuit 143 determines that the vehicle is in the unlocked state. Then, in this case, the status signal: 0 indicating the unlocked state is output to the timing counter 142. On the other hand, when the phase difference data from the phase difference detection circuit 12 is 0
If the value converges to the vicinity, it is determined that the carrier is locked, and the status signal 1 indicating the locked state is output to the timing counter 142.

The timing counter 142 is an arbitrary length counter. When the carrier is in a locked state, that is, when the state signal is 1, the operation is stopped. On the other hand, when the carrier is in the unlocked state, that is, when the state signal is 0, the count-up is performed at a predetermined timing, for example, a timing synchronized with the system clock, and every time the counter overflows, the next-stage phase error generation counter 141
Output a count pulse signal. Note that the length of the counter until the timing counter 142 counts up is determined based on the clock to be counted, how the control signal Θ is desired to be changed, and the like.

The phase error generation counter 141 changes the phase error generation counter 141 based on the count pulse signal from the timing counter 142 and outputs phase error data to the NCO 15. For example, if the phase error generation counter 141 has 8 bits, the initial value starts from 0, and every time a count pulse signal is input from the timing counter 142, -1, 1, -2, 2, -3,. -12
The state transitions to 6, 126, -127, 127, and -128, and returns to the source 0.

If the carrier reproduction is locked and the count pulse signal is not input, the phase error counter
Keep the current state. However, even in the locked state, the phase error generation counter 141 is counted up by a count-up pulse signal from a loop filter output counter 152 described later, and is counted down by a count-down pulse signal.

That is, in the unlocked state of the carrier, the phase error generation counter 141 outputs phase difference data for actively changing the control signal Θ. When the locked state is reached, the timing counter 1
Since the count pulse from 42 stops, the output is locked at that time. However, as described above, the value changes according to the pulse from the loop filter output counter 152.

In the NCO 15, the phase error fine adjustment circuit 1
When the output of the loop filter 13 is 0, 51 outputs the phase error data from the phase error generating circuit 14 as it is to the next-stage ROM 16 as the control signal Θ. When the output of the loop filter 13 is a negative value, a value obtained by adding 1 to the phase error data from the phase error generating circuit 14 is output to the next-stage ROM 16 as a control signal Θ. When the output of the loop filter 13 is a positive value, the phase error generation circuit 14
The value obtained by subtracting 1 from the phase error data from the control signal 制 御
Is output to the ROM 16 at the next stage.

Thus, when the carrier is locked, the control signal Θ is controlled according to the signal from the loop filter 13.
Is changed.

The loop filter output counter 152
Has two counters internally, and the loop filter 13
Monitor the output of When the output of the loop filter 13 is a positive value, the counter on the positive side is incremented and the counter on the negative side is cleared at the same time. Also,
When the output of the loop filter 13 is a negative value, the counter on the negative side is incremented and the counter on the positive side is cleared at the same time. Each counter is
When an overflow occurs, a count-up pulse signal or a count-down pulse signal is output to a phase signal generation counter 141 in the phase error generation circuit 14.

The output of the loop filter 13 alternates between a plus value and a minus value around 0 when the carrier is locked. However, the carrier may gradually shift to one side depending on a temperature change or the like. In such a case, the phase difference data sequentially increases, and the carrier lock is released as it is.

However, in the present embodiment, the carrier lock is released and the output of the loop filter 13 becomes a value biased to the plus side or the minus side, whereby the loop filter output counter 152 counts up to the phase error occurrence counter or Outputs countdown signal. Thus, the phase error data output from the phase error generation counter is changed, and the control signal あ っ た corresponding to the phase error at that time is output. Thus, the control can be continued without the carrier lock coming off.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital Costas loop circuit according to the present invention.

FIG. 2 is a block diagram specifically showing FIG. 1;

FIG. 3 is a block diagram illustrating one configuration of a conventional digital Costas loop circuit.

FIG. 4 is a diagram showing a phase difference in the case of QPSK.

[Explanation of symbols]

11 complex multiplication circuit, 12 phase difference detection circuit, 13 loop filter, 14 phase error generation circuit, 15 NCO,
16 ROM.

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[Procedure amendment]

[Submission Date] June 19, 2000 (2006.1.
9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

According to the present invention, there is provided a phase difference detection circuit for detecting a residual carrier component as a phase difference component from I and Q signals including a residual carrier component, and a phase difference component from the phase difference detection circuit. A control signal conversion circuit for converting the control signal into a control signal for removing the residual carrier component, a complex multiplication circuit for removing the residual carrier component by complexly multiplying the control signal by I and Q signals including the residual carrier component,
A digital Costas loop circuit comprising: an error generation circuit that supplies a phase difference that actively changes to the control signal conversion circuit based on the phase difference component detected by the phase difference detection circuit and changes the control signal .

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

As described above, in addition to the conventional digital Costas loop circuit, the provision of a phase error generating circuit for actively providing a phase difference provides a quick carrier reproducing operation. This makes it possible to realize a quick carrier reproduction operation.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

The error generating circuit includes a lock determining circuit that determines whether the control signal has a predetermined accuracy based on the phase difference component detected by the phase difference detecting circuit. And a phase error generation circuit that actively generates a phase difference that fluctuates when the lock is determined .

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

[0015] Then, in the phase difference detection circuit includes a loop filter for smoothing the detected phase difference component, a detection circuit for detecting a variation in the output of the loop filter, and according to the detected value of the detection circuit Then, the output of the phase error generating circuit at the time of locking is changed, and the control signal is changed .

Claims (3)

[Claims] 1. A phase difference detecting circuit for detecting a residual carrier component as a phase difference component from I and Q signals including a residual carrier component, and a control for removing the residual carrier component from the phase difference detecting circuit from the phase difference detecting circuit. A digital Costas loop circuit comprising: a control signal conversion circuit that converts the signal into a signal; and a complex multiplication circuit that removes the residual carrier component by complexly multiplying the control signal by I and Q signals including the residual carrier component. A digital Costas loop circuit, comprising: an error generating circuit that supplies a actively changing phase difference to the control signal conversion circuit based on a phase difference component detected by a phase difference detection circuit and changes the control signal. 2. The circuit according to claim 1, wherein the error generation circuit determines whether the control signal has a predetermined accuracy based on a phase difference component detected by the phase difference detection circuit. And a phase error generation circuit that actively generates a phase difference that fluctuates when it is determined that the lock is unlocked in the lock determination circuit. 3. The circuit according to claim 2, wherein the phase difference detection circuit comprises a loop filter for smoothing the detected phase difference component, and a detection circuit for detecting a change in the output of the loop filter. A digital Costas loop circuit, wherein an output of the phase error generating circuit at the time of locking is varied in accordance with a detection value of the detection circuit to change the control signal.