JP2000252970A - Frame synchronizing signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame synchronizing signal generator that outputs no erroneous frame synchronizing signal even when a header part of a time slot has an error. SOLUTION: When a 1st correlation detection section 10A compares a bit pattern of a header part of a desired time slot with a predetermined bit pattern and detects correlation, a bit count section 12 starts counting bits. When an error detection section 11 detects an error of a data part and detects no error, a synchronization detection section 13 outputs a logic '1' as a correlation output selection signal to allow a correlation output selection section 10C to select a 2nd correlation detection section 10B. The 2nd correlation detection section 10B detects the correlation with the header part of an adjacent time slot through similar bit pattern comparison to that by the 1st correlation detection section 10A. Upon the receipt of a logic '1' respectively as a 2nd correlation detection signal 102B and a count end signal 104, the synchronization detection section 13 outputs a logic '1' as a frame synchronizing signal 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization signal generator in a time division multiplex communication system,
More specifically, the present invention relates to a frame synchronization signal generation device that reliably detects a desired time slot.

[0002]

2. Description of the Related Art In a time division multiplexing communication system including a base station and a plurality of terminal stations, data transmission and reception are performed by sharing one transmission path among a plurality of terminals. Generally, in a communication system employing a frame multiplexing method among the time division multiplexing methods, data transmitted on a transmission path is stored by being divided into a plurality of frames at a period peculiar to each communication system. Each frame is
It consists of multiple time slots. Each terminal station
Data transmission / reception with the base station is performed by repeatedly selecting a specific time slot (hereinafter, referred to as a desired time slot) among the time slots constituting the frame for each frame. Therefore, in order for the base station and the terminal station to transmit and receive data accurately, it is essential to synchronize the frames with each other. Therefore, the data transmitting side provides a header portion storing data (hereinafter, referred to as slot information) necessary for the data receiving side to select a desired time slot, and transmits the data. On the data receiving side, the frame synchronization signal generator detects a predetermined correlation by comparing a bit pattern set in advance to select a desired time slot with a bit pattern in a header portion of an input time slot. Then, it is determined that the time slot is a desired time slot, and the frame synchronization signal is output.

FIG. 4 is a block diagram showing a configuration of a conventional frame synchronization signal generation device 400. The conventional frame synchronization signal generation device 400 includes a correlation detection unit 30, an error detection unit 31, and a synchronization detection unit 32.

FIG. 5 shows a frame synchronization signal generation device 400.
, A correlation detection signal 302 generated by the correlation detection section 30, an error detection signal 303 generated when the error detection section 31 detects an error in the data section,
3 shows a frame synchronization signal 304 generated by the synchronization detection unit 32. A time slot forming a frame is composed of a header part for synchronizing and a data part containing data.

Referring to FIG. 5, first, when a frame 301 is input to a correlation detecting section 30, the correlation detecting section 30 detects a correlation between a preset bit pattern and a bit pattern in a header portion of a time slot. I do. Correlation detector 30
When detecting the correlation by comparing the bit pattern of the header part with a preset bit pattern, the signal generator generates a correlation detection signal and outputs the signal to the error detector 31 and the synchronization detector 32. When the error detection unit 31 receives the correlation detection signal,
The error detection of the data part following the header part is performed. Here, the data portion has been subjected to error coding in advance. The error detection unit 31 generates a logic “1” as an error detection signal 303 when detecting an error from a data portion continuously input to the header portion of the time slot in which the correlation detection unit 30 has detected the correlation, and performs synchronization detection. Output to the unit 32. The synchronization detection unit 32 starts bit counting from the point in time when the logic “1” is input as the correlation detection signal 302, and counts the bit length of the data part continuously input to the header part.
The error detector 31 detects an error in the data part while the synchronization detector 32 counts the bits. Synchronization detector 32
Refers to the error detection signal 303 when the counting for the bit length is completed. The synchronization detector 32 outputs the error detection signal 3
As a result of referring to No. 03, if no error is detected (logic “0” is output as error detection signal 303), logic “1” is generated and output as frame synchronization signal 304.

FIG. 6 shows a frame synchronization signal generation device 400.
5 is a flowchart showing the operation of the synchronization detection unit 32 included in FIG. Hereinafter, the operation of the synchronization detection unit 32 will be described with reference to FIG. 6 together with FIG. 4 and FIG.

[0007] The synchronization detecting section 32 determines whether or not a logic "1" has been input as the correlation detection signal 302 (step S1). Unless logic “1” is input as the correlation detection signal 302, the step does not proceed. Here, the correlation detection unit 30
The time slot with the header part for which the correlation should be detected is
It is expected that there will always be one in one frame. If there is no time slot having a header part in which the correlation detection unit 30 can detect the correlation in one frame, the correlation detection unit 30 does not output the logic “1” as the correlation detection signal 302. In this case, the correlation detection unit 30 continues to output logic “0” as the correlation detection signal. Therefore, the synchronization detection unit 32 cannot generate a frame synchronization signal. When the correlation detection unit 30 detects the correlation with the header part and outputs a logic “1” as the correlation detection signal 302, the synchronization detection unit 32 that has received the correlation detection signal 302 determines the bit of the data part following the header part. The operation waits for a long time (step S2).
The standby time is a time when the error detection unit 31 detects an error in the data part. When the time corresponding to the bit length of the data portion has elapsed, the synchronization detection unit 32 refers to the error detection signal 303 (Step S3). When the logic “1” is input as the error detection signal 303, the synchronization detection unit 32 returns to step S1. On the other hand, if the logic “1” is not input as the error detection signal 303, the logic “1” is output as the frame synchronization signal 304.
Is output (step S4).

FIG. 7 is a block diagram showing a configuration of a conventional frame synchronizer. Conventional frame synchronization device 500
Is a frame synchronization signal generation unit 400 and a synchronization protection unit 20
0. The frame synchronization signal generation unit 400
This is the same as the frame synchronization signal generation device 400 shown in FIG.

The frame synchronization signal generation section 400 receives the received data, generates a frame synchronization signal, and outputs the frame synchronization signal to the synchronization protection section 200. The synchronization protection unit 200 generates a frame timing signal based on the frame synchronization signal.
The frame timing signal is output at the same timing as the frame synchronization signal in a normal state where the frame synchronization is established. The synchronization protection unit 200 constantly monitors whether or not a frame synchronization signal is output within a preset time range for each frame (hereinafter, referred to as an allowable time range). Further, parameters (setting of the number of protection stages and the like) necessary for determining whether or not the synchronization performed by the synchronization protection unit 200 is synchronized are provided from a control unit (not shown).
The synchronization protection unit 200 outputs a frame timing signal based on a previously input frame synchronization signal without immediately determining that synchronization has been lost even if a frame synchronization signal is input outside the allowable time range in a state where synchronization is established. At the same time, the number of times the frame synchronization signal is input outside the allowable time range is counted, and when the counting result exceeds a predetermined value based on a parameter given from the control unit, it is determined that the state is out of synchronization. In the out-of-synchronization state, the synchronization protection unit 200
Does not output a frame timing signal. Thus, even if an error occurs accidentally in a specific frame, the receiving side can perform data processing based on the timing given by the frame timing signal, and can prevent unnecessary data input. In addition, the synchronization protection unit 2
In the out-of-synchronization state, even if a frame synchronization signal is input within the allowable time range, the synchronization state is not immediately determined, but the number of times the frame synchronization signal is input within the allowable time range is counted. When the result exceeds a predetermined value based on a parameter given from the control unit, it is determined that synchronization is established, and a frame timing signal is generated. As a result, the receiving side can accurately return from the out-of-synchronization state to the synchronized state. From the above, it can be said that the frame timing signal is a signal in which the reliability of the frame synchronization signal is further improved. The operation of the synchronization protection unit 200 described above is hereinafter referred to as a protection operation.

[0010]

Conventionally, as described above, frame synchronization signal generating apparatus 400 has detected a correlation only between a preset bit pattern and a bit pattern of a header portion of a desired time slot. . For this reason, an error occurs in the bit pattern indicating the slot information of the header portion on the transmission path for some reason, and the bit pattern of the header portion of the wrong time slot is accidentally replaced with the bit pattern of the header portion of the desired time slot. If they match, the conventional frame synchronization signal generating apparatus 400 detects the correlation between the preset bit pattern and the bit pattern of the header part of the wrong time slot and outputs a correlation detection signal. After that, the frame synchronization signal generation device 400
Starts error detection of the data part input following the header part where the correlation is detected, and when no error is detected in the data part, the erroneous time slot is determined to be a desired time slot, and the frame is determined. A synchronizing signal (hereinafter referred to as an incorrect frame synchronizing signal) was output.

Assume that the received data (bit string) is input, and the frame synchronization signal generating device 400 outputs the first frame synchronization signal. The following problem occurs when the first frame synchronization signal is an incorrect frame synchronization signal.

The frame synchronization signal is input to a synchronization protection section 200. Since the synchronization protection unit 200 cannot determine whether or not the frame synchronization signal is correct when the first frame synchronization signal is input, a desired time slot is inserted based on the frame synchronization signal. It recognizes the frame period and outputs a frame timing signal. Therefore, the synchronization protection unit 200 erroneously recognizes the frame period when an incorrect frame synchronization signal is input first. As a result, even if a correct frame synchronization signal is input in the next frame, the synchronization protection unit 200 performs the above-described protection operation, and is not the correct frame synchronization signal.
A frame timing signal (hereinafter, referred to as a wrong frame timing signal) is output based on a wrong frame synchronization signal input first. Since the wrong frame timing signal is output based on the protection operation performed by the synchronization protection unit 200 as described above, it is repeatedly output for each frame while a predetermined number of frames are input. Accordingly, during this time, not only the data of the desired time slot is not input, but also the data of other unnecessary time slots is input to the receiving side. In this case, there has been a problem that the original function of the frame timing signal as a Merck mark cannot be fulfilled because a desired time slot is accurately detected.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a frame synchronizing signal generating apparatus which does not generate an erroneous frame synchronizing signal even if an error occurs in a header of a time slot on a transmission line.

[0014]

A first aspect of the present invention is a frame synchronization signal generating apparatus for detecting a desired time slot existing in each frame of a frame-multiplexed digital signal based on a bit pattern. A correlation detecting means for detecting a correlation by comparing a bit pattern of a header portion of a plurality of time slots with a preset bit pattern to generate a plurality of correlation detection signals;
A synchronization signal generating means for generating a frame synchronization signal when all of the plurality of correlation detection signals are received.

As described above, according to the first aspect, since the frame synchronization signal is generated based on the plurality of correlation detection signals, the synchronization signal generation device does not generate an erroneous frame synchronization signal in the first frame. .

A second invention is an invention according to the first invention, wherein the correlation detecting means determines a correlation between a predetermined first bit pattern and a bit pattern of a header portion of a desired time slot. A first correlation detecting means for detecting and outputting a first correlation detection signal, a second predetermined bit pattern and a header part of another time slot existing in the same frame as the desired time slot; And a second correlation detection means for outputting a second correlation detection signal and detecting a correlation of the frame synchronization signal when the first correlation detection signal and the second correlation detection signal are input. Is generated.

As described above, according to the second aspect, the first aspect
Since the frame synchronization signal is generated based on the second correlation detection signal and the second correlation detection signal, the synchronization signal generation device hardly generates an incorrect frame synchronization signal in the first frame, and has a simple configuration. .

[0018]

FIG. 1 is a block diagram showing a configuration of a frame synchronization signal generating apparatus 100 according to one embodiment of the present invention. 1, the frame synchronization signal generation device 100 includes a correlation detection unit 10, an error detection unit 11, a bit counting unit 12, and a synchronization detection unit 13. The correlation detection unit 10 includes a first correlation detection unit 10A, a second correlation detection unit 10B, and a correlation output selection unit 10C. In the present embodiment, it is assumed that the data transmission side and the data reception side transmit and receive data based on a predetermined communication protocol.

FIG. 2 shows a frame synchronization signal generating apparatus 100.
, A first correlation detection signal 102A output by the first correlation detection unit 10A, a second correlation detection signal 102B output by the second correlation detection unit 10B, and a correlation output by the correlation output selection unit 10C. A detection signal 102, an error detection signal 103 output by the error detection unit 11, a count completion signal 104 output by the bit counting unit 12, a correlation detection signal 105 and a frame synchronization signal 106 output by the synchronization detection unit 13 are shown. ing. The configuration of the frame 101 is the same as that of the frame 301 shown in FIG. Also,
The synchronization detector 13 outputs a correlation output selection signal 105 that causes the correlation output selector 10C to select the first correlation detector 10A. When the first correlation detection section 10A outputs the first correlation detection signal 102A, the synchronization detection section 13 outputs the correlation output selection signal 105 such that the correlation output selection section 10C next selects the second correlation detection section 10B. .

Referring to FIG. 1, first, synchronization detecting section 13
Is a logical "0" as the correlation output selection signal 105 so that the correlation output selection unit 10C selects the first correlation detection unit 10A.
Is output. Accordingly, the correlation output selection unit 10C selects the first correlation detection unit 10A. When the frame 101 is input to the first correlation detection unit 10A, the first correlation detection unit 10A
The correlation between the bit pattern set in advance and the bit pattern in the header of the time slot is detected. as a result,
Upon detecting the correlation, the first correlation detection unit 10A outputs the logic “1” to the error detection unit 11, the bit counting unit 12, and the synchronization detection unit 13 as the first correlation detection signal 102A. When logic "1" is input as the first correlation detection signal 102A, the error detection unit 11 performs error detection on the data portion following the header portion. Here, the data portion has been subjected to error coding in advance. When detecting an error from the data portion, the error detection unit 11 outputs a logic “1” as the error detection signal 103.
Is output to the synchronization detecting unit 13. The bit counting unit 12 starts counting the number of bits from the point in time when the logic “1” is input as the first correlation detection signal 102A, counts the same number of bits as one time slot, and then counts the completion signal 104 And outputs a logic “1” to the synchronization detecting unit 13.
Here, what the bit counter 12 counts is the total number of bits of the data part of the time slot in which the correlation is detected and the header part of the time slot adjacent to the time slot. The synchronization detection unit 13 outputs the first correlation detection signal 102A
The error detection signal 103 is referred to after a lapse of the data length of the time slot from the input of the logic "1". As a result, if there is no error, the synchronization detection unit 13 sets the logic “1” as the correlation output selection signal 105 to the correlation output selection unit 1.
Output to 0C. Accordingly, correlation output selecting section 10C cuts off the input from first correlation detecting section 10A and accepts the input from second correlation detecting section 10B. On the other hand, if there is an error, the synchronization detection unit 13 outputs logic “0” as the correlation output selection signal 105. The second correlation detection unit 10B detects a correlation between a preset bit pattern and a header portion of a time slot adjacent to a time slot having a header portion whose correlation is detected by the first correlation detection unit 10A. The method of correlation detection performed by the second correlation detection unit 10B is the same as the method of correlation detection performed by the first correlation detection unit 10A. Second
When detecting the correlation between the bit pattern set in advance and the header part of the adjacent time slot, the correlation detection unit 10B outputs a logic “1” as the second correlation detection signal 102B. The synchronization detector 13 outputs the second correlation detection signal 102B
When the logic “1” is input as the count completion signal 104, the logic “1” is output as the frame synchronization signal 106 and the logic “0” is output as the correlation output selection signal 105.

In the present embodiment, as a second correlation detection, a header portion of a time slot adjacent to a time slot in which the first correlation detection section 10A outputs a logical "1" as a correlation detection signal, and a second correlation In order to perform the detection, a correlation with a preset bit pattern is detected, but the present invention is not limited to this. The second correlation detection unit 10B may detect a correlation between the bit pattern set in advance and a bit pattern of a header part of a time slot existing at an arbitrary position in another frame. In this case, the bit counting unit 12
Instead of counting the number of bits corresponding to the bit length of one time slot, the number of bits may be counted as an integral multiple of the bit length of one time slot.

FIG. 3 shows a frame synchronization signal generating apparatus 100.
4 is a flowchart showing the operation of the synchronization detection unit 13 included in FIG. The operation of the synchronization detection unit 13 will be described with reference to FIG. 3 together with FIG. 1 and FIG.

The synchronization detector 13 outputs the correlation output selection signal 10
The logic "0" is output as 5 (step S11). Correspondingly, the correlation output selection unit 10C changes the first correlation detection unit 10A.
Select Upon detecting a correlation with a header portion of a desired time slot, the first correlation detecting section 10A detects a correlation detection signal 1
The logic "1" is output as 02A. Next, the synchronization detection unit 13 determines whether or not logic “1” has been input as the first correlation detection signal 102A (Step S12). The step does not proceed unless the logic "1" is input as the first correlation detection signal 102A. When the logic "1" is input as the first correlation detection signal 102A, the synchronization detection unit 13 waits for the operation for the bit length of the data part (step S13).
This data part is a data part following the header part where the first correlation detection unit 10A has detected a correlation. Next, the synchronization detection unit 13
Determines whether the logic "1" has been input as the error detection signal 103 (step S14). Error detection signal 10
When the logic "1" is input as 3, the synchronization detection unit 13 returns to step S12. When logic "0" is input as the error detection signal 103, the synchronization detection unit 13 outputs logic "1" as the correlation output selection signal 105 (step S1).
5). In response, the correlation output selection unit 10C selects the second correlation detection unit 10B. Next, the synchronization detection unit 13 determines whether or not the logic “1” has been input as the count completion signal 104 (Step S16). The synchronization detection unit 13 waits for the operation until the logic “1” is input as the count completion signal 104. When logic "1" is input as the count completion signal 104, the synchronization detection unit 13 determines whether or not logic "1" is input as the second correlation detection signal 102B (step S).
17). If logic “1” is not input as the second correlation detection signal 102B, the synchronization detection unit 13 returns to Step S12. On the other hand, logic "1" is used as the second correlation detection signal 102B.
When the logic “1” is input as the count completion signal 104, the synchronization detection unit 13 outputs the logic “1” as the frame synchronization signal 106 and outputs the logic “0” as the correlation output selection signal 105.

When the frame synchronization signal generator 100 according to one embodiment of the present invention is applied in place of the frame synchronization signal generator 400 shown in FIG. Rarely generates an incorrect frame synchronization signal even in the first frame. Therefore, as a result, the synchronization protection unit 2
00 can output a logical “1” as an accurate frame timing signal in the first frame to be input.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a frame synchronization signal generation device 100 according to an embodiment of the present invention.

FIG. 2 is a frame synchronization signal generating apparatus 100 shown in FIG.
FIG. 4 is a diagram showing a timing chart of a signal generated by and a frame to be input.

FIG. 3 is a diagram showing a frame synchronization signal generating apparatus 100 shown in FIG. 1;
4 is a flowchart showing the operation of the synchronization detection unit 13 included in FIG.

FIG. 4 is a block diagram showing a conventional frame synchronization signal generation device 400.

5 is a frame synchronization signal generation device 400 shown in FIG.
FIG. 4 is a diagram showing a timing chart of a signal generated by and a frame to be input.

FIG. 6 shows a frame synchronization signal generation device 400 shown in FIG.
5 is a flowchart showing the operation of the synchronization detection unit 32 included in FIG.

FIG. 7 is a block diagram showing a frame synchronization device 500 to which a conventional frame synchronization signal generation device 400 is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Correlation detection part 10A ... First correlation detection part 10B ... Second correlation detection part 10C ... Correlation output selection part 11 ... Error detection part 12 ... Bit counting part 13 ... Synchronization detection part 101 ... Frame 102A ... First correlation detection signal 102B: second correlation detection signal 102: correlation detection signal 103: error detection signal 104: count completion signal 105: correlation output selection signal 106: frame synchronization signal

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroyuki Imai 1006 Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5K028 AA14 NN01 NN12 NN44 5K047 AA04 CC02 HH01 HH15 HH21 HH54 MM11

Claims (2)

[Claims] An apparatus for generating a frame synchronization signal for detecting a desired time slot existing in each frame of a digital signal subjected to frame multiplexing based on a bit pattern, comprising: a header section for a plurality of time slots in one frame; Correlation detecting means for detecting a correlation by comparing a bit pattern with a preset bit pattern to generate a plurality of correlation detection signals, and synchronizing to generate a frame synchronization signal when all of the plurality of correlation detection signals are received. A frame synchronization signal generation device, comprising: a signal generation unit. 2. The correlation detecting means detects a correlation between a predetermined first bit pattern and a bit pattern of a header portion of a desired time slot, and performs a first
A first correlation detecting means for outputting a correlation detection signal of the following, and detecting a correlation between a predetermined second bit pattern and a header portion of another time slot existing in the same frame as the desired time slot. And a second correlation detection means for outputting a second correlation detection signal, wherein the synchronization signal generation means generates a frame synchronization signal when the first correlation detection signal and the second correlation detection signal are input. The frame synchronization signal generation device according to claim 1, wherein the frame synchronization signal generation device generates the frame synchronization signal.