JP2000252814A - Information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce overhead due to reconfiguration and to shorten the information processing time by preparing plural hardware modules and preferentially taking out a hardware module in a shape which matches the hardware constitutable region of the programmable logic circuit. SOLUTION: A hardware module acquiring means 300 obtains a hardware module to perform the same process with a software module from a storage device 200, by using the identification code described in the header part of an application program 100. Then the module acquiring means 300 reconfigures a circuit, having actualized the obtained hardware module on the programmable logic circuit 16. Then an execution module determining means 600 determines which module of hardware by the programmable logic circuit 16 and software by a CPU11 processing is to be used to perform the processing for each processing module and performs the processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system including a programmable logic circuit capable of reconfiguring a desired logic in accordance with circuit information describing a logic circuit, and more particularly to a plurality of processes described in a programming language. The present invention relates to an information processing system of a type in which at least a part of a series of processes configured by modules is replaced with a hardware circuit reconfigured on a partially rewritable programmable logic circuit and executed.

More specifically, the present invention relates to an information processing system of a type in which each processing module is determined to be executed by a software module or a hardware module and is processed, by reconfiguring a program logic circuit. The present invention relates to an information processing system that reduces overhead and reduces the processing time of the entire processing module.

[0003]

2. Description of the Related Art With the recent technological innovation, various information processing devices have been researched and developed, and have been widely used. Generally, information processing equipment is a semiconductor circuit component (LSI: Large) integrated by advanced semiconductor technology.
Scale Integration). Some LSIs include custom ICs optimally designed for specific applications, that is, ASICs (Apps).
ligation Specific Integra
ted Circuit) technology.

In the recent ASIC field, a field programmable gate array (FPGA: Field Program) has been developed in order to further shorten the product development period.
mmable Gate Array) or a programmable logic device (PLD: Programmable Logic Device)
Able Logic Device), CPLD (C
omple Programmable Logic
Devices, such as programmable logic circuit devices, have begun to be widely used.

[0005] This type of programmable logic circuit device is
By reading circuit information describing a logic circuit into the logic circuit device, the connection between the internal logic circuits and the logic circuits can be freely configured. As a result, it is possible to shorten the time required to manufacture an integrated circuit, which conventionally required several weeks to several months after the completion of circuit design. In particular, the programmable logic device disclosed in U.S. Pat. No. 4,700,187 has an electrically reconfigurable configuration, and a circuit once manufactured can be freely changed as necessary. Has the advantage of being able to reconfigure circuits, and is becoming more and more widely used.

A programmable logic circuit device called an FPGA is a device that can reconfigure a desired logic circuit by externally writing a bit stream that controls a switch connecting logic gates and wiring. Storage means for holding data of switch control between the internal circuit configuration and the logic gate is provided in the device, and devices having various operating characteristics are provided in the art depending on the type of the storage means.

As storage means for holding switch control data between logic gates or wirings, an antifuse type, EEPROM (Electrically) is used.
Erasable and Programmable
Read Only Memory) type, SRA
M (Static Random Access Me)
memory) type.

In the SRAM type, a volatile memory is connected to the gate of a transistor serving as a switch.
Although the area occupied by the SRAM memory in the rewritable device is large, the rewriting time is shorter than other types,
Since the contents of the memory can be rewritten by specifying the address, the logic can be reconfigured during the operation of the system. Furthermore, the function of continuing the operation of the part that is not reconfigured is realized, and partial rewriting in the device is enabled.

FP that can be partially rewritten in real time
GA is, in particular, DR-FPGA (Dynamicall).
y Reconfigurable Field Pr
This is referred to as an “ommable gate array”. X-Links XC6200 series and Virtex series of DR-FPGA,
AT6000 AT6000 series and AT40K
Series, ORCA by Lucent Technology, USA
The 3C / 3T series and the like are already commercially available.

[0010] The complexity of processing required for recent logic circuits has increased, and the circuit scale has increased to a scale that cannot be realized with a single programmable logic circuit device alone. As one method for solving this problem, it has been considered to realize different logic circuits at different times by reconfiguring the programmable logic circuit device during the processing.

According to this method, even if the size of a circuit that can be built in is limited as in an extremely miniaturized information processing system such as a mobile device, various processing can be performed without increasing the number of circuit components. Has the advantage that it can be implemented as hardware by a programmable logic circuit and executed at relatively high speed.

However, when the programmable logic device is reconfigured, there is a disadvantage that extra time is required to read the circuit information again. In order to reconfigure the logic device in the middle of the process, the process is temporarily suspended, the data at that time is temporarily stored in a storage device external to the programmable logic circuit device, and new circuit information is read and re-read. A series of extra processes are needed to configure and input data before reconstruction and new data accompanying the reconstruction.

To solve the above problems associated with the reconfiguration of programmable logic devices, a data book “CONFIGUABLE LOGI” provided by Atmel, USA
C "and a data book" TH provided by Xilinx Corporation of the United States.
The programmable logic circuit device described in “E PROGRAMMABLE LOGIC” (U.S. version) has a data storage device for storing data when performing reconfiguration. By reading a part of the information and performing a partial reconfiguration, the time required to reconfigure the logical device is minimized.

However, in order to suitably apply such a partially reconfigurable programmable logic circuit to an information processing system, a process executed on the information processing system must be performed as follows.
It is necessary to establish a technique for separating hardware processing performed by a programmable logic circuit from software processing performed by a fixed logic circuit device whose circuit configuration such as a microprocessor cannot be changed.

As a method of solving such a problem relating to the separation of processing, there have been proposed some techniques for making a part of an application into hardware by using a reconfigurable function of a programmable logic circuit. The reason that part of the application is left to hardware processing using a program logic circuit device instead of software processing using a general-purpose processor depends on the reason that the latter has a higher processing speed than the former.

For example, Japanese Patent Application Laid-Open No. Hei 9-74556 describes a method of downloading a part of an application via a network. That is,
According to the publication, as an application using a programmable logic circuit, it is conceivable that encoded image data and a decoding program are received via a network, and the image is reproduced by decoding using both software and the programmable logic circuit. I have. FIG. 11 shows a schematic configuration of an image reproducing apparatus disclosed in the publication.
Hereinafter, the image reproducing apparatus will be described with reference to FIG.

The image reproducing apparatus includes a receiving unit for downloading a program for reconstructing a moving image decoding unit and encoded moving image data via a network, and transmitting the received data depending on whether the received data is a program or moving image data. Switching means for switching the destination, a video decoding unit capable of reconfiguring the processing system, a program conversion unit for converting a received program into a format changeable to the configuration of the video decoding unit, and a reception unit and switching means And a control unit for controlling the program conversion unit and the video decoding unit.

The program conversion unit converts a received program into a format that can change the configuration of the moving picture decoding unit (that is, a part that is converted into hardware), and a second program that is executed by the control unit during reproduction of the moving picture. A dividing unit that divides the first program part into a format that can change the configuration of the moving picture decoding unit (a hardware compiler); A second conversion unit (software compiler) for converting the second program portion into a format in which the control unit can decode and execute the processing.

The video decoding unit includes an inverse quantization unit that can change the content of the inverse quantization process and an inverse transform unit that can change the content of the inverse transform process. The inverse quantization unit inversely quantizes the quantized image data, and the inverse transform unit inversely transforms the transformed image data.

Next, an operation procedure of the image reproducing apparatus will be described.

When a moving picture reproducing program and encoded moving picture data are input via a network, a receiving section first receives a reproducing algorithm program described in a logical description language.

The received data is transmitted to a program conversion unit, and is divided by a division unit into a hardware processing unit and a software processing unit.

The hardware processing section is passed to a first conversion section, where it is converted into a format (bit stream) in which a programmable logic circuit device (FPGA) can be rewritten. Then, the inverse quantization unit and the inverse transform unit are rewritten.

On the other hand, the software processing part is passed to the second converter, converted into an executable form that can be processed by the processor, and then passed to the controller.

When moving image data is sent to the reconstructed image reproducing apparatus via the network, the moving image data is received by the receiving unit, transmitted to the moving image decoding unit by the switching unit, and output as decoded data.

As described above, the inverse quantization unit and the inverse transform unit are represented by F
By configuring the processing program such as PGA with a changeable element, the hardware of the video decoding unit is adapted to the optimum processing capability.

Japanese Patent Application Laid-Open No. 6-301522 discloses a system configuration method of a computer including a fixed unit whose circuit configuration cannot be changed and a variable unit whose circuit configuration can be changed like a programmable logic circuit. . This gazette proposes that a plurality of programs be used to configure hardware on a programmable logic circuit. Hereinafter, this computer system will be described with reference to FIG.

As shown in FIG. 12, a source program executed by a computer refers to an object code by referring to a library in which information on the configuration of a fixed part and information on a circuit that can be configured by a variable part are stored. Is converted to hardware configuration data.

That is, the compiler analyzes the flow of the source program and detects the frequency of the function. Based on the detection frequency, a function with a large number of calls is determined as a function to be processed by hardware, and hardware configuration data is created and output. Next, a code indicating that a portion determined to be processed by hardware is processed by a predetermined variable portion is added to a portion processed by the remaining software,
Create and output object code.

The computer system uses a fixed unit whose circuit configuration cannot be changed and a variable unit configured by hardware configuration data to execute processing according to the object code. In this way, the speed of the entire process is increased by implementing several functions having a large number of calls at the time of compilation at the time of compiling.

Also, Nikkei Open System August 1997
An article published on pages 213 to 219 of the monthly issue "Internet server operation ISP and V
"An AN provider provides services" proposes a case where a plurality of servers are accessed via a network.

This article describes the Internet and closed-V services as a service called network outsourcing.
It deals with AN. In this book, access to various servers such as a mail server and a name server, which are essential servers for the Internet, is explained in detail.

In order to access the server faster, it is better to access all the programs at once and download from the program that has been accessed earlier than to access each one of the programs used. It is already known in the art that the total access time is low. Therefore, in a situation where the program is stored in a plurality of servers, the program accesses the program according to the method described above,
Downloading is becoming more common. For example, programs are distributed and stored in a plurality of servers in order to classify and organize program data, have different jurisdictions, or reduce network traffic and server load.

However, in each of the conventional examples described above, the following problem remains when a part of the processing is performed by the programmable logic circuit.

A hardware module that realizes a part of the processing is reconfigured on a programmable device.
That is, when a hardware module is developed as a physical circuit, not only does a predetermined number of cells on a device be consumed, but also a cell region having a certain predetermined shape is occupied. Therefore, in order to perform partial rewriting on a programmable device, it is not enough that an empty area of a size (that is, gate scale) in which a hardware module can be written exists on the device. It must be able to completely contain the shape.

Even if the size of the free area (ie, the gate size) on the programmable device is different from the hardware
Even if the size of the module is exceeded, partial rewriting cannot be performed if the module does not conform to a shape that can constitute a hardware module. In such a case, the reconfiguration operation is not performed until another process on the device is completed, the used cell area is released, and an empty area is secured to match the shape of the newly reconfigured hardware module. I will be kept waiting.

As a result, overhead occurs in the reconstruction time. In addition, as processing modules whose shape does not conform to the free area follow, the overhead further increases, and a large amount of time is consumed in addition to the time required for processing as a whole. In addition, it is difficult to say that such a usage form of the programmable device effectively utilizes the cell resources of the device.

[0038]

SUMMARY OF THE INVENTION An object of the present invention is to provide an excellent information processing system of a type including a programmable logic circuit capable of reconfiguring a desired logic in accordance with circuit information describing a logic circuit. is there.

A further object of the present invention is to provide a hardware circuit in which at least a part of a series of processes constituted by a plurality of processing modules described in a program language is reconfigured on a partially rewritable programmable logic circuit. An object of the present invention is to provide an excellent information processing system of a type which is executed by replacing the above.

It is a further object of the present invention to provide an excellent information processing system of the type in which each processing module is executed by determining whether it should be executed by a software module or a hardware module.

A further object of the present invention is to provide an excellent information processing system capable of reducing the overhead due to the reconfiguration of the program logic circuit and shortening the processing time of the entire processing module.

A further object of the present invention is to provide a programmable
The free space on the device is sufficient, but the inconsistency in shape makes it impossible to reconfigure the hardware module, thereby reducing the overhead that occurs and also reducing the overall processing time. An object of the present invention is to provide an excellent information processing system that can be shortened.

[0043]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and a first aspect of the present invention is an information processing system for executing a series of processing including a plurality of processing modules. Program receiving means for receiving a series of processing in the form of a program in which each processing module is constituted by a software module described in a programming language; a processor capable of executing the software module; A programmable logic circuit that can be partially rewritten according to the hardware module, and storage means for storing a hardware module described by circuit information for reconfiguring the same processing as the software module on the programmable logic circuit; Among the processing modules that make up a series of processing, Execution module determining means for determining what should be executed by the module, and hardware module obtaining means for extracting the hardware module determined by the execution module determining means from the storage means and reconfiguring the module on the programmable logic circuit. The storage means prepares a plurality of hardware modules that realize the same processing but have different shapes when reconfigured on the programmable logic circuit, and the hardware module acquisition means includes This is an information processing system characterized in that a hardware module having a shape conforming to a hardware configurable area is preferentially extracted.

Here, the hardware modules stored in the storage means may be represented by a rectangular shape.

The shape of the hardware configurable area may be defined by the number of logic cells in the horizontal and vertical directions on the programmable logic circuit.

A second aspect of the present invention is a method for managing a hardware module for reconfiguring a partially rewritable programmable logic circuit, which realizes the same processing. When reconfiguring on a programmable logic circuit, multiple hardware
Hardware that features a module
This is a method for managing modules.

A third aspect of the present invention is an apparatus for managing a hardware module for reconfiguring a partially rewritable programmable logic circuit, and realizes the same processing. When reconfiguring on a programmable logic circuit, multiple hardware
Means for storing a module, and means for preferentially extracting a hardware module having a shape conforming to the hardware configurable area of the programmable logic circuit from the storage means. It is a device for management.

[0048]

The information processing system according to the present invention executes a series of processing including a plurality of processing modules. Each processing module is constituted by a software module described in a programming language, and the information processing system receives a series of processing in the form of a so-called software program.

The information processing system includes a processor capable of executing a software module, and a programmable logic circuit partially rewritable according to a hardware module described by circuit information. When executing a series of processing, it is determined whether each processing module is to be executed as a software module or a hardware module, and is executed.

Further, the information processing system includes storage means for storing a hardware module described by circuit information for reconfiguring the same processing as the software module on the programmable logic circuit.

When reconfigured on a programmable logic circuit, a hardware module uses a predetermined number of cells and occupies a cell region having a predetermined shape. In the present invention, a plurality of hardware modules which realize the same processing for each software module but have different shapes when reconfigured on the programmable logic circuit are prepared in the storage means.

When the partial rewriting of the programmable logic circuit is performed, of a plurality of hardware modules that realize the same processing but have different shapes, the shape of an empty area in the programmable logic circuit, that is, the shape of the hardware configurable area is changed. Matching items are given priority.

In order to perform partial rewriting on a programmable device, it is not sufficient that there is an empty area on the device in which a hardware module can be written, and the empty area completely changes the shape of the hardware module. Must be able to be included. In other words, the reconfiguration operation is delayed until other processes on the programmable logic circuit are completed and the used cells are released, and a free area sufficient for the shape of the hardware module to be reconfigured is secured. (See above).

According to the present invention, a plurality of hardware modules realizing the same processing but having different shapes are prepared, and the hardware module which conforms to the shape of the empty area on the programmable logic circuit is preferentially used. Since it is used, the overhead caused by the inability to reconfigure the hardware module can be minimized. As a result, the overall processing time can be reduced.

Further, the shape of the hardware module is represented by the smallest rectangle including the occupied cell area. This rectangle can be defined only by the number of logic cells in each of the horizontal and vertical directions. That is, whether or not the hardware module fits in the hardware module configurable area can be determined based on an extremely small amount of data. In addition, since the logic cells of the programmable logic circuit can be used efficiently, the execution of the processing and the configuration of the device can be performed in parallel, and the overall processing time can be reduced. .

Still other objects, features and advantages of the present invention are:
It will become apparent from the following more detailed description based on the embodiments of the present invention and the accompanying drawings.

[0057]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 schematically shows a hardware configuration of an information processing system 10 suitable for realizing the present invention.

The information processing system 10 is, for example, a general-purpose computer system called a “workstation” or a “personal computer”, and an example thereof is a PC / AT compatible machine of IBM Corporation in the United States or a successor thereto. This type of system 10 is OADG (PC Op
en Architecture Development
r's Group) specification and, for example, "Windows 95/98 / NT" of Microsoft Corporation in the United States is installed as an operating system (OS). Hereinafter, each unit in the information processing system 10 will be described.

The CPU (Central Processing Unit) which is the main controller of the system 10
nit) 11 is an operating system (OS)
Various processes are executed under the control of.

The "processing" referred to here is a series of processing including a plurality of processing modules. Such a series of processing,
Usually, each processing module is supplied to the information processing system 10 in the form of a “program” composed of software modules described in a programming language.

The circuit logic of the CPU 11 is fixed and cannot be reconfigured. Therefore, the CPU 11 executes only the software modules described in the program language among the processing modules, and does not execute the hardware modules as described later. The CPU 11 may be, for example, “Pentium II” manufactured by Intel Corporation in the United States.

The information processing system 10 of the present embodiment has a PCI (Peripheral Component) as a local bus for connecting each peripheral device locally.
An interconnect bus 14 is provided.
This PCI bus and the host bus 11B directly connected to its own external pin of the CPU 11 are interconnected via a bus bridge 13 composed of a chipset.

The chip set 13 of this embodiment is a
The configuration includes a data buffer for absorbing a difference in data transfer speed between 1B and 14, and a memory controller for controlling an access operation to the main storage memory 12.

The main memory 12 is a writable memory, and usually includes a plurality of DRAMs (Dynamics).
Random Access Memory) chip. The main storage memory 12 stores a BIOS (Basi
c Input / Output System (basic input / output system), a device driver, an OS, and a program code for realizing various processes such as an application program, and for temporarily storing work data during the process. Used.

The PCI bus 14 is a bus capable of relatively high-speed data transfer (bus width 32/64 bits, maximum operating frequency 33/66 MHz, maximum data transfer rate 13
2/264 Mbps), and various interface adapters for realizing an interface protocol with the PCI bus 14 are connected. The PCI architecture originates from the proposal of Intel Corporation in the United States, and has a so-called PnP (plug and play) function.

In this embodiment, that is, in FIG. 1, a hard disk interface 17, a communication interface 19, and a programmable logic circuit interface 15 are listed as interface adapters connected to the PCI bus 14.

Hard Disk Interface 17
Is an interface for connecting a large-capacity external storage device such as the hard disk device 18;
(Integrated Drive Electro
nics) and SCSI (Small Computer)
Specifications such as System Interface are standard in the art. Hereinafter, the hard disk drive 18 in the system 10 is also referred to as a “local disk”.

The communication interface 19 is a LAN (L
This is an adapter for connecting to a network 20 external to the system 10, such as the local area network or the Internet.

A plurality of external devices are usually connected to the network 20. An example of the external device is a server such as a file server or a print server that provides various resource services to the information processing system 10. In FIG. 1, a storage device 21 is connected to the network 20. The storage device 21 is, for example, a large-capacity hard disk device provided by a file server or the like.
The system 10 can transparently access the disk to the storage device 21. Hereinafter, the hard disk drive 21 on the network 20 will be referred to as a “network disk” to distinguish it from a “local disk”.

The programmable logic circuit interface 15 is an adapter for connecting the programmable logic circuit 16 to the system 10. The programmable logic circuit 16 is provided, for example, in a form mounted on an “adapter card”. The programmable logic circuit 16 is a type of device capable of performing a partial rewrite operation as described later. Hereinafter, the hardware partially written on the programmable logic circuit 16 is referred to as a “hardware module”. The hardware module is usually described in the form of circuit information for reconfiguring the logic circuit 16, is stored in a predetermined storage location, and is appropriately taken out and used.

In this embodiment, a number of hardware modules described as circuit information are stored in the local disk 18 or the network 2 in the information processing system 10.
0 on the network disk 21.
The programmable logic circuit 16 includes a local
Has memory. When performing partial rewriting,
Necessary hardware modules are transferred from the local disk 18 or the network disk 21 to the local disk.
Once downloaded to the memory, rewrite processing is performed.
The procedure of the partial rewriting operation of the logic circuit 16 will be described later in detail.

Note that in order to configure the information processing system 10, many hardware components and the like other than those shown in FIG. 1 are required. However, since these are well known to those skilled in the art and do not constitute the gist of the present invention, they are omitted in this specification. Also, it should be noted that only some of the connections between the hardware blocks in the drawings are shown in order to avoid complication of the drawings.

Next, the internal structure of the programmable logic circuit 16 will be described.

FIG. 2 logically illustrates the structure of the programmable logic circuit 16. As shown in the figure, the programmable logic circuit 16 includes a configuration memory 160 for storing circuit information and a circuit element 1
64. The circuit element is an aggregate including a logic cell 161, a wiring region 164, and an input / output terminal 163, as described later.

FIG. 3 schematically shows a physical structure in a chip constituting the programmable logic circuit 16. As shown in FIG.
.. Are arranged in a matrix. The wiring region 162 is laid in a lattice shape so as to run between the logic cells 161. A number of input / output terminals 163... For inputting / outputting electric signal data to / from the logic circuit 16 are arranged in a row at the periphery of the chip.

Configuration memory 160
Is storage means for writing circuit information in the logic cell 161 and the wiring area 162, and is an SRAM, a DRAM,
Rewritable memory element.

An address is allocated to the configuration memory 160. When data describing new circuit information is stored at a certain address, the circuit configuration in the logic cell 161 corresponding to the address and the logic cell 16
1 and the wiring area 16 for connecting the input / output terminals 163 to each other
2 are reconfigured according to this new circuit information.

As shown in FIG. 2, when data to be processed is input to a circuit element reconfigured and formed in the programmable logic circuit 16, the result of the processing is output. I have.

A series of operations for reconfiguring the circuit configuration of the programmable logic circuit 16 is called “configuration”. In the programmable logic circuit 16 according to this embodiment, by rewriting only a part of the configuration memory 160, the circuit can be partially reconfigured even when the programmable logic circuit 16 is operating. That is, a partial rewriting function is provided.

FIG. 4 schematically shows a mechanism in which the information processing system 10 executes a series of processing including a plurality of processing modules. However, a series of processes is supplied to the information processing system 10 in the form of a program described in a programming language, that is, an application program 100 (for example, installed in the hard disk device 18). .

The application program 100
A series of processes to be executed can be divided into multiple processes,
One module is formed for each of the divided processes. This module is referred to as a “processing module” in this specification.

Each processing module constituting the application program 100 is initially a format in which the CPU 11 can execute processing, that is, a software program described in a programming language. A software program for each processing module
In this specification, it is called a “software module”. In other words, the application program 100
It can be said that it is an aggregate of a plurality of software modules.

The same processing as performed by each software module can be executed as hardware configured on the programmable logic circuit 16. The hardware processing by the programmable logic circuit 16 generally includes
It is faster than the corresponding software processing.

A unit module describing circuit information for reconfiguring hardware corresponding to a software module on the program logic circuit 16 is referred to as a “hardware module” in this specification. The storage device 200 in FIG. 4 stores hardware modules that realize the same processing as each software module that configures the application program 100. However, the entity of the storage device 200 is the local disk 18 or the network disk 2 shown in FIG.
I want to be grasped as 1.

Here, the application program 1
The structure of 00 will be described in more detail.

FIG. 5 schematically shows the configuration of the application program 100. As shown in FIG. 1, the application program 100 includes a header section and a main body section.

As described above, the main body is composed of a set of a plurality of software modules. In the header portion, an identification code for each hardware module corresponding to each software module is described.

In this embodiment, the hardware module stores not only the circuit information for reconfiguring the same processing as the corresponding software module on the programmable logic circuit 16 but also the circuit information on the programmable logic circuit 16. It describes the shape of the cell area occupied when reconstructed. Here, the shape of the hardware module is expressed as a rectangle that completely covers the occupied cell area. Therefore, the shape is PFU (Programmable F) in each of the horizontal and vertical directions of the rectangle.
(unit number), that is, the number of cells, so that only a small amount of data is required.

FIG. 6 illustrates how a hardware module is represented by a rectangle. As shown in the figure, the circuit itself constituted by the hardware module has a complicated polygonal shape, and if this is geometrically defined, the data size becomes large and the processing becomes complicated. Therefore, the shape of the hardware module is represented by a minimum rectangle including the constituent circuits of the hardware module, and the shape of the hardware module is defined by the number of cells in the horizontal and vertical directions of the rectangle.

It is preferable that the identification numbers of the respective hardware modules are given so that the correspondence relation with the software modules performing the same processing becomes clear.
In the example shown in FIG. 4 and FIG. 5, the identification code of the hardware module corresponding to each software module is described in the header part by the sequence number according to the processing execution order on the application program 100. In such a case, the identification number of the hardware module corresponding to the processing module used repeatedly is repeatedly described in the header portion.

Returning to FIG. 4, the information processing system 10
The description of the mechanism for executing the application program 100 will be continued above.

Hardware module acquisition means 300
The execution module determining means 600 is deeply involved in the operation of executing the processing module as a hardware module. These means 300 and 600 can be implemented, for example, in the form of a part of the function of the OS installed on the information processing system 10.

Hardware module acquisition means 300
Acquires from the storage device 200 a hardware module that performs the same processing as that performed by the software module, using the identification code described in the header section of the application program 100. Then, the hardware module acquisition unit 300 reconfigures the circuit that has realized the acquired hardware module on the programmable logic circuit 16.

As shown in FIG. 4, the hardware module acquisition means 300 includes an acquisition request sending means 310 and an acquisition reconfiguration means 320. When acquiring a hardware module from the recording device 200, the acquisition request sending unit 310 issues an acquisition request for all necessary hardware modules.

Whether the execution module is a software module by the CPU 11 or a hardware module by the programmable logic circuit 16 can be determined when the program is executed. In this case, the acquisition request sending unit 310 sends a hardware module acquisition request including the identification codes of all the hardware modules described in the header of the application program 100.

Further, the execution module can be determined before the execution of the program 100. In this case, the acquisition request sending unit 310 sends a hardware module acquisition request including the identification code of the hardware module determined to be executed by the hardware module processing.

Hardware module acquisition means 300
The acquisition / reconstruction means 320 within the hardware module recognizes the information of the hardware module acquired from the storage means 200 by the identification code added thereto, and recognizes that the hardware module has not yet been acquired in the system 10. After confirmation, the circuit realizing the hardware module is reconfigured on the programmable logic circuit 16. At this time, the identification code of the reconfigured hardware module is recorded in the identification code recording means 800 and the hardware device 200 (for example, the hard disk device 18 or the main storage memory 12) in the system 10 stores the hardware code. -Store module information.

On the other hand, the application program 10
The software processing by the software module 0 is executed by the CPU 11.

Actual application program 10
0, the execution module determining means 600
Determines for each processing module whether the processing is performed by hardware or software, and executes the processing.

Although not shown in FIG. 4, the execution module determining means 600 may be provided with a selection condition setting means. The selection condition setting means presupposes various selection condition items such as a processing time by each of the software module and the hardware module, a memory consumption amount, a reconfiguration time of the programmable logic circuit 16, and selects one or more of the selection condition items. An execution module selection condition consisting of a combination of a plurality of condition items is set. Execution module determining means 600
The execution module can appropriately determine an execution module by evaluating the selection condition.

Next, a procedure for executing a processing module by a hardware module will be described in detail. FIG.
Shows this procedure in the form of a flowchart.
Hereinafter, each step of this flowchart will be described.

However, the application program 100 in which the processing is executed has four processing modules A, B, C, and D executed as hardware modules.
And the respective processing modules are executed in the order of A → B → C → B → D (note that the processing B is called again after the execution of the processing C after the execution is once completed. Want). Also, it is assumed that hardware processing by the programmable logic circuit 16 for which configuration is completed is faster than corresponding software processing.

As described above, the hardware module obtaining means 300 and the execution module determining means 600
Are each implemented by one function in the OS operating on the information processing system 10, that is, implemented as software. Therefore, this operation is executed by the OS in response to the start of the application program 100.

When the application program 100 is started, the identification code (see FIG. 5) of the hardware module described in the header section of the program 100 is read (step S11). As described above, the identification code includes circuit information for reconfiguring the same processing as each software module on the programmable logic circuit 16 and information regarding the shape of the reconfigured hardware module.

Here, the shape of the hardware module is represented by a rectangle which completely reconstructs the hardware module on the programmable logic circuit 16 and completely occupies the cell area occupied by the hardware module. It is defined by the number of cells (PFU) in each of the horizontal and vertical directions (described above).

The shape of a hardware module for performing the same processing is not limited to a single shape, but may be plural. In the present embodiment, a plurality of hardware modules having different shapes but executing the same processing are prepared (described later).

The execution of the application program 100 proceeds in such a manner that each processing module is sequentially executed according to a scheduled order. Then, when reaching the processing part by the hardware module, the necessary hardware module is configured on the programmable logic circuit 16. The portion surrounded by the broken line in FIG. 7 corresponds to this.

In this embodiment, the application program 100 includes A, B, and B as processing modules that are determined to be executed as hardware modules.
C and D, and the execution order of the processing modules is specified as A → B → C → B → D (described above).

First, in step S12, a hardware module (A) for implementing the process A is configured on the programmable logic circuit 16. Next, in step S13, a hardware module (B) that implements the process B is configured on the programmable logic circuit 16.

FIG. 8 shows that each hardware module for realizing the processing A and the processing B is a programmable logic circuit 1
6 is schematically shown on the screen 6. In the figure, the logic cell areas corresponding to the hardware modules (A) and (B) are indicated by reference numerals 222 and 221 respectively. Further, an empty area at this time, that is, an area where a hardware module can be configured yet is indicated by reference numeral 223.

When step S13 for configuring the hardware module (B) is completed, the hardware acquisition means 300 acquires the hardware module (C) necessary for the next processing C from the storage means 200. Try.

In this embodiment, as shown in FIG. 8, three hardware modules <Ca>, <Cb>, and <Cc> having different shapes for executing the same process C.
> Are prepared in the storage device 200. However, for convenience of explanation, <Ca> is a conventionally prepared hardware module, and the remaining <Cb>
And <Cc> are hardware modules newly added in the present invention. As shown, each hardware module <Ca>, <Cb>, and <Cb>
The rectangular shapes of C−c> are 6 × 4, 4 × 6, 3 × 8, respectively.
It is.

On the other hand, the hardware
The shape of the module configurable area 223 is 4 × 7.
Therefore, the hardware module acquisition means 300
Determines that the only hardware module that can be configured is <Cc>, acquires this, and configures the hardware module configurable area 223 (step S16). When the configuration is completed, the process C is executed after the execution of the process B is completed.

On the other hand, the processes A and B for which the configuration has already been completed are executed simultaneously with the start of the configuration of the hardware module <Cc> (steps S14 and S1).
5). When step S14 ends, the hardware module (A) becomes unnecessary, so the used cell area 222 is released and becomes a hardware module configurable area. However, since the process B is called again after executing the process C (described above), the used cell area 221 is not released when step S15 ends.

FIG. 9 schematically shows the state of the programmable logic circuit 16 when each hardware module for realizing the processing C is configured on the programmable logic circuit 16. As shown in the figure, the hardware module (B) and <C-c
Logic circuits corresponding to each of the cell regions 221
And 226. In addition, the cell area 222 related to the processing A that has already been executed is released, and as a result, a hardware module configurable area 227 is newly formed.

When step S16 for performing the configuration of the hardware module (C) is completed, the hardware obtaining means 300 stores the data in the storage means 20.
From 0, an attempt is made to acquire a hardware module (D) necessary for the next process D.

In the present embodiment, as shown in FIG. 9, three hardware modules <Da>, <Db>, and <Dc> having different shapes for executing the same process D.
> Are prepared in the storage device 200. However, for convenience of explanation, <Da> is a hardware module prepared conventionally, and the remaining <Db>
And <Dc> are hardware modules newly added in the present invention. As shown, each hardware module <Da>, <Db>, and <
D-c> are 6 × 2, 4 × 3, 3 × 4, respectively.
It is.

On the other hand, the hardware
The shape of the module configurable area 227 is 4 × 3.
Therefore, the hardware module acquisition means 300
Determines that the only configurable hardware module is <Db>, acquires this, and configures the hardware configurable cell area 227 (step S17).

When the configuration of the hardware module <D-b> in step S17 is started, the processing A (step S14) has been completed. Therefore, the processing B (step S14) is performed simultaneously with the start of step S17.
15) is executed.

Also, the hardware module <Db
When the configuration of <> is completed and the execution of the process B is completed, the execution of the process C is started by the already configured hardware module <Cb> (step S28).

When the processing C is completed, the hardware module (B) occupying the cell area occupies the processing B
Is executed again (step S19), and then the process D is executed by the hardware module <Db> (step S20).

FIG. 10 shows each hardware in the order of process A → process B → process C → process B → process D according to this embodiment.
The processing flow in which the module is executed is displayed in chronological order while comparing with the conventional example. That is, FIG. 3A shows the present embodiment, and FIG. 3B shows the conventional example.
However, in the conventional example, for each of process C and process D,
The hardware modules <Ca> and <D-
It is assumed that only one of a> is prepared in the storage device 200 (described above).

In FIG. 10, the time required for each process is represented by a band having a length corresponding to time. In the figure, uppercase letters A, B, C, D and lowercase letter "t" indicating each processing are shown.
The combination of prefixes consisting of indicates the time required to configure the corresponding hardware module. In addition, capital letters A, B, C, D indicating each processing
The combination of a prefix consisting of and a capital letter "T" indicates the time required for each process by the configured hardware module. However, tC and TC
Is the required time for the hardware module <Cb> in the embodiment (a), and
Here, each required time for the hardware module <Ca> is shown. Similarly, tD and TD are the hardware module <Db> in the embodiment (a).
In the conventional example (b), each required time is related to the hardware module <Da>.

FIG. 10 will be described below in chronological order.

First, the processing flow in this embodiment will be described. At time t0, the configuration of the hardware module (A) necessary for the process A starts. Next, at time t1, the hardware
When the configuration of the module (A) is completed, the configuration of the hardware module (B) necessary for the process B starts.

At time t2, when the configuration of the hardware module (B) is completed, the hardware module configurable area 223 (see FIG. 8) among the hardware modules required for the processing C is set. Selectively acquire <Cb> that can be assigned, and start configuration. At the same time, the processing A is started by the hardware module (A).

At time t3, the configuration of the hardware module (C) ends. At this point, there is no cell area on the programmable logic circuit 16 where a hardware module required for the processing D can be configured. In the present embodiment, three hardware modules <Da>, <Db>, and <Dc> having different shapes capable of executing the process D are prepared. Logic circuit 16
Can not be allocated to the free space. Therefore, the configuration operation waits until the other hardware module being executed ends and the cell area is released.

At the time t4, when the processing A is completed,
The cell area used by the hardware module (A) is released, and a new hardware module configurable area 227 is generated (see FIG. 9). Of the hardware modules that execute the process D, <Db> that can be assigned to the hardware module configurable area 227 is selectively acquired, and the configuration is started. At the same time as the completion of the process A, the process B starts using the hardware module (B).

Thereafter, using each hardware module configured on the programmable logic circuit 16, the process C starts at the end of the process B (time t6), and the process B starts at the end of the process C (time t6). At time t8), the process D starts with the end of the process B (time t8).
11) Finally, the process D ends (time t12).

Next, a processing flow in the conventional example will be described. At time t0, the configuration of the hardware module (A) necessary for the process A starts. Next, at time t1, when the configuration of the hardware module (A) ends, the configuration of the hardware module (B) necessary for the process B starts.

At time t2, when the configuration of the hardware module (B) is completed, the processing A is started by the hardware module (A).

Further, a hardware module necessary for the process C executed after the process B must be configured on the programmable logic circuit 16. However, in the conventional example, only <Ca> is prepared as a hardware module for executing the process C. As can be seen with reference to FIG. 8, the hardware module <Ca> has the shape of the number of logic cells 6 × 4, whereas the hardware module configurable area 223 at this point is 4 × 6 and cannot be configured.

As a result, after the processing B is completed, the cell area used by the hardware module (B) is released, and a sufficient hardware module configurable area for the hardware module <Ca> is obtained. Until the possible time t6, the configuration of <Ca> is waited.

At the time t7, when the configuration of the hardware module <Ca> is completed, the process C is started by using this.

At the time t9, when the process C is completed, the hardware module <Ca> is deleted from the programmable logic circuit 16, and the hardware module (B) required for the process B is again deleted. Start configuration. It should also be noted that in the prior art, the hardware module (B) must be configured twice.

Next, at time t10, when the configuration of the hardware module (B) is completed, the processing B is started by using this.

Next, when the processing B is completed at time t13, the hardware module (B) is deleted from the programmable logic circuit 16 again, and the hardware module <Da> required for the next processing D is performed. Start configuration. In the conventional example, since only <Da> is prepared as a hardware module for processing D, the configuration of <Da> is continued until the cell area used by the hardware module (B) is released. It is important to pay attention to the fact that the application will be awaited.

Next, at time t14, when the configuration of the hardware module <Da> ends, the processing D starts. Then, at time t15, the process D using this ends.

As described above, in the conventional example, unlike the case of this embodiment, at time t2 and t4, the hardware modules <C required for each of the processing C and the processing D are different.
-A> and <Da> cannot be performed concurrently with the execution of the processing A and the processing B. Further, the hardware module (B) required for the process B must be reconfigured at t9.

Such a loss of processing time in the conventional example is such that a hardware module necessary for the next processing is acceptable in a cell size within a hardware module configurable area on the programmable logic circuit 16. However, it was caused because it could not fit in shape. As a result, the hardware modules (B), <Ca>, <
The processing by the hardware module takes a long time by the sum of the respective configuration times of D-a>.

In the example shown in FIG. 10, A → B → C → B →
D, a total of five processes were performed. As the number of processes increases, the difference in processing time loss between the present embodiment and the conventional example will increase. That is, it can be understood that the present invention is a very effective method for reducing the overall processing time. The present invention also makes efficient use of the hardware module configurable area on the programmable logic circuit, that is, the cell resources.

In the example shown in FIG. 10, only one type of hardware module (B) is required for the processing B. The size of the hardware module (A) required for the process A is excessively large, and both the hardware modules (A) and (B) are simultaneously connected to the programmable logic circuit 16.
Assuming a situation where the above configuration cannot be performed, processing B will be a bottleneck and a loss of processing time will occur as in the conventional example.

In the example shown in FIG. 10, the execution time TA of the process A is longer than the configuration time tC of the hardware module <Cb>.
It is assumed that the execution time TB of the process B is longer than the configuration time tD of the hardware module <Db>. Conversely, the execution time T of the process A
The configuration time tC of the hardware module <Cb> is longer than the configuration time A, and the hardware module <Db is longer than the execution time TB of the process B.
>, The processing B (but the second time) and the processing D are executed after the configuration of the hardware modules <Cb> and <Db>. Will be.

[Supplement] The present invention has been described in detail with reference to the specific embodiments. However, it is obvious that those skilled in the art can modify or substitute the embodiment without departing from the spirit of the present invention. That is, the present invention has been disclosed by way of example, and should not be construed as limiting. In order to determine the gist of the present invention, the claims described at the beginning should be considered.

[0146]

As described above in detail, according to the present invention,
An excellent information processing system including a programmable logic circuit capable of reconfiguring desired logic in accordance with circuit information describing the logic circuit can be provided.

Further, according to the present invention, a hardware circuit in which at least a part of a series of processes constituted by a plurality of processing modules described in a program language is reconfigured on a partially rewritable programmable logic circuit An excellent information processing system of a type that executes in place of the above can be provided.

Further, according to the present invention, it is possible to provide an excellent information processing system of a type in which each processing module is determined to be executed by a software module or a hardware module and is processed.

Further, according to the present invention, it is possible to provide an excellent information processing system capable of reducing the overhead due to the reconfiguration of the program logic circuit and shortening the processing time of the entire processing module.

Also, according to the present invention, the programmable
The free space on the device is sufficient, but the inconsistency in shape makes it impossible to reconfigure the hardware module, thereby reducing the overhead that occurs and also reducing the overall processing time. An excellent information processing system that can be shortened can be provided.

According to the present invention, a plurality of hardware modules realizing the same processing but having different shapes are prepared, and a hardware module which conforms to the shape of the empty area on the programmable logic circuit is preferentially used. Since it is used, the overhead caused by the inability to reconfigure the hardware module can be minimized. As a result, the overall processing time can be reduced.

Further, the shape of the hardware module is represented by the smallest rectangle including the occupied cell area. This rectangle can be defined only by the number of logic cells in each of the horizontal and vertical directions. That is, it is possible to determine whether or not the hardware module fits in the hardware module configurable area based on an extremely small amount of data. At the same time, since the logic cells of the programmable logic circuit can be efficiently used, the execution of the processing and the configuration of the device can be performed in parallel, and the overall processing time can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a hardware configuration of an information processing system 10 suitable for realizing the present invention.

FIG. 2 logically illustrates the structure of a programmable logic circuit 16;

FIG. 3 is a diagram schematically showing a physical structure of a programmable logic circuit 16;

FIG. 4 is a diagram schematically illustrating a state in which the information processing system 10 executes a series of processing including a plurality of processing modules (however, the series of processing is configured by each processing module described in a programming language). The program 10 is supplied to the system 10 in the form of a program to be executed.)

FIG. 5 is a diagram schematically showing a configuration of an application program constituting a series of processes.

FIG. 6 is a diagram schematically illustrating a state in which the shape of a hardware module is represented by a rectangle.

FIG. 7 is a flowchart showing a procedure for executing a processing module by a hardware module.

FIG. 8 is a diagram schematically showing a state in which an optimum one is selected from a plurality of hardware modules having different shapes but executing the same processing and reconfigured on the programmable logic circuit 16; Specifically, FIG. 3 is a diagram illustrating a state in which each hardware module that implements the processing A and the processing B is configured on the programmable logic circuit 16.

FIG. 9 is a diagram schematically showing a state in which an optimum one is selected from a plurality of hardware modules having different shapes but executing the same processing and reconfigured on the programmable logic circuit 16; Specifically, FIG. 4 is a diagram illustrating a state of the programmable logic circuit 16 when each hardware module that implements the process C is configured on the programmable logic circuit 16.

FIG. 10 shows processing A → processing B → processing C according to the present embodiment.
FIG. 11 is a diagram showing a processing flow in which each hardware module is executed in the order of → processing B → processing D in a time-series manner while comparing with a conventional example.

FIG. 11 is a diagram schematically showing a configuration of an image reproducing apparatus disclosed in Japanese Patent Application Laid-Open No. 9-74556.

FIG. 12 is a diagram schematically showing a configuration of a computer system disclosed in Japanese Patent Application Laid-Open No. 6-301522.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Information processing system, 11 ... CPU, 11B ... Host bus, 12 ... Main memory, 13 ... Bus bridge, 14 ... PCI bus, 15 ... Programmable logic circuit interface, 16 ... Programmable logic circuit, 1
7: Hard disk interface, 18: Hard disk drive, 19: Communication interface, 20
... Network, 21 ... Storage device, 100 ... Application program, 160 ... Configuration memory, 161 ... Logic cell, 162 ... Wiring area, 16
Reference numeral 3 represents an input / output terminal, 164 represents a circuit element, 300 represents a hardware module acquisition unit, 310 represents an acquisition request sending unit, 320 represents an acquisition reconfiguration unit, 600 represents an execution module determination unit, and 800 represents an identification code recording unit.

Claims (5)

[Claims] 1. An information processing system for executing a series of processing including a plurality of processing modules, wherein each processing module performs a series of processing in the form of a program constituted by software modules described in a programming language. Receiving a program, a processor capable of executing a software module, a programmable logic circuit partially rewritable according to a hardware module described by circuit information, and performing the same processing as the software module on the programmable logic circuit. Storage means for storing hardware modules described by circuit information to be reconfigured in an execution module; and execution module determination means for determining what should be executed by the hardware module among the processing modules constituting a series of processing. The execution mod Hardware Remove the hardware modules determined by Lumpur determining means from the storing means to reconstruct on the programmable logic circuit,
Module acquisition means, wherein the accumulation means implements the same processing, but prepares a plurality of hardware modules having different shapes when reconfigured on the programmable logic circuit, wherein the hardware module acquisition means comprises: An information processing system, wherein a hardware module having a shape conforming to a hardware configurable area of the programmable logic circuit is preferentially extracted. 2. The hardware stored in said storage means.
The information processing system according to claim 1, wherein the module is represented by a rectangular shape. 3. The configuration according to claim 1, wherein the shape of the hardware configurable area is defined by the number of logic cells in the horizontal and vertical directions on the programmable logic circuit. Information processing system. 4. A method for managing a hardware module for reconfiguring a partially rewritable programmable logic circuit, wherein the same processing is realized, but the shape is reduced by reconfiguring on the programmable logic circuit. A method for managing a hardware module, comprising preparing a plurality of hardware modules different from each other. 5. An apparatus for managing a hardware module for reconfiguring a partially rewritable programmable logic circuit, which realizes the same processing but is reconfigured on the programmable logic circuit. Means for storing a plurality of hardware modules different from each other, and means for preferentially extracting from the storage means a hardware module having a shape conforming to the hardware configurable area of the programmable logic circuit. A device for managing featured hardware modules.