JP3738802B2 - Information processing system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing system in which at least a part of processing can be processed by a programmable logic circuit whose circuit configuration can be reconfigured. In particular, the information processing system can execute efficient processing. It relates to the invention to do.
[0002]
[Prior art]
In the field of digital circuit devices, particularly application-specific integrated circuits (ASICs), programmable logic circuits composed of field programmable gate arrays (FPGAs), programmable logic devices (PLDs), and the like have been developed in order to shorten product development periods. Widely used.
[0003]
These programmable logic circuits can freely configure the connection between the internal logic circuit and the logic circuit by causing them to read circuit information describing the logic circuit. For this reason, the use of a programmable logic circuit device has an advantage that it does not require time for manufacturing an integrated circuit, which conventionally required several weeks to several months after the circuit design is completed. In particular, an electrically reconfigurable programmable logic circuit device such as the invention of U.S. Pat. No. 4,700,187 has the advantage that a circuit once produced can be freely changed as many times as necessary. Programmable logic circuit devices are becoming more and more widely used.
[0004]
By the way, the complexity of recent logic circuits has increased, and the circuit scale has grown to a scale that cannot be realized with a single programmable logic circuit device.
[0005]
As one method for solving this problem, it has been proposed to reconfigure a programmable logic circuit in the middle of processing in order to realize different logic circuits at different times. By using this method, since the apparatus is small like a portable information terminal, there is an advantage that various processes can be performed at a relatively high speed even when the circuit scale that can be incorporated is limited.
[0006]
However, when the programmable logic circuit is reconfigured, the circuit information of the entire circuit is read again, so that there is a disadvantage that it takes time to reconfigure. Furthermore, reconfiguration in the middle of processing temporarily interrupts processing, saves the data at that time to a storage device outside the programmable logic circuit, reads and reconfigures new circuit information, and reconfigures the data before reconfiguration. Therefore, an extra process of inputting new data associated with the reconstruction is necessary, and the process of taking in and out the data becomes redundant.
[0007]
In order to solve this problem, it is described in a programmable logic circuit described in a data book named “CONFIGURABLE LOGIC” of Atmel in the United States, and in a data book named “THE PROGRAMMABLE LOGIC” in the United States of America. A programmable logic circuit has a data storage device for storing data. For reconfiguration by reading a part of circuit information from an external storage device and performing partial reconfiguration even during circuit operation I try to keep time to a minimum.
[0008]
The problem with using such a programmable logic circuit in an information processing system is that the process is separated into a process performed by a programmable logic circuit and a process performed by a fixed logic circuit device such as a microprocessor that cannot change the circuit configuration. The technology to do is not established.
[0009]
As one of methods for solving this problem, there is an example of a computer disclosed in Japanese Patent Laid-Open No. 6-301522. This will be described as Conventional Example 1 with reference to FIG.
[0010]
That is, in the conventional example 1 of FIG. 20, the source program 1000 executed by the computer includes a fixed unit that cannot change the circuit configuration and a variable unit that can change the circuit configuration like a programmable logic circuit. The library 1001 stores information on the configuration of the fixed unit and information on circuits that can be configured by the variable unit.
[0011]
The compiler 1002 analyzes the source program 1000 and converts it into object code and hardware configuration data while referring to the library 1001. For example, the compiler 1002 analyzes the flow of the source program, detects the frequency of the function, determines a function with a large number of calls as a function to be processed by hardware based on the detected frequency, and sets the hardware configuration data 1003. Is created and output.
[0012]
Next, the compiler 1002 generates a code indicating that a portion determined to be processed by hardware is processed by a predetermined variable unit. Then, this code is added to the portion to be processed by the remaining software to create and output an object code 1004. The computer 1005 executes processing according to the object code using the fixed unit and the variable unit configured by the hardware configuration data.
[0013]
In this way, in Conventional Example 1, the speed of the entire process is increased by implementing a function having a large number of calls at the time of compilation into hardware.
[0014]
Next, a case of a computer device disclosed in Japanese Patent Application Laid-Open No. 5-150943 will be described as Conventional Example 2 for solving the above problem. In this conventional example 2, the processing separated into the processing performed by the programmable logic circuit and the processing performed by the fixed logic circuit device is executed as the application program by the computer device as the information processing system.
[0015]
The computer device of Conventional Example 2 includes a CPU, a memory, a programmable logic circuit, an external storage device such as a hard disk, and other input / output interfaces.
[0016]
The external storage device stores circuit data of the programmable logic circuit and an application program. The memory stores an initial loading program for loading an application program from an external storage device.
[0017]
The CPU executes these programs and writes circuit data to the programmable logic circuit. The programmable logic circuit is connected to the bus line of the CPU, receives a signal on the bus line, performs logic processing, and returns the signal to the bus line. The processing procedure in the conventional example 2 is shown in FIG.
[0018]
First, a program file to be executed is designated (step S1). Next, it is determined whether or not circuit data is included in the designated program file (step S2). If included, the circuit data writing program is loaded and executed (step S3), and then the circuit data is loaded. (Step S4), the circuit data is written in the programmable logic circuit (Step S5). Thereafter, the application program is loaded (step S6) and executed (step S7).
[0019]
If the designated program file does not include circuit data, the process jumps from step S2 to step S6, and the application program is loaded and executed as it is.
[0020]
As described above, in the case of Conventional Example 2, the circuit performs a predetermined logic process when executing an instruction using a function on the programmable logic circuit. Thereby, without providing special hardware for each application, it is possible to configure a logic circuit as necessary to increase the processing speed.
[0021]
An information processing system that processes a part of the processing described above with a programmable logic circuit can be used by being connected to a network. As an example of such a case, an image reproducing device disclosed in Japanese Patent Laid-Open No. 9-74556 is shown as Conventional Example 3 below.
[0022]
As shown in FIG. 22, this image reproduction device is encoded with a moving image decoding unit 1100 that can reconfigure the processing system by a programmable logic circuit, and a program for reconfiguring the moving image decoding unit 1100. The receiving unit 1200 for downloading the moving image data from the network NT, switching means 1300 for switching the transmission destination depending on whether the received data is a program or moving image data, and the program can be changed to the configuration of the moving image decoding unit 1100. It comprises a program conversion unit 1400 for converting into a format, a receiving unit 1200, a switching unit 1300, a program conversion unit 1400, and a control unit 1500 for controlling the moving image decoding unit 1100.
[0023]
The moving image decoding unit 1100 performs inverse quantization on the quantized image data and can change the inverse quantization processing content, and inverse transforms the converted image data. And an inverse transformation unit 1102 that can change the content of the inverse transformation process.
[0024]
The program conversion unit 1400 includes a first program part (hardware processing part) that converts the program into a format that can change the configuration of the moving picture decoding unit 1100, and a second program part that is executed by the control unit 1500 during moving picture reproduction. A dividing unit 1401 that divides (software processing part), a first conversion unit (hardware compiler) 1402 that converts the first program part into a format that can change the configuration of the moving picture decoding unit 1100, and a second program A second conversion unit (software compiler) 1403 that converts the part into a format in which the control unit 1500 can decode and execute the processing.
[0025]
This image reproduction apparatus receives a moving image reproduction program and encoded moving image data from the network NT, and operates as follows.
[0026]
First, the reproduction algorithm program described in the logical description language is received by the receiving unit 1200. The received data is transmitted to the program conversion unit 1400 through the transmission switching unit 1300, and is divided into a hardware processing part and a software processing part by the dividing unit 1401.
[0027]
The hardware processing part is transferred to the first conversion unit 1402 and converted into a format (bit stream) that can rewrite the programmable logic circuit (FPGA), and the inverse quantization unit 1101 and the inverse conversion unit 1102 are controlled by the control unit. Rewriting is performed under control from 1500. Further, the software processing part is transferred to the second conversion unit 1403, converted into a format that can be processed by the processor, and then transferred to the control unit 1500.
[0028]
When moving image data is sent from the network NT to the image reproduction apparatus of FIG. 22 configured as described above, it is received by the receiving unit 1200, transmitted to the moving image decoding unit 1100 by the switching means 1300, and output as decoded data. The
[0029]
As described above, by configuring the inverse quantization unit 1101 and the inverse transform unit 1102 with elements whose circuit configuration can be changed, it is possible to deal with image data reproduced by different algorithms, The hardware of the decoding unit has an optimum processing capability.
[0030]
[Problems to be solved by the invention]
However, the conventional examples 1 to 3 related to the information processing system for processing a part of the processing with the programmable logic circuit described above have the following problems.
[0031]
In Conventional Example 1, the processing executed by the programmable logic circuit is determined in a unified manner such as a function having a large number of calls in one program. For this reason, when the information processing system performs a plurality of processes as a series of processes at once using a plurality of programs, there is a disadvantage that the process using the programmable logic circuit cannot be efficiently used.
[0032]
For example, if the number of calls in one program is small, but there are functions that are commonly called in the entire process that is sequentially executed as a series of processes, it is more efficient to execute the process with a programmable logic circuit. Good. However, in Conventional Example 1, it is not possible to determine that the processing of the function with a small number of calls in one program is executed by the programmable logic circuit.
[0033]
In addition, depending on the function, the size of the corresponding circuit information is large, so it takes a long time to reconfigure the circuit information in the programmable logic circuit. Even if the number of calls is large, the software processing time may be shorter. However, in Conventional Example 1, even such function processing is determined as processing by a programmable logic circuit because the number of calls is large.
[0034]
In Conventional Example 2, a part to be processed by hardware is predetermined for each application, and the part to be processed by hardware is mounted on a programmable logic circuit before starting a program. For this reason, there is a problem that software processing that does not require hardware processing is not started until the circuit configuration is completed.
[0035]
In particular, when the writing time to the programmable logic circuit is long due to the large size of the circuit data, the entire processing time may be shorter when the processing is performed by software having a processing speed slower than the hardware processing.
[0036]
That is, in the case of Conventional Example 2, the problem is that only the processing time of each hardware processing and software processing is focused, and the reduction of the entire processing time including the reconfiguration time of the programmable logic circuit is not considered. There is. In addition, since the programmable logic circuit is reconfigured for each program, there is also a problem that the circuits that are commonly used when executing a plurality of programs are also configured redundantly, which is inefficient.
[0037]
In Conventional Example 3, since a program described in a logical description language is downloaded from the network, there is a problem that it takes time to convert the program into circuit information in the image reproducing apparatus.
[0038]
That is, the process of converting logic description language to circuit information is converted from logic description language to netlist, technology mapping is performed according to the device, layout processing of placement and routing is performed, and the result is converted to circuit information. Need to be converted to In particular, it is known that the placement and routing process has a complicated algorithm and takes time.
[0039]
In other words, in Conventional Example 3, the client uses a description method with a high degree of abstraction such as a logical description language for the purpose of making the program stored in the server on the network and shared by the client compatible. There is a problem in that the amount of pre-processing increases and the overall processing time becomes long enough to impair the reduction of processing time by hardware processing.
[0040]
In Conventional Example 3, the program is acquired from the network. However, transmission over the network has a problem in terms of reliability because communication may be interrupted and the program may not be downloaded.
[0041]
Furthermore, transmission over the network is slower in transmission speed than bus transmission within the information processing system. In addition, when the load on the network or server is not constant and is congested, there is a problem that the transfer speed becomes very slow.
[0042]
For example, taking the case where circuit information to be reconfigured into a programmable logic circuit is acquired from a network as an example, even if software processing takes time-consuming processing by replacing it with hardware processing by a programmable logic circuit, Considering the hardware processing time as the time from the first step of downloading a program from the network to the end of the processing, the problem of increase in processing time due to instability of the transfer rate from the network cannot be ignored.
[0043]
Also, in hardware processing by programmable logic circuits, network transfer time and reconfiguration time of circuit information to programmable logic circuits is an overhead with respect to the original hardware processing time. Is much slower than the reconfiguration speed of circuit information to the programmable logic circuit, there is a problem that the larger the file size of the circuit information, the larger the network transfer portion of the overhead.
[0044]
As described above, as a problem common to the above-described conventional examples 1 to 3, the reconfiguration time of the programmable logic circuit including the time for acquiring circuit information and a plurality of programs executed as a series of processes are common. It can be mentioned that the processing is centrally separated into hardware processing and software processing without considering the processing used.
[0045]
In addition, the problem in obtaining necessary information through a network is a problem that must be solved in terms of overall processing time and efficiency.
[0046]
The present invention solves the problem of processing efficiency such as processing speed when processing is performed by combining software and hardware in an information processing system that can execute part of processing using a programmable logic circuit. An object of the present invention is to solve the above-described problems when obtaining necessary information from a network.
[0047]
[Means for Solving the Problems]
In order to solve the above problems, an information processing system according to the invention of claim 1
A series of processes is divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of software modules in which the processes are described in a program language, and An information processing system in which a part of a series of processing can be processed by a programmable logic circuit,
A hardware module in which the same processing as that performed by the software module in the program is described by circuit information for reconfiguring the programmable logic circuit is obtained from a storage device on the network, and the programmable logic circuit is reconfigured. Hardware module acquisition means for
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating the hardware module that performs the same processing as the processing performed by the software module is described in the program,
The hardware module acquisition means includes
A hardware module corresponding to the identification code described in the program is obtained from a storage device on the network,
A storage device storing a hardware module corresponding to the identification code is searched from a plurality of storage devices on the network, and a storage device having the fastest transfer speed of the hardware module is selected from the plurality of corresponding storage devices. Search means to
Acquisition execution means for executing acquisition of the hardware module from the storage device selected by the search means and reconfiguration of the programmable logic circuit;
It is characterized by having.
[0048]
An information processing system according to the invention of claim 2
A series of processes are divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of hardware modules in which the processes are described by circuit information included in a programmable logic circuit. And an information processing system in which a part of the series of processes can be processed by the programmable logic circuit,
A storage unit that stores a software module in which the same processing as that performed by the hardware module in the program is described in a program language;
Software module acquisition means for obtaining the software module from the storage device and storing it in the execution program storage;
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating a software module that performs the same processing as that performed by the hardware module is described in the program.
The software module acquisition means includes
Obtaining a software module corresponding to the identification code and storing it in the execution program storage unit,
A storage device storing the software module corresponding to the identification code is searched from a plurality of storage devices on the network, and the storage device having the fastest transfer speed of the software module is selected from the plurality of corresponding storage devices. Search means to
Acquisition execution means for executing acquisition of the software module from the storage device selected by the search means;
It is characterized by having.
[0049]
The invention of claim 3 is the information processing system according to claim 1 or 2,
The acquisition execution means executes the transfer of the hardware module or the software module from the network, and when the transfer amount per unit time is smaller than a predetermined expected value, the transfer speed is It changes so that the said hardware module or the said software module may be acquired from the memory | storage device of a place.
[0050]
An information processing system according to the invention of claim 4
A series of processes is divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of software modules in which the processes are described in a program language, and An information processing system in which a part of a series of processing can be processed by a programmable logic circuit,
A hardware module in which the same processing as that performed by the software module in the program is described by circuit information for reconfiguring the programmable logic circuit is obtained from a storage device on the network, and the programmable logic circuit is reconfigured. Hardware module acquisition means for
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating the hardware module that performs the same processing as the processing performed by the software module is described in the program,
The hardware module acquisition means includes
Acquisition execution means for acquiring the hardware module corresponding to the identification code described in the program from the storage device on the network in the execution order of the processing by the program and reconfiguring the programmable logic circuit When,
In parallel with the processing in the acquisition execution means, the parallel acquisition means for acquiring another hardware module corresponding to the identification code from the storage device on the network and storing it in the storage device in the system,
Means for reconfiguring the programmable logic circuit with circuit information of the hardware module acquired by the parallel acquisition means;
It is characterized by providing.
[0051]
An information processing system according to the invention of claim 5
A series of processes are divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of hardware modules in which the processes are described by circuit information included in a programmable logic circuit. And an information processing system in which a part of the series of processes can be processed by the programmable logic circuit,
A storage unit that stores a software module in which the same processing as that performed by the hardware module in the program is described in a program language;
Software module acquisition means for obtaining the software module from the storage device and storing it in the execution program storage;
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating a software module that performs the same processing as the processing performed by the hardware module is described in the program,
The software module acquisition means includes
Obtaining a software module corresponding to the identification code and storing it in the execution program storage unit,
Execution software for acquiring the software module corresponding to the identification code described in the program from the storage device on the network in the execution order of the processing by the program and storing it in the execution program storage unit Wear module storage means;
Parallel acquisition means for acquiring another software module corresponding to the identification code from the storage device on the network and storing it in the storage device in the system in parallel with the processing in the execution software module storage means ,
Means for storing the software module acquired by the parallel acquisition means in the execution software module storage means;
Furthermore, the invention of claim 6 is the information processing system according to claim 4 or claim 5,
In the program, the file size of the hardware module or software module corresponding to each identification code is described corresponding to the identification code,
In the parallel acquisition means, the hardware modules or software modules corresponding to the identification codes described in the program are sequentially acquired in descending order of the file size.
It is characterized by that.
[0052]
[Action]
In the information processing system according to the invention of each claim having the above-described configuration, one of the software module or the hardware module is described in advance in the program, and the other of the software module or the hardware module is a plurality of on the network. It is stored in the storage unit.
[0053]
The hardware (or software) module stored in the storage unit on the network is acquired by hardware (or software) acquisition means, and circuit information is reconfigured (or stored in the storage unit) in the programmable logic circuit. )
[0054]
The execution module determining means determines whether the processing unit is executed by the software module or the hardware module at the time of executing the program or before executing the program.
[0055]
As in the past, in the application program, the software processing part and the hardware processing part are not fixedly determined in advance, so the reconfiguration time of the programmable logic circuit at the time of determining the execution module is also taken into consideration It is possible to decide to select an efficient execution module as a whole of the processing described in the program based on the various conditions entered in.
[0056]
And according to invention of Claim 1 of said structure, a hardware module searches the memory | storage device which stores the hardware module corresponding to an identification code from the several memory | storage device on a network, Obtained from the storage device having the fastest transfer speed of the hardware module among the storage devices. Therefore, the network transfer time as an overhead with respect to the processing time can be minimized, and the overall processing efficiency can be improved.
[0057]
Similarly, in the invention of claim 2, the software module searches a plurality of storage devices on the network for a storage device storing the software module corresponding to the identification code, and among the plurality of corresponding storage devices. Obtained from the storage device with the fastest transfer speed of the software module. Therefore, the network transfer time as an overhead with respect to the processing time can be minimized, and the overall processing efficiency can be improved.
[0058]
Further, in the invention of claim 3, the transfer from the storage device determined to be fast in the transfer rate in claim 1 or claim 2 is executed, and the transfer amount per unit time is a predetermined expected value. If it is smaller than the above, the hardware module or the software module is changed from the storage device with the next highest transfer rate.
[0059]
This is because when multiple information acquisition requests to a storage device registered as having a high transfer rate are overlapped, each request destination is processed by a method such as time division processing in order to answer the multiple requests. This corresponds to the fact that the actual transfer time is increased in order to distribute data.
[0060]
According to another aspect of the present invention, the hardware module corresponding to the identification code described in the program is obtained from the storage device on the network in the execution order of the processing by the program and reconfigured into a programmable logic circuit. In parallel with this, another hardware module is acquired, transferred to a storage device in the system, and stored.
[0061]
According to a fifth aspect of the present invention, software modules corresponding to the identification codes described in the program are obtained from the storage device on the network in the execution order of the processing by the program, and stored in the execution program storage unit. In parallel with the processing, another software module is acquired from the storage device on the network and stored in the storage device in the system.
[0062]
Therefore, this parallel processing can reduce the overhead for actual processing and shorten the overall processing time.
[0063]
In the invention of claim 6, in particular, the capturing process performed in parallel is acquired in descending order of file size. Therefore, it is possible to perform efficient capturing with less influence of overhead and to shorten the processing time as a whole.
[0064]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of an information processing system according to the present invention will be described below with reference to the drawings.
[0065]
[First Embodiment]
FIG. 1 shows a main conceptual configuration of the first embodiment of the information processing system in which at least a part of the processing is processed by a programmable logic circuit capable of reconfiguring the circuit configuration according to the present invention.
[0066]
In this embodiment, a target application program (in the following description, it may be simply referred to as a program) 100 separates a series of processes to be executed by the program into a plurality of processes. Each process is configured as a module. This module will be referred to as a processing module in this specification.
[0067]
In the first embodiment, each processing module constituting the program 100 is constituted by a software program in which processing is described in a program language so that the CPU executes processing. The software program for each processing module is referred to as a software module in this specification. Therefore, in the case of this embodiment, the application program 100 consists of a set of a plurality of software modules SM.
[0068]
In this embodiment, a module (in this specification, this module is referred to as a hardware module) HM described by circuit information for reconfiguring the same processing as that performed by each of the software modules SM into a programmable logic circuit. And stored in the storage device 200 on the network. In this case, the storage device 200 includes a plurality of storage devices (servers) on the network.
[0069]
In the case of this example, as shown in FIG. 2, the program 100 includes a header part HED and a main part PRG, and the main part PRG is composed of a set of a plurality of software modules SM as described above. . In the header portion HED, the identification code ID of the corresponding hardware module HM described with circuit information for reconfiguring the same processing as each software module SM into a programmable logic circuit is described.
[0070]
In this case, the identification code ID is described in the program 100 so that the correspondence between the software module SM performing the same processing and the hardware module HM is attached. For example, in this example, the identification code ID of the hardware module HM corresponding to each software module SM in the order according to the processing execution order on the programs of the plurality of software modules SM of the main body part PRG is the header part HED. Described in Therefore, a module that is repeatedly used is repeatedly described repeatedly.
[0071]
The hardware module acquisition unit 300 uses the identification code ID described in the program 100 to obtain the hardware module HM that executes the same process as the process executed by the software module SM from the storage device 200 on the network. get. Then, the hardware module acquisition unit 300 reconfigures the circuit based on the acquired hardware module HM on the programmable logic circuit 400.
[0072]
Prior to the acquisition of the hardware module HM, the hardware module acquisition unit 300 collects information on the transfer processing capability of a plurality of storage devices (servers) on the network, and stores any hardware module HM in any storage device. Is stored in the search means 310 as a server list.
[0073]
The search range of the storage device at this time is determined according to, for example, the scale of the application, for example, if the scale is small, about the LAN, and if large, on the Internet.
[0074]
When the hardware module HM acquires the hardware module HM, the hardware module HM first acquires the storage list of the network in which the hardware module HM to be acquired by the search unit 310 is stored. When a plurality of storage devices are searched as a result of the search, the hardware module information is selected from the one having the highest transfer processing capability.
[0075]
The acquisition execution unit 320 of the hardware module 300 acquires the hardware module HM from the storage device selected by the search unit 310 through a network. Further, in this embodiment, the acquisition execution means 320 monitors the transfer amount in the first unit time when the access is concentrated on the selected storage device and the transfer capability is reduced, and the unit If the transfer amount in time is smaller than a predetermined threshold value, it can be switched to another storage device.
[0076]
The software processing by the software module SM of the program 100 is executed by the CPU 500.
[0077]
The actual processing of the application program 100 is executed for each processing module by the execution module determination means 600 selecting whether to execute the software module SM or the hardware module HM. In this embodiment, the execution module determination unit 600 determines which module to execute the processing module on the basis of the execution module selection condition set in the selection condition setting unit 700.
[0078]
The selection condition setting means 700 assumes various selection condition items such as processing time by software or hardware, memory consumption, reconfiguration time of a programmable logic circuit, and the like. Execution module selection conditions can be set by combining these condition items.
[0079]
The selection condition setting means 700 is provided so that the user can change the execution module selection condition. Therefore, when a specific execution module selection condition is determined in advance for the execution module determination unit 600 and the execution module is determined according to the selection condition without changing the selection condition, the selection condition setting unit 700 is included in the execution module determination unit 600, and in that case, it is not necessary to provide the module 700 in particular.
[0080]
Execution module determination by the execution module determination means 600 is performed in two ways: before execution of the program and when executing the program. In the first embodiment, the execution module is determined when the program is executed and when the execution of each processing module is started.
[0081]
[Hardware Configuration Example of the First Embodiment]
FIG. 3 is a block diagram illustrating a hardware configuration example of the information processing system 10 according to the first embodiment of this invention. In the information processing system 10 of this embodiment, a main memory 13 composed of, for example, a DRAM is connected to a host bus 11B of a CPU 11 via a memory controller (not shown) included in a chip set 12.
[0082]
The host bus 11B is also connected to the PCI bus 14 via a host-PCI bus bridge (not shown) included in the chipset 12. A programmable logic circuit 16 through a programmable logic circuit interface 15, a hard disk drive 18 through a hard disk interface 17, and a communication interface 19 are connected to the PCI bus 14.
[0083]
The communication interface 19 is connected to a plurality of storage devices (servers) 21, 22, 23 in which circuit information reconfigured in the programmable logic circuit 16 is stored via a network 20 such as a LAN or the Internet.
[0084]
An application program is stored in the hard disk read / written by the hard disk drive 18. The application program may be stored in a storage device on the network 20.
[0085]
In addition, the hardware module HM acquired from the storage devices 21 to 23 on the network 20 may be temporarily stored in the hard disk of the hard disk drive 18 or the main memory 13. Further, the programmable logic circuit 16 may be provided with a local memory, and the circuit information of the hardware module HM obtained from the network may be stored in the local memory.
[0086]
The information of the hardware module HM stored in the storage device in the information processing system is configured by, for example, overwriting the programmable logic circuit 16 when the hardware module is repeatedly used, for example. Used when not. That is, without obtaining the hardware module HM from the network, the circuit information of the hardware module HM is transferred from the storage device in the system to the programmable logic circuit 16 and reconfigured. In this case, compared to the transfer from the network 20, the bus transfer in the system can be performed at a high speed.
[0087]
In this embodiment, the hardware module acquisition unit 300 and the execution module determination unit 600 are implemented as software as one function of the OS of the information processing system 10 shown in FIG.
[0088]
Next, the structure of the programmable logic circuit 16 is shown in FIG. As shown in FIG. 5, the programmable logic circuit 16 includes a configuration memory 160 for storing circuit information, a logic cell 161, a wiring region 162, and an input / output terminal 163.
[0089]
The configuration memory 160 is composed of rewritable memory elements such as SRAM and DRAM in the logic cell 161 and the wiring area 162. When the address ADR is given to the configuration memory 160 and new circuit information data DA is stored, the circuit configuration in the logic cell 161 and the logic cell 161 and the input / output terminal 163 are connected to each other according to this circuit information. The connection state of the wiring area 162 to be reconfigured is reconfigured. This series of operations is called configuration. By rewriting a part of the configuration memory 160, the circuit can be partially reconfigured even when the programmable logic circuit is operating.
[0090]
As shown in FIG. 5, data to be processed is input to a circuit element 164 formed by reconfiguring the programmable logic circuit 16, and the processing result is output.
[0091]
[Description of Processing According to First Embodiment]
FIG. 6 is a flowchart showing a flow of basic processing in the first embodiment of the present invention. As described above, in this example, the determination time point in the execution module determination means 600 is at the time of program execution, and the determination of which module to use is performed at the start of execution of each processing module.
[0092]
Further, as described above, in this embodiment, the hardware acquisition unit 300 and the execution module determination unit 600 in FIG. 1 are implemented as software as one function of the OS of the information processing system 10 in FIG. When the application program 100 is started, processing is executed by the OS.
[0093]
In the example described below, it is assumed that the selection condition setting unit 700 of FIG. 1 is not provided and is included in the execution module determination unit 600. In the first embodiment, hardware processing by a programmable logic circuit whose configuration has been completed can generally be performed at higher speed than the corresponding software processing. It is determined whether or not the reconfiguration of the hardware module corresponding to the processing module to be executed into the programmable logic circuit 16 is completed. When the reconfiguration is completed, the processing module is reconfigured by the hardware module. Is executed by a programmable logic circuit.
[0094]
Prior to the execution of the application program 100, the CPU 11 accesses the plurality of storage devices 21 to 23 on the network 20 through the communication interface 19 in advance, and relates to the transfer processing capabilities of the storage devices 21 to 23 on the network 20. In addition to collecting information, information on which hardware modules are stored in each of the storage devices 21 to 23 is also collected, for example, in the form of a table, and as a server list, the main memory 13 or It is held on the hard disk of the hard disk drive 18.
[0095]
Prior to the execution of the actual application program, first, as shown in FIG. 2, the identification code ID of the hardware module HM described in the header part HED in the program 100 is read, and the application program The hardware module HM configured on the programmable logic circuit 16 to be used is recognized by the hardware module acquisition unit 300 (step S11).
[0096]
Next, the application program is executed, and two routines are executed in parallel. One is the execution of configuration of the programmable logic circuit 16 by the hardware module acquisition means 300, and the other is the software module SM or hardware module for each processing module executed by the program by the execution module determination means 600. HM determination and execution of its processing module.
[0097]
As described above, the hardware module acquisition unit 300 determines in which storage device on the network 20 the circuit information of the hardware module HM corresponding to the first identification code ID of the previously read identification code ID exists. Thus, a search is performed using the server list that has been collected and created in advance. When it is determined that the hardware module HM indicated by the identification code is stored in a plurality of storage devices on the network 20, the transfer processing capability of the storage devices is referred to and the transfer process is most performed. A storage device having a high capability is selected and determined as an acquisition destination of the hardware module HM (step S12).
[0098]
Then, the hardware module is acquired from the storage device on the network 20 that has been selected and determined, transferred to the configuration memory 160 of the programmable logic circuit 16, and the configuration is executed. In response to the inquiry from the execution module determination means 600, The success or failure of the configuration is answered (step S13).
[0099]
Then, when the configuration of the first hardware module HM is completed, the hardware module acquisition unit 300 determines whether there is a next hardware module HM (step S14), and if there is a next hardware module HM. Returning to step S12, the storage device on the network 20 for storing the circuit information of the hardware module HM corresponding to the identification code ID, which has a high transfer processing capability, is selected and determined. The hardware module HM is acquired from the storage device, transferred to the configuration memory 160 of the programmable logic circuit 16, and the configuration is executed.
[0100]
The hardware module acquisition unit 300 executes the above-described processing for all the hardware modules HM having the identification code ID read in advance, and performs the configuration.
[0101]
The execution module determination unit 600 inquires of the hardware module acquisition unit 300 to determine whether or not the configuration of the hardware module HM corresponding to the processing module to be executed has been completed (step S15), and the corresponding processing is performed. If the configuration of the hardware module HM has been completed, the processing by the hardware module HM is performed (step S16). If the configuration has not been completed, the processing by the corresponding software module SM is executed (step S17). ).
[0102]
When the processing of the processing module is completed, it is determined whether or not there is a next processing module (step S18). If there is a next processing module, the process returns to step S15. The process by is terminated.
[0103]
Here, the communication between the hardware module acquisition unit 300 and the execution module determination unit 600 is specifically performed as follows in the system 10 of FIG.
[0104]
That is, when the hardware module HM is configured on the programmable logic circuit 16, it is detected by the OS running on the CPU 11 via the PCI bus 14, and the hardware module acquisition means functioning as part of the OS. From 300, the execution module determination means 600 is notified.
[0105]
Further, the processing status of the program is detected by the OS running on the CPU 11, and the circuit of the hardware module HM is sent from the execution module determination unit 600 functioning as a part of the OS to the hardware module acquisition unit 300. Instructed to transfer information and start or stop configuration.
[0106]
As described above, in this embodiment, when a processing module is executed, if the corresponding hardware module HM is reconfigured in the programmable logic circuit 16, the processing of the processing module is performed by the hardware. Make it run in a module.
[0107]
As described above, normally, if the time for the configuration to the programmable logic circuit is not taken into consideration, it is possible to perform processing at high speed by hardware. Therefore, as described above, a series of processing by the application program can be performed at high speed by executing processing with the hardware module for which the configuration has been completed from the time when the configuration has been completed.
[0108]
In this embodiment, since the circuit information of the hardware module HM is obtained from the storage device having the highest transfer processing capacity on the network, the transfer time from the network as the overhead of the configuration time is It can be minimized.
[0109]
[Specific Example of Processing (First Example)]
Next, a first example, which is a specific example of the processing according to the first embodiment, will be described below with reference to the flowcharts of FIGS. 7, 8, 9 and 10.
[0110]
FIG. 7 is a flowchart showing the entire flow of detailed processing corresponding to the flowchart of FIG. 6 in the first embodiment. FIG. 8 shows a detailed flowchart of step S22 of the configuration routine R40 of the hardware module HM in FIG. 9 is a detailed flowchart of step S43 of the transfer routine R60 from the network in FIG. 8, and FIG. 10 is a flowchart of step S32 of the processing routine R50 by the software module SM or the hardware module HM of FIG. A detailed flowchart is shown.
[0111]
In FIG. 7, the routine R30 for processing by the software module SM or the hardware module HM and the routine R20 for configuration of the hardware module HM are executed in parallel.
[0112]
Here, in the first embodiment, it is assumed that M types of processing modules by the software module SM or the hardware module HM are performed, and a series of processing consisting of these M types of processing modules is repeated N times.
[0113]
As shown in FIG. 7, prior to executing the application program, the identification code of the hardware module HM is read from the header portion HED of the application program (step S11). Thereafter, a routine R20 for configuring the hardware module HM and a routine R30 for performing processing by the software module SM or the hardware module HM are executed in parallel.
[0114]
In the routine R20, first, a variable i indicating how many hardware modules HM of the M types of hardware modules are configured is initialized (step S21), and then the configuration of the hardware modules HM is configured. The process proceeds to step S22 for executing the process routine R40.
[0115]
In the configuration processing routine R40 in step S22, as shown in FIG. 8, it is confirmed whether or not the i-th hardware module HM exists on the programmable logic circuit 16 (step S41). Then, the OS is notified that it is already configured on the programmable logic circuit 16 (step S45).
[0116]
If the i-th hardware module HM does not exist on the programmable logic circuit 16, the i-th hardware module HM exists in a storage device (such as the hard disk drive 18 or the main memory 13) in the information processing system 10. It is confirmed whether or not to perform (step S42).
[0117]
If the i-th hardware module HM exists in the storage device in the system 10, the process proceeds to step S44 to perform configuration. If it does not exist in the storage device in the system, in step S43, the processing routine R60 for transfer from the network 20 is executed to search the storage devices 21 to 23 on the network 20 as described above. The circuit information of the hardware module HS is acquired from the selected storage device, and then the process proceeds to step S44 to execute configuration.
[0118]
In the network circuit transfer routine R60 in step S43, as shown in FIG. 9, the information of the hardware module HM is stored from the identification code of the hardware module HM requesting acquisition and the server list. The storage device which is the priority server having a high transfer processing capacity is selected and determined (step S61), and the transfer is started (step S62).
[0119]
Then, if the amount of data transferred during a unit time immediately after the start of transfer, for example, several tens of nanoseconds, is compared with a predetermined expected value, if it is large, the transfer is continued as it is (step S64). Then, the storage device is changed to the storage device having the next highest transfer processing capacity (step S61), and the transfer is started.
[0120]
Note that when the storage device storing the hardware module HM corresponding to the identification code is not found, the transfer from the network 20 is stopped and the processing by the software module SM is performed.
[0121]
Returning to FIG. 8, when the transfer in step S43 and the configuration of the hardware module HM in step S44 are completed, the process proceeds to step S45 to notify the OS of the end of the configuration, and returns to FIG. Is counted up (step S23).
[0122]
If the processing corresponding to the hardware module HM is started before the configuration of the hardware module HM is completed, the software module SM or the routine R30 for processing by the hardware module HM performs the software module. Processing by the SM is performed, but the configuration of the hardware module HM is continued.
[0123]
Then, during the configuration of all of the M types of hardware modules HM, it is determined that the variable j that counts the series of repeated processes executed by the application program 100 is j> N (step S24). When the application is terminated, some of the M types of hardware modules HM are not configured.
[0124]
However, if there is room in the storage device in the information processing system 10, it is possible to continue acquiring circuit information from the storage device on the network 20. By doing so, when the same kind of application is subsequently executed, the circuit information from the network 20 has been taken into the storage device in the system, and the access time can be reduced accordingly. it can. Further, when an attempt is made to acquire from the network 20 later, even if a failure occurs in the network 20 and a necessary hardware module HM cannot be acquired, the influence is minimized.
[0125]
Next, in order to confirm whether or not the hardware module HM to be configured remains, the variable i and the variable M are compared (step S25). If the variable i is equal to or smaller than the variable M, the configuration of the next hardware module HM is started. If the variable i is larger than the variable M, all the hardware modules HM are configured on the programmable logic circuit 16. The configuration process in FIG. 8 is terminated.
[0126]
Next, in FIG. 7, in a routine R30 executed in parallel with the routine 20, first, a variable j for counting a series of repeated processing is initialized (step S31), and then the software module SM or hardware Control goes to step S32 of the routine R50 for executing processing by the module HM.
[0127]
In the routine R50 of step S32, as shown in FIG. 10, first, a variable k for counting the number of processing modules of the M types of processing modules is initialized (step S51).
[0128]
Next, in order to confirm whether or not the k-th hardware module HM has been configured on the programmable logic circuit 16, in this routine R50, up to what number of configurations of the M types of hardware modules HM are selected. A comparison is made between a variable i indicating whether the processing has been completed and a variable k indicating which of the M types of processing modules the processing module to execute the processing is (step S52).
[0129]
If the variable k is smaller than the variable i, it can be seen that the configuration of the hardware module HM corresponding to the k-th processing module is completed on the programmable logic circuit 16, and therefore the processing is executed by the hardware module HM ( Step S53).
[0130]
If the variable k is equal to or greater than the variable i, the hardware module HM corresponding to the k-th processing module has not yet been configured on the programmable logic circuit 16, so that the processing is performed by the software module SM. Is executed (step S54).
[0131]
Next, the variable k indicating the number of the processing module is counted up (step S55), and the next k + 1-th processing module is started from step S52 in the same manner as the previous k-th processing module. Step S55 is executed, and this is repeated until the last M-th processing module (step S56). When the process for the last M-th processing module is completed, the routine returns to the routine of FIG.
[0132]
In FIG. 7, the iteration variable j is counted up (step S33), and the next iteration process is started. When the repeated process is performed N times, the application ends (step S34).
[0133]
As described above, in the first embodiment, in the application program for the process of performing N repetitions of M types of processing modules, the process by the software module SM is first executed. In the meantime, the configuration of the M types of hardware modules HM is gradually completed, and the completed hardware modules HM are sequentially used. Therefore, as the number of repetitions of the repeated processing increases, the number of hardware modules HM that complete the configuration also increases, the processing speed gradually increases, and the overall processing time is shortened.
[0134]
[Second Embodiment]
FIG. 11 shows a main conceptual diagram of the second embodiment of the information processing system according to the present invention. As shown in FIG. 11, in the second embodiment, the hardware module acquisition unit 300 includes a parallel acquisition unit 330 in addition to the search unit 310 and the acquisition execution unit 320.
[0135]
Further, in the second embodiment, the identification information of the hardware module HM acquired from the network by the hardware module acquisition unit 300 and reconfigured in the programmable logic circuit is recorded in the identification information recording unit 800. . Furthermore, the circuit information of the hardware module HM acquired from the network and reconfigured into a programmable logic circuit is stored in a storage device such as a hard disk drive in the information processing system.
[0136]
Others are configured in the same manner as in the first embodiment.
[0137]
The acquisition execution means 320 obtains the hardware module corresponding to the identification code ID described in the header part HED in the program 100 from the storage device on the network 20 in the execution order of the processing by the program 100, and obtains programmable logic. The circuit 400 is reconfigured. This is exactly the same as in the first embodiment. In this embodiment as well, the hardware module is acquired from the storage device having a high transfer processing capacity on the network 20 by the search means 310 and the programmable logic circuit 400 is obtained. To reconfigure.
[0138]
In parallel with the processing in the acquisition execution unit 320, the parallel acquisition unit 330 captures the information of the hardware module HM that has not yet been imported from the network into the storage device in the information processing system into the storage device in the system. Process to do. Whether or not the data is stored in the storage device in the information processing system can be known by referring to the identification code recorded in the identification code recording device 800.
[0139]
In the case of the second embodiment, the parallel acquisition unit 330 sequentially acquires the hardware module HM having a large file size in order from the network. For this reason, in the header part HED of the program 100 in the case of the second embodiment, as shown in FIG. 12, the files of the hardware modules HM correspond to the identification codes of the hardware modules HM. The size is described.
[0140]
In the identification code recording means 800, since the identification code of the hardware module acquired by the hardware module acquisition means 300 and reconfigured in the programmable logic circuit is recorded, by checking the recorded contents, When the same hardware module HM is repeatedly used in the program 100, the configuration of the programmable logic circuit 400 is prevented from being repeatedly executed. This saves configuration time and allows efficient processing.
[0141]
Even in the hardware module HM in which the identification code is recorded in the identification code recording means 800, the programmable logic circuit 400 is overwritten by the circuit information and does not exist on the programmable logic circuit 400. In this embodiment, if the identification code is recorded in the identification code recording means 800, the circuit information is recorded in the storage device in the system. By reading out the hardware module HM from the computer and configuring it in the programmable logic circuit 400, rapid configuration is possible without transfer from the network and acquisition.
[0142]
In the hardware configuration of the second embodiment, the hardware module acquisition unit 300 is one of the OSs in the information processing system, and the identification code recording unit 800 is configured as described below. This can be realized with the same hardware configuration as the information processing system 10 that implements the first embodiment shown in FIG.
[0143]
That is, when the configuration of the hardware module HM is completed and the OS is notified of the end of the configuration as shown in step S45 of FIG. 8, the identification code of the hardware module HM that has completed the configuration is The identification code recording means 800 is realized by recording in the storage device 10 such as the hard disk drive 18 or the main memory 13 shown in FIG.
[0144]
[Specific example of processing]
FIG. 13 is a flowchart showing the flow of processing of the second embodiment. The process in FIG. 13 is a process in which a parallel network transfer process (routine R70) for executing the process in parallel with the process shown in FIG. 7 is added. This parallel network transfer process is executed by the parallel acquisition unit 330 of the hardware module acquisition unit 300.
[0145]
Of the three processing routines R30, R20, and R70 shown in FIG. 13, the two processing routines R30, R20, on the left are exactly the same as those in the first embodiment described with reference to FIG. Are routines for executing processing by the software module SM or the hardware module HM, respectively.
[0146]
The right processing routine R70 in FIG. 13 is the parallel network transfer processing routine, and the processing is executed in parallel with the routines R20 and R30. Since the routines R20 and R30 are as described above, the parallel network transfer processing routine R70 will be mainly described here.
[0147]
When the application program 100 is started, first, the identification code ID of the hardware module HM and each file size are read from the header part HED of the application program 100 (step S11). Thereafter, a first routine R30 for performing processing by the software module SM or the hardware module HM, a second routine R20 for configuring the hardware module HM, and storing the hardware module HM in the system from the network. The third routine R70 for transferring to the apparatus is executed in parallel.
[0148]
In the second routine R20, the acquisition of the hardware module HM from the network is performed, but in the third routine R70, a hardware module HM having a large file size that takes time to transfer is separately stored in advance. The data is transferred to a storage device in the system.
[0149]
In the third routine R70, the storage devices 18 and 13 in the information processing system are searched for the identification code of the read hardware module HM, and the hardware module HM not in the storage device in the system is extracted (step S71). . Then, these hardware modules HM are sorted according to the size based on the file size described in the header portion HED (step S72). Then, according to the sorting result, the data is transferred from the storage device on the network to the storage device in the information processing system in order from the hardware module HM having the largest file size.
[0150]
In this case, the transfer method is similar to the above-described method, in which a storage device having a high transfer processing capability is searched and the transfer is preferentially performed from the storage device. Then, the actual transfer amount for a predetermined unit time is calculated from the start of the transfer, and if the transfer amount is smaller than the predetermined expected value, the transfer is performed from the storage device having the next highest transfer processing capacity. I do. However, in all the storage devices, when the calculated transfer amount is smaller than the predetermined minimum data amount, the transfer is performed from the storage device first tried.
[0151]
As described above, when the hardware modules HM are acquired and configured in the program order in the routine R20, the routine R70 is executed in parallel to store the other hardware modules HM in the system. Since the capture to the device is executed, when the acquisition and configuration processing of the next hardware module is started in the routine R20, the hardware module is already captured in the storage device in the system. No acquisition from the network is required, and only the configuration from the storage device in the system is required.
[0152]
Therefore, the overhead for acquiring the hardware module from the network for the configuration of the programmable logic circuit is reduced, and a high-speed configuration is possible.
[0153]
[Specific Example of Processing (Second Example)]
Next, as a specific example of processing in the case of the second embodiment (second example), the case of image processing will be described as an example.
[0154]
In the second embodiment, image processing for sharpening an unclear image by performing three types of processing of linear transformation processing, noise removal processing, and edge enhancement processing on image data using three types of image filters. To do.
[0155]
The structure of this application program AP will be described with reference to FIG. A list of identification code IDs for associating the software module SM used in the application program AP with the hardware module HM is added to the header portion HED of the application program AP.
[0156]
In the program, the hardware module SM and the software module HM are called as a duplicated process.
[0157]
There are three processing modules to be used: noise removal processing ABC001 using a Gaussian filter, contour enhancement processing XYZ001 using a Laplacian filter, and linear transformation processing PQR001. In the header portion HED, identification codes HmABC001, HmXYZ001, and HmPQR001 of the hardware module HM corresponding to these processes are described.
[0158]
Further, in this example, the hardware module identification codes HmABC001, HmXYZ001, and HmPQR001 of the header part HED are given codes that rank the file sizes. The upper limit file size is determined by the programmable logic circuit to be used. In this example, the file sizes are ranked as A, B,.
[0159]
For example, the hardware module of the noise removal processing ABC001 having the smallest rank A file size is HmABC001A. Similarly, in this example, HmXYZ001B and HmPQR001B are described. The corresponding software module is given a prefix with a prefix of Sm.
[0160]
The software module SM and the hardware module HM have the same arguments and return values and are completely compatible, and are configured to appear to the same processing module from the application program AP.
[0161]
Next, this image processing operation is shown in FIG. 15 and the flowcharts shown in FIGS. The flowcharts of FIG. 15, FIG. 16, and FIG. 17 correspond to the processing operations described with reference to FIG. 13 and FIG. 7 to FIG. 10, and the corresponding steps are denoted by the same step numbers. is there.
[0162]
FIG. 18 shows a timing chart of this image processing operation. The image processing operation of the second embodiment will be described below using the flowcharts of FIGS. 15 to 17 and the timing chart of FIG. In FIG. 18, the process a shows the linear transformation PQR001, the process b shows the noise removal process ABC001 using the Gaussian filter, and the process c shows the contour enhancement process XYZ001 using the Laplacian filter.
[0163]
Also, since there are three types of processing modules to be used, linear transformation PQR001, noise removal processing ABC001, and edge enhancement processing XYZ001, the number M of processing modules in FIGS. Further, since the process a to the process c are repeatedly executed for each plane of R (red data), G (green data), and B (blue data) of the image, the number of repetitions N in FIGS. 3
[0164]
In FIG. 18, when the application program is activated at time t0, initialization processing of the program AP and preparation of a processed image are performed. Simultaneously, a processing routine R20 for reading the identification code ID in the header part HED of the application program AP (step S11), obtaining the circuit information of the hardware module HM described therein, and configuring it on the programmable logic circuit is provided. , Starting from time t1. This processing routine R20 acquires and loads the hardware modules HM in the order of programs (the order of identification codes described in the header part HED).
[0165]
When the program is started, the first hardware module HmPQR001B is not configured on the programmable logic circuit. First, the storage device in the system is searched, and if the hardware HmPQR001B exists, it is downloaded from the storage device. . If it does not exist in the storage device in the system, it is transferred from the network.
[0166]
At the same time, the preprocessing of the parallel network transfer processing routine R70 starts at time t1. In this preprocessing, a storage device such as a hard disk or local memory in the system is searched to check whether there is a hardware module that matches the read identification code other than HmPQR001 (step S71). The hardware modules that do not exist in the storage device in the system are sorted in descending order of the file size at the end of the identification code (step S72), and the hardware module information is sorted in the order of the file size. Transfer is started from the storage device 20 to the storage device in the system (time t2).
[0167]
In FIG. 18, the hardware module HmABC001A that performs the process b and the hardware module HmXYZ001B that performs the process c do not exist in the system. Since the size is large, the transfer of the hardware module HmXYZ001B is started.
[0168]
If there are a plurality of storage devices on the network that store the corresponding hardware module HM, the storage device is determined to have a high transfer capability (step S732), and the data of the hardware module HM from the network is stored in the storage device in the system. Is started (step S733). The transfer amount per unit time immediately after the start is compared with a predetermined expected value (step S734). If the transfer amount exceeds the expected value, the transfer is continued as it is (step S735). Returning to step S731, the connection is switched to another storage device and the transfer amount is similarly evaluated. If the transfer amount does not exceed the expected value in all of the plurality of storage devices, transfer is performed by switching the connection to the fastest storage device tried so far.
[0169]
When the transfer of the data of the hardware module HM to the storage device in the system is completed, it is notified to the OS (step S736), and when the necessary loading of all the hardware modules HM into the system is completed, The end of the transfer process is notified to the OS (step S737).
[0170]
On the other hand, in the routine R30 of processing by the software module SM or the hardware module HM, in FIG. 15, the variable j for counting the number of repetitions is initialized to j = 1 (step S31), and the R plane of the image The process for is started. Next, a variable k indicating the number of module data to be processed is initialized to k = 1 (step S51).
[0171]
In FIG. 18, at the time t3 immediately before executing the process a (PQR001), the OS is inquired of the completion of configuration (step S52). If not completed (k ≧ i), the application program AP executes processing using the software module SmPQR001B (step S53).
[0172]
Thereafter, the same inquiry is made to the OS at time points t7 and t9 immediately before the process b and the process c. However, in this example, as shown in the timing chart of FIG. 18, since the configuration of the corresponding hardware modules HmABC001A and HmXYZ001B is not completed, the processing is executed using the software modules SmABC001 and SmXYZ001, respectively. The first iteration is completed.
[0173]
On the other hand, as shown in FIG. 18, the configuration of the hardware module HmPQR001B in process a on the programmable logic circuit is completed at time t4, and the OS is notified of the completion of configuration (step S45). .
[0174]
Subsequently, the hardware module HmABC001A in the process b is configured on the programmable logic circuit, but since this module does not exist in the storage device inside the system at this time, it is transferred from the storage device on the network and configured. Perform
[0175]
The transfer procedure from the storage device on the network is the same as that of the hardware module HmXYZ001B described above, but if the transfer amount does not exceed the expected value in all of the plurality of storage devices on the network, the transfer is interrupted. The configuration is not performed and the processing by the software module SM is performed.
[0176]
In this example, the transfer of the hardware module HmABC001A is completed at time t10, followed by configuration, and completed at time t12.
[0177]
In addition, the transfer processing of the hardware module HmXYZ001B, which has been transferred in so-called background processing by the parallel network transfer processing, is completed at time t13, and then the configuration is performed. At time t15, the configuration is performed. Complete.
[0178]
After the first repetition of the above-described repetition process, the second repetition of the repetition process for processing the G plane of the image starts (j = 2), and when the program proceeds again to a time point t14 immediately before the process a, the OS again Is inquired of the completion of configuration (step S52). If there is a response indicating that the configuration is complete (k <i), this time, the processing data is passed to the hardware module HmPQR001B and processed by the hardware. Then, at time t16, only the result processed by the hardware is returned to the program ( Step S54).
[0179]
Then, when an inquiry is made to the OS at time t17 immediately before the process b (step S52), since the configuration of the corresponding hardware module HmABC001A is completed, the process is performed by the hardware module HmABC001A (step S52). S53).
[0180]
Further, when an inquiry is made to the OS at time t19 immediately before the process c (step S52), since the configuration of the corresponding hardware module HmXYZ001B is completed, the process is performed by the hardware module HmXYZ001B (step S54). ), The second iteration is completed.
[0181]
After the second iteration, the third iteration of processing the B plane of the image begins (j = 3). At this time, when the configuration is inquired to the OS immediately before each processing, the corresponding hardware modules HmPQR001B, HmABC001A, and HmXYZ001B are all configured on the programmable logic circuit, so that the processing a, b, c Are all executed by the hardware modules HmPQR001B, HmABC001A, and HmXYZ001B, the third iteration of the repeat process is completed, and the application is also terminated (time t26).
[0182]
As described above, also in the second embodiment, the configuration of the hardware logic programmable logic circuit 16 is performed in parallel while executing the processing by the software module, and the configuration is completed. Since the hardware processing by the programmable logic circuit 16 is performed, the software processing and the hardware processing are efficiently performed without considering the configuration time, and the processing time as a whole is reduced. Shortening can be achieved.
[0183]
[Third Embodiment]
In the first and second embodiments described above, whether each processing module is performed by the software module SM or the hardware module HM is determined when the application program is executed. In addition, it may be performed before the application program is executed.
[0184]
In the third embodiment, in FIG. 1 or FIG. 11, the execution module determination unit 600 determines the execution module before executing the application program.
[0185]
In the case of the third embodiment, the identification code of each software module SM and the identification code of the hardware module HM are described correspondingly in the header part HED of the application program. For example, information on the capacity of each module, for example, the time required for each processing, the memory usage of the software module, the programmable logic circuit cell usage of the hardware module, and the like are described.
[0186]
The information processing system according to the third embodiment acquires the information of the header portion HED before executing the application program. Then, information about the capabilities of the software module SM and the hardware module HM is displayed on the display screen of the information processing system.
[0187]
The user uses the key operation unit to determine which module to perform each processing module in consideration of the expected processing time, the amount of memory provided in the information processing device, and the number of cells provided in the programmable logic circuit. Instruct.
[0188]
In accordance with this instruction, the execution module determination unit 600 stores information on whether each processing module is executed by a software module or a hardware module. Then, the execution module determination unit 600 performs control so that processing is executed by the set module when each processing module is executed.
[0189]
In the case of the third embodiment, the hardware module HM searched and acquired by the hardware module acquisition means 300 is all hardware modules whose identification codes are described in the header portion HED of the program. Only the pre-selected hardware module HM is required instead of the HM.
[0190]
As described above, in the case of the third embodiment, before starting the program, the user freely selects and instructs which of the software module and the hardware module is used for execution of each processing module. be able to. Therefore, it is possible to perform appropriate processing in consideration of not only processing speed but also memory usage.
[0191]
[Fourth Embodiment]
In the first embodiment, the second embodiment, and the third embodiment described above, the application program is composed of a set of software modules and performs the same processing as the software module. Is obtained from the identification code of the header part HED of the program, and the execution module is determined before or during execution of the program.
[0192]
However, conversely, the application program is composed of a set of hardware modules, and a software module that performs the same processing as the hardware module is transferred to a storage device or network in the system by the identification code of the header HED of the program. Also when acquiring from the storage device, the same processing as the first embodiment, the second embodiment, and the third embodiment described above is performed only by replacing the software module and the hardware module. be able to.
[0193]
This is because, after obtaining both modules, the procedure for determining the execution module is the same, and the software module stored in the main memory 13, for example, which is the main storage device as the execution program storage unit, This is because it is not necessary to acquire the software module again, and the software module can be stored in the main memory before starting the application.
[0194]
FIG. 19 shows a block diagram in the case of the fourth embodiment. FIG. 19 corresponds to the second embodiment. In the case of the configuration corresponding to the first embodiment, the identification information storage unit 800 does not exist.
[0195]
In this case, the hardware module HM described in the application program 110 is transferred to the programmable logic circuit 400 and reconfigured.
[0196]
Further, the software module acquisition unit 330 corresponding to the hardware module acquisition unit 300 of the above-described embodiment performs transfer in consideration of the processing capability of the storage device on the network, as in the above-described embodiment, The acquired software module is stored in the execution program storage means 550 and executed by the CPU 500. As described above, the execution program storage unit 440 includes the hard disk drive 18 and the main memory 13 in the information processing system.
[0197]
[Effect of the embodiment]
As described above, in the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, at least a part of the processing is a programmable logic circuit that can reconfigure the circuit configuration. In the information processing system to be processed, the reconfiguration time of the program logic circuit is considered by configuring the hardware module that performs the same processing as the software module in parallel with the execution of the application program by the software module. The program can be executed with the best combination of software modules and hardware modules, and the highest processing capability of the information processing system can be exhibited.
[0198]
Therefore, unlike the prior art, there is no need to fixedly determine in advance the portion to be processed between the software module and the hardware module in the application program.
[0199]
Further, when acquiring hardware module information or software module information from the network, the information acquisition is executed by selecting a storage device (server) having a high transfer processing capability from a plurality of storage devices (servers) on the network. Therefore, since the information can be acquired from the network at high speed, the overall processing speed can be improved.
[0200]
Further, in the second embodiment and the fourth embodiment, in parallel with the routine for acquiring the hardware modules or software modules from the network in the order of the programs, they are not yet acquired in the order of the largest file size. Since the hardware module or software module is acquired and stored in the storage device in the system, the overall processing speed can be improved.
[0201]
In addition, according to the first embodiment, the second embodiment, and the third embodiment, the hardware module is stored in the storage device on the network, and the network communication is disconnected during the processing. Even if there is, it is possible to continue the processing by the software module without interrupting the processing.
[0202]
Similarly, according to the fourth embodiment, even if the software module is stored in the storage device on the network and the network communication is interrupted in the middle of the processing, the hardware is not interrupted. The processing can be continued by the wear module.
[0203]
Further, in the case of the third embodiment, by instructing a module for processing before starting a program, it is possible to perform processing according to the state of the information processing apparatus and user preference.
[0204]
In the above embodiment, a search is performed to select the storage device having the highest transfer capability among the storage devices on the network that have the circuit information indicated by the identification code. Although the processing is performed based on the list of storage devices, this processing can also be performed by a LAN controller, a server controller, or the like.
[0205]
The storage device in the system transferred from the network is a hard disk device as an example, but a memory on the CPU bus or a local memory of a programmable logic circuit can provide the same or more effect.
[0206]
【The invention's effect】
As described above, according to the present invention, in an information processing system in which at least a part of processing is processed by a programmable logic circuit capable of reconfiguring a circuit configuration, processing is executed by software or hardware by a programmable logic circuit It is possible to flexibly determine whether or not to execute the process, and it is not necessary to fixedly determine in advance the part to be processed between the software module and the hardware module in the application program as in the prior art.
[0207]
According to the first or second aspect of the present invention, a plurality of storage devices on the network are searched for a storage device storing a hardware module or software module corresponding to the identification code, and the plurality of corresponding storage devices are searched. In order to select the storage device with the fastest transfer speed of the hardware module or software module, the hardware module or software module can be obtained from the fastest storage device at that time. The time can be shortened, and as a result, the processing time of the entire program can be shortened.
[0208]
According to the invention of claim 3, even when the transfer processing capability of the storage device is high, the actual transfer time due to the concentration of access requests in the storage device is increased, The transfer time can be shortened.
[0209]
According to the invention of claim 4 or claim 5, in parallel with the process of obtaining the hardware module or software module in the order of execution of the program, the hardware module or software module that is not in the information processing system is installed in the system. By taking in the storage device, the overhead time acquired from the network can be minimized.
[0210]
According to the sixth aspect of the present invention, when hardware modules or software modules are fetched from the network in parallel, the modules are obtained in descending order of file size. Because the file size is large, hardware or software modules that take a long time to transfer from the network can be efficiently imported into the storage device in the information processing system, further reducing the overhead time for processing. is there.
[0211]
In particular, even hardware module data that is difficult to configure by the time of execution should be transferred from the network storage device to the system storage device in parallel with the program execution order by the time of execution. Therefore, it is possible to transfer only through the bus in the system where the transfer speed is stable at the time of execution, and it can be expected that the number of times the processing module is executed by the hardware module will increase, and the processing time of the entire program Can be shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a conceptual configuration of a first embodiment of an information processing system according to the present invention;
FIG. 2 is a diagram for explaining an example of an application program used in the first embodiment of the information processing system according to the present invention;
FIG. 3 is a diagram showing a hardware configuration example of the first embodiment of the information processing system according to the present invention;
FIG. 4 is a diagram for explaining an example of a programmable logic circuit;
FIG. 5 is a diagram for explaining an example of a programmable logic circuit;
FIG. 6 is a flowchart for explaining main processing operations of the first embodiment of the information processing system according to the present invention;
FIG. 7 is a flowchart for explaining a specific example (first example) of processing of the information processing system according to the first embodiment of the present invention;
8 is a flowchart for explaining a part of the processing routine of FIG. 7;
FIG. 9 is a flowchart for explaining a part of the processing routine of FIG. 7;
FIG. 10 is a flowchart for explaining a part of the processing routine of FIG. 7;
FIG. 11 is a block diagram showing a conceptual configuration of a second embodiment of the information processing system according to the present invention;
FIG. 12 is a diagram for explaining an example of an application program used in the second embodiment of the information processing system according to the present invention;
FIG. 13 is a flowchart for explaining a processing flow in the second embodiment;
FIG. 14 is a diagram for explaining an example of an application program used in a specific example of processing in the second embodiment;
FIG. 15 is a flowchart for explaining a processing flow of a specific example of processing according to the second embodiment;
16 is a flowchart of a part of the flowchart of FIG.
FIG. 17 is a partial flowchart of the flowchart of FIG. 16;
FIG. 18 is a timing chart for explaining the flow of processing in a specific example of processing in the second embodiment;
FIG. 19 is a block diagram showing a conceptual configuration of the second embodiment of the information processing system according to the present invention;
FIG. 20 is a diagram for explaining an example of a conventional information processing system.
FIG. 21 is a diagram for explaining another example of a conventional information processing system.
FIG. 22 is a diagram for explaining still another example of a conventional information processing system.
[Explanation of symbols]
10 Information processing system
11 CPU
12 chipsets
13 Main memory
14 Bus
15 Programmable logic circuit interface
16 Programmable logic circuit
17 Hard disk interface
18 Hard disk drive
19 Communication interface
20 network
21, 22, 23 Network storage device
100 application programs
160 Configuration memory
200 Network storage devices
300 Hardware module acquisition means
330 Software module acquisition means
400 Programmable logic circuit
440 Execution program storage means
500 CPU
600 Execution module determination means
700 Selection condition setting means
800 Identification code storage means

Claims (6)

A series of processes is divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of software modules in which the processes are described in a program language, and An information processing system in which a part of a series of processing can be processed by a programmable logic circuit,
A hardware module in which the same processing as that performed by the software module in the program is described by circuit information for reconfiguring the programmable logic circuit is obtained from a storage device on the network, and the programmable logic circuit is reconfigured. Hardware module acquisition means for
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating the hardware module that performs the same processing as the processing performed by the software module is described in the program,
The hardware module acquisition means includes
A hardware module corresponding to the identification code described in the program is obtained from a storage device on the network,
A storage device storing a hardware module corresponding to the identification code is searched from a plurality of storage devices on the network, and a storage device having the fastest transfer speed of the hardware module is selected from the plurality of corresponding storage devices. Search means to
Acquisition execution means for executing acquisition of the hardware module from the storage device selected by the search means and reconfiguration of the programmable logic circuit;
An information processing system comprising: A series of processes are divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of hardware modules in which the processes are described by circuit information included in a programmable logic circuit. And an information processing system in which a part of the series of processes can be processed by the programmable logic circuit,
Software module acquisition means for obtaining a software module in which the same processing as that performed by the hardware module in the program is described in a program language from a storage device on a network and storing it in a storage unit for an execution program;
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating a software module that performs the same processing as the processing performed by the hardware module is described in the program,
The software module acquisition means includes
Obtaining a software module corresponding to the identification code and storing it in the execution program storage unit,
A storage device storing the software module corresponding to the identification code is searched from a plurality of storage devices on the network, and the storage device having the fastest transfer speed of the software module is selected from the plurality of corresponding storage devices. Search means to
Acquisition execution means for executing acquisition of the software module from the storage device selected by the search means;
An information processing system comprising: In the information processing system according to claim 1 or 2,
The acquisition execution means executes the transfer of the hardware module or the software module from the network, and when the transfer amount per unit time is smaller than a predetermined expected value, the transfer speed is The information processing system is modified so as to obtain the hardware module or the software module from a storage device. A series of processes is divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of software modules in which the processes are described in a program language, and An information processing system in which a part of a series of processing can be processed by a programmable logic circuit,
A hardware module in which the same processing as that performed by the software module in the program is described by circuit information for reconfiguring the programmable logic circuit is obtained from a storage device on the network, and the programmable logic circuit is reconfigured. Hardware module acquisition means for
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating the hardware module that performs the same processing as the processing performed by the software module is described in the program,
The hardware module acquisition means includes
Acquisition execution means for acquiring the hardware module corresponding to the identification code described in the program from the storage device on the network in the execution order of the processing by the program and reconfiguring the programmable logic circuit When,
In parallel with the processing in the acquisition execution means, the parallel acquisition means for acquiring another hardware module corresponding to the identification code from the storage device on the network and storing it in the storage device in the system,
Means for reconfiguring the programmable logic circuit with circuit information of the hardware module acquired by the parallel acquisition means;
An information processing system comprising: A series of processes are divided into a plurality of processing modules, and each processing module executes the series of processes described by a program composed of hardware modules in which the processes are described by circuit information included in a programmable logic circuit. And an information processing system in which a part of the series of processes can be processed by the programmable logic circuit,
Software module acquisition means for obtaining a software module in which the same processing as that performed by the hardware module in the program is described in a program language from a storage device on a network and storing it in a storage unit for an execution program;
Execution module determining means for determining whether the processing module described in the program is to be executed by the software module or the hardware module before or at the time of execution of the program;
With
An identification code indicating a software module that performs the same processing as the processing performed by the hardware module is described in the program,
The software module acquisition means includes
Obtaining a software module corresponding to the identification code and storing it in the execution program storage unit,
Execution software for acquiring the software module corresponding to the identification code described in the program from the storage device on the network in the execution order of the processing by the program and storing it in the execution program storage unit Wear module storage means;
Parallel acquisition means for acquiring another software module corresponding to the identification code from the storage device on the network and storing it in the storage device in the system in parallel with the processing in the execution software module storage means ,
Means for storing the software module acquired by the parallel acquisition means in the execution software module storage means;
An information processing system comprising: In the information processing system according to claim 4 or 5,
In the program, the file size of the hardware module or software module corresponding to each identification code is described corresponding to the identification code,
The information processing system according to claim 1, wherein the parallel acquisition unit sequentially acquires hardware modules or software modules corresponding to identification codes described in the program in descending order of the file size.

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