JP2000252408A - Method for overlaying semiconductors upon another and overlaid chip-on-chip type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip-on-chip type semiconductor device constituted by overlaying a plurality of semiconductor chips upon another with their surfaces being faced to each other. SOLUTION: An insulating film 14 on which predetermined wiring patterns 16 and 20 are formed is prepared. First and second semiconductor chips 11 and 17 are overlaid upon another with the insulating film 14 in between and joined to each other. The bump 13a of the first chip 11 is connected to the bump 19a of the second chip 17 through the wiring pattern 16. Similarly, the bump 13b of the first chip 11 is connected to the bump 19b of the second chip 17 through the wiring pattern 20. In addition, the bumps 13b and 13c of the first chip 11 are connected to each other through the wiring pattern 20. Consequently, a chip-on-chip type semiconductor device having a high degree of freedom for design can be provided, because the semiconductor chips 11 and 17 on which electrodes are arranged at different intervals and positions can be overlaid upon another and connected to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called chip-on-chip type semiconductor device in which a plurality of semiconductor chips are joined in a laminated structure such that a semiconductor chip is superimposed on a semiconductor chip, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device, proposals have been made from a conventional two-dimensional structure to a three-dimensional structure in order to achieve miniaturization and high integration. However, when a semiconductor device having a three-dimensional structure is formed by a continuous manufacturing process, the yield is often poor and difficult.

Therefore, the inventors of the present application have proposed that the surface of a semiconductor chip be superimposed on the surface of a semiconductor chip.
Research has been conducted on the practical application of a semiconductor device having a so-called chip-on-chip structure in which a plurality of semiconductor chips are joined into a two-layer laminated structure.

[0004]

When the surface of a semiconductor chip and the surface of a semiconductor chip are superimposed and joined, it is necessary to correctly align the two semiconductor chips so that the electrodes to be joined do not shift. In addition, the electrodes of two semiconductor chips to be superimposed must be arranged so that they can be joined in advance, and there is a problem that semiconductor chips having different electrode arrangement pitches cannot be overlapped and joined. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has as its main object to provide a semiconductor device having a chip-on-chip structure in which a plurality of semiconductor chips are overlapped and joined so that their surfaces face each other. And Another object of the present invention is to provide a practical method for manufacturing a chip-on-chip type semiconductor device.

[0006]

According to the first aspect of the present invention, there is provided a method of stacking a first semiconductor chip and a second semiconductor chip to form a stacked structure,
Preparing an insulating film on which a predetermined wiring pattern is formed, and laminating a first semiconductor chip and a second semiconductor chip so as to sandwich the insulating film; Is the way.

According to a second aspect of the present invention, there is provided a first semiconductor chip, an insulating film having a predetermined wiring pattern formed on the surface of the first semiconductor chip, and a second semiconductor chip formed on the insulating film. A chip-on-chip type semiconductor device comprising: two semiconductor chips. The invention according to claim 3 is the chip-on-chip type semiconductor device according to claim 2, wherein a surface of the first semiconductor chip and a surface of the second semiconductor chip are opposed to each other with the insulating film interposed therebetween, A first connection portion provided on one surface side of the insulating film and connected to a predetermined electrode of the first semiconductor chip; a first connection portion provided on the other surface side of the insulating film; A chip-on-chip type semiconductor device, wherein a wiring pattern including a second connection portion that can be connected to the first electrode and a wiring that electrically connects the first connection portion and the second connection portion is formed. .

According to the method of the first aspect, a predetermined electrical connection is made between the first semiconductor chip and the second semiconductor chip by using the insulating film on which the predetermined wiring pattern is formed. As described above, both semiconductor chips can be overlapped. That is, if a wiring pattern necessary for connecting the first semiconductor chip and the second semiconductor chip is formed in advance on the insulating film, the electrodes to be connected to the first semiconductor chip and the electrodes to be connected to the second semiconductor chip are formed. The electrodes to be connected are electrically connected by a wiring pattern formed on the insulating film. As the insulating film, a very thin film made of, for example, polyimide or the like may be used. The wiring pattern can be formed by, for example, double-sided printing. If small holes are formed in predetermined positions on the insulating film before printing the wiring pattern on the insulating film, the wiring on both sides of the insulating film is electrically connected when the wiring pattern is printed on the insulating film. become.

According to the chip-on-chip type semiconductor device of the second aspect, similarly to the above-described method, the electrical connection between the first semiconductor chip and the second semiconductor chip is achieved by the insulating film on which the predetermined wiring pattern is formed. As a result, a chip-on-chip type semiconductor device in which a plurality of semiconductor chips are stacked in various modes can be provided.

[0010] In particular, in the device of the third aspect, even if the electrode arrangement pitch of the first semiconductor chip is different from the electrode arrangement pitch of the second semiconductor chip, for example, the electrode of the first semiconductor chip and the second electrode are arranged. Since the electrodes of the semiconductor chip are connected via a wiring pattern provided on the insulating film, both electrodes can be electrically connected irrespective of a difference in electrode arrangement pitch or the like.

In each of the above structures, the surface of the semiconductor chip is generally covered with a passivation film except for the electrode portions. Therefore, even if the wiring pattern formed on the insulating film contacts the surface of the semiconductor chip, there is no danger of short-circuiting the circuit formed on the semiconductor chip.
In each of the above-described configurations, the first semiconductor chip and the second semiconductor chip are electrically connected via an insulating film having a predetermined wiring pattern. If a wiring pattern that can electrically connect a plurality of electrodes of one semiconductor chip is provided, the electrodes of the first semiconductor chip can be connected to each other.

Further, an insulating film sandwiched between the first semiconductor chip and the second semiconductor chip is configured to extend outward from a joint surface of the two semiconductor chips, and a wiring pattern of the extended insulating film is formed. ,
By connecting to a semiconductor chip different from the first semiconductor chip and the second semiconductor chip, a semiconductor device having a stacked structure of three or more layers can be realized.

[0013] Further, by extending the peripheral portion of the insulating film sandwiched between the first semiconductor chip and the second semiconductor chip and connecting a wiring pattern provided on the insulating film to a package substrate or the like, the insulating film is formed. A wiring pattern can be used instead of wire bonding. Further, if the wiring to be the power supply line is formed in advance on the wiring pattern of the insulating film, it is not necessary to form the power supply line on the semiconductor chip to be overlapped with the insulating film, and the size of the semiconductor chip can be reduced. it can. That is, conventionally, all the circuits including the power supply lines are formed on the surface of the semiconductor chip, and such semiconductor chips are overlapped. However, according to the present invention, a power supply line and the like are omitted from a circuit formed on the surface of a semiconductor chip by forming a large-capacity wiring line such as a power supply line on a sandwiched insulating film, and a chip-on-chip type. A completed circuit can be configured when combined with a semiconductor device. Thus, a chip-on-chip type semiconductor device with further reduced size can be obtained.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. Prior to the description of a specific embodiment, a related technique of stacking semiconductor chips using an insulating film will be described. FIG. 1A shows a semiconductor chip 2 using an insulating film 1.
FIG. 4 is an illustrative longitudinal sectional view showing a method of superimposing and joining 3 and 3. FIG. 1B is a schematic plan view of the insulating film 1.

As shown in FIG. 1B, an insulating film 1 in which a large number of minute metal spheres 4 are regularly and horizontally arranged at regular intervals is prepared. Each metal ball 4 is arranged in a state penetrating the insulating film 1 up and down. Then, as shown in FIG. 1A, the semiconductor chip 2 and the semiconductor chip 3 are overlapped so that the insulating film 1 is sandwiched. At this time, the semiconductor chip 2 and the semiconductor chip 3 are superposed such that the surface 2a and the surface 3a of the semiconductor chip 3 face each other with the insulating film 1 interposed therebetween. The surface 2 of the semiconductor chip 2
a formed on the electrode 2b and the surface 3a of the semiconductor chip 3
Are overlapped so that the electrode 3b formed in the above-mentioned manner is opposed. As a result, the electrode 2b and the electrode 3b
Are electrically connected by any one of the metal spheres 4 provided in the first stage.

The surface 2a of the semiconductor chip 2 and the surface 3a of the semiconductor chip 3 are covered with a passivation film except for the electrodes 2b and 3b. Therefore, the metal sphere 4 sandwiched between the surfaces 2a and 3a of these semiconductor chips
There is no need to worry about short circuits in the semiconductor chips 2 and 3. However, in the bonding method using a general-purpose insulating film 1 as shown in FIGS. 1A and 1B, the electrode 2b of the semiconductor chip 2 and the electrode 3b of the semiconductor chip 3 must be provided at positions facing each other. Therefore, the semiconductor chips 2 and 3 to be superimposed must be semiconductor chips having predetermined electrode arrangements, and the configuration of the semiconductor chips that can be superimposed is limited.

Therefore, in this embodiment, the semiconductor chips to be overlapped are not limited by the electrode arrangement and the like. FIG. 2 is an illustrative sectional structural view for explaining a configuration of a chip-on-chip type semiconductor device manufactured by the overlaying method according to one embodiment of the present invention. In FIG. 2, reference numeral 11 denotes a first semiconductor chip, and bumps 13a,
13b and 13c are provided. Each bump 13a, 1
Reference numerals 3b and 13c denote conductive portions for connection provided on the electrodes disposed below, for example, A
u, Pd, Pt, Ag, Ir, Ni, Cu, etc.

On the surface 12 of the first semiconductor chip 11, an insulating film 14 is laminated. The insulating film 14
For example, an insulating film 15 made of polyimide
And a wiring pattern 1 which is predetermined on the film 15.
6, 20 are formed. On the insulating film 14, a second semiconductor chip 17 is further laminated. The second semiconductor chip 17 is stacked so that its surface 18 faces the first semiconductor chip 11 via the insulating film 14. Surface 18 of second semiconductor chip 17
Similarly to the first semiconductor chip 11, bumps 19a and 19b formed on electrodes arranged at predetermined positions are provided.

The bumps 13a of the first semiconductor chip 11 and the bumps 19a of the second semiconductor chip 17 are formed by superposing the first semiconductor chip 11 and the second semiconductor chip 17 so as to sandwich the insulating film 14 therebetween. Are electrically connected via the wiring pattern 16. Further, the bumps 13 b of the first semiconductor chip 11 and the bumps 19 b of the second semiconductor chip 17 are connected via the wiring pattern 20. Further, the bumps 13 b and 13 c of the first semiconductor chip 11 are electrically connected via the wiring pattern 20. Then, by being superposed and pressed and heated, the respective bumps are melted and joined to the connection portions of the wiring pattern, whereby a chip-on-chip type semiconductor device can be obtained.

Wiring pattern 1 on insulating film 14
6 and 20 can be formed by, for example, double-sided printing. If the small holes 21 and 22 are formed at predetermined positions of the film 15 before double-sided printing, the wiring pattern 1
When both sides of the film 15 are printed, the wiring patterns on both sides of the film 15 are electrically conducted through the small holes 21 and 22.

The wiring pattern 16 includes a first connection portion 23 provided on one side of the film 15. The first connection portion 23 is a portion that can be connected to the bump 13a of the first semiconductor chip 11, and is preferably formed so that the conductive material rises. The wiring pattern 16 includes a second connection portion 2 provided on the other surface of the film 15.
4 are included. The second connection portion 24 is a portion that can be connected to the bump 19 a of the second semiconductor chip 17, and is also formed so that the conductive material rises from the surface of the film 15.

The wiring pattern 22, like the wiring pattern 16, includes a connection portion 25 that can be connected to the bump 13b and a connection portion 26 that can be connected to the bump 19b. Further, a connection portion 27 that can be connected to the bump 13c is provided, and the connection portions 25 and 27 are electrically connected. As a result, the bumps 13b and 13c of the first semiconductor chip 11 are electrically connected by the wiring pattern 20. As described above, the wiring patterns 16 and 20 provided on the insulating film 14 correspond to the first semiconductor chip 11.
Not only can predetermined bumps of the second semiconductor chip 17 be electrically connected to each other, but also predetermined bumps of the first semiconductor chip 11 can be electrically connected to each other.

The plurality of bumps 13b and 13c of the first semiconductor chip 11 (the same semiconductor chip) are
When the connection is made by the wiring pattern 20 of No. 4, there are the following advantages. The first semiconductor chip 11 needs, for example, a power supply line, and has a circuit configuration in which power is supplied to the plurality of bumps 13b and 13c by the power supply line. In this case, conventionally, it was necessary to form a power supply line on the surface of the first semiconductor chip 11. However, in this embodiment, a power supply line is formed in the wiring pattern 20 of the insulating film 14. When a large-capacity wiring line such as a power supply line is formed on the first semiconductor chip 11, the size of the first semiconductor chip 11 must be increased. However, if a power supply line is formed as the wiring pattern 20 of the insulating film 14 as in this embodiment, the overall size of the device can be reduced.

When the insulating film 14 is used, it is more convenient to adjust the alignment and the like by using a large film including an unnecessary portion at the peripheral portion at the time of bonding. After the bonding, the unnecessary portion of the film 15 protruding from the semiconductor chip may be cut. FIG. 3 is an illustrative longitudinal sectional view showing a configuration example of a chip-on-chip type semiconductor device according to another embodiment of the present invention. The semiconductor device shown in FIG. 3 has a three-layer structure in which two semiconductor chips 33 and 34 are stacked on a semiconductor mother chip 31 with an insulating film 32 interposed therebetween. The child chip 33 and the child chip 34 are overlapped so that their surfaces face each other with the insulating film 32 interposed therebetween. The electrical connection between the daughter chips 33 and 34 is the same as in the embodiment described with reference to FIG.
2 is realized by a wiring pattern (not shown) provided in the device 2.

Further, the peripheral portion of the insulating film 32 is superimposed on the surface 35 of the parent chip 31,
The wiring patterns formed on the insulating film 32 are connected to the bumps 36 on the electrodes arranged on the first surface 35. Thereby, the three semiconductor chips 31, 33, 34
An electrical connection between them is realized. In addition, parent chip 3
1 and the sub chip 33 are fixed with, for example, an insulating adhesive or the like.

By using the insulating film 32 having a predetermined wiring pattern as in this embodiment, a chip-on-chip type semiconductor device having a three-layer structure can be manufactured. In addition, if the configuration is devised, a chip-on-chip type semiconductor device having a laminated structure of three or more layers can be manufactured. Further, the degree of freedom in electrode arrangement and wiring layout is increased.

FIG. 4 is an illustrative longitudinal sectional view showing the configuration of a semiconductor device according to still another embodiment of the present invention. In this embodiment, the semiconductor chips 37 and 38 are overlapped so as to sandwich the insulating film 39. As in the above-described embodiments, a predetermined wiring pattern is formed on the insulating film 39, and the electrodes of the semiconductor chips 37 and 38 are connected to each other via the wiring pattern. Further, in this embodiment, the peripheral portion of the insulating film 39 has the semiconductor chips 37,
The wiring pattern extending from the surface of the insulating film 39 is connected to the electrode on the surface of the package substrate 40.

In the conventional semiconductor device, the package substrate 4
Wire bonding is used for electrical connection between the semiconductor chip and the semiconductor chip. In this embodiment, an insulating film 39 joining the semiconductor chips 37 and 38 to each other.
By using the wiring pattern formed on the substrate and using this wiring pattern instead of wire bonding, the electrical connection between the package substrate 40 and the semiconductor chips 37 and 38 is realized.

With such a configuration, the semiconductor chip 37 may be a chip having a smaller area than the semiconductor chip 38. As described above, by using the insulating film 39 on which the predetermined wiring pattern sandwiched when the semiconductor chips 37 and 38 are overlapped with each other is used instead of wire bonding, the semiconductor device has a high degree of freedom in the laminated structure and arrangement. Equipment can be made.

The present invention is not limited to the embodiment described above, and various changes can be made within the scope of the claims.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a technique related to the present invention in a method of stacking semiconductor chips using an insulating film, and in particular, A illustrates a method of stacking and joining semiconductor chips using an insulating film. FIG. 2 is a schematic longitudinal sectional view showing how to perform the operation, and B is a schematic plan view of an insulating film.

FIG. 2 is an illustrative longitudinal sectional view for explaining a method and a structure of a chip-on-chip type semiconductor device according to an embodiment of the present invention;

FIG. 3 is a schematic longitudinal sectional view of a chip-on-chip type semiconductor device according to another embodiment of the present invention.

FIG. 4 is a schematic longitudinal sectional view of a semiconductor device according to still another embodiment of the present invention.

[Explanation of symbols]

11 First semiconductor chip 12 Surface of first semiconductor chip 13a, 13b, 13c Bump of first semiconductor chip 14 Insulating film 15 Film 16, 20 Wiring pattern 17 Second semiconductor chip 18 Surface of second semiconductor chip 19a, 19b Bump of second semiconductor chip 23, 24, 25, 26, 27 Connection

Claims (3)

[Claims] 1. A method of laminating a first semiconductor chip and a second semiconductor chip to form a laminated structure, wherein an insulating film on which a predetermined wiring pattern is formed is prepared, and the insulating film is sandwiched. And a method of superimposing a plurality of semiconductor chips, the method comprising superimposing a first semiconductor chip and a second semiconductor chip. 2. A semiconductor device comprising: a first semiconductor chip; an insulating film on a surface of the first semiconductor chip on which a predetermined wiring pattern is formed; and a second semiconductor chip overlaid on the insulating film. A chip-on-chip type semiconductor device characterized by including: 3. The chip-on-chip type semiconductor device according to claim 2, wherein a surface of the first semiconductor chip and a surface of the second semiconductor chip are opposed to each other with the insulating film interposed therebetween. A first connection portion provided on one surface side of the insulating film and connectable to a predetermined electrode of the first semiconductor chip; a first connection portion provided on the other surface side of the insulating film and connected to a predetermined electrode of the second semiconductor chip. A chip-on-chip type semiconductor device, comprising: a second connection portion that can be connected; and a wiring pattern including a wiring that electrically connects the first connection portion and the second connection portion.