JP2000252151A - Capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor, capable of achieving high capacitance and low inductance. SOLUTION: In this capacitor 10, a lower electrode layer 2 and an extended part 2a are coated and formed on an insulating substrate 1. A dielectric layer 3 is coated and formed on the lower electrode layer 2. An upper electrode layer 4 is coated and formed on the dielectric layer 3. An insulating protection film 5 for exposing the part of the upper electrode layer 4 in the central part, and the extended part 2a of the lower electrode layer 2 at edges is coated and formed on the upper electrode layer 4. External terminal electrodes 6a, 6b are formed in the exposed area of the insulating protection film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-inductance, large-capacity capacitor used for, for example, an electric circuit operating at a high speed and used for bypassing high-frequency noise or for preventing fluctuation of a power supply voltage. is there.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, the size, thickness, and frequency of electronic components installed in the electronic devices have been accelerated.

In particular, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz and the clock frequency of the bus between chips is also 100 MHz even at the personal computer level. The speedup is remarkable. In such a high frequency, for example,
In particular, it has become essential to exhibit excellent characteristics with respect to high-frequency or high-speed pulses. In such a circuit, a decoupling capacitor, which is mounted near the IC and prevents a reduction in the operating voltage of the IC, is an essential component.

[0004] A capacitor used as a decoupling capacitor in a high-frequency circuit is excellent in high-frequency characteristics and supplies power at high speed.

That is, it is necessary to sufficiently consider not only the capacitance value but also the resistance component, the inductance component, and the like.
As the frequency increases, the capacitance component tends to decrease while the inductance component tends to increase. As the operating frequency increases, the current to be supplied by the inductance component is limited, causing a circuit error.

For such a capacitor having a reduced inductance component, for example, the capacitor electrode layer is shaped so as to shorten the length of current flow, or the dielectric layer and the capacitor electrode layer are arranged alternately. A terminal electrode is provided such that the flow direction of the current flowing in the capacitor electrode layer is opposite to the flow direction of the current flowing in the adjacent capacitor electrode layer, thereby forming an inductance generated by the flow of the current. Components are canceled each other so that no inductance component is generated (U
SP481490, JP-A-4-211191).

[0007]

However, in order to control the shape of the capacitor electrode layer and shorten the current path flowing through the electrode layer, various restrictions are imposed on the shape, and the inductance component is reduced. Often this cannot be achieved.

In a capacitor in which inductance components generated by a current flow cancel each other, a terminal electrode connected to a capacitor electrode layer has a complicated arrangement, or a dielectric layer and a capacitor electrode layer are attached to a mounting substrate. Since they are arranged in the vertical direction, it is difficult to reduce the height.

The present invention has been devised in view of the above-mentioned problems, and an object of the present invention is to provide a capacitor capable of realizing high capacitance and low inductance.

[0010]

According to the present invention, there is provided a capacitor comprising:
Forming a first capacitor electrode layer having an extension part partially extending to the outer peripheral end of the insulating substrate, a dielectric layer, and a second capacitor electrode layer on the insulating substrate in this order; And covering the capacitor portion with an insulating protective film having an opening (hereinafter, referred to as an exposed portion) that exposes an extended portion of the first capacitance electrode layer and a central portion of the second capacitance electrode layer. An extended portion of the first capacitor electrode layer and a second
This is a capacitor in which an external terminal electrode connected to a capacitor electrode layer is formed.

According to a second aspect of the present invention, a plurality of the capacitor portions are vertically stacked, and an opening is provided in a center portion of the first capacitor electrode layer and the dielectric layer of each capacitor portion. Are connected to each other.

[0012]

According to the present invention, the external terminal electrode connected to the extension of the first capacitor electrode layer is formed on the edge of the insulating protective film, and the external terminal electrode connected to the second capacitor electrode layer is Is disposed at the center of the insulating protective film. That is, for example, when a current flows from an external terminal electrode connected to the first capacitor electrode layer to an external terminal electrode connected to the second capacitor electrode layer, the current path is radial toward the center. Further, when a current flows from the external terminal electrode connected to the second capacitor electrode layer to the external terminal electrode connected to the first capacitor electrode layer, the current path is radially outward. That is, when this current is considered as a vector, these currents cancel each other, and the self-inductance component can be effectively reduced by the flow of the current.

In the present invention, low inductance can be achieved only by forming the external terminal electrode at one potential in the center and the external terminal electrode on the other potential on the peripheral portion.

Further, in the present invention, the first capacitor electrode layer, the dielectric layer, the second capacitor electrode layer, the insulating protective film, and the external terminal electrode are laminated on the insulating substrate in a planar manner. The manufacturing method is very simple, and the height can be reduced by forming a capacitor electrode layer and a dielectric layer using thin film technology.

According to the second aspect, the first capacitor electrode layer and the dielectric layer have an opening substantially at the center, and the second capacitor electrode layer has a flat plate shape. The first capacitor electrode layer has an extended portion provided on the outer periphery thereof to form a capacitor portion.

Therefore, when the insulating protective film is formed on the surface of the capacitor portion, specifically, the external terminal electrode connected to the first capacitor electrode layer can be formed around the edge of the insulating protective film. In addition, an external terminal electrode connected to the second capacitor electrode layer through the opening of the first capacitor electrode layer and the dielectric layer can be formed at the center of the insulating protective film.

Thus, the inductance component can be effectively reduced as described above, and the first capacitor electrode layer, the dielectric layer, the second capacitor electrode layer, the dielectric layer,. Are stacked in this order to form a capacitor having a high capacitance component.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a capacitor according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is an external perspective view of the capacitor of the first invention, FIG. 2 is a sectional view taken along line AA in FIG. 1, and FIG. 3 is an exploded external perspective view of the capacitor.

1 to 3, a capacitor 10 is
A first capacitor electrode layer (hereinafter, referred to as a lower electrode layer) 2, a dielectric layer 3, a second capacitor electrode layer (hereinafter, referred to as an upper electrode layer) 4, and an insulating protective film 5 are sequentially stacked on an insulating substrate 1. It is configured.

The insulating substrate 1 is made of, for example, rectangular alumina,
The lower electrode layer 2 is formed on a material such as ceramic such as aluminum nitride, quartz, a surface silicon oxide substrate, and glass.

The lower electrode layer 2 is formed in a substantially rectangular shape on the insulating substrate 1, and has an extension 2a extending from the lower electrode layer 2 on the outer periphery. The extension 2a of the lower electrode layer 2
For example, a portion exposed from the outer periphery of the above-described dielectric layer 3 is referred to as an extended portion 2a, and its shape is provided around the entire periphery of the lower electrode layer 2 or is formed around the lower electrode layer 2. It may be a projecting extension 2a extending at a predetermined interval.

The lower electrode layer 2 and the extension 2a are made of platinum,
A simple substance such as gold, Ag, Pd, Cu, or Ni, or an alloy containing these as a main component is suitable, and has a single layer or a multi-layer structure. For example, in a multilayer structure, Ti / Pt / A
g can be exemplified. It is important that the lower electrode layer 2 and the extension 2a are made of a material that has low reactivity with the dielectric layer 3 in the lower electrode layer 2 and can prevent the extension 2a from being eroded by the external terminal electrode material. Become.
The lower electrode layer 2 and the protruding portion 2a are formed by vacuum deposition or sputtering using a metal mask having a predetermined shape. The thickness is, for example, up to about 1.0 μm.

A dielectric layer 3 is formed on the lower electrode layer 2. An extension 2a of the lower electrode layer 2 extends from the outer periphery of the dielectric layer 3. The dielectric layer 3 only needs to have a high dielectric constant in a high frequency region, and includes a dielectric composed of a perovskite-type oxide crystal containing Pb, Mg, and Nb, and PZT, PLZT, B
aTiO ₃ , SrTiO ₃ , Ta ₂ O _5, or compounds obtained by adding or substituting other metal compounds to these may be used. The dielectric layer 3 is deposited and formed by a thin film forming technique such as sputtering while controlling the target and the introduced gas so that the above-described dielectric material can be formed. Further, for example, Pb, Mg, Nb
Was added to a predetermined volume to prepare a dielectric sol solution, and the sol solution was applied by spin coating to a thickness of, for example, 0.25 mm, dried, and baked at about 820 ° C. to give a thickness of 0.7 μm. Is formed. Thereafter, the dielectric layer 3 may be patterned using an etching solution that does not erode the lower electrode layer 2 and the extension 2a using a negative resist. The dielectric layer 3 has a thickness of 0.3 to 1 μm in order to secure a low profile, a high capacity and an insulating property.
In particular, 0.4 to 0.8 μm is desirable.

An upper electrode layer 4 is formed on the dielectric layer 3. This upper electrode layer 4 is desirably formed so as to be located in the region where the dielectric layer 3 is formed. The upper electrode layer 4 is made of platinum, like the lower electrode layer 2 described above.
A simple substance of gold, Ag, Pd, Cu, Ni, or an alloy containing these as a main component is suitable, and is a material having low reactivity with the dielectric layer 3. Further, the external terminals 6 are formed. It is important that, for example, there is a bonding property with the material of the external terminal 6.

With the structure described above, the dielectric layer 3 sandwiched between the lower electrode layer 2 and the upper electrode layer 4
During this time, a predetermined capacitance component is generated. And
Such a capacitance component is caused by the extension 2 a of the lower electrode layer 2, that is, the portion exposed to the periphery from the outer peripheral portion of the dielectric layer 3 and the portion of the upper electrode layer 4 formed on the dielectric layer 3. It will be derived from any location.

An insulating protective film 5 is formed on such a substrate 1. Specifically, the extension 2 of the lower electrode layer 2
a, formed in a region covering the dielectric layer 3 and the upper electrode layer 4;

A through-hole is formed in the insulating protective film 5 so as to expose the extension 2a of the lower electrode layer 2 and a part of the upper electrode layer 4. Of these through holes, the through hole that exposes the extension 2a of the lower electrode layer 2 is called an exposed portion 5a of the lower electrode layer 2, and the through hole that exposes a part of the upper electrode layer 4 is called the upper electrode layer. Of the exposed portion 5b.

It is formed correspondingly. In the figure, the exposed portion 5 a of the lower electrode layer 2 is provided around the entire outer peripheral portion of the dielectric layer 3, and is provided so as to be dotted around an edge near the outer periphery of the insulating protective film 5.

The exposed portion 5b of the upper electrode layer is
Are formed around the central portion of the. In the figure, it is dotted so as to be surrounded by the exposed portion 5a of the lower electrode layer.

The insulating protective film 5 is made of a photocurable resin such as photosensitive polyimide, or a material such as SiO ₂ .
For example, when using a photocurable resin such as photosensitive polyimide, for example, to form a coating film by spin coating,
The exposed lower electrode layer 5a and the exposed upper electrode layer 5b are formed by exposure and development. In addition, of the exposed parts 5a and 5b,
The opening diameter is, for example, about 100 to 200 μm. In addition,
In the case of using SiO ₂ , for example, it is formed by sputtering using a predetermined metal mask. The thickness of the insulating protective film 5 is about 3 to 20 μm.

The external terminal electrodes 6 (exposed portions 5a and 5b) are provided on the exposed portions 5a and 5b so that a capacitance component can be easily derived from the extended portion 2a of the lower electrode layer 2 and the upper electrode layer 4. 6a and the exposed portion 5b
Is formed as the external external terminal electrode 6). The external terminal electrode 6 is formed of a bump shape or a conductive film. For example, it is a solder bump in which solder is filled over the through holes constituting the exposed portions 5a and 5b, and further, the bumps protrude. In addition, each exposed part 5a, 5b
The inside is filled with a metal material made of Ag-Pd, gold or the like in addition to solder, and solder bumps formed by solder balls or solder paste are formed on the surface.

For example, in forming a solder ball, for example, printing is performed on each of the exposed portions 5a and 5b using a screen having an opening diameter of 200 μm by a solder paste, and by heating, the surface tension of the solder is increased. , Diameter 100
A solder ball of about μm can be formed.

In the case of a conductor film, a screen printing of a paste such as Ag-Pd, Ni-solder plating, Ni-
It is formed by a known technique such as Sn plating.

As described above, according to the structure, the lower electrode layer
The external external terminal electrode 6a connected to the second extended portion 2a can be led out from the edge of the insulating protective film 5, and the external terminal electrode 6b connected to the upper electrode layer 4 can be led out from the central portion of the insulating protective film 5.

Thus, as shown in FIGS. 4A and 4B, when a current flows from the external terminal electrode 6b to the external terminal electrode 6a, the current flows from the center to the outside. It will flow radially. That is, when this current is considered as a vector, these currents cancel each other, and the directivity can be eliminated, so that the self-inductance component can be effectively reduced.

That is, conventionally, attention has been paid to a current flow path, and a current path flowing in the opposite direction is formed so as to directly cancel an inductance component generated in the current path. As shown in FIG. 4B, the flow of current between the external terminal electrode 6b and the external terminal electrode 6a is offset as a whole. Moreover,
Structurally, the inductance component can be effectively reduced by a simple arrangement structure in which the external terminal electrode 6b is arranged at the central portion of the element and a plurality of external terminal electrodes 6a are arranged at the outer peripheral portion. FIG. 4A is a plan view seen from above the insulating protective film 5, and a dotted line indicates a region where the upper electrode layer 4 is formed.
A dashed line indicates a formation region of the dielectric layer 3, a black circle indicates an external terminal electrode 6a connected to the extension 2a of the lower electrode layer 2, and a white circle indicates an external terminal electrode 6b connected to the upper electrode layer 4. I have.

A capacitor having a high frequency characteristic with a capacitance C of 30 nF and an inductance L of about 100 pH at Hz can be obtained.

The lower electrode layer 2, the dielectric layer 3, the upper electrode layer 4, the insulating protective film 5, and the external terminal electrodes 6
Is subjected to a planar film forming process, so that the manufacturing method is greatly simplified. In addition, if the lower electrode layer 2, the dielectric layer 3, the upper electrode layer 4, and the insulating protective film 5 are formed by sputtering or spin coating, the entire thickness including the substrate 1 becomes 1 mm or less, and the height is extremely low. Is possible.

The lower electrode layer 2, the dielectric layer 3, the upper electrode layer 4, and the insulating protective film 5 are formed by using a thick film conductive paste, a thick film dielectric paste, and an insulating protective glass in addition to the spin coating method and the thin film technique. The above-described low inductance can be achieved even when the paste is used to form a layer on the insulating substrate by selective printing and drying and firing. Further, a dielectric green sheet may be used instead of a dielectric layer formed by applying a thick film dielectric paste.

FIG. 5 is an exploded perspective view of a main part of the capacitor according to the second invention, FIG. 6 is a sectional view of the capacitor, and FIGS.
(I) is a plan view during the manufacturing process.

In contrast to the single dielectric layer shown in FIGS. 1 to 3, the capacitor according to the second aspect of the present invention is provided with a plurality of dielectric layers to obtain a high capacitance. The structure of the capacitor part 50 is substantially the same as that of the first capacitor electrode layer 56 having an opening at the center and having an extension on the outer periphery, except for the lower electrode layer and the dielectric layer on the substrate side; A substantially rectangular opening between the first and second capacitance electrode layers 56 and 58; and a rectangular second capacitance electrode layer 58 facing the first capacitance electrode layer 56; It is configured with a ring-shaped dielectric layer 57 that exposes the protrusion 56a to the outer periphery.

In FIG. 5, one capacitor main body 50, a ring-shaped first capacitance electrode layer 56, a ring-shaped dielectric layer 57, a rectangular second capacitance electrode layer 58, and a structure for further increasing the capacitance. Other ring-shaped dielectric layers 57 and other ring-shaped first capacitor electrode layers 56 are provided.

The ring-shaped first capacitance electrode layer 56 has an opening 56b at the center thereof for connecting a plurality of second capacitance electrodes 58 arranged in the vertical direction. And an extension 56a for connection to another first capacitance electrode layer 56 and to the external terminal electrode 6a.

The ring-shaped dielectric layer 57 has an opening 57a at the center thereof so that a plurality of rectangular second capacitor electrode layers 58 can be connected to each other. The opening 5
7a has a slightly smaller shape than the opening 56b of the first capacitance electrode layer 56, and completely covers the inner edge of the opening 56b of the first capacitance electrode layer 56.

The outer shape of the dielectric layer 57 is slightly smaller than the shape of the first capacitor electrode layer 56.
The extension 56a is exposed around the first capacitance electrode layer 56.

Further, the second capacitor electrode layer 58 has a substantially rectangular shape, and its outer shape is slightly smaller than the outer shape of the dielectric layer 57.

As a result, when the two first capacitance electrode layers 56, two dielectric layers 57, and one second capacitance electrode layer 58 shown in FIG. Since the dielectric layer 57 is disposed between the two layers with the two-capacitance electrode layer 58, the region where the capacitance component is generated increases.

The external terminal electrode 6a is connected to the outer peripheral portion of the first capacitor electrode layer 56, and the central portion of the second capacitor electrode layer 58 (the opening 56b of the first capacitor electrode layer 56, the opening of the dielectric layer 57). The external terminal electrode 6b is connected to the external terminal electrode (via the portion 57a).

The capacitor body 50 shown in FIG.
The uppermost layer is the first capacitance electrode layer 56. However, whether the uppermost layer is the dielectric layer 57 or the second capacitor electrode layer 58 may be arbitrarily changed since the above-described connection structure is achieved.

FIGS. 6 and 7A to 7I show a capacitor having a capacitor body 50. FIG. FIG.
Will be described with reference to a plan view of a manufacturing process of each layer in FIG.

First, as shown in FIG.
7 is prepared, and then, as shown in FIG. 7B, a lower electrode layer 52 is formed on the insulating substrate 51 over substantially the entire surface.

On this lower electrode layer 52, a rectangular dielectric layer 53 is formed. This dielectric electric layer 53
The peripheral portion of the lower electrode layer 52 is exposed as an extension 52a (FIG. 7C).

An upper electrode layer (second capacitor electrode layer) 54 having a substantially rectangular shape is formed on such a rectangular dielectric layer 53 (FIG. 7D). Here, the second capacitance electrode layer 54 does not protrude to the outer periphery of the rectangular dielectric layer 53 and does not short-circuit to the extension 52a of the lower electrode layer 52, for example,
The size is slightly smaller than the outer shape of the rectangular dielectric layer 53.

A ring-shaped dielectric layer 55 is formed on the rectangular second capacitor electrode layer 54 (FIG. 7D). The ring-shaped dielectric layer 55 has the same shape as the dielectric layer 57 described above with reference to FIG. 5, that is, the outer shape is substantially the same as the rectangular dielectric layer 53 described above, or has a rectangular second capacitance. The shape is slightly larger than the outer shape of the electrode layer 54. A substantially rectangular opening 55a is formed at the center of the dielectric layer 55. The opening 55a exposes a central portion of the rectangular capacitor electrode layer 54.

A ring-shaped first capacitor electrode layer 56 is formed on such a ring-shaped dielectric layer 55 (FIG. 7F). As described with reference to FIG. 5 described above, the first capacitance electrode layer 56 has dimensions slightly larger than the dielectric layers 53 and 55, and extends from the lower electrode layer 52.
has an extension 56a that overlaps with a. And the first
A substantially rectangular opening 56b is provided at the center of the capacitor electrode layer 56.
Are formed. The shape of the opening 56b is slightly larger than the opening 55a of the ring-shaped dielectric layer 55 described above. From the opening 56b, the opening 55a of the above-described ring-shaped dielectric layer 55 is completely visible, and the center of the second capacitor electrode layer 54 is exposed.

A ring-shaped dielectric layer 57 is formed on such a first capacitor electrode layer 56 (FIG. 7 (g)), and a rectangular second capacitor electrode layer 58 is further formed on the first capacitor electrode layer 56. (FIG. 7 (h)).

The insulating protective film 5 is formed on the rectangular second capacitor electrode layer 58, and the external terminal electrode connected to the extension, which is the peripheral portion of the first capacitor electrode layer 56. 6a, an external terminal electrode 6b connected to a part of the second capacitor electrode layer 58 is formed (FIG. 7 (i)).

The partial electrode layer 52 and the rectangular upper electrode layer (the second
Rectangular dielectric layer 5 sandwiched between the capacitor electrode layer 54
Capacitance components corresponding to the facing areas are generated in three portions.

Further, in this embodiment, the portion of the ring-shaped dielectric layer 55 interposed between the rectangular second capacitor electrode layer 54 and the ring-shaped first capacitor electrode layer 56 and the ring-shaped first Capacitance components are respectively generated in the ring-shaped dielectric layers 57 interposed between the capacitance electrode layer 56 and the rectangular second capacitance electrode layer 58.

The extension 52a of the lower electrode layer 52 and the extension 56a of the first capacitor electrode layer 56 are connected, and the second capacitor electrodes 54, 58 having a rectangular shape are connected to each other by a ring-shaped dielectric. Opening 55a of body layer 55, first capacitance electrode layer 56
Are connected through the opening 56b of the first capacitor electrode layer 56, ie, the extension 56a of the first capacitor electrode layer 56 and the second connection.
External terminal electrodes 6a, 6 connected to a part of the capacitor electrode layer 58
From b, each capacitance component is synthesized and derived in parallel.

That is, the capacitance component is increased as compared with the structure shown in FIGS. In addition, the external terminal electrodes 6 having different potentials are provided on the outer peripheral portion and the central portion of the capacitor.
Since a and 6b are arranged, the current path can be made radial as shown in FIG. 4, so that the inductance can be reduced.

The ring-shaped dielectric layer, the ring-shaped first capacitance electrode layer, the ring-shaped dielectric layer, the rectangular second capacitance electrode layer,...・ By laminating the capacitors, a capacitor with a larger capacity can be obtained.

The openings 56b of the first capacitor electrode layer 56,
Openings 55a, 57a of ring-shaped dielectric layers 55, 57
Is a region for conducting the second capacitor electrode layers 54 and 58 and achieving connection with the external terminal electrode 6b, and the opening shape does not need to be rectangular.

[0065]

As described above, according to the present invention, the flow of the current is radially divided between one capacitor electrode layer, the dielectric layer, and the other capacitor electrode layer at the central portion and the outer peripheral portion of the capacitor. be able to. For this reason, the inductance components generated by being regulated in the direction of the current flow cancel each other, so that a low inductance can be achieved.

Moreover, since the dielectric layer can be formed as a thin film, a high capacitance component can be obtained.

Further, a higher capacitance component can be obtained by forming the dielectric layers in parallel with the substrate.

[Brief description of the drawings]

FIG. 1 is an external perspective view of a capacitor according to the present invention.

FIG. 2 is a sectional view taken along line AA in FIG.

FIG. 3 is an exploded perspective view of the capacitor of the first invention.

4A and 4B are diagrams for explaining the operation of the capacitor of the present invention, wherein FIG. 4A is a schematic plan view, and FIG. 4B is a schematic plan view showing a current path.

FIG. 5 is an exploded perspective view of a main part of the capacitor of the second invention.

FIG. 6 is a sectional view of a capacitor showing an example of the second invention.

FIGS. 7A to 7I are schematic plan views in respective steps of the capacitor of FIG. 6;

[Explanation of symbols]

 1, 51: insulating substrate 2, 52: lower electrode layer 3, 53: dielectric layer 4: upper electrode layer 5: insulating protective film 6a, 6b: external terminal Electrode 54 ... second capacitor electrode layer (upper electrode layer) 55, 57 ... ring-shaped dielectric electric layer 56 ... first capacitor electrode layer 58 ... second capacitor electrode layer

Claims (2)

[Claims] A first capacitor electrode layer having an extension portion on the outer periphery, a dielectric layer, and a capacitor portion including a second capacitor electrode layer, wherein the extension portion of the first capacitance electrode layer is led out. (1) A capacitor, wherein a second external terminal electrode extending from a central portion of the second capacitor electrode layer is formed as the external terminal electrode. 2. The method according to claim 1, further comprising: stacking a plurality of the capacitor units vertically and providing an opening in the center of the first capacitor electrode layer and the dielectric layer of each capacitor unit; The capacitor according to claim 1, wherein the electrode layers are connected to each other.