JP2000245166A - Inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunctions of an AC load, when an inverter is started by alternately on/off-controlling every pair of a plurality of pairs of switching elements for AC conversion, when a DC voltage reaches a certain constant level. SOLUTION: When a switch 60 is made and power is supplied to an AC conversion control circuit 50, a comparator 52 in a comparing means 55 compares a DC voltage VDC outputted from a DC converter circuit 2 via a smoothing capacitor 7 with a reference voltage VRD of a reference power source 51. Since the DC voltage VDC is lower than the reference voltage VRD when the inverter is started, a comparison output signal VCP of a low level is outputted from the comparator 52 inside the comparing means 55. Since drive signals VG1, VG2 from drive signal generating circuits 36, 38 are inputted directly to drive circuits 18, 19 respectively, and MOSFETs 8, 9 are alternately on/off- controlled, no AC power will be supplied to a load 15 from an AC converter circuit 14. Consequently, malfunctions of an AC load can be prevented, when the inverter is started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device, and more particularly to an inverter device capable of preventing a malfunction of an AC load at the time of starting.

[0002]

2. Description of the Related Art FIG. 10 shows a circuit diagram of an inverter device which has been widely used conventionally. This inverter device is
A DC conversion circuit (2), a smoothing capacitor (7) connected between the output terminals of the DC conversion circuit (2), an AC conversion circuit (14),
A rectification control circuit (16). DC conversion circuit (2)
Is composed of first and second thyristors (3) and (4) as bridge-connected rectifying switching means and first and second diodes (5) and (6). And the second
The commercial AC voltage V supplied from the single-phase commercial AC power supply (1) by turning on / off the thyristors (3) and (4)
_IN is converted to a constant level DC voltage _VDC . The AC conversion circuit (14) includes two pairs of first and second MOS-FETs serving as a plurality of pairs of AC conversion switching elements connected in a bridge.
(8), (9) and the third and fourth MOS-FETs (10), (1
1), filter reactor (12) and filter capacitor
(13), two pairs of first and second MOS-FETs
(8), (9) and the third and fourth MOS-FETs (10), (1
1) The converts the DC voltage V _DC output through the smoothing capacitor from the DC converter (2) (7) by alternately turning on-off control for each pair of sinusoidal alternating voltage V _AC single-phase To the load (15). Rectification control circuit as rectification control means
(16) is a pair of first and second MOS-FETs (8), (9) and third and fourth MO-FETs constituting an AC conversion circuit (14).
The first and second thyristors (3) and (3) of the DC conversion circuit (2) are driven by ON / OFF operations of the S-FETs (10) and (11) according to the DC voltage _VDC of the smoothing capacitor (7). On / off control of (4).

[0003] The AC conversion circuit (14) includes an AC conversion control circuit (1).
7), first and fourth driving circuits (18) and (21), second and third driving circuits (19) and (20), a driving power supply (22), and a first charge pump. The circuit includes a circuit (29), a second charge pump circuit (30), and a third charge pump circuit (31). AC conversion control circuit as AC conversion control means (17)
The first and fourth MOS-FET in accordance with the sinusoidal alternating voltage V _AC supplied to the load (15) (8), (11) and the second and third MOS-FET (9), ( 10) outputs the alternating on-off control the first variable duty ratio to the driving signal V _G1 and second drive signals V _G2 to. The first and fourth drive circuits (1
8), (21) and the second and third drive circuits (19), (20)
The first drive signal V output from the AC conversion control circuit (17)
_G1 and the second drive signal V _G2 are respectively set to the first and fourth M
OS-FETs (8) and (11) and second and third MOS-Fs
ET (9) and (10) are assigned to each gate terminal. Power supply for driving
(22) supplies the drive DC voltage _VDR to the AC conversion control circuit (17) and the first and third drive circuits (18) and (20).
The first charge pump circuit (29) includes a diode (23) and a capacitor (26), and converts a voltage charged in the capacitor (26) during the ON period of the first MOS-FET (8) into a driving power. To the second drive circuit (19). The second charge pump circuit (30) includes a diode (24) and a capacitor.
The voltage that has been charged in the capacitor (27) during the ON period of the third MOS-FET (10) is supplied to the fourth drive circuit (21) as drive power. The third charge pump circuit (31) is composed of a diode (25) and a capacitor (28), and converts the voltage charged in the capacitor (28) during the ON period of the second MOS-FET (9) into driving power. To the rectification control circuit (16).

As shown in FIG. 11, an AC conversion control circuit (1
7) includes a reference sine wave oscillator (32), an error amplifier (33), a triangular wave oscillator (34), a PWM comparator (35), a first drive signal generation circuit (36), and an inverter (37). ), A second drive signal generation circuit (38), an AC conversion control circuit (17), and a drive power supply.
(22) and the AC conversion control circuit (1
And 7) a main switch (60) for supplying power to each section. Reference sine wave oscillator (32) outputs a reference sine wave signal V _RA to control the reference value of the sinusoidal alternating voltage V _AC supplied to the load (15). The error amplifier (33) detects a level difference between the reference sine wave signal V _RA sinusoidal AC voltage V _AC and the reference sine wave oscillator (32). The triangular wave oscillator (34) controls a switching frequency, for example, a reference triangular wave signal V _{T of} 20 kHz.
Is output. The PWM comparator (35) is connected to the error amplifier (3
3) by comparing the reference triangular wave signal V _T of the error output signal V _A and the triangular wave oscillator (34) for forming a PWM modulation signal V _PWM.
The first drive signal generation circuit (36) includes all the MOS-FETs.
Dead time t _D during which (8) to (11) are in the off state
Is added to the PWM modulation signal V _PWM of the PWM comparator (35) to form a first drive signal _VG1 . The inverter (37)
And it outputs the inverted signal -V _PWM of the PWM signal V _PWM of the PWM comparator (44). Second drive signal generation circuit (38)
Adds the dead time t _D to the output signal −V _PWM of the inverter (37) to form the second drive signal _VG2 .

As shown in FIG. 12, a rectification control circuit (16)
Is a gate control signal generation circuit (43) and a positive / negative judgment circuit (44)
An inverter (45) for outputting an inverted signal of the output signal of the positive / negative determination circuit (44); a first AND gate (46);
And a D gate (47). Gate control signal generation circuit
(43) is composed of two resistors (39) and (40) connected in series between the power input terminal (a) and the GND terminal (b), and the base terminal is connected to the resistor (3).
9) and (40), the emitter terminal is connected to the DC voltage input terminal (c), and the collector terminal is connected to the power supply input terminal (a) via the resistor (41).
2), and outputs a gate control signal _VSG having a pulse width corresponding to the level of the DC voltage _VDC of the smoothing capacitor (7) input through the DC voltage input terminal (c). The positive / negative determination circuit (44) outputs a high (H) level signal when the polarity of the commercial AC voltage V _IN of the commercial AC power supply (1) input through the commercial AC input terminal (d) is positive. And outputs a low (L) level signal when negative. First AND gate
(46), a gate control signal generation circuit gate control signal V _SG drive signal output terminal a logical product signal of the output signal of the sign determination circuit (44) as a third driving signal V _G3 of (43) (e) Output via. Second AND gate (47), the drive signal outputs a logical product signal of the output signal of the gate control signal V _SG and inverter (45) of the gate control signal generating circuit (43) as a fourth driving signal V _G4 Output via terminal (f).

As shown in FIG. 13, a first drive circuit (18)
Is an NPN transistor (48) and a PNP transistor connected in series between a pair of power input terminals (g) and (h).
(49). NPN transistor (48) and PN
The connection point of the base terminal of the P-type transistor (49) is connected to the drive signal input terminal (i), and the NPN-type transistor (48)
The connection point of the emitter terminal of the PNP transistor (49) is connected to the drive signal output terminal (j). The second to fourth drive circuits (19) to (21) also have the same configuration as the first drive circuit (18).

When the inverter shown in FIG. 10 is driven, the main switch (60) is turned on to supply power from the driving power supply (22) to each part of the AC conversion control circuit (17). together with the first of the first drive signal V _G1 from the drive signal generating circuit (36) in (17) is outputted to the first drive circuit (18) and a fourth driving circuit (21), the second drive The second drive signal _VG2 is output from the signal generation circuit (38) to the second drive circuit (19) and the third drive circuit (20). Further, since the power input terminals (g) and (h) of the first and third drive circuits (18) and (20) are connected to the drive power source (22), the first and third drive circuits (18) and (20) are connected. circuit (18), (20) a DC voltage V _DR for driving is applied to the AC conversion control circuit (17) first and second from the drive signal V _G1, V _G2 of the first and third, respectively Drive circuit (18),
(20), the first and third drive circuits (1
8) and (20), the first and third MOS-FETs (8), (1)
A control voltage is applied to the gate terminal of (0). Therefore, the first and third MOS-FETs (8) and (10) start on / off operations alternately.

When the first MOS-FET (8) is in the ON state, the first charge pump circuit (29) is supplied from the driving power supply (22).
Via the diode (23) and the capacitor (26)
-A current flows through the FET (8) and the first charge pump circuit (2
The capacitor (26) of (9) is charged to the voltage _{VDR of the} driving power supply (22). Similarly, when the third MOS-FET (10) is in the ON state, the third MOS-FET is turned on from the driving power supply (22) via the diode (24) and the capacitor (27) of the second charge pump circuit (30). -A current flows through the FET (10), and the capacitor (27) of the second charge pump circuit (30) changes the voltage V of the driving power source (22).
_Charged to _DR . First and second charge pump circuits
The voltage V _DR charged in each of the capacitors (26) and (27) of (29) and (30) is the second and fourth drive circuits (19) and (21), respectively.
And the first and second signals from the AC conversion control circuit (17).
Fourth and second drive circuits of the drive signal V _G1, V _G2, respectively (21), because it is assigned to (19), the fourth and the second M
A control voltage is applied to the gate terminals of the OS-FETs (11) and (9), and the fourth and second MOS-FETs (11) and (9) start on / off operations alternately.

When the second MOS-FET (9) is on, the capacitor (26) of the first charge pump circuit (29) to the diode (25) of the third charge pump circuit (31) and the capacitor ( A current flows through the second MOS-FET (9) via the second charge pump circuit (28), and the electric charge accumulated in the capacitor (26) of the first charge pump circuit (29) is transferred to the capacitor of the third charge pump circuit (31). Move to (28), and the capacitor (28)
It is charged up to the voltage _{VDR of} 2). At this time, the voltage V charged in the capacitor (28) of the third charge pump circuit (31)
_DR is supplied to the power input terminal (a) of the rectification control circuit (16), the rectification control circuit (16) starts operating, and the DC voltage input terminal
DC voltage V of the smoothing capacitor (7) input through (c)
A gate control signal _VSG having a pulse width corresponding to the _DC level is output from the gate control signal generation circuit (43). Moreover, the commercial AC voltage V _IN is input commercial AC input terminal negative determination circuit via the (d) (44) commercial AC power source (1), when the polarity of the commercial AC voltage V _IN is positive or negative, high Outputs a low or high level signal. The output signal of the positive / negative determination circuit (44) is directly and via the inverter (45) together with the gate control signal _{VSG of the} gate control signal generation circuit (43) and the first and second ANs.
It is input to D gates (46) and (47).

When the polarity of the commercial AC voltage V _IN of the commercial AC power supply (1) is positive, a high-level signal is output from the positive / negative determination circuit (44), and the output from the first AND gate (46) is output. The logical product signal is equal to the gate control signal V _SG of the gate control signal generation circuit (43), and the third drive signal V has a pulse width corresponding to the level of the DC voltage _VDC of the smoothing capacitor (7).
_G3 is output from the drive signal output terminal (e). On the other hand, the second
The AND signal output from the AND gate (47) is at a low level, and the fourth drive signal _VG4 output from the drive signal output terminal (f) is constant at a low level. Rectification control circuit
The third and fourth drive signals _VG3 and _VG4 output from the drive signal output terminals (e) and (f) of (16) are DC conversion circuits, respectively.
The first thyristor (3) is applied to each gate terminal of the first and second thyristors (3) and (4) in (2), and the first thyristor (3) is turned on / off according to the DC voltage _VDC of the smoothing capacitor (7). The second thyristor (4) is turned off while being turned off. At this time, a current flows from the commercial AC power supply (1) through the path of the first thyristor (3), the smoothing capacitor (7), and the second diode (6), and the smoothing capacitor (7) has a fixed polarity with the illustrated polarity. Voltage V _DC
Is charged. Conversely, when the polarity of the commercial AC voltage V _IN of the commercial AC power supply (1) is negative, a low-level signal is output from the positive / negative determination circuit (44), so that the signal is output from the first AND gate (46). The logical product signal becomes low level, and the third drive signal _VG3 output from the drive signal output terminal (e) becomes low level and constant. On the other hand, the logical product signal output from the second AND gate (47) becomes equal to the gate control signal _VSG of the gate control signal generation circuit (43), so that the level of the DC voltage _VDC of the smoothing capacitor (7) is reduced. A fourth drive signal _VG4 having a corresponding pulse width is output from the drive signal output terminal (f). The third and fourth drive signals V _G3 and V _G4 output from the drive signal output terminals (e) and (f) of the rectification control circuit (16) are respectively the first and second drive signals in the DC conversion circuit (2). Of the thyristors (3) and (4) are turned off, the first thyristor (3) is turned off, and the second thyristor (4) is turned on in accordance with the DC voltage _VDC of the smoothing capacitor (7). Is controlled on / off. At this time, current flows from the commercial AC power supply (1) through the path of the second thyristor (4), the smoothing capacitor (7), and the first diode (5), and the smoothing capacitor (7) has a constant polarity with the illustrated polarity. Voltage V
_DC is charged. As a result, the commercial AC voltage V _IN of the commercial AC power supply (1) is converted into a DC voltage by the DC conversion circuit (2), and is supplied from the DC conversion circuit (2) via the smoothing capacitor (7) at a certain level. _VDC is output.

The constant level DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7) is supplied to the first and fourth MOS-FETs (8) in the AC conversion circuit (14). , (11)
And turning on / off of the second and third MOS-FETs (9) and (10).
The OFF operation is converted into an AC voltage, the sinusoidal alternating voltage V _AC is supplied to a filter reactor (12) and the load through the filter capacitor (13) (15). Sinusoidal alternating voltage V _AC supplied to the load (15), the inverting input terminal of the error amplifier of the AC conversion control circuit (17) in (33) (-) is input to a sine wave at the error amplifier (33) detected level difference between the reference sine wave signal V _RA of the reference sine wave oscillator is input to an AC voltage V _AC and a non-inverting input terminal (+) (32), the error output signal from the output terminal in accordance with the level difference _VA is output. The error output signal _VA of the error amplifier (33) is supplied to the PWM comparator (3
In 5) is compared with a reference triangular wave signal V _T of the triangular wave oscillator (34), the relationship between the error output signal V _A and the reference triangular wave signal V _T becomes low level when the V _A> V _T, V _A <V _T The pulse train signal which becomes high level at the time of is PWM comparator (35)
To generate a PWM modulation signal V _PWM . PWM
The PWM modulation signal V _PWM of the comparator (35) is directly input to the first drive signal generation circuit (36) and the inverter (37)
Are input to the second drive signal generation circuit (38) via the drive signal generation circuit, and the respective drive signal generation circuits (36) and (38) add a dead time t _D to each of the drive signal generation circuits (36) and (38). The first and second drive signals V _G1 and V _{G2 shown} in FIG. In the AC conversion control circuit (17), the sine wave AC voltage V supplied to the load (15) is
_{When AC} is higher than a predetermined level, first and second drive signals _VG1 and _VG2 having a narrow pulse width are formed, and first to fourth drive circuits (18) to (21) are used to generate first to fourth drive signals. 4 MOS-FETs (8) to (1)
Narrowing the pulse width of the gate output applied to 1), which makes it possible to reduce the level of the sine wave AC voltage V _AC. Conversely, the load when the sinusoidal alternating voltage V _AC is supplied to the (15) is lower than a predetermined level, the first wide pulse width and a second
First to fourth drive circuit form a drive signal V _G1, V _G2 of
From (18) to (21), the pulse width of the gate output given to the first to fourth MOS-FETs (8) to (11) is increased, whereby
It is possible to increase the level of the sine wave AC voltage V _AC.
Therefore, the first output from the AC conversion control circuit (17) is
And by the second drive signal V _G1, V _G2, load the first and fourth MOS-FET of the AC conversion circuit (14) in response to a sinusoidal AC voltage V _AC (15) (8), (11 ) And the second and third M
OS-FETs (9) and (10) are alternately turned on and off, and highly stable single-phase sinusoidal AC power is supplied to the load (15) via the filter reactor (12) and the filter capacitor (13). Is done.

[0012]

By the way, FIG.
The conventional inverter device is small, lightweight and low cost.
First to fourth driving of the AC conversion circuit (14)
Circuits (18) to (21), AC conversion control circuit (17) and DC conversion circuit
The drive power for the rectification control circuit (16) in the path (2) is used for one drive
Powered by power (22). The first and the second in the AC conversion circuit (14)
The reference potential of the third drive circuits (18) and (20) is a drive power supply (22)
Since this is the same as the reference potential of
Supply driving power to the first and third drive circuits (18) and (20)
it can. However, the second and fourth driving circuits (19) and (21)
Since the reference potential is different from the reference potential of the drive power supply (22),
Operating power supply (22) from the first charge pump circuit (2
9), the first MOS-FET (8) and the second charge port.
Via the amplifier circuit (30) and the third MOS-FET (10).
Supply drive power to the second and fourth drive circuits (19) and (21);
ing. Further, the capacitor of the first charge pump circuit (29)
Charge accumulated in the sensor (26) via the second MOS-FET (9).
Transfer to the capacitor (28) of the third charge pump circuit (31)
As a result, power for driving the rectification control circuit (16) is obtained.
You. Therefore, the first and fourth MOs of the AC conversion circuit (14) are
S-FETs (8) and (11) and second and third MOS-FEs
Rectification control after T (9) and (10) start on / off operation
The circuit (16) is driven, whereby the DC conversion circuit (2)
DC voltage V via smoothing capacitor (7) _DCIs output
You. Therefore, the DC conversion circuit (2)
DC voltage V output via (7)_DCIs enough to rise
The AC conversion circuit (14) starts operating before
Therefore, low level sine wave
AC voltage V_ACSupplied from the AC conversion circuit (14) to the load (15).
It is. This sine wave AC voltage V_ACIndicates that the load (15) operates normally
Load (15) malfunctions because it is lower than the minimum operating voltage
Caused.

Accordingly, an object of the present invention is to provide an inverter device that can prevent a malfunction of an AC load at the time of starting.

[0014]

An inverter device according to the present invention converts an AC voltage (V _AC ) of an AC power supply (1) into a DC voltage (V _DC ).
DC conversion circuit (2), a smoothing capacitor (7) for smoothing the DC output of the DC conversion circuit (2), and a DC output of the DC conversion circuit (2) through the smoothing capacitor (7). An AC conversion circuit (1
4). The AC conversion circuit (14) includes a plurality of pairs of bridge-connected AC conversion switching elements (8) (9), (10) (1).
1) and a plurality of pairs of switching elements for AC conversion (8) (9), (1
0) (11) AC conversion control means (50) that alternately turns on and off a pair to generate an AC output to the load (15),
DC conversion circuit (2) is rectifying switching means (3), (4)
And a plurality of pairs of AC conversion switching elements (8), (9), (10), (11) of the AC conversion circuit (14), which are driven by on / off operations and provide rectification switching means (3), (4). A rectification control means (16) for performing on / off control to generate a DC output to the smoothing capacitor (7). The AC conversion control means (50) of the inverter device alternately turns on and off only one of a plurality of pairs of AC conversion switching elements (8) (9) and (10) (11) when the inverter device is started. Rectification control means (1
6), and when the DC voltage (V _DC ) output from the DC conversion circuit (2) via the smoothing capacitor (7) reaches a certain level or after starting the inverter device, When the time has elapsed, a plurality of pairs of AC conversion switching elements (8), (9), (10), and (11) are alternately turned on and off for each pair.

In the embodiment of the present invention, the reference voltage (V _RD )
And a DC conversion circuit (2)
DC voltage (V
_DC conversion) and comparison means (55) for comparing the reference voltage (V _RD ) are provided in the AC conversion control means (50). When the DC voltage (V _DC ) is less than the reference voltage (V _RD ), the comparing means (55) _selects one of a plurality of pairs of AC conversion switching elements (8), (9), (10), and (11). ON / OFF control alternately charges the smoothing capacitor (7) with the current flowing through the DC conversion circuit (2) .When the DC voltage (V _DC ) is higher than the reference voltage (V _RD ), multiple pairs of AC The switching elements (8), (9), (10), (11) for conversion are alternately turned on / off for each pair.

When the inverter device is started, the comparing means (55)
Compares the DC voltage (V _DC ) output from the DC conversion circuit (2) via the smoothing capacitor (7) with the reference voltage (V _RD ) of the reference power supply (51). When the DC voltage (V _DC ) is less than the reference voltage (V _RD ), the comparing means (55) selects one of a plurality of pairs of AC conversion switching elements (8) (9) and (10) (11). Only the ON / OFF control is performed alternately to drive the rectification control means (16), and the smoothing capacitor (7) is charged by the current flowing through the DC conversion circuit (2). Multiple pairs of AC conversion switching elements (8) (9), (10)
Since only one pair of (11) is alternately turned on / off, no AC output to the load (15) is generated. in this way,
When the inverter device is started, the DC voltage (V _DC ) output from the DC conversion circuit (2) via the smoothing capacitor (7) does not reach a certain level, and the reference voltage ( V _RD ), the load from the AC conversion circuit (14)
Since the AC power is not supplied to (15), malfunction of the AC load at the time of starting the inverter device can be prevented.

The current flowing through the DC conversion circuit (2) sufficiently charges the smoothing capacitor (7) so that its DC voltage (V _DC ) reaches a certain level and the reference voltage (V _DC ) of the reference voltage generating means (51) (V _RD ) or more, the comparison means (55) alternately turns on and off a plurality of pairs of AC conversion switching elements (8) (9), (10) (11) for each pair, Smoothing capacitor
The DC output of the DC conversion circuit (2) can be converted to an AC output via (7), and the AC output can be supplied to the load (15).

The AC conversion circuit (14) includes first and fourth drive circuits (18) and (21) and second and third drive circuits (19) and (2).
0). The AC conversion control means (50) is a drive signal pulse-width controlled based on the AC output to the load (15).
A first drive for applying (V _G1 ) and (V _G2 ) to one of the first and fourth drive circuits (18) and (21) or the second and third drive circuits (19) and (20) Signal generation circuit (36) and second drive signal generation circuit
(38). The comparing means (55) generates the signals from the first drive signal generation circuit (36) and the second drive signal generation circuit (38) only when the DC voltage (V _DC ) is equal to or higher than the reference voltage (V _RD ). The drive signals (V _G1 ) and (V _G2 ) are supplied to first and fourth drive circuits (18),
(21) or the other of the second and third drive circuits (19) and (20). The comparing means (55) includes a comparator (52) having an input terminal connected to the smoothing capacitor (7) and the reference voltage generating means (51); a comparator (52); a first drive signal generating circuit (36); A gate circuit (55a) connected to the second drive signal generation circuit (38). The gate circuit (55a) is connected to the other of the first and fourth drive circuits (18) and (21) or the second and third drive circuits (19) and (20) by the drive signals (V _G1 ) and (V _G2 ).

In another embodiment of the present invention, a timer means (64) for outputting drive signals (V _G1 ) and (V _G2 ) when a certain period of time has elapsed since the start of the inverter device. Is provided in the AC conversion control means (50). AC conversion control means
(50) is a plurality of pairs of switching elements for AC conversion when the drive signals (V _G1 ) and (V _G2 ) are output from the timer means (64).
(8) (9), (10), and (11) are alternately turned on and off for each pair.

When the inverter device is started, a plurality of pairs of AC conversion switching elements are provided by AC conversion control means (50).
(8) (9), (10) (11) to drive the rectification control means (16) by alternately ON / OFF control only one pair, the rectification control means (16)
Rectification switching means (3) of the DC conversion circuit (2),
Each of (4) is on / off controlled to generate a DC output to the smoothing capacitor (7). Since only one of a plurality of pairs of AC conversion switching elements (8), (9), (10), and (11) of the AC conversion circuit (14) is alternately turned on and off, the AC to the load (15) is controlled. No output occurs. Thus, the DC voltage (V _DC ) output from the DC conversion circuit (2) through the smoothing capacitor (7)
The AC conversion circuit
Since AC power is not supplied from (14) to the load (15), malfunction of the AC load at the time of starting the inverter device can be prevented.

When a certain period of time has elapsed since the start of the inverter device and the DC voltage (V _DC ) of the smoothing capacitor (7) is in a stable state, a driving signal is transmitted from the timer means (64).
(V _G1 ) and (V _G2 ) are output. At this time, AC conversion control means
(50) is a plurality of pairs of AC conversion switching elements (8) (9), (1)
Since the on / off control of (0) and (11) is performed alternately for each pair, the DC output of the DC conversion circuit (2) is converted to an AC output via the smoothing capacitor (7), and the AC output is applied to the load (15). Can be supplied.

The AC conversion circuit (14) includes first and fourth drive circuits (18) and (21) and second and third drive circuits (19) and (2).
0). The AC conversion control means (50) is a drive signal pulse-width controlled based on the AC output to the load (15).
A first drive for applying (V _G1 ) and (V _G2 ) to one of the first and fourth drive circuits (18) and (21) or the second and third drive circuits (19) and (20) Signal generation circuit (36) and second drive signal generation circuit
(38). Timer means (64) is a smoothing capacitor
The drive signal (36) and the drive signal (38) generated from the second drive signal generation circuit (38) when a predetermined time has elapsed since the input of the DC voltage (V _DC ) of (7). V _G1 ) and (V _G2 ) are applied to the other of the first and fourth drive circuits (18) and (21) or the second and third drive circuits (19) and (20). Timer means (64)
Is a timer circuit (63) that generates an output signal ( _VH ) when a certain period of time has elapsed since the start of the inverter device.
And a gate circuit connected to the timer circuit (63), the first drive signal generation circuit (36), and the second drive signal generation circuit (38)
(55a). The gate circuit (55a) is a timer circuit
First and fourth drive circuits according to the output signal (V _H ) from (63)
(18), (21) or drive signals (V _G1 ) and (V _G2 ) are applied to the other of the second and third drive circuits (19) and (20).

The rectification control means (16) includes a smoothing capacitor (7).
Of each of the rectifying switching means (3) and (4) of the DC conversion circuit (2) according to the voltage (V _DC ). That is, the drive signal (V _G3 ), (V _G4 ) of the pulse width according to the DC voltage (V _DC ) of the smoothing capacitor (7), the rectification switching means (3),
Each of (4) can be on / off controlled.

Furthermore, the inverter apparatus _{(A 1), (A 2} ) connected to the plurality parallel, a plurality of inverter devices (A _1), one of the inverter device of (A ₂₎ (A ₁₎ , (A ₂ ) are activated with a delay, a plurality of pairs of AC conversion switching elements constituting the AC conversion circuit (14) of the inverter devices (A ₁ ) and (A ₂ )
(8) Only one pair of (9), (10) and (11) is alternately turned on and off at different time ratios. Thereby, among the plurality of inverter devices (A ₁ ) and (A ₂ ) connected in parallel,
It is possible to prevent an abnormal rise in the DC voltage (V _DC ) at the input side of the AC conversion circuit (14) of the inverter device started with a delay.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of an inverter device according to the present invention will be described below with reference to FIGS. However, in these drawings, substantially the same parts as those shown in FIGS. 10 to 14 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 1, the inverter device according to the present embodiment includes an input terminal of a DC voltage _VDC of a smoothing capacitor (7) and an AC conversion control circuit (17) of the conventional inverter device shown in FIG. third and fourth driving circuit (20) includes an AC conversion control circuit obtained by adding the output terminal of the logical product signal V _A2, V _A1 as a driving signal to the (21) (50). As shown in FIG. 2, the AC conversion control circuit (50) includes a reference power supply (51) as reference voltage generation means, a comparator (52), and a first AND circuit.
A gate (53) and a second AND gate (54) are provided. A first AND gate (53) and a second AND gate (54)
Constitutes a gate circuit (55a). The reference power supply (51) generates a reference voltage V _RD for controlling a reference value of the DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7). The comparator (52) compares the level of the DC voltage _VDC of the smoothing capacitor (7) with the level of the reference voltage V _RD of the reference power supply (51), and compares the level of the DC voltage _{VDC with} the level of the reference voltage V _RD . Outputs a low-level comparison output signal V _CP when V _DC <V _RD , and outputs a high-level comparison output signal V _CP when V _DC ≧ V _RD . First AND gate (53)
The logical product signal V _A1 of the first drive signal V _G1 and comparison output signal V _CP of the comparator (52) output from the first drive signal generating circuit (36) fourth drive circuits (21) Output to The second AND gate (54) is connected to a second drive signal generation circuit (38).
Drive signal _VG2 output from the comparator and the comparator (52)
And outputs a logical product signal V _A2 with the comparison output signal V _CP to the third drive circuit (20). The comparator (52), the first and second AND gates (53) and (54) are used when the DC voltage _VDC of the smoothing capacitor (7) is less than the reference voltage (V _RD ) of the reference power supply (51). The first and second drive circuits (1) in the AC conversion circuit (14)
8) and (19), the first and second MOS-FETs (8),
(9) ON / OFF control alternately and smoothing capacitor (7)
The first and fourth drive circuits (1) in the AC conversion circuit (14) when the DC voltage V _DC of the AC power supply is higher than the reference voltage V _RD of the reference power supply (51).
8), (21) and the first and fourth MOS-FETs (8), (11) and the second drive circuit via the second and third drive circuits (19), (20).
And a comparison means (55) for alternately turning on and off the third MOS-FETs (9) and (10) in pairs. Other circuit configurations include the conventional inverter device shown in FIG.
This is substantially the same as the conventional AC conversion control circuit (17) shown in FIG.

In the above configuration, the main switch (60)
Is turned on and the power is supplied to the AC conversion control circuit (50),
The comparator (52) in the comparison means (55) is a DC conversion circuit (2)
DC voltage V output from the
_DC is compared with a reference voltage V _RD of a reference power supply (51). When the inverter device is started, the DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7) is applied to the reference power supply.
Since it is lower than the reference voltage V _RD of (51) (V _DC <V _RD ), the comparator (52) in the comparing means (55) outputs a low (L) level comparison output signal V _CP . The low-level comparison output signal V _CP is supplied to the first and second drive signal generation circuits (36), (3
8) and the first and second drive signals _VG1 and _VG2 are input to the first and second AND gates (53) and (54), respectively. At this time, the first and second AND gates (53), (54)
The AND signals V _A1 and V _A2 output to the fourth and third drive circuits (21) and (20) respectively become low as shown in FIGS. 3 (D) and (C), and And the fourth drive circuit (2
0) and (21) to the third and fourth MOS-FETs (10) and (11)
Low level logical product signals V _A2 and V _A1 are applied to the respective gate terminals, and both the third and fourth MOS-FETs (10) and (11) maintain the off state. On the other hand, first and second drive circuits
(18) and (19) respectively show the first and second drive signals V _G1 from the first and second drive signal generation circuits (36) and (38) shown in FIGS. 3 (A) and (B). , V _G2 are directly input, and the first and second
The first and second MOS-Fs are driven by the driving circuits (18) and (19) of FIG.
ET (8) and (9) are alternately turned on and off. Therefore, the DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7) does not rise sufficiently, and the reference power supply
Since the first and second MOS-FETs (8) and (9) are only turned on and off alternately when the inverter device which is lower than the reference voltage V _RD of (51) is started, the AC conversion is performed. Circuit (14)
Does not supply AC power to the load (15).

The ON / OFF operation of the first and second MOS-FETs (8) and (9) causes the third charge pump circuit (31)
Capacitor (28) is charged to a voltage V _DR of the drive power supply (22), commutation control circuit (16) is driven by a voltage V _DR charged in the capacitor (28). At this time, a smoothing capacitor
The third and fourth drive signals V _G3 , from the drive signal output terminals (e) and (f) of the rectification control circuit (16) according to the DC voltage _VDC of (7),
_VG4 is output and applied to the respective gate terminals of the first and second thyristors (3) and (4) in the DC conversion circuit (2). Thereby, the first and second thyristors in the DC conversion circuit (2) according to the DC voltage _VDC of the smoothing capacitor (7).
(3) and (4) are alternately turned on and off, and the DC conversion circuit
A current flows through (2), the commercial AC voltage V _IN from the commercial AC power supply (1) is converted into a DC voltage, and the smoothing capacitor (7) is charged to a constant voltage _VDC with the polarity shown. As described above, a constant level of the DC voltage _VDC is output from the DC conversion circuit (2) via the smoothing capacitor (7).

The DC voltage _VDC of the smoothing capacitor (7) reaches a certain level, and is equal to or higher than the reference voltage V _RD of the reference power supply (51).
_{When DC} ≧ V _RD ), the comparator (5) in the comparing means (55)
From 2), a high (H) level comparison output signal V _CP is output,
The first and second drive signal generation circuits (36) and (38)
And the second drive signals _VG1 and _VG2 are input to the first and second AND gates (53) and (54), respectively. At this time, the logical product signal V output from the first and second AND gates (53) and (54) to the fourth and third drive circuits (21) and (20).
_A1 and V _A2 are the first as shown in FIGS. 4 (D) and 4 (C), respectively.
And the second drive signals V _G1 and V _G2 . On the other hand, the first and second drive circuits (18) and (19) respectively have the configuration shown in FIG.
And (B) the first and second drive signal generation circuits (36),
The first and second drive signals V _G1 and V _G2 from (38) are directly input. Thereby, the first and fourth drive circuits (18),
(21) and the first and second drive signals _VG1 and _VG2 are input to the second and third drive circuits (19) and (20) respectively.
And fourth and fourth MOS-FETs (8) and (11), and second and third MOS-FETs (8) and (11).
MOS-FETs (9) and (10) are alternately turned on and off. Therefore, the DC conversion circuit (2)
(7) when the above reference voltage V _RD reference DC voltage V _DC outputted through the power source (51), the load of the AC conversion circuit in response to a sinusoidal AC voltage V _AC (15) (14) First and fourth MOS
-FETs (8) and (11) and second and third MOS-FETs
(9) and (10) are alternately turned on and off, and highly stable single-phase sinusoidal AC power is supplied to the load (15) via the filter reactor (12) and the filter capacitor (13).

In the inverter device of the embodiment shown in FIG. 1, the DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7) satisfies the reference voltage V _RD of the reference power supply (51). During startup, the AC converter circuit (1
Only the first and second MOS-FETs (8) and (9) in (4) are alternately turned on and off to drive the rectification control circuit (16) and load the load (15) from the AC conversion circuit (14). ) Is not supplied with AC power. Thereafter, when the DC voltage _VDC of the smoothing capacitor (7) reaches a certain level and becomes equal to or higher than the reference voltage V _RD of the reference power supply (51), the first and second signals in the AC conversion circuit (14) are compared by the comparing means (55). The fourth MOS-FETs (8) and (11) and the second and third MOS-FETs (9) and (10) are alternately turned on and off, and the load (15) is supplied from the AC conversion circuit (14). Sinusoidal AC voltage V
_AC is supplied. Therefore, when the DC voltage _VDC output from the DC conversion circuit (2) through the smoothing capacitor (7) is unstable and lower than the reference voltage V _RD of the reference power supply (51), the AC conversion circuit AC power is not supplied from (14) to the load (15), and malfunction of the AC load when the inverter device is started can be prevented.

The inverter device of the embodiment shown in FIG. 1 can be modified. For example, in the inverter device of the embodiment shown in FIG. 5, the connection positions of the rectification control circuit (16) and the third charge pump circuit (31) are changed to the third and fourth MOS-Fs.
ET (10) and (11) have been changed. In this case, when the DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7) is less than the reference voltage V _RD of the reference power supply (51), the start-up in the AC conversion circuit (14) is started. 3rd and 4th MOS-F
Only the ETs (10) and (11) are alternately turned on and off to supply the driving power from the third charge pump circuit (31) to the rectification control circuit (16), and the DC voltage of the smoothing capacitor (7) the first and fourth MOS-FET of the AC conversion circuit (14) when V _DC is equal to or higher than the reference voltage V _RD of the reference power source (51) (8), (11) and the second and third MOS -The FETs (9) and (10) may be alternately turned on and off.

In the inverter device according to the embodiment shown in FIG. 6, another rectification control circuit (56) and a diode
(57) and a capacitor (58) and a rectification control circuit (56)
Charge pump circuit (59) for supplying driving power to the power supply
Are connected to the third and fourth MOS-FETs (10) and (11), and the rectification control circuit (16) operates when the commercial AC voltage V _{IN of} the commercial AC power supply (1) has a positive half cycle. The first thyristor (3) in the DC conversion circuit (2) is turned on and off, and when the commercial AC voltage V _IN has a negative half cycle, the rectification control circuit (56) controls the thyristor (3) in the DC conversion circuit (2). On / off control of the second thyristor (4). In this case, the commercial AC voltage V of the commercial AC power supply (1)
_IN is a positive half cycle, and the DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7) is the reference voltage (5
If the reference voltage V _RD in (1) is not reached, the AC conversion circuit (14)
Of the first and second MOS-FETs (8) and (9) are alternately turned on and off, so that the driving power is supplied from the third charge pump circuit (31) to the rectification control circuit (16). Should be supplied. Further, the commercial AC voltage V _IN has a negative half cycle and the DC voltage _VDC output from the DC conversion circuit (2) via the smoothing capacitor (7) is less than the reference voltage V _RD of the reference power supply (51). At this time, the third and fourth MOs in the AC conversion circuit (14)
The drive power may be supplied from the fourth charge pump circuit (59) to the rectification control circuit (56) by alternately turning on and off only the S-FETs (10) and (11). When the DC voltage _VDC of the smoothing capacitor (7) becomes equal to or higher than the reference voltage V _RD of the reference power supply (51), the first voltage in the AC conversion circuit (14) is reduced.
And fourth and fourth MOS-FETs (8) and (11), and second and third MOS-FETs (8) and (11).
MOS-FETs (9) and (10) may be alternately turned on and off.

As shown in FIG. 7, instead of the comparing means (55) of the AC conversion control circuit (50) shown in FIG. 2, a set pulse generation circuit (61), a reset pulse generation circuit (62), a timer A timer means (64) including a circuit (63) and a gate circuit (55a) may be provided, and the input terminal of the smoothing capacitor (7) for the DC voltage _VDC may be omitted. Set pulse generation circuit (61)
Is the drive power supply (2) when the main switch (60) is turned on.
In synchronization with the rising edge of the voltage V _DR 2) and outputs a set pulse signal V _S. Reset pulse generation circuit (62)
Is the drive power (2) when the main switch (60) is turned off.
In synchronization with the falling edge of the voltage V _DR 2) outputs a reset pulse signal V _R. Timer circuit (63) is set terminal set pulse signal V _S is constant since the input time from the (S) to the set pulse generating circuit (61), for example, a smoothing capacitor DC voltage V _DC is constant (7) outputs the output signal V _H of high level when the time to reach the level has passed, low level output when the reset pulse signal V _R from the reset pulse generating circuit (62) is input to the reset terminal (R) The signal _VL is output. The timer circuit (63) includes, for example, a flip-flop, a counter, and a CR (a capacitor and a resistor).
It can be configured in combination with a circuit. Further, the set pulse generation circuit (61), the reset pulse generation circuit (62) and the timer circuit (63) may be constituted by a digital IC for timer such as 555.

In the inverter device provided with the AC conversion control circuit (50) shown in FIG. 7, the main switch (60) is turned on to turn on the power to the AC conversion control circuit (50). pulse signal generating circuit (61) set pulse signal V _S is outputted from and inputted to the set terminal of the timer circuit (63) (S). At this time, the timer circuit (63) is set, and starts counting the elapsed time. When the inverter device is started, a low-level output signal _VL is output from the timer circuit (63), so that the first and second AND gates are output.
The AND signals V _A1 and V _A2 output from (53) and (54) to the fourth and third drive circuits (21) and (20) respectively become low level, and the third and fourth MOS- Both the FETs (10) and (11) maintain the off state. On the other hand, first and second drive circuits
(18) and (19) respectively include the first and second drive signals V _G1 and V _G2 from the first and second drive signal generation circuits (36) and (38).
Are directly input, the first and second driving circuits (18),
According to (19), the first and second MOS-FETs (8) and (9) are alternately turned on and off. Thereby, the capacitor (28) of the third charge pump circuit (31) is charged to the voltage _{VDR of the} driving power supply (22), and the rectification control circuit (16) is driven.
First and second thyristors (3) in a DC conversion circuit (2),
(4) is turned on / off to generate a DC voltage _VDC across the smoothing capacitor (7). Therefore, the DC conversion circuit
When starting the inverter device in which the DC voltage _VDC output from (2) via the smoothing capacitor (7) is unstable, the first and second MOS-FETs (8) and (9) are turned on alternately. AC power is not supplied from the AC conversion circuit (14) to the load (15) because only the off control is performed.

When a certain period of time has passed since the set pulse signal V _S of the set pulse generation circuit (61) was input to the set terminal (S) of the timer circuit (63), a high level output from the timer circuit (63) was output. A signal V _H is output and the first and second ANs are output.
It is given to D gates (53) and (54). At this time, the AND signals V _A1 and V _A2 output from the first and second AND gates (53) and (54) to the fourth and third drive circuits (21) and (20) are respectively equal to the first. And the second drive signals V _G1 and V _G2 . On the other hand, the first and second drive circuits (18) and (19) respectively provide the first and second drive signals V _G1 from the first and second drive signal generation circuits (36) and (38), _VG2 is directly input.
As a result, the first and second drive signals V _G1 and V _G2 are respectively supplied to the first and fourth drive circuits (18) and (21) and the second and third drive circuits (19) and (20). The first and fourth MOS-FETs (8) and (11) and the second and third MOS-FETs
The FETs (9) and (10) are alternately turned on and off so that the DC output of the DC conversion circuit (2) can be converted to an AC output and the AC output can be supplied to the load (15). Main switch (60)
Turning off, the output reset pulse signal V _R from the reset pulse generating circuit (62), is input to the reset terminal of the timer circuit (63) (R). This allows the timer circuit (6
3) is in the reset state, so that the low-level output signal V _L
Is output, and the AC conversion control circuit (50) returns to the initial state, that is, the state at the time of starting the inverter device. At the same time, the supply of power to each part of the AC conversion control circuit (50) stops, and the operation of the inverter device stops. Therefore, in this case, substantially the same operation and effect as those of the embodiment shown in FIG. 1 can be obtained.

By the way, as shown in FIG.
Connect the inverter device of the embodiment shown in two parallel, one inverter apparatus A ₁ is the time to start with a delay the other inverter device A ₂ at the time of normal operation, the other inverter in the apparatus A ₂ The DC voltage _VDC of the smoothing capacitor (7) may rise abnormally. That is, the other inverter device A ₂ at the time of startup, the third and fourth MOS-FET in the AC conversion circuit (14) (10), (11) to the OFF state and the first and second in the MOS- When the FETs (8) and (9) are turned on and off alternately, the AC conversion circuit (14) operates as a step-up converter in the opposite direction, and the smoothing capacitor connected to the input side of the AC conversion circuit (14) ( Since 7) is boosted and charged, the DC voltage _VDC of the smoothing capacitor (7) rises abnormally. To explain the details of the operation of the AC circuit of the other inverter in the device A ₂ in this case (14), a second MOS-F
When the ET (9) is on and the first MOS-FET (8) is off, the filter reactor (12), the fourth
Current flows through the path of the parasitic diode (not shown), the second MOS-FET (9) and the load (15) built in the MOS-FET (11), and energy is accumulated in the filter reactor (12). . Next, when the second MOS-FET (9) is turned off and the first MOS-FET (8) is turned on, the energy stored in the filter reactor (12) is released, and the load is reduced.
(15) to the filter reactor (12), the fourth MOS-FE
A current flows through a path of a parasitic diode (not shown), a smoothing capacitor (7), a first MOS-FET (8) and a load (15) built in T (11), and the smoothing capacitor (7) is boosted and charged. Is done. Therefore, in the embodiment shown in FIG. 8, when activating the other inverter device A ₂ later than one inverter device A _1, the DC voltage V _DC of the other smoothing capacitor in the inverter device A ₂ (7) Is the reference voltage V of the reference power supply (51)
When it is lower than _{RD, the} AC conversion circuit is
The third and fourth MOS-FETs (10) and (11) in (14) are turned off as shown in FIGS. 9D and 9C, and the first and second MOS-FETs are (8) and (9) are shown in FIG.
As shown in (B), on / off control is performed alternately at different time ratios. This will prevent the operation of the reverse boost converter AC conversion circuit (14) at the time of activation of the other inverter device A _2, can prevent abnormal rise of the DC voltage V _DC of the smoothing capacitor (7).

The embodiments of the present invention are not limited to the above embodiments, and various changes can be made. For example, in each of the above embodiments, the DC conversion circuit (2) is configured by bridging two thyristors (3) and (4) with two diodes (5) and (6). , Two thyristors (3), (4)
Is replaced with a diode to form a bridge rectifier circuit, and a thyristor is connected to one or both of a pair of rectified output lines between the bridge rectifier circuit and the smoothing capacitor (7) to form a DC converter circuit (2). However, the thyristor may be turned on / off in accordance with the DC voltage _VDC of the smoothing capacitor (7). Also, a thyristor bridge circuit is constructed by replacing the two diodes (5) and (6) with thyristors, and each thyristor of the thyristor bridge circuit is controlled to be turned on / off according to the DC voltage _VDC of the smoothing capacitor (7). Is also good. Further, the connection positions of the two thyristors (3) and (4) and the two diodes (5) and (6) may be interchanged.
Further, a transistor may be used instead of the thyristor. Further, the DC conversion circuit (2) is not limited to the bridge rectifier circuit, but may be a center tap rectifier circuit having a transformer or a half-wave rectifier circuit. In each of the above embodiments, a MOS-FET (MOS-FET) having a parasitic diode as an AC conversion switching element constituting the AC conversion circuit (14) is used.
Type field-effect transistor),
General junction type bipolar transistor, J-FET
(Junction field effect transistor) or IGBT (insulated gate bipolar transistor) can also be used.
Similarly, a MOS-FET, a junction bipolar transistor, a J-FET, an IGBT, or the like can be used in place of the thyristor used as the rectifying switching means constituting the DC conversion circuit (2) in each of the above embodiments. Further, in each of the above-described embodiments, an embodiment in which the present invention is applied to a single-phase AC inverter device having a DC conversion circuit (2) and an AC conversion circuit (14) having a single-phase bridge configuration has been described. The present invention is also applied to a three-phase AC inverter device having a DC conversion circuit and an AC conversion circuit having a bridge configuration, or a multi-phase AC inverter device having a DC conversion circuit and an AC conversion circuit having a four-phase or more polyphase bridge configuration. Applicable.

[0037]

According to the present invention, when the DC voltage output from the DC conversion circuit via the smoothing capacitor and to be converted to the AC voltage is less than the steady level, the supply of the AC power to the load is prevented. After the DC voltage reaches the steady level, stable AC power is supplied to the load, so that a malfunction of the load can be prevented when the inverter device is started.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of an inverter device according to the present invention.

FIG. 2 is a circuit block diagram showing an internal configuration of the AC conversion control circuit shown in FIG.

FIG. 3 is a time chart of first and second drive signals and respective AND signals when the inverter device shown in FIG. 1 is started;

FIG. 4 is a time chart of first and second drive signals and respective AND signals during a normal operation of the inverter device shown in FIG. 1;

5 is an electric circuit diagram showing a modified embodiment of the inverter device shown in FIG.

6 is an electric circuit diagram showing another modified embodiment of the inverter device shown in FIG.

FIG. 7 is a circuit block diagram showing an internal configuration of an AC conversion control circuit of an inverter device according to another embodiment of the present invention.

FIG. 8 is a block diagram showing an embodiment of the inverter device of the present invention during parallel operation.

FIG. 9 is a time chart of the first and second drive signals and respective logical product signals when the other inverter device shown in FIG. 8 is activated.

FIG. 10 is an electric circuit diagram showing a conventional inverter device.

11 is a circuit block diagram showing an internal configuration of the AC conversion control circuit shown in FIG.

12 is an electric circuit diagram showing an internal configuration of the rectification control circuit shown in FIG.

13 is an electric circuit diagram showing an internal configuration of the first to fourth drive circuits shown in FIG.

FIG. 14 is a time chart of first and second drive signals of the inverter device shown in FIG. 10;

[Explanation of symbols]

(1) ··· commercial AC power supply (AC power supply); (2) · · · DC conversion circuit; (3) · · · first thyristor (rectifying switching means); (4) · · · second thyristor (rectifying switching means) ), (5) ··· First diode, (6) ··· Second
Diode, (7) ··· smoothing capacitor, (8) · · · 1st
MOS-FET (switching element for AC conversion),
(9) ··· Second MOS-FET (switching element for AC conversion), (10) · · · Third MOS-FET (switching element for AC conversion), (11) · · · Fourth MOS-FET
(Switching element for AC conversion), (12) Filter reactor, (13) Filter capacitor, (14)
・ AC conversion circuit, (15) ・ ・ Load, (16) ・ ・ Rectification control circuit (rectification control means), (17) ・ ・ AC conversion control circuit (AC conversion control means), (18) ・ ・ First Drive circuit,
(19) a second drive circuit, (20) a third drive circuit,
(21) ··· Fourth drive circuit, (22) ··· Power supply for drive,
(23), (24), (25) · Diode, (26), (27), (28)
..Capacitor, (29) first charge pump circuit, (30) second charge pump circuit, (31)
Third charge pump circuit, (32) ··· Reference sine wave oscillator, (33) · · · Error amplifier, (34) · · · Triangle wave oscillator,
(35) ··· PWM comparator, (36) · · · First drive signal generation circuit, (37) · · · Inverter, (38) · · · Second drive signal generation circuit, (39), (40), (41) ・ ・ Resistance, (42) ・
· NPN transistors, (43) · · Gate control signal generation circuits, (44) · · Positive / negative judgment circuits, (45) · · Inverters,
(46) ··· First AND gate, (47) ··· Second AN
D gate, (48) NPN transistor, (49)
· PNP type transistor, (50) · · · AC conversion control circuit (AC conversion control means), (51) · · · Reference power supply (reference voltage generation means), (52) · · · Comparator, (53) · ·
AND gate of (54) ··· second AND gate, (5)
5) Comparison means, (55a) Gate circuit, (56)
Rectification control circuit (rectification control means), (57) Diode, (58) Capacitor, (59) Fourth charge pump circuit, (60) Main switch, (61) Set pulse Generator circuit, (62) reset pulse generator circuit, (63) timer circuit, (64) timer means

Continuation of the front page (72) Inventor Yuji Fujino 3-6-3 Kitano, Niiza-shi, Saitama F-term (reference) in Sanken Electric Co., Ltd. 5H007 CA02 CB05 CC05 CC12 DA03 DA06 DB01 DB09 DC05 EA13 GA01 5H410 BB04 CC03 DD03 EA03 EA11 EA35 EA39 EB05 EB09 FF03 FF25 HH02 KK01 LL04 LL18

Claims (9)

[Claims] 1. A DC conversion circuit for converting an AC voltage of an AC power supply into a DC voltage, a smoothing capacitor for smoothing a DC output of the DC conversion circuit, and a DC output of the DC conversion circuit via the smoothing capacitor. An AC conversion circuit that converts the AC output into an AC output and supplies the AC output to a load, wherein the AC conversion circuit includes a plurality of pairs of bridge-connected AC conversion switching elements, and the plurality of pairs of AC conversion switching. AC conversion control means for generating the AC output to the load by alternately turning on and off the elements in pairs, wherein the DC conversion circuit comprises a rectifying switching means and the plurality of pairs of the AC conversion circuits. The rectifying switching means is driven by the on / off operation of the AC conversion switching element, and the rectifying switching means is turned on / off to generate the DC output to the smoothing capacitor. An AC conversion control unit, wherein the AC conversion control unit alternately turns on and off only one pair of the plurality of pairs of AC conversion switching elements when the inverter device is started up, and the rectification control unit And when the DC voltage output from the DC conversion circuit via the smoothing capacitor reaches a certain level or when a certain time has elapsed since the start of the inverter device, the plurality of pairs are driven. An on / off control of the AC conversion switching elements alternately for each pair. 2. The AC conversion control means includes: a reference voltage generation means for generating a reference voltage; and a comparison means for comparing a DC voltage output from the DC conversion circuit via the smoothing capacitor with the reference voltage. The comparing means, when the DC voltage is less than the reference voltage, alternately ON / OFF only one pair of the plurality of pairs of AC conversion switching elements by a current flowing through the DC conversion circuit. Charging the smoothing capacitor,
2. The inverter device according to claim 1, wherein when the DC voltage is equal to or higher than the reference voltage, the plurality of pairs of AC conversion switching elements are alternately turned on / off for each pair. 3. The AC conversion circuit includes first and fourth drive circuits and second and third drive circuits, and the AC conversion control means controls a pulse width based on an AC output to the load. A first drive signal generation circuit and a second drive signal generation circuit for applying the obtained drive signal to one of the first and fourth drive circuits or the second and third drive circuits. Only when the DC voltage is equal to or higher than the reference voltage, the drive signal generated from the first drive signal generation circuit and the second drive signal generation circuit is transmitted to the first and fourth drive circuits or the second and fourth drive circuits. 3. The inverter device according to claim 2, wherein the inverter device is provided to the other of the driving circuits of (3). 4. A comparator having an input terminal connected to the smoothing capacitor and the reference voltage generator, and the comparator, the first drive signal generator, and the second drive signal generator. 4. The inverter device according to claim 3, further comprising a connected gate circuit, wherein the gate circuit supplies a drive signal to the other of the first and fourth drive circuits or the second and third drive circuits. 5. 5. An AC conversion control means comprising: a timer means for outputting a drive signal when a certain time has elapsed since the activation of the inverter device, wherein the AC conversion control means comprises: 2. The inverter device according to claim 1, wherein when the drive signal is output, the plurality of pairs of AC conversion switching elements are alternately turned on / off for each pair. 6. The AC conversion circuit includes first and fourth drive circuits and second and third drive circuits, and the AC conversion control unit controls pulse width based on an AC output to the load. A first drive signal generation circuit and a second drive signal generation circuit for applying the obtained drive signal to one of the first and fourth drive circuits or the second and third drive circuits. The drive signals generated from the first drive signal generation circuit and the second drive signal generation circuit when a certain period of time has elapsed since the activation of the inverter device, and the first and fourth drive circuits or Second and third
The inverter device according to claim 5, which is provided to the other one of the drive circuits. 7. A timer circuit for generating an output signal when a certain period of time has elapsed since the start of the inverter device, the timer circuit and the first circuit.
And a gate circuit connected to the second drive signal generation circuit, wherein the gate circuit receives the first and fourth drive circuits or the second and third drive circuits in accordance with an output signal from the timer circuit. The inverter device according to claim 6, wherein a drive signal is applied to the other of the drive circuits. 8. The inverter device according to claim 1, wherein the rectification control unit controls on / off of the rectification switching unit of the DC conversion circuit according to a voltage of the smoothing capacitor. 9. When a plurality of the inverter devices according to claim 1 are connected in parallel, and one of the plurality of inverter devices is started with a delay, An inverter device, characterized in that only one of the plurality of pairs of AC conversion switching elements constituting the AC conversion circuit of the inverter device is alternately turned on and off at different time ratios.