JP2000244363A - Circuit and device for generating pn code - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PN code generating device capable of speedily generating a PN code. SOLUTION: Four kinds of PN code generating circuits 11 to 14 are connected in parallel with respect to a clock control circuit CC and a data selector DS and are respectively provided with a reset switch RS and a code switch terminal CT in addition. A clock signal CLK and a number of stages switch signal CT are inputted to the clock control part CC. A code switch signal NT1 from the part CC for switching an output signal from the respective parts 11 to 14 is inputted to the data selector DS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CDMA (code d)
The present invention relates to a communication device that employs an ivision multiple access (code division multiple access) system or an SSMA (spread spectrum multiple access) system, and particularly relates to a pseudo random code (PN) in this communication device.
Code) at a high speed.

[0002]

2. Description of the Related Art In the CDMA system or the SSMA system, a specific PN code is assigned to a line, a modulated wave of the same carrier frequency is spread with this PN code and transmitted to the same relay device. Is a multiple access method for identifying a line by taking A communication device adopting such a system has a built-in PN code generation circuit (or device) for generating a desired PN code. In this type of PN code generation circuit, usually, a plurality of stages of registers are connected in cascade, a required number of register outputs are fed back to the first stage register, and the required number of register outputs are appropriately selected, so that the PN code is selected. It is generated.

FIG. 12 shows a flip-flop (hereinafter referred to as F / F), which is an example of a register, connected in cascade at 19 stages, and outputs the outputs of the F / Fs of a predetermined stage and a final stage to a plurality of stage number switching gates G2 and EXOR (Exclusive-O
R) The first stage F /
It is a principal part block diagram of the PN code generation circuit fed back to F # 1. Actually, the input section of the first stage F / F # 1 has an OR gate for inputting a reset signal and data and a terminal for inputting a clock signal, but these are not shown here. is there. In this PN code generation circuit, 1 to 3
The first, fifth, ninth, thirteenth, seventeenth, and last stages are fed back to the first stage F / F # 1 via feedback taps, and the seventh stage F / F # 7 is returned. , 13th stage F /
The outputs of the F / F # 17 of the 17th stage and the F / F # 19 of the 19th stage (final stage) are input to the data selector DS. The data selector DS can selectively output four types of PN codes by appropriately switching these outputs.

[0004]

In the PN code generating circuit, when the output of each stage F / F is fed back to the first stage F / F # 1, the propagation delay time corresponding to the number of feedback taps is accumulated. You. That is, the operable upper limit speed of the PN code generation circuit is determined by the accumulated value of the propagation delay time of the EXOR gate G1, the stage number switching gate G2, and the F / Fs # 1 to # 19. In the case of the configuration example of FIG. 12, the last stage shift register #
By the time the output of No. 19 is fed back to the input terminal of the first stage shift register # 1, thirteen stage number switching gates G2 and E
An XOR gate G1 is interposed. Each gate G1, G2, F
/ F # 1 to # 19 as ECL (Emitter Coupled Logi
It is known that the propagation delay time can be reduced by using the c) type IC, but the current IC is 0.6 [ns].
ec]. Therefore, 13 ICs
7.8 [nsec] (= 0.6 [nsec]
× 13), and each F / F # 1
Assuming that the setup time of # 19 to # 19 is 0.175 [nsec], it is necessary to consider a propagation delay time of 7.975 [nsec] in total. This is about 1 in terms of frequency.
25 [MHz]. Therefore, the conventional PN code generation circuit cannot generate a high-speed PN code of 200 [MHz] or more.

The PN code output from the F / F at each stage is different depending on the position of the feedback tap.
For example, FIGS. 13 to 16 are composed of the same seven stages of F / Fs, but since the positions of the feedback taps are different, the final stage F / Fs are shown.
The PN codes output from the F # 7 are different from each other (note that the configuration of the input section of the first stage F / F # 1 is omitted as in FIG. 12).
As described above, when a plurality of types of PN codes are used, it is necessary to separately configure PN code generation circuits in which the positions of the feedback taps are changed, and the scale of a communication device incorporating the PN code becomes large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a PN code generation circuit and a device having a simple configuration capable of generating a PN code at a higher speed.

[0007]

According to the PN code generation circuit provided by the present invention, some output signals of a plurality of cascade-connected registers are directly fed back to an input portion of a first-stage register to form a feedback loop. Between the registers of the predetermined stage,
A logic circuit for judging a logical condition between an output signal of a register at a preceding stage and a branch signal of the feedback loop, and inputting a decision result to a register at a subsequent stage is inserted and connected, and a required register determined by the decision result of the logic circuit. Is extracted so as to be extracted as a PN code.

In another PN code generation circuit of the present invention, a feedback loop is formed by directly outputting an output signal of a last register among a plurality of cascade-connected registers to an input portion of a first register. Between the registers of the stage, a logic circuit for judging the logical condition of the output signal of the register of the previous stage and the branch signal of the feedback loop and inputting the judgment result to the register of the subsequent stage is inserted and connected. Switch means for controlling the conduction of the branch signal to a circuit,
An output signal of a required register determined by a control result by the switch means and a result of determination of a logic circuit associated therewith is extracted as a PN code. The logic circuit may be inserted and connected between all registers except the first and last stages so that the number of register stages can be arbitrarily changed according to the control result of the switch means.

The present invention also provides a plurality of PN code generation circuits which are connected in parallel to a common signal source and generate PN codes having different arrangement structures, and a PN code from these PN code generation circuits. There is also provided a PN code generation device having code switching means for selectively outputting. Preferably, the plurality of PN code generation circuits are the PN code generation circuits of the present invention described above, and each of the plurality of PN code generation circuits is constituted by a different number of register rows.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a configuration diagram of a PN code generator to which the present invention is applied. This PN code generator 1 has 4
Code generation circuit 1 for generating various types of PN codes
1, 12, 13, and 14 are connected in parallel to a clock control circuit CC that is a common signal source, and each output is input to a data selector DS that is an example of code switching means. . Each PN code generation circuit 11-1
The reset signal RS is input to each of the input sides of the clock signal 4, and the clock signal CLK and the sign switching control signal CT are input to the clock control circuit CC. Based on the code switching control signal CT, the clock control circuit CC outputs a code switching signal NT1 for switching the outputs of the PN code generation circuits 11 to 14 to the data selector DS. This determines which output of the PN code generation circuits 11 to 14 is to be selected.

In this example, the PN code generation circuit 11
This is a shift register with a stage configuration, and a P
The N code is generated. Similarly, the PN code generation circuit 12 is a shift register having a 13-stage configuration, the PN code generation circuit 13 is a shift register having a 17-stage configuration, and the PN code generation circuit 14 is a shift register having a 19-stage configuration. Is generated.

These PN code generation circuits 11 to 14
This is an improvement of a conventional PN code generation circuit of this type. Hereinafter, this improvement will be described by referring to the seven-stage PN code generation circuit 11 shown in FIG.
The N-code generation circuit will be described as an example (the configuration of the input section of the first stage F / F # 1 is omitted for the sake of convenience. The same applies to the description of the embodiment hereinafter).

The conventional PN code generation circuit shown in FIG. 13 uses feedback taps from the first to third stages. In this case, the output signal of each stage is a repetitive signal that makes one round of 127 bits as shown in FIG. However, in the configuration shown in FIG. 13, a plurality of EXOR gates G
1 intervenes, the output of the F / F of each stage becomes the F / F of the first stage.
The propagation delay time is accumulated until the signal is returned to # 1.

On the other hand, the PN code generation circuit 11 according to the present embodiment outputs the F / F output of each stage to the F / F # of the first stage.
1 to form a feedback loop by directly feeding back to the input unit (OR gate for determining the OR condition with the reset signal)
The XOR gate G1 is inserted and connected between the fourth and fifth stages, between the fifth and sixth stages, and between the sixth and seventh stages. This EXOR gate G1 is connected to the F
The logic condition (exclusive OR condition) between the output signal of / F and the branch signal of the feedback loop is determined. The output signal of each stage in this case is as shown in FIG.
It is a repetitive signal that makes one round of bits, and the change in the signal at the seventh stage shows the same change as in FIG. That is,
By adopting the connection method of this embodiment, the propagation delay time can be made as close to zero as possible while generating the same PN code as the PN code generation circuit shown in FIG. 13 (only the OR gate portion of the input section). )be able to.

3 to 5 show a 13-stage configuration, a 17-stage configuration,
FIG. 3 is a diagram illustrating a configuration example of a PN code generation circuit having a 19-stage configuration; These PN code generation circuits 12 to
Similarly to the seven-stage configuration in FIG. 2, the EXOR gate G1 in the feedback loop is omitted, and the EXOR gate 14 is inserted and connected between the corresponding F / Fs.

As in the conventional PN code generation circuit shown in FIG. 12, the PN code generation circuits shown in FIGS. 2 to 5 are integrated to selectively output the output of each stage. However, for that purpose, it is necessary to insert and connect some stage number switching gates G2 to the feedback loop (still faster than the PN code generation circuit shown in FIG. 12).
Therefore, the operation speed is reduced accordingly. In order to avoid such a situation, in the present embodiment, as shown in FIG.
Each of the PN code generation circuits 11 to 14 is connected to a clock control circuit CC.
Are connected in parallel, and different PN codes are generated for the same signal source at the same time. As described above, according to the PN code generator 1 of the first embodiment, a PN code can be generated at a high speed with a simple configuration.

(Second Embodiment) In the PN code generator 1 of the first embodiment shown in FIG.
14 can generate a PN code having one kind of array structure. When the arrangement structure of the required PN codes is fixed, such a PN code generation device 1 is preferable because the device configuration is simplified, but actually, the required PN codes are There may be more than one type. In this case, it is necessary to change the position of the return tap. Thus, the PN code generator 2 shown in FIG. 6 is capable of arbitrarily changing the position of the feedback tap while maintaining the same device configuration.

In this PN code generator 2, four types of PN code generation circuits 21, 22, 23, and 24 are connected in parallel to a clock control circuit CC. A reset signal RS is input to the input side of each of the PN code generation circuits 21 to 24, and a clock signal CLK and a code switching control signal CT are input to the clock control circuit CC. On the basis of the point and code switching control signal CT, the clock control circuit CC
The output of the code switching signal NT1 for switching the output of the data selector # 24 to the data selector DS is the same as that of the first embodiment.
This is the same as the N code generator 1.

The PN code generator 2 of this embodiment is designed so that each of the PN code generation circuits 21 to 24 can output the PN code with its length and code arrangement arbitrarily changed. The number-of-stages switching signal NT2 for controlling the position of the feedback tap is input to the generation circuits 21 to 24. Such a special configuration example will be described with reference to the PN code generation circuit 21 having a seven-stage configuration shown in FIG. 7 as an example.

Referring to FIG. 7, EXOR gate G1
Is connected between the F / Fs of all stages except the first and last stages of the plurality of F / Fs, and a branch signal from a feedback loop is connected to each EXOR gate G1 via a stage number switching gate G2. Is to be entered. The stage number switching gate G2 is provided with a stage number switching signal NT2 from the switching circuit SW.
Is used to control the conduction of the branch signal. In the PN code generation circuit 21 having such a configuration, the F / F #
EXO in feedback loop from # 2 to # 7 to first stage F / F # 1
Since the R gate G1 does not intervene, there is no accumulation of the propagation delay time. When changing the number of register stages, that is, the code length,
The required stage number switching gate G2 is turned ON / OFF by the stage number switching signal NT2 from the switching circuit SW. Accordingly, the OFF stage number switching gate G2 is equivalent to the case where it does not exist, while the ON stage number switching gate G2 is connected to the branch signal of the feedback loop and the F signal of the preceding stage.
The exclusive OR condition with the output signal of / F is determined, and the determination result is input to the subsequent F / F, so that a feedback tap is formed, and the required code length and PN code of the arrangement are provided. Can be obtained. 13-stage configuration, 17-stage configuration, 1
The same applies to the nine-stage PN code generation circuits 22 to 24. As described above, according to the PN code generation device 2 of the second embodiment, it is possible to generate PN codes of any length and arrangement at high speed with a simple configuration.

[0021]

In the second embodiment, an example is shown in which the EXOR gate G1 is inserted between all the F / Fs except the first stage and the last stage. However, from the viewpoint of generating a high-speed PN code, the EXO gate G1 is used.
The R gate only needs to be inserted between some F / Fs. 8 to 11 show the PN code generation circuit 2 in FIG.
1 to 24 are introduced in a form close to an actual operation mode. 8 is a 7-stage configuration, FIG. 9 is a 13-stage configuration, and FIG.
FIG. 11 shows an example of a PN code generation circuit having a seven-stage configuration and a nineteen-stage configuration. Symbols # 1 to # 19 are D-type F / Fs, which are examples of registers. The D-type F / F is a terminal to which a logical OR output of the code data and the reset signal RS is input, the CK terminal to which a clock signal CLK is input, and the code data is Output Q terminal, logic low
It has an R terminal to which the signal “L” is connected. G11 is an EXOR gate, and G12 is a stage number switching gate. Here, for example, a 3-bit binary signal (which becomes a logical High signal “H” when the switch is turned on) is input to each PN code generation circuit from the switching circuits SW1 to SW4, thereby adjusting the position of the feedback tap. I have to.
For example, FIG. 8 shows a configuration for realizing a feedback tap corresponding to FIG.

In FIG. 9, when the uppermost switch of the switching circuit SW2 is N1, the middle switch is N2, and the lower switch is N3, the output level (binary level) of each of the switches N1, N2, N3 is I system (1,0,
0), II system (0, 1, 0), and III system (0, 0, 1). The feedback tap positions in the I system are # 13, # 12, # 10, # 9, and the feedback tap positions in the II system are # 13, # 9, # 8, # 6, # 4, #
3, the return tap position in III system is # 13, # 1
2, # 8, # 6, # 5, and # 4.

Also in the case of FIG. 10, the uppermost switch of the switching circuit SW3 is N1, the middle switch is N2, the lower switch is N3, and the I system (1, 1) is determined by the combination of the output levels of the switches N1, N2 and N3. 0,0), II system (0,
1,0) and III system (0,0,1) can be selected. However, as shown in the figure, a specific system, for example, a system I may not be used (OPEN). In the case shown, the feedback tap positions in the II system are # 17, # 1
The feedback tap positions in the # 6, # 15, # 14, and III systems are # 17, # 16, # 14, and # 1.

Similarly, in the case of FIG. 11, the uppermost switch of the switching circuit SW4 is N1, the middle switch is N2, the lower switch is N3, and the I system (in accordance with the combination of the output levels of the switches N1, N2 and N3). 1,0,0), II system (0,1,0), and III system (0,0,1). In the illustrated case, the feedback tap positions in the I system are # 19, #
The feedback tap positions in 18, 18, 17, 14, and II systems are # 19, # 16, # 12, # 10, # 9, # 7, II
The return tap positions in the I system are # 19, # 16, # 1
3, # 12, # 11, and # 10.

In the examples shown in FIGS. 8 to 11, the PN code in any one of the three systems can be selected, but the number of the systems may be arbitrary.
Further, the EXOR gate G11 and the stage number switching gate G21
Can be appropriately changed according to the use of the PN code.

In the above embodiment or example, F
Although the EXOR gates G1 and G11 are used as the logic circuits inserted and connected between / F, it goes without saying that the logic circuits can be replaced with other logic gates. The same applies to the stage number switching gates G2 and G21. (Communication Device) The PN code generation circuits shown in FIGS. 2 to 5, 7, and 8 to 11 can be used alone.
Such a PN code generation circuit alone, or as a PN code generation device 1 or 2 having a plurality of PN code generation circuits as shown in FIG. 1 or FIG.
It can be used as a code generation unit of a communication device adopting the SMA system. In this case, the modulation wave of the carrier frequency is spread with the generated PN code and transmitted. By using the communication device configured as described above, high-speed communication using spread spectrum can be performed.

[0027]

As described above, according to the present invention, by generating a PN code similar to that of the conventional PN code generation circuit, the generation element of the propagation delay time can be reduced by devising the insertion point of the logic circuit. Can be reduced. As a result, it is possible to generate a high-speed PN code that can be used even at a frequency of 200 [MHz] or higher, which was impossible in the past.

In the PN code generator of the present invention, a plurality of PN code generation circuits are arranged in parallel with respect to the signal source, and the PN codes from these PN code generation circuits are selectively output. Therefore, a faster PN code can be generated.

Furthermore, since the number of register stages in each PN code generation circuit can be switched as appropriate, PN codes having an arbitrary arrangement structure can be easily generated with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PN code generator according to a first embodiment of the present invention.

FIG. 2 is a main part configuration diagram of a seven-stage PN code generation circuit according to the first embodiment;

FIG. 3 is a main part configuration diagram of a PN code generation circuit having a 13-stage configuration according to the first embodiment;

FIG. 4 is a main part configuration diagram of a 17-stage PN code generation circuit according to the first embodiment;

FIG. 5 is a main part configuration diagram of a 19-stage PN code generation circuit according to the first embodiment;

FIG. 6 is a configuration diagram of a PN code generator according to a second embodiment of the present invention.

FIG. 7 is a main part configuration diagram of a seven-stage PN code generation circuit according to a second embodiment;

FIG. 8 is a main part configuration diagram of a seven-stage PN code generation circuit according to the embodiment.

FIG. 9 is a main part configuration diagram of a PN code generation circuit having a 13-stage configuration according to the embodiment.

FIG. 10 is a main part configuration diagram of a PN code generation circuit having a 17-stage configuration according to the embodiment.

FIG. 11 is a main part configuration diagram of a 19-stage PN code generation circuit according to an embodiment.

FIG. 12 is a configuration diagram of a conventional PN code generation circuit.

FIG. 13 is a main part configuration diagram of a conventional seven-stage PN code generation circuit.

FIG. 14 is a main part configuration diagram of a conventional seven-stage PN code generation circuit.

FIG. 15 is a configuration diagram of a main part of a conventional PN code generation circuit having a seven-stage configuration.

FIG. 16 is a main part configuration diagram of a conventional seven-stage PN code generation circuit.

FIG. 17 is an actual measurement diagram of a code array by the PN code generation circuit shown in FIG. 2;

18 is an actual measurement diagram of a code array by the conventional PN code generation circuit shown in FIG.

[Explanation of symbols]

 1, 2, PN code generator 11 to 14, 21 to 24 PN code generator CC clock control circuit DS data selector SW, SW1 to SW4 switching circuit CLK clock signal G1, G11 EXOR gate G2, G21 stage number switching gate CT switching control Signal RS Reset signal NT1 Sign switching signal NT2 Stage number switching signal

Claims (8)

[Claims] 1. A feedback loop is formed by directly feeding back some output signals of a plurality of cascade-connected registers to an input section of a first-stage register, and an output of a preceding-stage register is provided between predetermined-stage registers. A logic circuit for judging a logical condition between the signal and the branch signal of the feedback loop and inputting the judgment result to a register at a subsequent stage is inserted and connected. An output signal of a required register determined by the judgment result of the logic circuit is PN. A PN code generation circuit configured to be extracted as a code. 2. An output signal of a last stage register among a plurality of stages of cascade-connected registers is directly fed back to an input portion of a first stage register to form a feedback loop. A logic circuit for judging the logical condition between the output signal of the register and the branch signal of the feedback loop and inputting the judgment result to the register at the subsequent stage is inserted and connected, and furthermore, the conduction of the branch signal to each logic circuit is determined. PN code, comprising a switch means for controlling, wherein an output signal of a required register determined by a control result by the switch means and a judgment result of a logic circuit associated therewith is extracted as a PN code. Generator circuit. 3. The method according to claim 1, wherein the logic circuit is inserted and connected between all registers except the first stage and the last stage, so that the number of register stages can be arbitrarily changed according to a control result of the switch means. The PN code generation circuit according to claim 2, characterized in that: 4. The switch means forms a logic signal of a required level by a combination of a plurality of bit arrays,
4. The PN code generation circuit according to claim 2, wherein the formed logic signal is input to each logic circuit. 5. Connected in parallel to a common signal source,
A plurality of Ps each generating a PN code having a different array structure
A PN code generation device comprising: an N code generation circuit; and code switching means for selectively outputting a PN code from the PN code generation circuit. 6. The PN code generator according to claim 5, wherein each of the plurality of PN code generators is the PN code generator according to any one of claims 1 to 4. 7. The PN code generation device according to claim 5, wherein the plurality of PN code generation circuits are configured to include register rows of different numbers of stages. 8. A PN code generation circuit according to claim 1 or a PN code generation device according to claim 5, 6 or 7, wherein a carrier wave is generated using the generated PN code. A communication apparatus characterized by being configured to transmit a modulated wave of a frequency spread spectrum.