JP2000242610A - Method for data transmitting of dual-port ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a transmitting processing for data efficient by arranging the dual-port RAM between two CPUs and sectioning the RAM into synchronous access areas and asynchronous access areas. SOLUTION: The dual-port RAM 1 is arranged between the two CPUs 2 and 3 and provided with a synchronous access area A1 which is accessed in synchronism with an interruption signal 4 from a master-side CPU 2 to a slave- side CPU 3 and a synchronous access area A2 for access from the slave-side CPU 3 to the master-side CPU. Further, the RAM is provided with an asynchronous access area B1 which is accessed without synchronizing with the interruption signal 4 from the master CPU 2 to the slave CPU and an asynchronous access area B2 which is accessed without synchronizing with the interruption signal 4 from the slave CPU 3 to the master CPU 2. Thus, the area is divided to efficiently transmit data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dual port RA.
More specifically, the present invention relates to a data transfer method for a dual-port RAM that performs data transfer that needs to be synchronized with a certain period and data transfer that does not need to be synchronized with the certain period in parallel.

[0002]

2. Description of the Related Art Recently, all digital servo amplifiers utilizing high-speed serial communication have been increasing. Among them, there is a servo amplifier which operates in synchronization with a synchronization signal by communication with a host controller, and the servo amplifier is required to have higher functions and performance. A large amount of data can be handled by high-speed serial communication, and a multi-CPU is required even inside the servo amplifier. Therefore, a dual-port RAM is employed so that data can be transferred between CPUs at high speed. Conventionally, the amount of data to be handled is small by limiting functions and performance according to the CPU processing speed used, and the data is used only in the synchronous access area.

[0003]

However, in order to improve the function and performance and to transfer a large amount of data at a high speed, time is consumed only in the data transfer processing of the dual port RAM, and processing relating to the main functions and performance is performed. There was a problem that time was running out. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for efficiently performing data transfer processing by a dual port RAM.

[0004]

In order to solve the above problem, the present invention relates to a method for transferring data of a dual port RAM arranged between two CPUs. C
A synchronous access area which is accessed in synchronization with an interrupt signal to the PU; and an asynchronous access area which is accessed without using the interrupt signal.
M is divided by time, and an access right flag indicating access to the asynchronous access area is set, so that access is performed in parallel with each other.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating the principle of the present invention. 1 is a dual port RAM, 2 is a master CPU, 3 is a slave CP
U, 4 are synchronous interrupt signals from the master CPU to the slave CPU, A1 is a synchronous access area for data transfer from the master CPU to the slave CPU, A2 is a synchronous access area for data transfer from the slave CPU to the master CPU, B1 Is an asynchronous access area for data transfer from the master CPU to the slave CPU, and B2 is an asynchronous access area for data transfer from the slave CPU to the master CPU. Synchronous access area A1, A2
Performs data transfer in synchronization with an interrupt signal by time. This is called synchronous access. The asynchronous access areas B1 and B2 exchange data regardless of the interrupt signal. This is called asynchronous access. FIG.
FIG. 3 is a diagram showing data transfer timing by synchronous access. In the synchronous access, as shown in FIG.
This is done by being output to In FIG. 2, T
c is the interrupt signal period, T0 is the maximum specified time for the slave CPU to access the synchronous access area A1, T1 is the maximum specified time for the slave CPU to access A2, M0
Is a time zone in which the master CPU can access the synchronous access area A2, and M1 is a time zone in which the master CPU can access the synchronous access area A1.
, S0 is a time zone in which the slave CPU can access the synchronous access area A1, and S1 is a time zone in which the slave CPU can access the synchronous access area A2. The processing of synchronous access by the master CPU 2 and the slave CPU 3 will be described below. After outputting the interrupt signal 4, the master CPU 2 completes reading the data in the synchronous access area A2 before the time T0 when the next interrupt signal 4 is output. Thereafter, the slave CPU 3 writes data in the synchronous access area A2 during the time T0. After receiving the interrupt signal 4, the slave CPU 3 completes reading the synchronous access area A1 during the time T1. Thereafter, the master CPU 2 completes writing to the synchronous access area A1 until the next interrupt signal 4 is output. FIG. 3 is a view for explaining a data transfer procedure by asynchronous access. Steps W11 to W14 are processes of the master CPU 2, and steps W21 to W24 are processes of the slave CPU 3. Asynchronous access is the master CPU as shown in FIG.
2. The slave CPU 3 is in the asynchronous access area B1, B2
As an access right flag for notifying the other party that the user is accessing the
2, FLAG1 and FLAG2 are allocated. The master CPU 2 reads the asynchronous access area B2,
Alternatively, processing for writing to the asynchronous access area B1 will be described below. The master CPU 2 turns on the FLAG 1 of the asynchronous access area B1 (step W11), reads the FLAG 2 of the asynchronous access area B2 (step W12), and if it is on, the asynchronous access areas B1, B
FLAG1 is turned off without reading / writing (Step W14). If the FLAG2 has been turned off, the asynchronous access area B2 is read or the asynchronous access area B1 is written (step W13). When the processing is completed, FLAG1 is turned off (step W14). The process for the slave CPU 3 to read the asynchronous access area B1 or write to the asynchronous access area B2 is described below. The slave CPU 3 turns on the FLAG 2 of the asynchronous access area B2 (step W2).
1), FLAG1 of asynchronous access area B1 is read (step W22), and if ON, FLAG2 is turned OFF without reading / writing of asynchronous access areas B1 and B2.
(Step W24). If the FLAG 1 is OFF, the reading of the asynchronous access area B1 or the writing to the asynchronous access area B2 is performed (step W2).
3). When the processing is completed, FLAG2 is turned off (step W24). Asynchronous access is performed using the vacant time of synchronous access. Therefore, synchronous access and asynchronous access can be performed in parallel.

[0006]

As described above, according to the present invention, the CPU
The dual-port RAM, which is the medium for transferring data between the two, is configured to be used separately in a synchronous access area synchronized with the interrupt signal and an asynchronous access area not depending on the interrupt signal. Data that needs to be processed by synchronous access, and data that can be processed at a low speed in an arbitrary cycle can be separated by performing asynchronous access, so that a large amount of data can be handled efficiently according to the processing speed of the CPU. Become like

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a dual port RAM data transfer method according to the present invention.

FIG. 2 is a diagram showing data transfer timing by synchronous access.

FIG. 3 is a diagram illustrating a data transfer procedure by asynchronous access.

[Explanation of symbols]

Reference Signs List 1 dual port RAM 2 master CPU 3 slave CPU 4 synchronous interrupt signal from master CPU to CPU slave A1 synchronous access area (data area from master to slave) A2 synchronous access area (data area from slave to master) B1 asynchronous access Area (data area from master to slave) B2 Asynchronous access area (data area from slave to master) Tc Interrupt signal period T0 Maximum specified time for slave CPU to access A1 T1 Maximum specified time for slave CPU to access A2 M0 Time zone during which the master CPU can access A2 M1 Time zone during which the master CPU can access A1 S0 Time zone during which the slave CPU can access A1 S1 Time zone during which the slave CPU can access A2 W11-14 Processing steps of master CPU W21-24 Processing steps of slave CPU

Claims (2)

[Claims] 1. A data transfer method for a dual port RAM disposed between two CPUs, wherein the dual port RAM is transferred from a master CPU to a slave C
A data transfer method for a dual-port RAM, wherein the data is divided into a synchronous access area accessed in synchronization with an interrupt signal to a PU and an asynchronous access area accessed without using the interrupt signal. 2. Accessing the synchronous access area in parallel by dividing the dual port RAM by time, and setting an access right flag indicating access to the asynchronous access area. The dual port R according to claim 1, wherein
AM data transfer method.