JP2000242236A - Shift register and liquid crystal display device using the register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a shift register, which is capable of surely conducting a data transfer even though an operating frequency is increased and a circuit element having a poor characteristics is used, and a liquid crystal display device using the register. SOLUTION: In an (n+1)th transfer stage, a Q output (c) of an (n-1)th D-FF D-FF11, a Q output (d) of an nth D-FF12 and a Q output (e) of a self D-FF13 are inputted to an OR gate 21, for example, and an ORing is taken for the three inputs to generate a selection clock control pulse (f) which switches switches 17a and 17b. Through the switching control of the switches 17a and 17b by the pulse (f), clocks CK1 and CK2 are taken in to the stage D-FF13 as internal clocks CK and CKX.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register and a liquid crystal display device using the same, and more particularly to a so-called selected clock type shift register for selectively taking in a clock signal for each transfer stage, and this selected clock type shift register. The present invention relates to an active matrix type liquid crystal display device using as a sampling generation circuit.

[0002]

2. Description of the Related Art In a driving system for inputting an analog video signal to each pixel by point-sequential scanning in an active matrix type liquid crystal display device, a sampling pulse generating circuit for generating a sampling pulse for sampling the analog video signal is used. , A shift register is generally used.

As described above, in a shift register used as a sampling pulse generation circuit of a liquid crystal display device,
Only the transfer stage to which data is transferred needs to be active. Therefore, the clock signal is not always supplied to all the transfer stages, but the clock signal is selectively supplied only to the active transfer stages. It has been proposed by the applicant (see JP-A-3-147598).

FIG. 9 shows a conventional example of this select clock type shift register. In the figure, among the multiple transfer stages (unit registers), the (n−1) th stage, the nth stage, and the (n + 1) th stage in the middle are shown.
Only each transfer stage and its peripheral circuits are shown.
These transfer stages are D-flip-flops (hereinafter DF)
F) 101, 102 and 103.

The D-FF 101 has switches 104a,
The clocks CK1 and CK2 having phases opposite to each other via 104b
Is given selectively. Similarly, D-FF102
To the D-FF1 via the switches 105a and 105b.
03 are selectively supplied with clocks CK1 and CK2 via switches 106a and 106b, respectively. The switches 104a and 104b are controlled by the output of the OR gate 107, and the switches 105a and 105b are controlled by the output of the OR gate 108.
Are controlled by the output of the OR gate 109.

[0006] The OR gate 107 is connected to the D-FF 101
(Data) input and Q output are two inputs. Similarly, the OR gate 108 has D input and Q output of the D-FF 102, and the OR gate 109 has two D input and Q output of the D-FF 103. That is, the OR gates 107, 108, and 109 respectively provide the D input and Q of the D-FFs 101, 102, and 103 of the own stage.
The output has two inputs, and the switching of the corresponding switch is controlled by the selected clock control pulse which is the OR output of these outputs.

[0007]

However, in the above-described conventional shift register, the D-FF 10 of each transfer stage is used.
The clocks CK1 and CK2 are supplied to the D-FF of the own stage using the inputs and outputs (ie, D input and Q output) of 1, 102 and 103.
Is performed, the following problem occurs when the operating frequency is increased or a circuit element having poor characteristics is used.

That is, for example, in the n-th transfer stage, the logical sum of the D input and the Q output of the D-FF 102 is
Considering the case where the switches 105a and 105b are switched by the selected clock control pulse which is the logical sum output of the R gate 108, when the delay amount in the control path is large, the switches 105a and 105b are switched. Is generated later than the transition timing of the clocks CK1 and CK2, the switches 105a and 105b
As a result, the leading edge of the active clock to be captured is cut off.

In this case, the D-FFs 101, 102, 10
3 becomes active sequentially, the leading part of the transfer data in each transfer stage is sequentially cut off. As is clear from the timing chart of FIG. , The width of the data gradually narrows (τ1>τ2>τ3>τ4> τ5), and the data to be transferred is eventually lost.

In the timing chart of FIG.
(A) and (b) show the clocks CK1 and CK2, and (c),
(D) shows the clocks CK1 and CK2 after passing through the switches 104a and 104b of the (n-1) th stage (that is, the D-FF 101).
(E) shows the internal clocks CK and CKX), (e) shows the Q output of the D-FF 101 in the (n-1) th stage, and (f) shows the OR gate 10
8, the selected clock control pulse is output from (g),
(H) shows the clocks CK1 and CK2 after passing through the switches 105a and 105b of the n-th stage (that is, the internal clocks CK and CKX of the D-FF 102), and (i) shows the DF of the n-th stage.
(J) is the D-FF1 of the (n + 1) th stage.
03, and (k) and (l) represent the respective Q outputs of the (n + 2) -th and (n + 3) -th D-FFs, not shown.

The reason why the head of the transfer data is sequentially cut off is that, for example, the Q output (e) of the D-FF 101 starts from the edges of the clocks CK1 (c) and CK2 (d) after passing through the switches 104a and 104b. ) Transitions (ie, the delay time in the D-FF) is T1, and the time from the transition of the Q output (e) to the transition of the selected clock control pulse (f) (ie, the OR gate). Delay time)
2. The time from the application of the selected clock control pulse (f) to the passage of the clocks CK1 and CK2 through the switches 105a and 105b (that is, the delay time in the switches) is T3, and the clocks CK1 (a) and CK2 (b 1) of the period
If / 2 is T0, it occurs when T1 + T2 + T3> T0.

As described above, the switches 104a, 104
When the clocks CK1 and CK2 are taken in by b, 105a, 105b, 106a, and 106b, the leading edge of these clocks is cut off, which causes the power supply voltage to be lowered when the circuit is operated with a high-speed clock. This is a problem when the circuit is formed by a circuit element having low characteristics, for example, a polysilicon TFT (thin film transistor).

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the object of the present invention even when the operating frequency is increased or a circuit element having poor characteristics is used.
An object of the present invention is to provide a shift register capable of reliably performing data transfer and a liquid crystal display device using the same.

[0014]

SUMMARY OF THE INVENTION A shift register according to the present invention is a shift register having clock control means for selectively taking in first and second clocks having mutually opposite phases for each transfer stage. The control means is configured to control the capture of the first and second clocks into the own transfer stage based on the output of the own transfer stage and the output of the transfer stage at least two stages before. .

In the selected clock type shift register having the above-described configuration, the means for selectively controlling the transfer of the first and second clocks to each transfer stage includes, in addition to the output of its own transfer stage, the output of the previous transfer stage. Of the transfer stages, and the control of taking in the first and second clocks into the own transfer stage is performed based on these inputs. The selection clock type shift register includes, in a driving system for inputting a video signal to each pixel by point-sequential scanning, a sampling pulse generation circuit for generating a sampling pulse for sampling the video signal. Is used as the sampling pulse generating circuit.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a select clock type shift register according to the first embodiment of the present invention. Here, among the multiple transfer stages (unit registers), the (n−1) th stage, the nth stage, the n + 1st stage, and the n + th stage
Only the second transfer stage and its peripheral circuits are shown. These transfer stages are constituted by D-FFs 11 to 14, respectively.

The D-FF 11 has switches 15a, 15
The clocks CK1 and CK2 having phases opposite to each other are selectively supplied via b. Similarly, the clocks CK1 and CK2 are selected for the D-FF 12 via the switches 16a and 16b, for the D-FF 13 via the switches 17a and 17b, and for the D-FF 14 via the switches 18a and 18b. Is given.

The switches 15a and 15b output the OR gate 19, and the switches 16a and 16b
The switches 17a, 17b
Are output from the OR gate 21 and the switches 18a, 1
8b is controlled by the output of the OR gate 22, respectively. That is, each output of the OR gates 19 to 22 becomes a selected clock control pulse for switching the switches 15a, 15b to 18a, 18b.

The OR gate 19 has three inputs: the Q output of the D-FF 11 in its own stage, its D input, and the Q output of the D-FF two stages before. Similarly, OR gate 20 has a D
-Q output of FF12, its D input, and D of the (n-2) th stage
The OR gate 21 outputs the Q output of the D-FF 13
The output, its D input and the Q output of the D-FF 11 are ORed
The gate 22 has three inputs each of the Q output of the D-FF 14, its D input and the Q output of the D-FF 12.

That is, each of the OR gates 19 to 22 has a Q output of its own stage D-FF, its D input, and a Q output of the D-FF two stages before (ie, the D input of the previous stage D-FF). Are input, and the corresponding switches are switching-controlled by a selected clock control pulse, which is the logical sum output, to take in the clocks CK1 and CK2 as the internal clocks CK and CKX of the D-FF of the own stage.

Next, the circuit operation of the selected clock type shift register according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG.

In the timing chart of FIG.
(A) and (b) show the clocks CK1 and CK2, (c) shows the Q output of the n-th stage D-FF 11, (d) shows the Q output of the n-th stage D-FF 12, and (e). ) Is the (n + 1) -th stage D-
(F) is the selected clock control pulse of the (n + 1) th stage (that is, the output pulse of the OR gate 21).
(G) and (h) are the switches 17a, 1 of the (n + 1) th stage.
7b after passing through clocks CK1 and CK2 (that is, DF
F13 (internal clocks CK and CKX).

Here, as an example, the operation of the (n + 1) th transfer stage will be described.
-Q output (c) of FF11, Q of n-th stage D-FF12
The output (d) and the Q output of the D-FF 13 of the own stage (e)
Is input to the (n + 1) th stage OR gate 21. The OR gate 21 calculates the logical sum of these three inputs,
A selection clock control pulse (f) for switching the switches 17a and 17b is output as the logical sum output.

Then, the switches 17a and 17b are turned on (closed) in response to the selected clock control pulse (f).
State, and the clocks CK1 and CK2 are
Thirteen internal clocks CK and CKX. As a result, the D-FF 13 becomes active, and the D-FF 13 in the preceding stage becomes active.
The transfer data received from the FF 12 is shifted to the next stage D-
Transfer to FF14.

As described above, not only the D input and the Q output of the D-FF of the own stage but also the Q output of the D-FF of the previous stage are added to obtain a logical sum of these, and the logical sum output is obtained. By performing switching control for taking in the clocks CK1 and CK2 as internal clocks by the selected clock control pulse, even if the amount of delay in the control path of the transfer stage is large, it is clear from the timing chart of FIG. The generation timing of the selected clock control pulse (f) is transmitted to the D-FF 13 of the own stage by the clock CK1.
Since clocks (a) and CK2 (b) need to be taken earlier, the clocks CK1 and CK2 can be taken as they are.

That is, even if the delay amount in the control path in the (n + 1) th transfer stage is large, the clock CK
1, CK2 is not cut off the edge of its head,
While maintaining the original pulse width, it is taken in as internal clocks CK and CKX of the D-FF 13 through the switches 17a and 17b. Therefore, the D-FF 13 is
The transfer data received from the preceding stage D-FF 12 can be directly transferred to the next stage D-FF 14 without shifting the data and cutting off the head of the data.

Here, in the control path of the (n + 1) th transfer stage, the Q output (c) of the D-FF 11 transitions from the edges of the clocks CK1 and CK2 after passing through the (n-1) th stage switches 15a and 15b. The time from the transition of the Q output (c) to the transition of the selected clock control pulse (f) (ie, the delay time at the OR gate) is T1. T2, the clocks CK1 and CK after the selection clock control pulse (f) is given
2 is the time required to pass through the switches 17a and 17b (that is, the delay time in the switches) is T3, and the clock CK1 is
Assuming that the half of the period of (a) and CK2 (b) is T0, the above holds under the condition of T1 + T2 + T3 ≦ 2T0.

FIG. 3 is a block diagram showing a configuration example of a select clock type shift register according to a second embodiment of the present invention. Here, among the multiple transfer stages (unit registers), the (n−1) th stage, the nth stage, the n + 1st stage, and the n + th stage
Only the second transfer stage and its peripheral circuits are shown. These transfer stages are constituted by D-FFs 31 to 34, respectively.

The D-FF 31 has switches 35a, 35
The clocks CK1 and CK2 having phases opposite to each other are selectively supplied via b. Similarly, the clocks CK1 and CK2 are selected for the D-FF 32 via the switches 36a and 36b, for the D-FF 33 via the switches 37a and 37b, and for the D-FF 34 via the switches 38a and 38b. Is given.

The switches 35a and 35b output from the OR gate 39, and the switches 36a and 36b
The switches 37a and 37b are output by the output of the R gate 40.
Are output from the OR gate 41, and the switches 38a, 3
8b is switching-controlled by the output of the OR gate 42, respectively. That is, each output of the OR gates 39 to 42 becomes a selection clock control pulse for switching the switches 35a, 35b to 38a, 38b.

The OR gate 39 has two inputs of the Q output of the D-FF 11 in the own stage and the Q output of the D-FF two stages before. Similarly, the OR gate 40 ORs the Q output of the D-FF 32 and the Q output of the n-th stage D-FF, and the OR gate 41 ORs the Q output of the D-FF 33 and the Q output of the D-FF 31. The gate 42 has two inputs each for the Q output of the D-FF 34 and the Q output of the D-FF 32.

That is, each of the OR gates 39 to 42 is connected to the Q output of the D-FF of its own stage and the D-FF of the previous stage.
(Ie, the D input of the preceding stage D-FF) has two inputs, and the corresponding switches are switching-controlled by the selected clock control pulse which is the logical sum output thereof, and the clocks CK1 and CK2 are supplied to the own stage D-FF. Internal clock C of FF
Control for taking in as K and CKX is performed.

Next, a circuit operation of the selected clock type shift register according to the second embodiment having the above configuration will be described.

Here, as an example, the operation of the (n + 1) th transfer stage will be described.
The Q output (c) of the -FF 11 and the Q output (e) of the D-FF 13 of the own stage are input to the (n + 1) th stage OR gate 41. The OR gate 41 outputs a selected clock control pulse (f) for switching the switches 37a and 37b by taking the logical sum of these two inputs.

Then, the switches 37a and 37b are turned on (closed) in response to the selected clock control pulse (f).
State, and the clocks CK1 and CK2 are
33 as internal clocks CK and CKX. As a result, the D-FF 33 becomes active, and the D-FF of the preceding stage is activated.
The transfer data received from the FF32 is shifted to the next stage D-
Transfer to FF34.

As described above, the Q output of the D-FF of the own stage and 2
The logical sum of the Q output of the preceding D-FF is taken and the clock CK is generated by the selected clock control pulse which is the logical sum output.
1 and CK2 as an internal clock, the switching control is performed in the same manner as in the first embodiment, even if the amount of delay in the control path of the transfer stage is large. The generation timing of f) is transmitted to the D-FF 33 of the own stage by the clocks CK1 (a),
Since it is earlier than the timing at which CK (2) needs to be taken, the clocks CK1 and CK2 can be taken as they are.

That is, even if the delay amount in the control path in the (n + 1) th transfer stage is large, the clock CK
1, CK2 is not cut off the edge of its head,
The signals are taken in as internal clocks CK and CKX of the D-FF 33 through the switches 37a and 37b while maintaining the original pulse width. Therefore, the D-FF 33 is
The transfer data received from the preceding stage D-FF 32 can be directly transferred to the next stage D-FF 34 without shifting the data and cutting off the head of the data.

Here, when the selected clock type shift register according to the second embodiment is compared with the selected clock type shift register according to the first embodiment, in the first embodiment, the OR gates 19 to 22 of each transfer stage are used in the first embodiment. While the logical sum of the Q output of the D-FF of its own stage, its D input and the Q input of the D-FF two stages before is ORed, in the second embodiment, the OR of each transfer stage is obtained. Gate D-FF at gate 39-42
And a logical sum of two inputs of the Q output of the D-FF two stages before.

This structural difference, that is, the OR gates 39-
When these OR gates 39 to 42 are formed by, for example, MOS transistors, the number of MOS transistors can be reduced by one for each transfer stage as compared with a three-input one when the number of inputs of the 42 is reduced by one. There is an advantage that the circuit configuration can be simplified and the delay time in the OR gates 39 to 42 can be shortened accordingly.

However, in the case of the second embodiment, in the timing chart of FIG. 2, the D input of the D-FF of the own stage, that is, the Q output (d) of the D-FF of the preceding stage is not input to the OR gate. , The falling timing of the Q output (c) of the D-FF two stages before and the DF of the own stage
If the rising timing of the Q output (e) of F does not completely match, there is a concern that whisker-like noise may occur in the selected clock control pulse (f).

To solve this, the OR gate 39
It is necessary to optimally set the constants of the circuit elements that constitute -42. Specifically, in FIG. 4 showing an example of a circuit configuration when the OR gate is formed by MOS transistors,
By setting the size of the N-channel MOS transistors Qn11 and Qn12 to be larger than that of the P-channel MOS transistors Qp11 and Qp12, it is possible to delay the response to the rise of the Q output (e) of the D-FF of the self-stage. Even if the falling timing of the Q output (c) of the preceding D-FF does not completely coincide with the rising timing of the Q output (e) of the D-FF of the own stage, the selected clock control pulse (f) That is, it is possible to avoid generation of beard-like noise.

Considering only the whisker-like noise, the first embodiment in which the OR gate has three inputs is more effective than the second embodiment in which the delay time in the OR gate is increased by one as the number of gate inputs increases by one. Although it is slightly longer than the case of
Even if the falling timing of the Q output (c) of the preceding D-FF and the rising timing of the Q output (e) of the own D-FF slightly deviate, generation of whisker-like noise is more reliable. Can be suppressed.

In the shift register of the selected clock type according to the first and second embodiments described above, the Q of the D-FF of its own stage is
Output (or Q input and D input) and DF two steps before
The logical sum of the Q output of F is taken and the switching for taking in the clocks CK1 and CK2 is performed by the selected clock control pulse which is the logical sum output. However, the switching is limited to the Q output of the D-FF two stages before. Instead, it is also possible to use the Q output of the D-FF three stages before.

For example, when the Q output of the D-FF three stages before is used, as shown in FIG. 5, the Q output (a) of the D-FF three stages before is used in the OR gate of each transfer stage. Own stage D
-The Q output (d) of the D-FF two stages before or the Q output (c) of the D-FF one stage before (c) is added to the Q output (d) of the -FF.
Must be input. This is, as is clear from the timing chart of FIG. 6, between the falling timing of the Q output (a) of the D-FF three stages before and the rising timing of the Q output (d) of the D-FF of its own stage. Because there is a time interval in the data, this interval is to be filled.

As described above, in the case of the selected clock type shift register using the Q output of the D-FF three stages before, T1
Under the condition of + T2 + T3 ≦ 3T0, it is possible to prevent the head of transfer data from being cut off at each transfer stage. That is, the margin can be increased by T0 by half the period T0 of the clocks CK1 and CK2 as compared with the first and second embodiments using the Q output of the D-FF two stages before. Therefore, as the number of stages increases, the margin can be further increased.

It should be noted that, instead of the three inputs obtained by adding the Q output (b) of the D-FF two stages before or the Q output (c) of the D-FF one stage before, the generation of the whisker-like noise described above is suppressed. From the viewpoint of this, it is more advantageous to use four inputs in which both are added.

The above-described selective clock type shift register according to the present invention is, for example, a polysilicon TFT as a switching element of each pixel arranged in a two-dimensional matrix.
It is used as a shift register of a horizontal driver in a so-called drive circuit integrated type liquid crystal display device in which an analog interface drive circuit is formed integrally with a pixel portion by a polysilicon TFT on a glass substrate on which an FT is formed. FIG. 7 illustrates an example of a configuration of a liquid crystal display device with an integrated drive circuit.

In FIG. 7, pixels 51 are arranged in a two-dimensional matrix to form an effective pixel area (pixel section) 52. In the effective pixel area 52, the pixel 51
TFT (thin film transistor) 5 which is a pixel transistor
3, a liquid crystal cell 54 having a pixel electrode connected to the drain electrode of the TFT 53, and an auxiliary capacitor 55 having one electrode connected to the drain electrode of the TFT 53.

In this pixel structure, the TF of each pixel 51
T53 has its gate electrode connected to a gate line (scan line) 56 and its source electrode connected to a source line (signal line) 57. Further, a common electrode 58 to which a common voltage VCOM is applied is connected to the opposite electrode of the liquid crystal cell 54 and the other electrode of the storage capacitor 55.
It is connected to the.

For example, a horizontal driver 59 is disposed on the upper side of the effective pixel area 52, and a vertical driver (scan driver) 60 is disposed on the left side, for example. The horizontal driver 59 and the vertical driver 60 are integrally formed on a glass substrate (panel) 61 together with the effective pixel area 52. The horizontal driver 59 selects and drives each of the pixels 51 in column units, and the vertical driver 60 selects and drives each of the pixels 51 in row units. The horizontal driver 59 and the vertical driver 60 include a scanning circuit for sequentially scanning in the horizontal direction (column direction) and the vertical direction (row direction), and a shift register is used as the scanning circuit.

FIG. 8 is a block diagram showing an example of an analog interface type horizontal driver. The analog interface type horizontal driver samples a horizontal shift register 61 that sequentially generates a sampling pulse as an address pulse and an input analog video signal in synchronization with a sampling pulse sequentially output from the horizontal shift register 61, And an analog switch group 62 for outputting to the source line 17 in FIG.

In this analog interface type horizontal driver, the selected clock type shift register according to each embodiment of the present invention described above is used as the horizontal shift register 61. Then, in the selected clock type shift register according to the first embodiment (see FIG. 1) or the second embodiment (see FIG. 3), the transfer data as the Q output of each transfer stage samples an analog video signal. Is supplied to the analog switch group 62 as a sampling pulse.

Since the selected clock type shift register has a configuration in which a clock signal is selectively applied only to an active transfer stage, power consumption can be reduced.
In addition, in the case where the operating frequency is high or a circuit element having poor characteristics such as a TFT is used and data transfer can be reliably performed, this selected clock type shift register is used as the horizontal shift register 61. In the conventional liquid crystal display device integrated with a driving circuit, lower voltage and lower power consumption can be realized, and the operating frequency can be improved.

In this application example, the case where the present invention is applied to a liquid crystal display device equipped with an analog interface drive circuit has been described. However, in a liquid crystal display device equipped with a digital interface drive circuit, the sampling pulse generation circuit of the horizontal driver is also used. (Horizontal shift register).

Further, the shift register according to the present invention is
The case where the shift register is used as a select clock type shift register that generates a sampling pulse in a drive circuit integrated type liquid crystal display device has been described as an example. However, the present invention is not limited to this, and a select clock using a TFT formed on a serial substrate is used. The present invention can be applied not only to the type shift register, but also to the general selection clock type shift register using not only the TFT but also a circuit element having poor characteristics.

[0057]

As described above, according to the present invention,
In a shift register configured to selectively take in the first and second clocks having phases opposite to each other for each transfer stage, a shift register based on the output of its own transfer stage and the output of the transfer stage at least two stages before. By controlling the capture of the first and second clocks into the transfer stages, the data transfer can be reliably performed even when the operating frequency is increased or a circuit element having poor characteristics is used. The operation frequency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a select clock type shift register according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms of respective units according to the first embodiment.

FIG. 3 is a block diagram showing a configuration example of a select clock type shift register according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an example of a circuit configuration of an OR gate.

FIG. 5 is a block diagram showing a modification of the present invention.

FIG. 6 is a timing chart showing waveforms at various portions in a modified example.

FIG. 7 is a block diagram illustrating an example of a configuration of a drive circuit integrated liquid crystal display device to which the present invention is applied.

FIG. 8 is a block diagram showing an example of the configuration of an analog interface type horizontal driver.

FIG. 9 is a block diagram showing a conventional example of a select clock type shift register.

FIG. 10 is a timing chart showing waveforms at various portions in a conventional example.

[Explanation of symbols]

11 to 14, 31 to 34 ... D-FF (flip-flop), 15a, 15b to 18a, 18b, 35a, 35
b to 38a, 38b ... switches, 19 to 22, 39 to 4
2… OR gate

Continued on the front page F-term (reference) 2H093 NA16 NC21 NC22 NC23 NC34 ND37 5C006 AF51 AF72 BB16 BC20 BF03 BF06 BF24 BF26 BF31 BF34 FA15 FA31 FA46 FA47 5C080 AA10 BB05 DD09 DD12 DD24 DD26 FF11 JJ02 JJ03 JJ04

Claims (8)

[Claims] 1. A shift register having clock control means for selectively taking in first and second clocks having phases opposite to each other for each transfer stage, wherein said clock control means includes an output of a transfer stage of its own stage. A shift register for controlling the capture of the first and second clocks to its own transfer stage based on the output of the transfer stage at least two stages before. 2. The clock control means according to claim 1, wherein said clock control means has an OR gate for performing an OR operation on an output of a transfer stage of its own stage and an output of a transfer stage at least two stages before.
The shift register as described. 3. The clock control means controls the capture of the first and second clocks by using also the output of a transfer stage located between the transfer stage of the own stage and the transfer stage two stages before. The shift register according to claim 1, wherein the shift is performed. 4. The clock control means includes: an output of a transfer stage of the own stage; an output of a transfer stage two stages before or before;
4. The shift register according to claim 3, further comprising an OR gate for performing an OR operation with an output of a transfer stage located between the transfer stage and the previous transfer stage. 5. A liquid crystal display device comprising: a driving system for inputting a video signal to each pixel by point-sequential scanning; and a sampling pulse generation circuit for generating a sampling pulse for sampling the video signal, As a sampling pulse generating circuit, there is provided clock control means for selectively taking in the first and second clocks having phases opposite to each other for each transfer stage, and this clock control means is connected to the output of its own transfer stage and at least two stages. A liquid crystal display device using a shift register that controls the capture of the first and second clocks into its own transfer stage based on the output of the previous and previous transfer stages. 6. The clock control means according to claim 5, wherein said clock control means has an OR gate for performing an OR operation on an output of a transfer stage of its own stage and an output of a transfer stage at least two stages before.
The liquid crystal display device according to the above. 7. The clock control means controls the capture of the first and second clocks by using also the output of a transfer stage located between the transfer stage of the own stage and the transfer stage two stages before. 6. The liquid crystal display device according to claim 5, wherein the operation is performed. 8. The clock control means outputs the output of the transfer stage of the own stage, the output of the transfer stage two stages before or before, and the transfer stage of the own stage.
8. The liquid crystal display device according to claim 7, further comprising an OR gate for performing an OR operation with an output of a transfer stage located between the transfer stage and the previous transfer stage.