JP2000241389A - Control interface making use of bidirectional memory of analyzer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a control interface which can be returned in a short period even when setting data is broken down by a device generating a high-voltage discharge noise, which reduces a communication load due to a program and whose reliability is enhanced. SOLUTION: In this control interface for an analyzer, control data and setting data are transmitted to the analyzer from a monitoring control device 1, and monitoring data is received. A bidirectional memory 2 which can be accessed is provided between the monitoring control device 1 and an external control circuit without competing from both. The control data and the setting data which are written in the bidirectional memory 2 are read out periodically from the monitoring control device 1 so as to be transmitted to external control circuits 11 to 18. After their transmission monitoring data are received from the external control circuits 11 to 18 so as to be written in the bidirectional memory 2. In addition, a means 4 by which parallel data is converted into serial data so as to be transmitted is provided. In addition, a means 9 by which serial data is received so as to be converted into parallel data is provided. An address is connected to the data so as to be transmitted and received by a serial transmitting-receiving line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control interface using a bidirectional memory of an analyzer for transmitting control and setting data and receiving monitoring data from a monitor and control device to the analyzer.

[0002]

2. Description of the Related Art In an analyzer system such as a mass spectrometer, the present invention relates to a method of setting a reference voltage to a power supply inside the device, a method of setting a mode, and a hardware technology for reading a state (power output, mode status) inside the device. Conventionally, when data is set in an external control circuit of an analyzer from a CPU that monitors and controls the analyzer, the CPU executes an instruction and sets data in a register or a DA converter of the external control circuit each time.

Further, when a plurality of monitor signals are obtained from an analyzer, conventionally, the CPU outputs a switching signal to a multiplexer and then reads the selected signal with an AD converter.

[0004]

However, in the conventional method as described above, when data set from the CPU to the external control circuit of the analyzer is reset (destroyed) by external noise such as high-voltage noise, it is re-established. , Had to be reset by the CPU. Further, after setting data, it is difficult to determine whether the data has been destroyed, and it has not been possible to execute appropriate resetting.

When data is set from the CPU to an external control circuit of the analyzer and a monitor signal is obtained, procedures specific to the apparatus such as control of a multiplexer for switching input signals and data acquisition from an AD converter include: The communication load by the program was heavy because it was created by the program.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and can recover the setting data in a short time even if the setting data is broken in a device in which high-voltage discharge noise is generated. It is intended to reduce and improve reliability.

For this purpose, the present invention relates to a control interface of an analyzer for transmitting control and setting data and receiving monitoring data from the monitoring controller to the analyzer, wherein the control interface is provided between the monitoring controller and an external control circuit. Equipped with a bi-directional memory that allows access from both sides without conflict, while periodically reading out control and setting data written to the bi-directional memory from the monitoring control device and transmitting the data to an external control circuit,
After the transmission, the monitoring data is received from the external control circuit and written into the bidirectional memory, and a means for converting the parallel data into serial data for transmission and receiving the serial data are provided. Means for converting the data into parallel data, connecting the monitoring control device and the external control circuit via a serial transmission / reception line, and connecting an address to data transmitted / received via the serial transmission / reception line. is there.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a control interface using a bidirectional memory of an analyzer according to the present invention, wherein (A) shows a CPU side, (B) shows an external control circuit side, and 1 shows a CPU; 2 is a bidirectional memory,
3, 18 are multiplexers, 4 and 16 are PS transmitters, 5 and 14 are oscillators, 6 and 15 are address counters, 7 is a clock generator, 8 is a buffer, and 9 and 11 are S
-P receiver, 12 is an address decoder, 13 is I / O
A register 17 indicates an AD converter.

The CPU side shown in FIG. 1A and the external control circuit side shown in FIG.
6 and SP receivers 9, 11 are coupled, for example, by optical signals. In FIG. 1A on the CPU side, the CPU 1 is a monitoring control device that reads and writes monitoring data from the analyzer and data to the external control circuit side of the analyzer with respect to the bidirectional memory 2. Memory 2 is
The access from the CPU 1 and the access from the external control circuit side can be made bidirectionally without conflict. The multiplexer 3 switches between a read address and a write address of the bidirectional memory 2. The PS transmitter 4 reads, for example, 16-bit parallel data from the bidirectional memory 2 through the buffer 8, converts the parallel data into serial data, connects the read address to the data, and transmits the read address to the external control circuit by an optical signal. The oscillator 5 generates the read timing signal, for example, the address counter 6 generates an 8-bit read address, and the clock generator generates a transmission clock for transmitting serial data to the external control circuit side. 7 The SP receiver 9 receives serial data from the external control circuit side, and
It converts the data into 6-bit parallel data, separates an 8-bit write address, and generates a read / write switching signal R / W. And a read / write switching signal R
/ W switches the multiplexer 3 from the read address to the write address, sets the bidirectional memory 2 to the write mode, and writes parallel data through the buffer 8.

In FIG. 1B on the external control circuit side, S
The −P receiver 11 receives serial data from the CPU side, converts the serial data into, for example, 16-bit parallel data, separates an 8-bit write address,
The write address is converted by the address decoder 12 and the data is held in the I / O register 13. The data held in the I / O register 13 is sent to a DA converter. The transmitter 14 and the address counter 15 sequentially generate read addresses of monitor signals when the SP receiver 11 has finished receiving signals from the CPU. The multiplexer 18 reads the monitor signal by sequentially switching according to the read address.
The D converter 17 converts this monitor signal into a digital signal. The PS transmitter 16 has an A
The parallel data of the digital signal converted by the D converter 17 is converted into serial data, the data is connected to the read address of the monitor signal, and transmitted to the CPU by an optical signal.

FIG. 2 is a timing chart of reading and writing on the external control circuit side of the bidirectional memory. Bidirectional memory 2
As shown in FIG. 2, the timing for accessing and reading / writing the data from the external control circuit side without competing with the access from the CPU 1 is as follows.
Is read out to the PS transmitter 4 from
The S transmitter 4 converts the parallel data into serial data and sends it out (SERIAL OUT). The access timing of the serial data of the monitor signal from the external control circuit is shifted by synchronizing the write timing in the bidirectional memory 2 with the read timing of the transmission data to the external control circuit in the bidirectional memory 2 so that they do not collide with each other. Set as follows. The serial data (SERIAL IN) received by the SP receiver 9 is converted into parallel data and written into the bidirectional memory 2 from the SP receiver 9 by DPM WRITE. At this time, the reading DPM READ of the bidirectional memory 2,
The write DPM WRITE is, for example, serial data (SERI) from the external control circuit side by the SP receiver 9.
The R / W generated based on the reception of the AL IN) may be used as it is.

As described above, the bidirectional memory 2
Is periodically read out, the memory address numbers are combined, converted into serial data, and then transferred to an external control circuit of the analyzer. For data transmission, an 8-bit address counter 6 is incremented, for example, every 16 μsec based on the clock of the transmitter 5, and 16-bit data is read from the bidirectional memory 2 for each address. As shown in FIG.
The bits are combined with a 4 MHz clock by the clock generator 7, biphase modulated, converted into a serial signal, and sent out. Therefore, since the first address is set in the address counter 6 when the final address is reached, data of 256 channels is continuously transmitted in order.
If data of one channel is transmitted every 16 μsec, it takes 16 μsec × 256 = 4096 μsec. The external control circuit generates a clock by performing serial / parallel conversion from the received data, and sets data selected by a necessary address in an output register, so that the data can be used for a DA converter or the like. In the external control circuit, the multiplexer is periodically switched, the monitor signal is converted by the A / D converter, the switching code of the multiplexer and the output data of the A / D converter are combined, converted into serial data, and sent out. On the side, after converting the received serial data into parallel data, the address and data are separated and written into the bidirectional memory, and this is read by the CPU 1 as necessary.

Note that the present invention is not limited to the above-described embodiment, and various modifications are possible. For example, in the above embodiment, the write timing on the external control circuit side of the bidirectional memory is generated by the SP receiver 9.
It may be generated based on the delay from the transmission timing to the external control circuit side. Further, it goes without saying that the present invention is not limited to a mass spectrometer but can be applied to other analyzers as well.

[0014]

As is apparent from the above description, according to the present invention, there is provided a bidirectional memory which can access between a CPU (monitoring control device) and an external control circuit without conflict from both sides. And periodically transmits device data (control and setting data) written to the bidirectional memory to the external control circuit, and after the transmission, receives monitoring data from the external control circuit and writes it to the bidirectional memory. With this configuration, the device data set in the bidirectional memory by the CPU can be periodically read and transferred independently of the CPU and set in the external control circuit, and the data is destroyed by the external control circuit on the device side. Data can be restored in the next transfer cycle. Therefore, since a high-voltage power supply is built in the device, high-voltage discharge noise causes
In an analyzer in which a trouble in which data set in a register is reset (destroyed) is likely to occur, data can be restored in a short time, and reliability can be improved.

The apparatus further comprises means for converting parallel data into serial data and transmitting the data, and means for receiving the serial data and converting the data into parallel data. By connecting and connecting the address to the data transmitted and received on the serial transmission / reception line, the number of connection signal lines is reduced,
It can easily cope with expansion of the number of bits of data. Further, since the CPU transfers data by hardware only by reading and writing to the bidirectional memory, the communication load by the program is eliminated, and the monitor data is also periodically written to the bidirectional memory. Data can be captured, and the program can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a control interface using a bidirectional memory of an analyzer according to the present invention.

FIG. 2 is a timing chart of reading and writing on the external control circuit side of the bidirectional memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... bidirectional memory, 3, 18 ... multiplexer, 4, 16 ... PS transmitter, 5, 14 ... transmitter, 6, 15 ... address counter, 7 ... clock generator, 8 ... buffer, 9 , 11 ... SP receiver, 12 ...
Address decoder, 13 ... I / O register, 17 ... AD
converter

Claims (3)

[Claims] 1. A control interface of an analyzer for transmitting control and setting data and receiving monitoring data from the monitoring controller to the analyzer, wherein the controller and the external control circuit compete with each other. A bidirectional memory that can be accessed without the need to periodically read out control and setting data written to the bidirectional memory from the monitoring and control device and transmit it to the external control circuit, and after transmitting the monitoring data from the external control circuit. A control interface using a bidirectional memory of the analyzer, wherein the control interface is configured to receive and write the received data into the bidirectional memory. And means for converting the parallel data into serial data and transmitting the data, and means for receiving the serial data and converting the data into parallel data. The control interface according to claim 1, wherein the control interface uses a bidirectional memory. 3. The control interface according to claim 1, wherein an address is linked to data transmitted / received through the serial transmission / reception line.