JP2000236064A - Junction capacitance for light receiving element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect each electrode of junction capacitance to a high impedance signal line without any malfunction with light beam by giving inverse bias as the function capacitance to the PN junction of the P-type base diffused layer and N-type emitter diffused layer formed within the N-type well. SOLUTION: The P-type base diffused layer 106A formed in the N-type well and the N-type emitter diffused layer 107 formed therein are comprised and an inverse bias is given to the PN junction thereof as the junction capacitance. This PN junction forms a function at the semiconductor layer near to the extremely shallower surface than the PN junction formed with the N-type epitaxial layers 105A, 105B, 105C and P-type semiconductor substrate 101A and is not influenced with the light beam. Therefore, a high impedance signal line can be connected to any terminal of the electrode wirings 113A, 114A at the electrode extracting port of the junction capacitance using the PN junction of the N-type emitter diffused layer 107A and P-type base diffused layer 106A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a junction capacitance used for an integrated circuit for a light receiving element.

[0002]

2. Description of the Related Art Conventionally, a capacitor using an insulating film such as a nitride film as shown in FIG. 3 is used as a junction capacitance in a light receiving element integrated circuit used for a photo sensor, a photo interrupter, a photo coupler, or the like. Have been.

In this conventional example, as shown in FIG. 3, an N-type epitaxial layer 3 formed on a P-type semiconductor substrate 37 is formed.
6 is separated into an epitaxial layer region of the capacitor portion and another epitaxial layer region by P-type diffusion layers 38 and 39. The N-type semiconductor layer 35 having a high impurity concentration is formed in the epitaxial layer region of the capacitor portion. , A nitride film 32 forming a capacitor portion, and a metal layer 33 forming one electrode of the capacitor are formed in this order. An ohmic contact is formed on a part of the N-type semiconductor layer 35 which becomes the other electrode of the capacitor. Is formed, and serves as a port for taking out the other electrode of the capacitor. The outside of the capacitor is covered with a thick protective film 31 such as an oxide film.

In this capacitor, the N-type semiconductor layer 35 and the N-type epitaxial layer 36 are electrically connected by the same N-type semiconductor, and the N-type epitaxial layer 36 is a P-type semiconductor substrate 37.
And a PN junction. The PN junction has the same configuration as the photodiode in the light receiving element and performs the same operation as the photodiode, so that a photocurrent is generated from the N-type epitaxial layer 36 toward the P-type semiconductor substrate 37.

[0005]

However, in the above conventional structure, the photocurrent is set to I3, and the metal layer 34 having an ohmic contact with the N-type epitaxial layer 36 is formed.
Is connected to the resistor load R31, a voltage drop represented by (R31 × I3) occurs in the metal layer 34, and one end of the capacitor undergoes potential fluctuation due to the photocurrent I3.

In order to solve the problem of the potential fluctuation,
Always set the metal layer 34 side to the ground potential GND or the power supply potential Vcc.
However, the conventional configuration has a problem that it cannot be connected to a high impedance signal line.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, in which a junction capacitor used in a light receiving element integrated circuit can be prevented from malfunctioning by light, and each electrode of the junction capacitor is connected to a high impedance signal line. An object of the present invention is to provide a junction capacitance for a light receiving element that can be connected.

[0008]

According to the present invention, a junction capacitance for a light-receiving element comprises a P-type semiconductor substrate constituting an integrated circuit for a light-receiving element, and a first P-type buried isolation diffusion layer on the P-type semiconductor substrate. And an N-type epitaxial layer formed in an island shape by the second P-type separation / diffusion layer and formed between the P-type semiconductor substrate and the first P-type buried separation / diffusion layer.
An N-type well is formed by the mold buried layer, the first P-type buried isolation diffusion layer above the first buried layer, and the second P-type isolation diffusion layer reaching the first P-type buried isolation diffusion layer; A P-type base diffusion layer formed in the N-type well;
An N-type emitter diffusion layer formed in the P-type base diffusion layer; and a PN junction between the N-type emitter diffusion layer and the P-type base diffusion layer is reverse-biased to provide a junction capacitance. The above object is achieved.

The PN junction between the N-type well and the P-type base diffusion layer may be reverse-biased to provide a junction capacitance.

The N-type emitter diffusion layer and the N-type well are electrically connected to each other, and a junction capacitance formed by reverse-biasing a PN junction between the N-type emitter diffusion layer and the P-type base diffusion layer; A configuration in which a PN junction of the P-type base diffusion layer and a junction capacitance obtained by reversely biasing the P-type base diffusion layer are connected in parallel may be adopted.

Further, the junction capacitance for a light receiving element of the present invention comprises a P-type semiconductor substrate constituting a light-receiving element integrated circuit, a first P-type buried isolation diffusion layer and a second P-type semiconductor substrate on the P-type semiconductor substrate.
A first N-type epitaxial layer which is formed in an island shape by the P-type isolation / diffusion layer to form an N-type well; a first P-type buried isolation / diffusion layer on the P-type semiconductor substrate;
A second N-type epitaxial layer which is formed in an island shape by the P-type separation / diffusion layer and does not constitute an N-type well;
A P-type base diffusion layer formed in the P-type well and an N-type emitter diffusion layer formed in the P-type base diffusion layer, wherein the first N-type epitaxial layer and the second N-type A power supply voltage or a predetermined reference voltage is applied to the epitaxial layer, and a PN junction between the first P-type buried isolation diffusion layer and the second P-type isolation diffusion layer and the N-type well is reverse-biased to form a junction capacitance. Therefore, the above object is achieved.

Preferably, the impurity concentration of the N-type well is higher than the impurity concentration of the N-type epitaxial layer.

The operation of the present invention will be described below.

According to the above configuration, the junction capacitance is constituted by the junction capacitance of the PN junction of the N-type emitter diffusion layer and the P-type base diffusion layer. This PN junction forms a junction at a portion much closer to the surface than the PN junction formed by the N-type epitaxial layer and the P-type semiconductor substrate.

On the other hand, signal light used in a photosensor, a photointerrupter, a photocoupler or the like is light having a long wavelength such as infrared light or red light. Most of the minority carriers (optical signal current) generated by these lights are generated in the P-type semiconductor substrate.
Absorbed by the PN junction between the p-type epitaxial layer and the p-type semiconductor substrate.

On the other hand, the PN junction between the N-type emitter diffusion layer and the P-type base diffusion layer forms a junction at a shallow portion of the semiconductor layer. The capacity can be configured.

Therefore, unlike the related art, it is not necessary to fix the potential of the semiconductor forming one of the electrodes of the junction capacitor to the power supply potential or the ground potential in order to suppress the potential fluctuation due to the photocurrent, and the junction capacitance is formed. Either the N-type emitter diffusion layer or the P-type base diffusion layer can be connected to the high impedance signal line.

Further, the N-type well and the P-type
Also in the N junction and the PN junction formed by the N-type well and the first P-type buried isolation diffusion layer and the second P-type isolation diffusion layer, the PN formed by the N-type epitaxial layer and the P-type semiconductor substrate is also used.
Since the junction is formed in a portion of the semiconductor layer which is shallower than the junction, the same operation as described above is provided.

The N-type emitter diffusion layer and the N-type well are made conductive, and the N-type emitter diffusion layer and the P-type
When a junction capacitance formed by reverse-biasing the N-junction and a junction capacitance formed by reverse-biasing the PN junction of the N-type well and the P-type base diffusion layer are connected in parallel, the capacitance value of the junction capacitance increases. It is possible to do.

Further, when the impurity concentration of the N-type well is made higher than the impurity concentration of the N-type epitaxial layer, the N-type well, the first P-type buried isolation diffusion layer, and the second P-type isolation diffusion It is possible to increase the junction capacitance of the PN junction composed of layers.

[0021]

Embodiments of the present invention will be specifically described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a cross-sectional structure of a semiconductor layer constituting a junction capacitance for a light receiving element according to Embodiment 1 of the present invention.

In the first embodiment, as shown in FIG. 1, a P-type semiconductor substrate 101A constituting an integrated circuit for a light receiving element is used.
And a first P-type buried isolation / diffusion layer 103A and a second P-type isolation / diffusion layer 104 on the P-type semiconductor substrate 101A.
An N-type buried layer 102A formed between a P-type semiconductor substrate 101A and a first P-type buried isolation / diffusion layer 103A in an N-type epitaxial layer 105A formed into islands by A, The upper first P-type buried isolation / diffusion layer 103A and the second P-type isolation / diffusion layer 104A reaching the first P-type buried isolation / diffusion layer 103A constitute an N-type well. And a N-type emitter diffusion layer 107 formed in the P-type base diffusion layer 106A.
A, which reverse biases the PN junction of the N-type emitter diffusion layer 107A and the P-type base diffusion layer 106A to form a junction capacitance.

The junction capacitance may be configured by reverse biasing the PN junction between the N-type well 105A and the P-type base diffusion layer 106A.

The N-type emitter diffusion layer 107A and the N-type well 105A are made conductive, and the N-type
A junction capacitance formed by reverse-biasing the PN junction between A and the P-type base diffusion layer 106A and a junction capacitance formed by reverse-biasing the PN junction between the N-type well 105A and the P-type base diffusion layer 106A are connected in parallel. It may be configured.

Further, the junction capacitance is determined by applying a power supply voltage or a predetermined reference voltage to the N-type epitaxial layers 105A and 105B, and forming a junction between the first P-type buried isolation diffusion layer 103A and the second P-type isolation diffusion layer 104A. P of N-type well 105A
The N junction may be configured with a reverse bias.

More specifically, in the first embodiment, FIG.
As shown in FIG. 5, the cross section of the portion where the junction capacitance is formed is formed on an N-type buried diffusion layer 102 on a P-type semiconductor substrate 101A.
A, first P-type buried isolation diffusion layer 103A, first P
An N-type epitaxial layer 105A formed in the N-type well and separated in an island shape by the type-buried isolation / diffusion layer 103A and the second P-type isolation / diffusion layer 104A; a base layer of the NPN transistor; And the same N-type emitter diffusion layer 10A formed in the P-type base diffusion layer 106A as the diffusion layer constituting the emitter layer of the NPN transistor.
7A and a protective film 116A of an oxide film or the like are formed in this order.

Further, an N-type emitter diffusion layer 108A for making ohmic contact with the N-type epitaxial layer (N-type well) 105A is formed in the upper layer of the N-type epitaxial layer, and the first P-type buried isolation diffusion layer is formed. 1
03A, 103B and the second P-type isolation / diffusion layers 104A, 104A,
N-type emitter diffusion layer 1 for making ohmic contact with N-type epitaxial layer 105B separated at 04B
09A is formed, and a P-type base diffusion layer 11 for making ohmic contact with the second P-type isolation / diffusion layer 104A is formed.
0A is formed.

An electrode wiring 111A is formed on the P-type base diffusion layer 110A, an electrode wiring 112A is formed on the N-type emitter diffusion layer 108A, and the P-type base diffusion layer 10A is formed.
An electrode wiring 113A is formed on 6A. Also,
An electrode wiring 114A is formed on the N-type emitter diffusion layer 107A, and an electrode wiring 115A is formed on the N-type emitter diffusion layer 109A.

According to the above configuration, the junction capacitance is determined by the PN of the N-type emitter diffusion layer 107A and the P-type base diffusion layer 106A.
It is constituted by the junction capacity of the junction. This PN junction is
N-type epitaxial layers 105B, 105B ', 105C
Then, a junction is formed in a portion of the semiconductor layer that is much closer to the surface than the PN junction formed by the P-type semiconductor substrate 101A.

On the other hand, the signal light used for the photosensor, photointerrupter, photocoupler and the like is light having a long wavelength such as infrared light or red light. Since the minority carriers (optical signal currents) generated by these lights are mostly generated in the P-type semiconductor substrate 101A, the N-type epitaxial layer 10 which is formed in an island shape and forms an N-type well is formed.
N-type epitaxial layers 105B and 10 in portions other than 5A
5B ′, 105C and P-type semiconductor substrate 101A
Absorbed at the junction.

On the other hand, the PN junction between the N-type emitter diffusion layer 107A and the P-type base diffusion layer 106A forms a junction at a shallow portion of the semiconductor layer, and is insensitive to such light.

Therefore, the N-type emitter diffusion layer 107A,
Electrode wirings 113A and 114 serving as an electrode outlet of a junction capacitance using a PN junction of the P-type base diffusion layer 106A
A high impedance signal line can be connected to any terminal of A.

Similarly, when the PN junction of the N-type well 105A and the P-type base diffusion layer 106A is used, the electrode wiring 112A, 1
A high impedance signal line can be connected to any terminal of 13A.

Further, the N-type emitter diffusion layer 107A and the N-type well 105A are connected to each other by a conductor such as a metal to make them conductive.
N-type emitter diffusion layer 107A and P-type base diffusion layer 106
A junction capacitance obtained by reverse-biasing the PN junction of A and a junction capacitance obtained by reverse-biasing the PN junction of the N-type well 105A and the P-type base diffusion layer 106A are connected in parallel. The value can also be increased.

Further, the first P-type buried isolation / diffusion layer 1
03A, 103B and the second P-type separation / diffusion layer 104A,
An N-type epitaxial layer 105B which is formed in an island shape by 104B and does not constitute an N-type well;
The N-type epitaxial layer 105A, which is formed in an island shape by the P-type buried isolation / diffusion layer 103A and the second P-type isolation / diffusion layer 104A and forms an N-type well, is used as a power supply voltage, P-type buried isolation diffusion layer 10
The PN junction between the first P-type buried isolation diffusion layer 103A and the N-type epitaxial layers 105B and 105A, and the second P The PN junction between the mold separation / diffusion layer 104A and the N-type epitaxial layers 105B and 105A is reverse-biased.

Here, the first P-type buried isolation / diffusion layer 1
03A and N-type epitaxial layer 105 which is an N-type well
A and the PN junction between the second P-type isolation / diffusion layer 104A and the N-type epitaxial layer 105A are also slightly affected by infrared light and red light.

Therefore, when the PN junction is reverse-biased and used as a junction capacitance, a high impedance signal line can be connected to any terminal of the electrode wirings 111A and 112A, which is an electrode outlet of the junction capacitance.

(Embodiment 2) FIG. 2 shows a sectional structure of a semiconductor layer constituting a junction capacitance for a light receiving element according to Embodiment 2 of the present invention.

As shown in FIG. 2, the second embodiment differs from the first embodiment in that a high-concentration N-type impurity diffusion region 201A is formed in the N-type well 105A.
Other configurations are the same as those in the first embodiment. With this configuration, it is possible to increase the junction capacitance.

Generally, the junction capacitance value is proportional to the impurity concentration of the P-type semiconductor and the N-type semiconductor constituting the PN junction. Therefore, the higher the impurity concentration, the larger the capacitance value of the junction capacitance.

However, the N-type well 10 shown in FIG.
5A is an N-type epitaxial layer, which has a low impurity concentration because it normally constitutes the collector region of the NPN transistor. Therefore, the junction capacitance of the PN junction composed of the N-type well 105A, the first P-type buried isolation / diffusion layer 103A, and the second P-type isolation / diffusion layer 104A cannot be increased.

On the other hand, as shown in FIG. 2, when the N-type impurity is diffused in the N-type well 105A at a high concentration to form the high-concentration N-type impurity diffusion region 201A, the high-concentration in the N-type well 105A is increased. N-type impurity diffusion region 201A
And the first P-type buried isolation / diffusion layer 103A can increase the junction capacitance of the PN junction. Therefore, the entire junction capacitance of the PN junction formed by the N-type well 105A, the first P-type buried isolation / diffusion layer 103A, and the second P-type isolation / diffusion layer 104A can be increased.

[0044]

As described above, the junction capacitance for a light-receiving element of the present invention is a PN junction between an N-type emitter diffusion layer and a P-type base diffusion layer, a PN junction between an N-type well and a P-type base diffusion layer, or Since the PN junction is formed by the N-type well, the first P-type buried isolation diffusion layer and the second P-type isolation diffusion layer, it is much shallower than the PN junction formed by the N-type epitaxial layer and the P-type semiconductor substrate. A junction can be formed in a portion of the semiconductor layer close to the surface.

Therefore, since minority carriers generated by signal light having a long wavelength such as infrared light or red light are mostly generated in the P-type semiconductor substrate, a PN junction between the N-type epitaxial layer and the P-type semiconductor substrate is generated. In the above-described configuration of the present invention in which a PN junction is formed in a shallow portion of the semiconductor layer, the junction capacitance is not affected by such light and is insensitive, and does not malfunction due to light.

As a result, it is not necessary to fix the potential of the semiconductor forming one of the electrodes of the junction capacitor to the power supply potential or the ground potential in order to suppress the potential fluctuation due to the photocurrent as in the conventional case. Both electrodes can be connected to a high-impedance signal line, and can provide signal transmission via a junction capacitance, so-called AC-coupled capacitance.

The N-type emitter diffusion layer and the N-type well are made conductive, and the N-type emitter diffusion layer and the P-type base
When a junction capacitance formed by reverse-biasing the N-junction and a junction capacitance formed by reverse-biasing the PN junction of the N-type well and the P-type base diffusion layer are connected in parallel, the capacitance value of the junction capacitance increases. Can be done.

Further, when the impurity concentration of the N-type well is made higher than the impurity concentration of the N-type epitaxial layer, the N-type well, the first P-type buried isolation diffusion layer, and the second P-type isolation diffusion The junction capacitance of the PN junction composed of layers can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor layer forming a junction capacitance for a light receiving element according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a cross-sectional structure of a semiconductor layer constituting a junction capacitance for a light receiving element according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a cross-sectional structure of a semiconductor layer constituting a conventional junction capacitance for a light receiving element.

[Explanation of symbols]

101A P-type semiconductor substrate 102A N-type buried layer 103A, 103B First P-type buried separation / diffusion layer 104A, 104B Second P-type separation / diffusion layer 105A Island-shaped N-type epitaxial layer 105B, 105B constituting N-type well '' Island-shaped N-type epitaxial layer 105C that does not form an N-type well 105C N-type epitaxial layer 106A, 110A P-type base diffusion layer 107A, 108A, 109A N-type emitter diffusion layer 111A to 115A Electrode wiring 116A Protective film 201A High concentration N-type impurity diffusion region

Claims (5)

[Claims] 1. A P-type semiconductor substrate constituting an integrated circuit for a light-receiving element, and an island-shaped separation on the P-type semiconductor substrate by a first P-type buried isolation diffusion layer and a second P-type isolation diffusion layer. An N-type buried layer formed between the P-type semiconductor substrate and the first P-type buried isolation diffusion layer in the N-type epitaxial layer formed by A buried isolation diffusion layer and the second P type buried isolation diffusion layer reaching the buried isolation diffusion layer;
An N-type well is formed by the P-type isolation diffusion layer, and has a P-type base diffusion layer formed in the N-type well and an N-type emitter diffusion layer formed in the P-type base diffusion layer. And a junction capacitance for a light receiving element, wherein the PN junction between the N-type emitter diffusion layer and the P-type base diffusion layer is reverse-biased to make a junction capacitance. 2. A P-type semiconductor substrate constituting an integrated circuit for a light receiving element, and an island-like separation by a first P-type buried isolation diffusion layer and a second P-type isolation diffusion layer on the P-type semiconductor substrate. An N-type buried layer formed between the P-type semiconductor substrate and the first P-type buried isolation diffusion layer in the N-type epitaxial layer formed by A buried isolation diffusion layer and the second P type buried isolation diffusion layer reaching the buried isolation diffusion layer;
An N-type well is formed by the P-type isolation diffusion layer, and has a P-type base diffusion layer formed in the N-type well and an N-type emitter diffusion layer formed in the P-type base diffusion layer. And a junction capacitance for a light-receiving element, wherein the PN junction between the N-type well and the P-type base diffusion layer is reverse-biased to be a junction capacitance. 3. A P-type semiconductor substrate constituting an integrated circuit for a light receiving element, and an island-like separation by a first P-type buried isolation diffusion layer and a second P-type isolation diffusion layer on the P-type semiconductor substrate. An N-type buried layer formed between the P-type semiconductor substrate and the first P-type buried isolation diffusion layer in the N-type epitaxial layer formed by A buried isolation diffusion layer and the second P type buried isolation diffusion layer reaching the buried isolation diffusion layer;
An N-type well is formed by the P-type isolation diffusion layer, and has a P-type base diffusion layer formed in the N-type well and an N-type emitter diffusion layer formed in the P-type base diffusion layer. The N-type emitter diffusion layer and the N-type well are electrically connected to each other;
A junction capacitance formed by reverse-biasing the PN junction between the N-type emitter diffusion layer and the P-type base diffusion layer and a junction capacitance formed by reverse-biasing the PN junction between the N-type well and the P-type base diffusion layer are connected in parallel. The junction capacitance for the light receiving element. 4. A P-type semiconductor substrate constituting an integrated circuit for a light-receiving element, and an island-shaped separation on the P-type semiconductor substrate by a first P-type buried isolation diffusion layer and a second P-type isolation diffusion layer. A first N-type epitaxial layer formed to form an N-type well, and an island-like isolation on the P-type semiconductor substrate by a first P-type buried isolation diffusion layer and a second P-type isolation diffusion layer A second N-type epitaxial layer formed without forming an N-type well, a P-type base diffusion layer formed in the N-type well, and an N-type emitter diffusion formed in the P-type base diffusion layer A power supply voltage or a predetermined reference voltage is applied to the first N-type epitaxial layer and the second N-type epitaxial layer; and the first P-type buried isolation diffusion layer and the second The PN junction between the P-type isolation diffusion layer and the N-type well is connected in reverse bias. The junction capacitance for the light receiving element to be the combined capacitance. 5. The semiconductor device according to claim 1, wherein said N-type well has an impurity concentration of said N-type well.
The junction capacitance for a light receiving element according to claim 1, wherein the junction capacitance is higher than an impurity concentration of the type epitaxial layer.