JP2000230965A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make surely specifiable a defective place in the scan path of a circuit for test in a zero-cycle test. SOLUTION: In a composite shift scan circuit 1 as a circuit for test, scan latches 21 to 23, scan latches 31 to 33 and scan latches 41 to 43 which are installed at this semiconductor integrated-circuit device and which are equipped with respective changeover functions are linked together so as to be connected, and scan paths are formed, and, scan chains SC1 to SC3 in the transverse direction and scan chains SC4 to SC6 in the longitudinal direction are constituted. In a zero-cycle test which confirms whether the composite shift scan circuit 1 itself is operated correctly or not, the scan chains in the longitudinal direction and the transverse direction in which a defective signal is outputted are detected. In the scan patches in a point in which the scan chains are crossed and which are equipped with the changeover functions are specified to be defective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for diagnosing a test circuit, and more particularly to a technique effective when applied to the determination of a defective portion of the test circuit itself.

[0002]

2. Description of the Related Art According to studies made by the present inventors, a test circuit for efficiently testing a logic gate from a small number of external terminals is incorporated in a semiconductor integrated circuit device. As a configuration of the test circuit, a shift scan circuit and a BIST (Build In Self)
Test).

The shift scan circuit is designed in advance to operate as a shift register by connecting scan latches provided in a semiconductor integrated circuit device in a daisy chain (scan path). Is controlled and observed.

The BIST has a built-in tester function such as a test pattern generation circuit, a test output compression circuit, and a test result determination circuit, and can perform a self-test without using an external tester.

In the shift scan circuit, a test for confirming whether or not the shift scan circuit itself operates properly, that is, a so-called zero cycle test is performed before the scan path test.

In the zero cycle test, a test signal is input from an external terminal and a zero cycle failure is determined by detecting whether the result of the test signal is correctly output to a predetermined external terminal.

As an example describing in detail a test circuit provided in this type of semiconductor integrated circuit device, see, for example, Ohm Co., Ltd.
The Institute of Electronics, Communication and Communication Engineers (ed.), “LSI Handbook” P165, P166, and this document describes the configuration of various scan path systems.

[0008]

However, in the test circuit provided in the semiconductor integrated circuit device as described above,
The inventors have found the following problems.

That is, in the shift scan circuit, when a zero cycle test is performed, only the result is output, so that it is impossible to logically analyze which scan latch in the scan path of the shift scan circuit has a defect. However, there is a problem that feedback to a manufacturing process or the like cannot be performed.

In addition, since the BIST has a test pattern generation circuit for generating random numbers, each node has a timing relationship between the bit shift operation of the test pattern generation circuit and the shift operation of the scan chain. There is a problem that regularity appears in the logical value given as a result and an undetectable failure assumption point appears.

An object of the present invention is to provide a semiconductor integrated circuit device capable of reliably specifying a defective portion of a scan path of a test circuit in a zero cycle test.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of greatly improving the detection rate of a faulty assumption point which is difficult to detect.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit device of the present invention, a first shift scan path for setting or reading arbitrary data and a second shift path whose input destination and output destination are different from those of the first shift scan path. A test circuit in a full scan scan path system including a scan path and all the latches provided in a circuit to which the first and second shift scan paths are connected, respectively.

Thus, by configuring the first and second shift scan paths, it is possible to easily and reliably specify a scan latch failure in the test circuit.

Further, according to the semiconductor integrated circuit device of the present invention, a first shift scan path for setting or reading arbitrary data, and a second shift path having an input destination and an output destination different from the first shift scan path are provided. A scan path, all the latches provided in a circuit to which the first and second shift scan paths are respectively connected, and a first test pattern generation for outputting a test pattern via the first shift scan path Unit, a second test pattern generation unit that outputs a test pattern via the second shift scan path, and a first test unit that compresses a test pattern output from the test target circuit via the first shift scan path. And a second data compression unit for compressing a test pattern output from the test target circuit via the second shift scan path. Those with more becomes test circuit and a circuit.

Furthermore, the semiconductor integrated circuit device of the present invention
The first and second test pattern generators comprise a pseudo random number generating circuit for generating a pseudo random number as a test pattern.

Thus, by providing the first and second test pattern generators, it is possible to eliminate the regularity that appears between the values input through the test circuit for the latch. In addition, it is possible to greatly reduce the number of fault assumption points such as stuck-at faults that are difficult to detect.

Further, in the semiconductor integrated circuit device according to the present invention, the latch is configured such that the latch switches a signal input from the first and second shift scan paths by a select signal, and a signal switched by the switch. , And an output unit that outputs a signal output from the scan latch to the first and second shift scan paths.

As described above, the failure analysis of the semiconductor integrated circuit device can be efficiently performed, and the reliability of the semiconductor integrated circuit device can be improved.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a schematic explanatory diagram of a shift scan circuit provided in a semiconductor integrated circuit device according to Embodiment 1 of the present invention, and FIG. 2 is a shift scan circuit according to Embodiment 1 of the present invention. FIG. 3 is a circuit explanatory diagram of a scan latch with a switching function provided in the scan circuit. FIG. 3 is a flowchart illustrating an algorithm by which the shift scan circuit according to the first embodiment of the present invention specifies a defective scan latch with a switching function. FIG. 5 is a layout image diagram when a scan latch with a switching function according to the first embodiment of the present invention is laid out on a semiconductor chip;
5 is a flowchart illustrating an algorithm when a horizontal scan chain of the shift scan circuit according to the first embodiment of the present invention is configured.

In the first embodiment, the composite shift scan circuit 1, which is a test circuit, provides shift paths for all the latches in the circuit. When testing this circuit, any data is supplied to the latches through the shift paths. Is a circuit that sets or reads data.
The test is performed by the scan path method of full scan.

As shown in FIG. 1, the composite shift scan circuit 1 has scan latches (latches) 2 ₁ to 2 ₃ , 3 ₁ to ₃ with a switching function provided in a semiconductor integrated circuit device.
It is constituted by a 3 _3, 4 ₁ to 4 _3. Switching function scan latch 2 _1, as shown in FIG. 2, and a connection destination transistor (switching section) for switching 5,6 and scan latch 7. One end of the transistor 5 and 6, has a switching function scan latch 2 ₁ shift input SI1, SI2,
The other connection of the transistors 5 and 6 is connected to the input of the scan latch 7.

[0026] the output of the scan latch 7, the shift output of the switching function scan latch 2 ₁ (output unit) S
O1 and SO2 are connected. The selector signal SEL is input to the gate of the transistor 5, and the transistor 6
The selector signal / SEL, which is an inverted signal of the selector signal SEL, is input to the gates of.

[0027] In FIG. 2 has been described for the switching function scan latch 2 _1, the switching function scan latch ₂ 2, 2 _3, 3 ₁ to 3 _3, 4 ₁ to 4 ₄
Configuration of also the same as the switching function scan latch 2 _1.

In FIG. 2, the transistors 5 and 6 are used for switching the connection destination. However, the connection destination switching means may be other than the transistor, and the shift input SI
A semiconductor element or a circuit having a selector function that can select an input signal from the terminals of SI1 and SI2 may be used.

Next, a scan latch 2 with a switching function
₂₁ to _3, as shown in FIG. 1, has a scan path coupled strung each scan chain (first shift scan path) SC1 is formed. The switching function scan latch 2 ₁ shift input SI1, and external terminals 8 which the test signal is input is connected, a predetermined external terminal 9 is connected to the output SO1 switching function scan latch 2 ₃ Have been.

Further, a scan latch 3 with a switching function
Even _{1-3 3,} has a scan path coupled strung each scan chain (first shift scan path) SC2 is formed. The switching function scan latch 3 ₁ shift input SI1, is connected to an external terminal 10 which the test signal is input, a predetermined external terminal 11 is connected to the output SO1 switching function scan latch 3 ₃ Have been.

Similarly, the scan latches 4 ₁ to 4 ₃ with the switching function also constitute a scan path, and constitute a scan chain (first shift scan path) SC3. The switching function scan latch 4 ₁ shift input SI1, external terminal 1 which the test signal is input
2 is connected, a predetermined external terminal 13 is connected to the output SO1 switching function scan latch 4 _3.

Further, the scan latches 2 ₁ , 3 ₁ , 4 ₁ with the switching function also constitute a scan path, and constitute a scan chain (second shift scan path) SC4. Scan latch with switching function 2 ₂ , 3
₂ , 4 ₂ and the scan latches 2 ₃ , 3 ₃ , 4 ₃ with the switching function are also scan paths, each of which is a scan chain (second shift scan path) SC
5, SC6.

Here, the scan chains SC1 to SC3
Is a horizontal scan chain in FIG. 1 and is called a horizontal scan chain.
SC6 is a vertical scan chain in FIG. 1 because it is a vertical scan chain.

[0034] In the scan chain SC4, the switching function scan latch 2 ₁ shift input SI2, which is the external terminal 14 is connected to the test signal is input, the output unit SO2 switching function scan latch 41 A predetermined external terminal 15 is connected.

[0035] In scan chain SC5, the switching function scan latch 2 ₂ shift input SI2, and the external terminal 16 which the test signal is input is connected, the output unit SO of the switching function scan latch 4 ₂
A predetermined external terminal 17 is connected to 2.

Further, in the scan chain SC5, and external terminals 18 which the test signal is inputted to the switching function scan latch 2 ₃ shift input SI2 is connected, the output unit SO2 switching function scan latch 4 ₃ Is connected to a predetermined external terminal 19.

Although the external terminals 8 to 19 are assigned as different terminals here, the external terminals 8, 10, 12
And the external terminals 14, 16, 18 may be shared. Similarly, external terminals 9, 11, 13 and external terminal 1
5, 17, and 19 may be shared. Further, FIG. 1 shows only the connection configuration of the composite shift scan circuit 1, and does not show other internal circuits to be tested or signals input / output to / from a scan latch having a switching function.

Next, a zero cycle test performed on the composite shift scan circuit 1 in the present embodiment will be described with reference to FIGS.

The zero cycle test is a test for confirming whether or not the composite shift scan circuit 1 itself operates properly. The external terminals 8, 10, 12, 14, 16, 16 and 1
8, a test signal is input from external terminals 9, 11, 1
Whether the result of the test signal is correctly output to 3, 15, 17, and 19 is detected, and the failure of the composite shift scan circuit 1 is determined.

When performing the zero cycle test, first, a predetermined test signal is input from the external terminals 8, 10, and 12, and the results of the test signals of the scan chains SC1 to SC3 are output to the external terminals 9, 11, and 13.

Next, predetermined test signals are inputted from the external terminals 14, 16, and 18, and the scan chains SC4 to SC4 are inputted.
The result of the test signal of No. 6 is output to the external terminals 15, 17, and 19.

If neither of the output terminals of the scan chains SC1 and SC4, that is, the external terminals 9 and 15, outputs a correct test signal, the scan with the function of switching the intersection of the defective scan chains SC1 and SC4. it is possible to specify that the latch 2 ₁ is defective.

The algorithm for specifying the scan latch having the failure switching function will be described with reference to the flowchart of FIG.

First, the stock of the NG scan chain in the vertical scan chain is cleared (step S101), and the count in the vertical scan chain is cleared (step S102).

The vertical scan chain is counted up (step S103), and it is determined whether or not the data output from the vertical scan chain is correct (step S103).
104). If the output result is correct in the processing of step S104, it is determined whether or not the count of the vertical scan chains counted up in the processing of step S103 is the maximum (step S105).

Further, in the process of step S104,
If the output result is different, the numerical value of the vertical scan chain is stocked (step S106). In the process of step S105, if the count of the vertical scan chain is not the maximum, steps S103 and S10
Steps S4 and S106 are repeated, and if the count of the vertical scan chain is the maximum, the stock of the scan chain which has become NG in the horizontal scan chain is cleared (step S107).

The count in the horizontal scan chain is cleared (step S108). The count of the horizontal scan chain is counted up (step S109), and it is determined whether the data output from the horizontal scan chain is correct (step S110).

If the output result is correct in the process of step S110, it is determined whether the count of the horizontal scan chain counted up in the process of step S109 is the maximum (step S111). If the output result is different in the process of step S110, the numerical value of the horizontal scan chain is stocked (step S112).

In the processing of step S111, if the count of the horizontal scan chain is not the maximum, the processing of steps S109, S110, and S112 is repeated. If the count of the horizontal scan chain is the maximum, the processing in the step S106 is repeated. It is confirmed whether or not there is a vertical scan chain that has become NG (step S113).

If there is an NG vertical scan chain in the process of step S113, the horizontal scan chain is checked (step S114). Then, a scan latch with a switching function that intersects the stocked vertical scan chain and horizontal scan chain is obtained and listed as a defective portion (step S115).

If there is no vertical scan chain in the process of step S113, it is confirmed whether or not there is an NG horizontal scan chain (step S116).
If there is no horizontal scan chain, there is no defect (step S117).

In the processing in steps S114 and S116, if there is no stock, there is a defect,
The mode becomes a mode in which the scan latch with the switching function of the failure cannot be specified (step S118). In step S118, the scan latch with the switching function has no defect. However, for example, a case where a signal is not transmitted due to disconnection or the like may be considered.

In this embodiment, both the horizontal and vertical scan chains have a logical meaning. The composite shift scan circuit 1 has a switching function in which scan chains are assembled in the vertical direction and the horizontal direction when drawing a logical schematic diagram (FIG. 1) because the scan chains are configured in a secondary manner. The row and column can be distinguished from vertical and horizontal because of the matrix of the attached scan latch. These are only logical and have nothing to do with the vertical and horizontal layout of the semiconductor chip.

FIG. 4 shows a layout image when the composite shift scan circuit 1 is laid out on a semiconductor chip.

Scan latches 2 ₁ to 2 ₃ , 3 _{1 to} 3 ₃ , 4 with a switching function in the composite shift scan circuit 1
_{1-4 3,} as shown in FIG. 4, are formed at random in the semiconductor chip.

[0056] As shown in FIG. 1, the switching function scan latch 2 ₁ to 2 _3, switching function scan latch 3 ₁ to 3 _3, the switching function scan latch 4 ₁
To 4 _third scan, respectively, by chain SC1, SC
2, SC3, scan latches 2 ₁ , 3 ₁ , 4 _{1 with} a switching function, scan latches 2 with a switching function
₂ , 3 ₂ , 4 ₂ and scan latches 2 ₃ , 3 ₃ , 4 ₃ with a switching function make scan chain SC 4, SC 4.
The connection may not be able to configure SC5 and SC6.

For this purpose, the scan chains SC4, S4
When configuring C5 and SC6, scan latches 2 ₁ , 3 ₁ , 4 _{1 with} a switching function, scan latches 2 ₂ , 3 ₂ , 4 _{2 with} a switching function, and scan latches 2 ₃ , 3 ₃ , 4 ₃ with a switching function. May be switched at random.

For example, as shown in FIG. 4, the scan chain SC4 is composed of scan latches 2 ₁ , 3 ₁ , 4 ₂ with a switching function, and the scan chain SC5 is a scan latch 2 ₂ , 2 with a switching function.
3 _2, 4 _3, scan chain SC5 is constituted by the switching function scan latch 2 _{3, 3} 3, 4 _1.

Next, an algorithm for forming a horizontal scan chain will be described with reference to the flowchart of FIG.

For example, as shown in FIG. 5, the composite shift scan circuit 1 includes a scan latch R having a switching function.
1 to R7, and the number of scan chains N =
3, the maximum scan chain length L = 4.

First, a scan latch R with a switching function
1, R2, the scan latch R3 with the switching function, and the scan latches R4 to R7 with the switching function form a vertical scan (step S201).

In FIG. 5, the vertical scan chains of the scan latches R1 and R2 having the switching function are the scan chain T1, the vertical scan chain of the scan latch R3 having the switching function is the scan chain T2, and the vertical scans of the scan latches R4 to R7 having the switching function are performed. Let the chain be the scan chain T3.

Then, counting is started from m = 0 (step S202) (step S203), and m = 1. Here, m is the number of the target horizontal scan. Next, counting up is performed from n = 0 (step S204) (step S205), and n = 1. n
Is the number of the target vertical scan.

It is determined whether or not the vertical scan chain T1 has a scan latch with a switching function not assigned to the horizontal scan chain (step S206). Here, since it is not assigned, the vertical scan chain T
It is determined whether or not No. 1 has a scan latch with a switching function assigned to the horizontal scan chain Y1 (step S207). In step S207, since there is no assigned scan latch with the switching function, the scan latch R1 with the switching function is assigned to the horizontal scan chain Y1 (step S208).

It is determined whether the number n of the vertical scan chains matches the number N of the vertical scan chains (step S2).
09), if they do not match, the number n is counted up (n = 2) in the processing of step S205, and step S2
05 to S209 to repeat the scan latches R1, R3, and R4 with the switching function to the horizontal scan chain Y
Assign to 1.

If the number n and the number N of scan chains match in the processing of step S209, the maximum scan chain length L and the number m of the horizontal scan chains
Is checked (step S210), and the processing of steps S203 to S210 is repeated until the maximum scan chain length L and the number m of the horizontal scan chains match, thereby making the scan latch R with the switching function available.
2 and R5 are assigned to the horizontal scan chain Y2, and the scan latches R6 and R7 with the switching function are assigned to the horizontal scan chains Y3 and Y4, respectively.

As a result, in the first embodiment, the failure of the scan latch with the switching function can be reliably specified by the composite shift scan circuit 1 composed of the vertical and horizontal scan chains. It can be performed efficiently. Further, since the failure analysis result can be fed back to the semiconductor manufacturing process, the reliability of the semiconductor integrated circuit device can be improved.

In the first embodiment, the scan test circuit 1 has nine scan latches having a switching function.
However, the number of the scan latches having the switching function is increased or decreased depending on the configuration of the internal circuit of the semiconductor integrated circuit device to be tested.

Further, according to the first embodiment, transistors 5 and 6 are used as switching units, but these switching units may be other than transistors.
Any device or circuit such as a selector that can switch the signal output destination may be used.

(Embodiment 2) FIG. 6 shows a BIST provided in a semiconductor integrated circuit device according to Embodiment 2 of the present invention.
FIGS. 7A to 7D are explanatory diagrams of an input pattern generated by the BIST circuit according to the second embodiment of the present invention, and FIGS. 8A to 8D are diagrams of the present invention. Explanatory diagram of an input pattern in a BIST circuit examined by a user,
FIG. 9 is an explanatory diagram in the case where a failure cannot be detected due to the regularity of the scan chain generated by the BIST circuit studied by the present inventors.

In the second embodiment, a BIST circuit 20 is provided in a semiconductor integrated circuit device as a test circuit. As shown in FIG. 6, the BIST circuit 20 includes test pattern generation circuits (first and second test pattern generation units, pseudo random number generation circuits) 21 and 22 and an expected value compression circuit (first and second data compression circuits). circuit) 23 and 24, a composite shifting scan circuit 1 similarly to the first embodiment switching function scan latch 2 ₁ to 2 _3, 3 _1,
3 ₃ and a, 4 ₁ to 4 _3.

The test pattern generation circuits 21 and 22 generate a pseudo random number pattern. Composite shift scan circuit 1
Like the first embodiment, the switching function scan latch 2 ₁ to 2 _3, 2 ₄ to 2 _6, the 2 _{7-2 9} is a horizontal scan chain scan chain SC1~S
A vertical scan is performed by the scan latches 2 ₁ , 3 ₁ , 4 _{1 with} the switching function, the scan latches 2 ₂ , 3 ₂ , 4 _{2 with} the switching function, and the scan latches 2 ₃ , 3 ₃ , 4 ₃ with the switching function. Scan chains SC4 to SC6, which are chains, are respectively configured.

Test pattern generation circuit 21 inputs random number data to scan chains SC1 to SC3, and test pattern generation circuit 22 generates scan chains SC4 to SC4.
The random number data is input to C6. Expected value compression circuit 23,2
4 compresses the input data and outputs it to the test result determination device.

Next, the BIST circuit 20 using the composite scan circuit 1 will be described with reference to FIGS.

First, pseudo random numbers are generated by the test pattern generating circuit 21, and while these pseudo random numbers are shifted laterally, as shown in FIG. 7A, the scan latch 2 with the switching function of all the scan chains SC1 to SC3 is provided. storing data in the _{1-4 3.}

Then, pseudo random numbers are generated by the test pattern generating circuit 22, and while these pseudo random numbers are vertically shifted, as shown in FIG. 7B, the scan latches 2 with the switching function of all the scan chains SC4 to SC6 are provided. storing data in the _{1-4 3.}

Also, pseudo random numbers are generated again by the test pattern generating circuit 22, and while these pseudo random numbers are vertically shifted, as shown in FIG. 7C, scan latches with a switching function of all the scan chains SC4 to SC6 are provided. storing data in 2 _{1-4 3.}

Thereafter, pseudo random numbers are generated by the test pattern generating circuit 21, and while these pseudo random numbers are horizontally shifted, as shown in FIG. 7D, the scan latch 2 with the switching function of all the scan chains SC1 to SC3 is provided. storing data in the _{1-4 3.}

These test pattern generation circuits 21 and 22
Thus, the randomness of the input pattern can be improved by testing the semiconductor integrated circuit device while randomly storing data while shifting the pseudo random numbers horizontally and vertically.

Next, the BIST circuit 5 examined by the present inventors
Regarding the regularity of the input pattern at 0, FIG.
This will be described with reference to FIG.

In the BIST circuit 50, there is only one test pattern generation circuit 51, and the scan chain is also constituted only by the vertical scan chain by the scan latch R having the switching function. For example, as shown in FIG. 8A, when the data generated first by the test pattern generation circuit 51 is “0”,
0 'is stored in the scan latch with the switching function at the top right.

Next, assuming that the test pattern generating circuit 51 generates data "1", the first generated "1"
0 'is stored in the scan latch R with the switching function located at the center of the uppermost part as shown in FIG. 8B.

The value “0” stored in the upper right scan latch R with the switching function is shifted and stored in the lower scan latch R with the switching function, and stored in the upper right scan latch R with the switching function. Is stored as '1'. If the test pattern generation circuit 51 generates data "1" again, the first generated "0"
Is stored in the scan latch with the switching function located at the upper left position as shown in FIG.

The value "0" stored in the scan latch R with the switching function at the uppermost center is shifted and stored in the scan latch R with the switching function below it.
Scan latch R with switching function at the top center
1 'is stored.

"1" is also stored in the scan latch R with the switching function at the top right, and "1" and "1" are stored in the two scan latches R with the switching function below it.
0 'will be stored. Here, in FIG. 8D, the scan latch R with the switching function at the lower right is shown in FIG.
Scan latch R with switching function in the middle of the middle row,
And scan latch R with switching function at the top left
Are stored as '0', and a certain regularity is generated in the scan chain, so that only a specific test pattern can be applied.

Further, a case where the BIST circuit 50 examined by the inventor cannot detect a failure due to this regularity will be described.

For example, as shown in FIG. 9, a scan latch R with a switching function at the upper left of the BIST circuit 50 is provided.
When the data of the scan latch R with the switching function at the center of the central column is input to the AND circuit 52, the Hi signal is input to the input section of the AND circuit 52. Will output only the Hi signal. Therefore, the logic circuit 52
1 'stuck-at fault cannot be detected.

However, as described above, the BIST circuit 2
Since 0 is provided with two test pattern generation circuits 21 and 22, by performing a test by randomly combining the vertical shift and the horizontal shift,
The regularity of the scan chain can be eliminated.

Thus, according to the second embodiment, B
Fault assumption points such as stuck-at faults that are difficult to detect by the IST circuit 20 can be significantly reduced.

Although the second embodiment has described that the number of assumed fault points can be reduced, in the case of a test circuit as shown in FIG. 10, the assumed fault points cannot be detected.

For example, in this test target circuit, AND circuits RS1 and RS2 and OR circuit RW are provided, and the output sections of AND circuits RS1 and RS2 are OR circuits R1 and R2.
W, respectively, and are connected to AND circuits RS1, R
One input unit and the other input unit of S2 are commonly connected.

When the output of the OR circuit RW is "0", both inputs of the OR circuit RW are "0".
Therefore, either “0” or “1” is input to one of the input units and the other input unit of the AND circuits RS1 and RS2.

When the output of the OR circuit RW is "1", the outputs of the AND circuits RS1 and RS2 are both "1". Therefore, “1” is input to both input units of the AND circuits RS1 and RS2.

Here, "0" is output to the output of the AND circuit RS2.
If there is a stuck-at fault, the output of the AND circuit RS1 becomes "1", but the output of the AND circuit RS2 becomes "0".
Will remain.

However, when one of the input units is “1” and the other input unit is “0”, the OR circuit RW outputs “1”.
1 'output of the OR circuit RS2
The 0 'stuck-at fault cannot be detected.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

[0097]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the provision of the test circuits constituting the first and second shift scan paths facilitates the failure of the scan latch having the switching function in the test circuits. It can be specified reliably.

(2) According to the present invention, the first and second test pattern generators are provided in the test circuit, so that the regularity of the scan chain can be eliminated, and the degeneration is difficult to detect. Failure assumption points such as failures can be greatly reduced.

(3) Further, in the present invention, according to the above (1) and (2), the failure analysis of the semiconductor integrated circuit device can be efficiently performed, and the feedback to the manufacturing process can be performed in a short time. The reliability of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory diagram of a shift scan circuit provided in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a scan latch having a switching function provided in the shift scan circuit according to the first embodiment of the present invention;

FIG. 3 is a flowchart illustrating an algorithm of the shift scan circuit according to the first embodiment of the present invention for specifying a scan latch with a switching function of a defect;

FIG. 4 is a layout image diagram when a scan latch with a switching function according to the first embodiment of the present invention is laid out on a semiconductor chip;

FIG. 5 is a flowchart illustrating an algorithm for forming a horizontal scan chain of the shift scan circuit according to the first embodiment of the present invention.

FIG. 6 is a schematic explanatory diagram of a BIST circuit provided in a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIGS. 7A to 7D are explanatory diagrams of an input pattern generated by a BIST circuit according to a second embodiment of the present invention.

FIGS. 8A to 8D are BISs examined by the present inventors.
FIG. 3 is an explanatory diagram of an input pattern in a T circuit.

FIG. 9 is an explanatory diagram in a case where a failure cannot be detected due to the regularity of a scan chain generated by a BIST circuit studied by the present inventors.

FIG. 10 is an explanatory diagram of an example of a circuit diagram of a test target circuit in which a fault assumption point cannot be detected even in a BIST circuit according to a second embodiment of the present invention;

[Explanation of symbols]

1 composite shift scan circuit 2 ₁ to 2 ₃ switching function scan latch (latch) 3 ₁ to 3 ₃ switching function scan latch (latch) ₄₁ to ₃ switching function scan latch (latch) 5,6 transistor (switching 7) scan latch SC1 to SC3 scan chain (first shift scan path) SC4 to SC6 scan chain (second shift scan path) 8 to 19 external terminal 20 BIST circuit 21 test pattern generation circuit (first test pattern) Generator, pseudo-random number generator 22 test pattern generator (first test pattern generator, pseudo-random number generator) 23, 24 expected value compression circuit (first and second data compression circuits) SI1, SI2 shift input SO1, SO2 shift output (output unit) SEL, / SEL Scan signal RS1, RS2 AND circuit RW OR circuit 50 BIST circuit 51 Test pattern generation circuit 52 AND circuit R Scan latch with switching function

Claims (4)

[Claims] A first shift scan path for setting or reading arbitrary data; a second shift scan path having an input destination and an output destination different from the first shift scan path; 2. A semiconductor integrated circuit device comprising: a test circuit including all latches provided in circuits to which two shift scan paths are respectively connected. 2. A first shift scan path for setting or reading arbitrary data; a second shift scan path having an input destination and an output destination different from the first shift scan path; All the latches provided in a circuit to which each of the two shift scan paths is connected, a first test pattern generator that outputs a test pattern via the first shift scan path, and the second shift A second test pattern generation unit that outputs a test pattern via a scan path; a first data compression unit that compresses a test pattern output from a test target circuit via the first shift scan path; A second data compression circuit for compressing a test pattern output from the test target circuit via the second shift scan path. A semiconductor integrated circuit device comprising a test circuit. 3. The semiconductor integrated circuit device according to claim 2, wherein the first and second test pattern generators comprise a pseudo random number generating circuit for generating a pseudo random number as a test pattern. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein the latch switches a signal input from the first and second shift scan paths according to a select signal. A scan latch for storing a signal switched by the switching unit, and an output unit for outputting a signal output from the scan latch to the first and second shift scan paths. Integrated circuit device.