JP2001273159A - Failure analysis test device and register circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To always generate a normal signature even to an undefined value output from an unused function block and to easily perform a failure analysis of an integrated circuit, etc., in a short time while securing high reliability. SOLUTION: An observation register circuit first preserves mask data inputted through an AND circuit 2 instead of shift data in a register 7 through a register 4. The AND circuit 5 is disconnected to prevent the input of an undefined value by storing 0 as the mask data in the register 7 in the case of being connected to a non-scanning circuit having a possibility of outputting an undefined value because the conduction and disconnection of the circuit 5 are controlled by the preserved value of the register 7. Then, in this case, the shift data of the preceding stage is preserved only in the register 4 through an AND circuit 2 and an exclusive OR circuit 3 to exclude the influence of the undefined value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a macroblock or IP (Intelligent Property)
The present invention relates to a register circuit for detecting a failure of the circuit and a failure analysis test device configured using the register circuit.

[0002]

2. Description of the Related Art A technique using a SCAN design is widely used in order to increase a failure detection rate in a mass production test of an LSI.
The failure detection of the SI can be easily performed. The SCAN design is a method in which a storage element in a logic circuit is replaced with a scan F / F and connected so that it can be used as a pseudo input / output terminal. It can be done easily.

[0003]

However, this SCAN
The method using the design requires elements for SCAN of the internal F / F, and has a problem that the circuit area increases and the operating frequency deteriorates. When using an IP or an existing macro cell, the circuit or pattern
N may not be designed, partial SCA
In N, coverage could not be raised sufficiently.

[0004] Also, the circuit designed for SCAN is ATP.
A test pattern is generated using G (Automatic Test Pattern Generator).
Even if TPG is performed, a sufficient failure detection rate may not be obtained. Especially for circuits designed at the transistor level, circuit analysis by ATPG is not sufficient,
ATPG takes a lot of time, and often results in an insufficient detection rate.

In such a case, the function check vector is effective for the IP, the arithmetic unit and the memory. In particular, in the case of a microprocessor, since an operation can be operated by an instruction, a designer considers in advance a combination of operation operands that are effective for a single IP, an operation unit, and a memory, and performs a failure simulation on a single operation unit. And performing a failure analysis, a pattern with a high detection rate can be created.

According to this method, it is not necessary to perform SCAN design for the target IP, the arithmetic unit, and the memory, so that a high-speed and small-area product can be created. Further, when the failure simulation is performed by itself, the circuit can be performed at high speed because the circuit is small.

However, when a failure simulation is performed by itself, the result is masked by a path from a target circuit to a pin that can be actually observed by a tester, or the result is stored in a register and is not output to the outside. Therefore, it is necessary to observe the output signal by itself.

Therefore, an observation register circuit as shown in FIG. 5 for observing the internal signal in a pseudo manner every cycle is required. The observation register circuit fetches the internal signal every cycle and performs signature compression.
(Linear Feedback Shift Register). By performing the signature compression during the calculation, reading the final result, and comparing the result with the simulation result, it is possible to perform a fault detection equivalent to performing a pseudo-per-cycle comparison.

FIG. 5 is a block diagram showing a configuration example of a conventional observation register circuit. The observation register circuit has a configuration in which the outputs of the AND circuits 31 and 32 are input to the exclusive OR circuit 33, and the output of the exclusive OR circuit 33 is held in the register 34.

Observed Data and Parallel
Enable (PE) is input to the AND circuit 31, and the shift data (Shift Data) and Shift Enable (SE) are input to the AND circuit 32.
To be entered. SE = 0, PE = 0
Then, the output of the exclusive OR circuit 33 becomes 0 and the register 34 is reset to 0. When SE = 0 and PE = 1, only the observation data is input to the exclusive OR circuit 33 through the AND circuit 31, so that the observation data is stored in the register 34 as it is. When SE = 1 and PE = 1, the observation data and the shift data are input to the exclusive OR circuit 33 through the AND circuit 31, and the result is stored in the register 34. Since the shift data of the next cycle becomes the saved value of the register 34 in the preceding stage, the exclusive OR of the observed data and the saved value is taken and saved in the register 34. Thereafter, the same operation is repeated to save the observed data. Signature compressed. When SE = 1 and PE = 0, a shift register operation is performed and the signature compression result stored in the register 34 is output.

However, in the LFSR, if an indefinite value is input even in 1 cycle, the signature may be broken and may not match the simulation result. In particular, when signatures are generated by combining the outputs of functional units having different functions by LFSR, there is a problem that the output of an indefinite value from an unused functional block breaks the signature and does not match the simulation result.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to always perform normal signature generation even for an indefinite value output from an unused function block. An object of the present invention is to provide an observation register circuit capable of performing a failure analysis of an integrated circuit or the like easily and in a short time while securing high reliability, and a failure analysis test device using the circuit.

[0013]

In order to achieve the above object, a feature of the invention of claim 1 is a logic means for logically processing observation data and shift data, and a first means for storing an output of the logic means. Storage means, second storage means for storing the mask data input as the shift data, and gate means for inputting and blocking the observation data with the mask data stored by the second storage means. Is to do.

A second feature of the present invention is that, after the mask data is input to the first storage means, the data is stored in the second storage means.

A third feature of the present invention is that a register circuit group formed by serially connecting a plurality of register circuits for inputting output data of a non-scanning circuit as observation data,
Each of the non-scanning circuits is provided, these register circuit groups are connected in series, and either the output of the last register circuit of the last register circuit group or the mask data is selected and the first register circuit group is selected. Is provided with data selection means for inputting the data to the first register circuit.

According to a fourth feature of the present invention, the register circuit performs logic processing on the observation data and the shift data, and first storage means for storing the output of the logic means.
A second storage unit that stores the mask data input as the shift data; and a gate unit that inputs and blocks the observation data based on the mask data stored by the second storage unit. .

A feature of the invention of claim 5 is that the shift data input simultaneously with the observation data as the output data of the plurality of non-scanning circuits is logically processed and stored, and this stored data is output as the subsequent stage shift data. A failure analysis test apparatus having an observation register circuit group for compressing the signature of the observation data, comprising: input means for inputting the mask data as the shift data to the register circuit group; and A storage means for storing data and a gate means for inputting and shutting off the observation data based on the stored mask data are provided in each of the register circuits constituting the register circuit group.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the observation register circuit of the present invention. The observation register circuit inputs the outputs of the AND circuits 1 and 2 to the exclusive OR circuit 3, holds the output of the exclusive OR circuit 3 in the register 4, and outputs the output to one input of the AND circuit 1. AND circuit 5, which is connected to input and cut off observation data,
A selector 6 for selecting one of the output of the register 4 and the output of the register 7 and inputting it to the register 7;
Has a register 7 for storing the selected data, and an AND circuit 8 for generating a control signal for the selector 6.

Observation data is input to one input of the AND circuit 1, shift data is input to one input of the AND circuit 2,
Is inverted to the AND circuit 1 and input to one input of the AND circuit 8, and SE is inverted to the AND circuit 2 and input to the other input of the AND circuit 8. The output of the register 7 is input to the other input of the AND circuit 5.

FIG. 2 is a block diagram showing an embodiment in which the observation register circuit shown in FIG. 1 is arranged in an integrated circuit. I
L composed of a P macro unit 10, a memory 20, and an SC unit 30
When there is an SI or the like, the IP macro unit 10 and the memory 2
When 0 is a non-scanning unit and SC unit 30 is a scanning unit, the same observation register circuit 4 as that shown in FIG.
By arranging 0s as shown in the figure, an integrated circuit test can be effectively performed.

FIG. 3 is a block diagram showing an embodiment of a failure analysis test apparatus configured by connecting a plurality of observation register circuits shown in FIG. A plurality of observation register circuits 40a are connected between the non-scanned IP / macro unit 51 and the scanned SC unit 61, and the non-scanned IP / macro unit 52 and the scanned SC unit are connected. A plurality of observation register circuits 40b are connected between 62. The observation register circuit 40a is connected in series, and the first observation register circuit 40a is connected to the external input pin 100.
And an output of the exclusive OR circuit 82.

The observation register circuit 40b is also connected in series, the head of which is connected to the end of the observation register circuit 40a, and the tail of the observation register circuit 40b is the external output pin 2
00 and connected to one input of an exclusive OR circuit 81. The output of the exclusive OR circuit 81 is connected to one input of an exclusive OR circuit 82, and the other input of the exclusive OR circuit 82 is connected to an output in the middle of the observation register circuit 40b connected in series. I have. However, the observation register circuits 40a and 40b are the same,
It has the same configuration as the observation register circuit shown in FIG.

Next, the operation of this embodiment will be described.
In FIG. 1, the observation register circuit of the present example includes a register 7 for storing mask information in bits, and the AND of the value of the register 7 and observation data (Observed Data) is obtained by an AND circuit 5. Whether the observation data is input to the AND circuit 1 or is blocked.

First, assuming that SE = 1 and PE = 0, mask information is input as shift data from the AND circuit 2 to the register 4 through the exclusive logic circuit 3 (period t1 in FIG. 4). When the shift input of 1 bit is completed in all the observation register circuits, SE = 0 and PE = 0 are set for one cycle (period t2 in FIG. 4). As a result, the output of the AND circuit 8 becomes 1 during this one cycle, and the selector 6 selects the output of the register 4, so that the mask information of the register 4 is input to the register 7. After that, SE = 1, P
Since E = 1 (period t3 in FIG. 4), the selector 6 selects the output value of the register 7 and inputs it to the register 7. Therefore, the mask information is held in the register 7, and the mask information is stored in the AND circuit 5. To control the conduction and cutoff of the AND circuit 5.

Here, in FIG. 3, the IP macro section 5
1 and there is a possibility that an indefinite value will be output because the IP / macro section 52 is not used.
Must be operated, and the observation register circuit 40b must not be operated. In such a case, mask information such that 1 is held in the register 7 of the observation register circuit 40a and 0 is held in the register 7 of the observation register circuit 40b is sequentially input from the external input pin 100 to the first observation register circuit 40a. input.

As a result, since 1 is held in the register 7 of the observation register circuit 40a, the AND circuit 5 of the observation register circuit 40a conducts, and
Since 0 is held in the register 7 of 0b, the AND circuit 5 of the observation register circuit 40b is shut off. Therefore,
Observation data is input only to the observation register circuit 40a,
Since observation data is not input to the observation register circuit 40b, it is possible to prevent an indefinite value output from the IP / macro unit 52 from being taken into the observation register circuit 40b.

Therefore, the selector 70 starts from the next cycle.
Is switched to the exclusive logic circuit 82 side, in the observation register circuit 40a, when SE = 1 and PE = 1 (period t3 in FIG. 4), the observation data and the shift data are input to the exclusive OR circuit 3. , And the result is stored in the register 4. Since the shift data in the next cycle becomes the stored value of the register 4 of the observation register circuit of the preceding stage, an exclusive OR of this stored value and the observed data is stored in the register 4, and thereafter, the same operation is repeated. And signature compression (t3 period in FIG. 4).

When the necessary cycles have been fetched, the result of the signature compression is serially output from the external output pin 200 with SE = 1 and PE = 0 (period t4 in FIG. 4) and prepared in advance by simulation or the like. By comparing the data with the data, the presence or absence of a failure can be detected.

During this time, the observation register circuit 40b shuts off the AND circuit 5 and does not input an indefinite value from the IP / macro section 52.
The failure analysis of the macro unit 51 can be performed normally.
Similarly, when the IP / macro section 52 operates and an indefinite value appears from the IP / macro section 51, the mask information to be initially input is changed, and 0 is set in the register 7 of the observation register circuit 40a, If 1 is input to the register 7 of the circuit 40b, the observation register circuit 40a
Does not input an undefined value, the failure analysis of the IP / macro unit 52 can be performed normally by the observation register circuit 40b.

According to the present embodiment, the mask information
The test of the IP / macro unit 51 and the test of the IP / macro unit 52 can be performed separately without being affected by indefinite values. Therefore, it is not necessary to initialize unrelated blocks, and the test can be performed by focusing only on the circuit to be tested. In addition, even when the test is performed separately, the observation register circuit group 40a and the observation register circuit 40b group are connected, and the LSFR is a large loop.
It is possible to prevent aliasing (passing).

[0031]

As described above in detail, according to the present invention, by inputting the mask data, the output of the indefinite value from the unused functional block is prevented, and Signature can be normally compressed, and failure analysis of an integrated circuit or the like can be performed easily and in a short time while ensuring high reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an observation register circuit of the present invention.

FIG. 2 is a block diagram showing an embodiment in which the observation register circuit shown in FIG. 1 is arranged in an integrated circuit.

FIG. 3 is a block diagram showing an embodiment of a failure analysis test device according to the present invention.

FIG. 4 is a time chart illustrating an operation of the observation register circuit illustrated in FIG. 1;

FIG. 5 is a block diagram showing a configuration example of a conventional observation register circuit.

[Explanation of symbols]

 1, 2, 5, 8 AND circuit 3, 81, 82 Exclusive OR circuit 4, 7, 40a, 40b Register 6, 70 Selector 10, 51, 52 IP / macro unit 20 Memory 30, 61, 62 SC unit 40 Observation register circuit 100 External input pin 200 External output pin

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA01 AB20 AC08 AK14 AK15 5B048 AA20 CC20 DD05 9A001 BB05 JJ49 KK31 LL05

Claims (5)

[Claims] 1. A logic unit for logically processing observation data and shift data, a first storage unit for storing an output of the logic unit, and a second storage unit for storing mask data input as the shift data. And a gate circuit for inputting and shutting off the observation data based on the mask data stored by the second storage unit. 2. The register circuit according to claim 1, wherein the mask data is stored in the second storage unit after being input to the first storage unit. 3. A register circuit group formed by serially connecting a plurality of register circuits for inputting output data of a non-scanning circuit as observation data is provided for each of the non-scanning circuits. Data selection means for connecting in series, selecting either the output of the last register circuit of the last register circuit group or the mask data and inputting it to the first register circuit of the first register circuit group A failure analysis test device characterized by the following. 4. A register circuit for performing logical processing on observation data and shift data, first storage means for storing an output of the logic means, and second storage means for storing mask data input as the shift data. 4. The failure analysis test apparatus according to claim 3, further comprising a storage unit, and a gate unit configured to input and block the observation data based on the mask data stored by the second storage unit. 5. The shift data input simultaneously with the observation data, which is output data of a plurality of non-scanning circuits, is logically processed and stored, and the stored data is output as shift data at a subsequent stage, thereby obtaining the observation data. A failure analysis test apparatus having a register circuit group for compressing a signature, comprising: input means for inputting mask data as the shift data to the register circuit group; and storage means for storing the input mask data; and A fault analysis test apparatus, comprising: a gate means for inputting and shutting off the observation data in accordance with the stored mask data in each of the register circuits constituting the register circuit group.