JP2000228429A - Micro computer having flash memory and method of inspecting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the production time by reducing the number of manufacturing processes as a whole, improve the precision in inspection by reliably screening defective memory cells, and guarantee the operation speed over the entire product operation guarantee period. SOLUTION: In the wafer test process, a VT screening process Tp1 is performed in a state a UV elimination process has not been performed in the diffusion process. Consequently, defective chips containing a memory cell having an abnormally high threshold due to a charge-up damage during the diffusion process can be screened, and the number of processes can be reduced in the diffusion process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer equipped with a flash memory and a test method thereof.

[0002]

2. Description of the Related Art In recent years, computer systems for controlling and managing OA equipment, industrial equipment, and the like have been required to increase the processing speed. Microcomputers with embedded flash memory are manufactured and widely used.

An outline of an inspection method in a manufacturing process of the above-described conventional flash memory mixed microcomputer will be described below. FIG. 2 is a flowchart showing a conventional method for testing a microcomputer with a flash memory embedded therein. FIG.
, D1 is ultraviolet erasing (UV erasing) in the diffusion process
Tc1 is a threshold selection (VT selection) step of selecting memory cells that did not reach a normal threshold level in a threshold test on the flash memory unit after the UV erasing step D1.
Tc2 is a gate stress application and VT selection step of applying a high voltage to the control gates of all memory cells in the flash memory unit for a certain period of time to select a chip in which the threshold value of the memory cell has changed by an allowable value or more. Tc4 is an erasure test step for all memory cells in the flash memory section, Tc6 is a bake step of baking the wafer to be inspected in a baking furnace for a fixed time and at a constant temperature, and Tc7 is a bake step for all memory cells in the flash memory section. The VT selection and the microcomputer part test step of selecting chips whose memory cell threshold values have changed by an allowable value or more by the baking in the baking step Tc6 and performing an operation test of the microcomputer part. The above steps Tc1 to Tc7 are tested in a wafer form. Is a wafer test process performed.

Tc8 is an assembly process, Tc9, Tc9
c11 is an erase test step for all memory cells in the flash memory section, Tc10 is a write test step for all memory cells in the flash memory section, Tc12 is a burn-in step for the microcomputer section, and Tc13 is a burn-in step Tc.
This is a burn-in selection and operation speed test process for selecting a chip that does not operate normally due to the burn-in of c12 and testing the operation speed of the microcomputer unit.
Tc13 is an assembly test step in which a test is performed in the form of an assembly.

[0005] Among the above steps, the UV erasing step D1 includes:
The threshold value of the memory cell whose threshold value becomes abnormally high due to the charge-up of the memory cell in the implantation process or the etching process in the diffusion process is adjusted to an intrinsic threshold value before the gate stress is applied in the following process. In the VT selection step Tc1, chips that do not meet the intrinsic threshold value in the UV erasing step D1 are selected as abnormal products.

[0006] Gate stress application and VT selection step T
c2 indicates that all memory cells are erased and all memory cells are erased in order to select defective products in a charge gain (electrons are injected into the floating gate) mode due to defects in a tunnel oxide film constituting the memory cells. After a high voltage is applied to the control gate for a certain period of time, the thresholds of all the memory cells are tested, and if the thresholds rise above an allowable value, the cells are selected as defective.

In the baking step Tc6 and the VT selection step and the microcomputer section test step Tc7, the VT selection step includes a charge loss (floating gate) caused by a defect in a tunnel oxide film constituting a memory cell or an ONO film between a floating gate and a control gate. In order to select defective products in the mode where electrons are emitted from the memory cells, the memory cells are written and baked for a certain period of time and at a certain temperature (with electrons injected into the floating gate). The threshold value is tested, and if the threshold value falls below an allowable value, it is classified as defective.

The burn-in selecting step of the burn-in step Tc12 and the burn-in selecting and operating speed test step Tc13 is a burn-in step Tc12 in which the microcomputer section is accelerated at a high temperature and a high power supply voltage as a burn-in to the microcomputer section. Chips that have failed in normal operation due to device initial failure due to oxide film defects and the like are selected as defective products in a burn-in selection process of process Tc13.

[0009]

However, the above-described conventional method for testing a microcomputer with a flash memory embedded therein has the following problems. First, in the diffusion step, the threshold values of the memory cells are aligned in the UV erasing step D1, so that the V step, which is the first step in the wafer test step, is performed.
In the threshold test in the T selection step Tc1, there is a problem that it is not possible to select memory cells that have suffered charge-up damage in an implantation step, an etching step, or the like in a diffusion step. When a polyimide resin is applied to the chip surface in the diffusion step, the ultraviolet light does not pass through and the UV erasing step D1 is performed.
In this case, there is a problem that the above-described process flow cannot be used.

Second, since the gate stress applying step exists independently in the wafer test step as the gate stress applying and VT selecting step Tc2, there is a problem that the number of steps in the inspection step increases. In addition, since the gate stress application test in this gate stress application process is a short-time test within several seconds, it is necessary to increase the applied voltage in order to obtain the acceleration required for quality assurance. In addition, there is a problem that a failure occurs due to the gate stress application test itself.

Third, since the speed test of the microcomputer operation, which operates while accessing each memory cell of the flash memory unit, is not performed immediately after the above-described gate stress application test, the microcomputer is required to perform a speed test throughout the product operation guarantee period. There is a problem that the operation speed cannot be guaranteed. This is because, when the product is actually used in the market, the memory cell with a low threshold value erased in the flash memory section is read disturb (when data is read from the memory, the memory cell on the same word line as the memory cell to be read) is read. (The control gate of the memory cell becomes the word line potential at the time of reading, and enters the charge gain mode.), And the threshold increases, so that the current capability of the memory cell transistor is reduced and the read access time is delayed. It is because of that.

The present invention solves the above-mentioned conventional problems. The present invention can reduce the number of steps in the entire manufacturing process, shorten the production time, and provide a defect even when ultraviolet erasing is impossible. The present invention provides a flash memory-mixed microcomputer capable of surely selecting the memory cell that has become the above, improving the inspection accuracy, and guaranteeing the operation speed over the entire product operation guarantee period, and an inspection method thereof.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a microcomputer with embedded flash memory and a method of inspecting the same according to the present invention are characterized as follows. The first means includes a memory cell having a threshold value abnormally high due to charge-up damage in the diffusion step by performing the threshold selection step in the wafer test step without performing the ultraviolet erasing step in the diffusion step. It is characterized in that defective chips can be selected and the number of steps in the diffusion step is reduced.

The second means is to simultaneously activate the gate stress test mode of the flash memory section during the burn-in test mode of the microcomputer, so that the gate stress of the flash memory section is simultaneously applied during the burn-in step, By performing the operation speed test including the threshold selection, the gate stress application can be performed simultaneously with the burn-in process of the microcomputer, and the independent gate stress application process is omitted.

Further, the third means makes it possible to guarantee the operation speed over the entire product operation guarantee period by performing the speed test of the microcomputer operation which operates while accessing the flash memory immediately after the gate stress is applied. It is characterized by the following. As described above, the number of steps in the entire manufacturing process can be reduced to shorten the production time, and the inspection accuracy can be improved by reliably selecting defective memory cells even when ultraviolet erasing is not possible. The operation speed can be guaranteed over the entire product operation guarantee period.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A flash memory embedded microcomputer inspection method according to claim 1 of the present invention is manufactured through at least a diffusion step, a wafer test step, and an assembly test step as manufacturing steps. A method for testing a microcomputer with embedded flash memory in which a memory unit is added and embedded, wherein in the diffusing step, an ultraviolet ray erasing step for aligning thresholds of all the memory cells in the flash memory unit is not performed. A method of performing a threshold selection step for inspecting and selecting thresholds of all the memory cells in the wafer test step.

According to this method, the threshold value selecting step is performed in the wafer test step without performing the ultraviolet erasing step in the diffusion step, so that the memory cell having an abnormally high threshold value due to charge-up damage in the diffusion step And the number of steps in the diffusion step can be reduced. The inspection method for a flash memory mixed microcomputer according to claim 2, wherein the flash memory is manufactured through at least a diffusion step, a wafer test step, and an assembly test step as a manufacturing step, and a flash memory section is added to the microcomputer section and mixed. An inspection method of a memory embedded microcomputer, wherein in the assembly test step, a gate stress applying step for applying a voltage to gates of all memory cells of the flash memory unit, and a burn-in for burning in the microcomputer unit. And a step are performed simultaneously as one step.

The flash memory hybrid microcomputer according to the present invention is manufactured through at least a diffusion process, a wafer test process, and an assembly test process as a manufacturing process, and a flash memory in which a flash memory portion is added to a microcomputer portion is mounted. A memory embedded microcomputer, wherein in the assembly test step, a gate stress applying step for applying a voltage to the gates of all the memory cells of the flash memory section, and a burn-in step for burning in the microcomputer section are included. It is configured so that it can be performed simultaneously as one step.

According to the above method and configuration, the gate stress test mode of the flash memory unit is simultaneously activated in the burn-in test mode of the microcomputer. By performing the operation speed test including the threshold selection, the gate stress application can be performed simultaneously with the burn-in process of the microcomputer, and the independent gate stress application process is omitted.

According to a third aspect of the present invention, there is provided an inspection method for a flash memory embedded microcomputer, which is manufactured through at least a diffusion step, a wafer test step, and an assembly test step as a manufacturing step, and a flash memory section is added to the microcomputer section. A flash memory embedded microcomputer inspection method, wherein in the assembly test step, after performing a gate stress applying step for applying a voltage to the gates of all the memory cells of the flash memory section, A method for performing an operation speed test step for inspecting the operation speed will be described.

According to this method, the speed test of the microcomputer operation which operates while accessing the flash memory is performed immediately after the gate stress is applied, so that the operation speed can be guaranteed over the entire product operation guarantee period. Hereinafter, a microcomputer with embedded flash memory and an inspection method thereof according to an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a flowchart showing a method for testing a microcomputer with embedded flash memory according to the present embodiment.
In FIG. 1, Tp1 is a threshold value selection (V) that selects a memory cell having an abnormally high threshold without reaching a normal threshold level in a threshold test for the flash memory unit at the end of the diffusion process.
T selection) process, Tp3 and Tp5 are write test processes for all memory cells in the flash memory unit, Tp4 are erasure test processes for all memory cells in the flash memory unit, and Tp6 is a process in which a wafer to be inspected is baked in a baking furnace at a constant time and temperature. The baking process for baking, Tp7, is a VT screening and microcomputer testing process for selecting chips whose memory cell threshold value has changed by an allowable value or more by the baking in the baking process Tp6 and performing an operation test of the microcomputer. Steps Tp1 to Tp7 are wafer test steps in which a test is performed in a wafer form.

Further, Tp8 is an assembly process, Tp9, Tp
p11 is an erase test step for all memory cells in the flash memory section, Tp10 is a write test step for all memory cells in the flash memory section, and Tp12 is a burn-in for the microcomputer section and a high voltage for control gates of all memory cells in the flash memory section. Gate stress application and burn-in step for simultaneously applying a predetermined time for a predetermined time, and Tp13 is a burn-in process for selecting a chip that has failed to operate normally due to the burn-in process of the burn-in process Tp12 and a burn-in test for testing the operating speed of the microcomputer unit that operates while accessing the flash memory. And an operation speed test process. The above processes Tp9 to Tp13 are assembly test processes in which a test is performed in an assembly form.

Of the above steps, the VT sorting step Tp1
The chip containing a memory cell whose threshold value is abnormally high due to charge-up of the floating gate of the memory cell in the implantation step or the etching step in the diffusion step (determined as having suffered charge-up damage) is regarded as an abnormal product. Sort out. This charge-up damage
This is because it causes a charge gain mode and a charge loss mode.

In the baking step Tp6, the VT selection and the microcomputer section test step Tp7, the VT selection step includes:
To select defective products in a charge loss (emission of electrons from the floating gate) mode due to defects such as a tunnel oxide film or an ONO film between the floating gate and the control gate that constitute the memory cell, the memory cell is written. After baking for a certain period of time and at a certain temperature (by injecting electrons into the floating gate), the threshold value of the memory cell is tested, and if the threshold value falls below an allowable value, the memory cell is classified as defective. .

In the burn-in step of the gate stress application and burn-in step Tp12 and the burn-in selection step of the burn-in selection and operation speed test step Tp13, the microcomputer is accelerated at a high temperature and a high power supply voltage in the burn-in step. In the meantime, a chip which has failed to operate normally due to the initial failure of the device due to an oxide film defect of the MOS transistor is selected in a burn-in selection step.

In the gate stress application and burn-in process Tp12, the gate stress application process and the burn-in selection and operation speed test process in the operation speed test process Tp13 are performed by charging due to defects in the tunnel oxide film forming the memory cell. In order to select the defective operation speed due to the gain (electrons are injected into the floating gate) mode, the memory cells are erased, and the gate stress is applied to the control gates of all the memory cells in the flash memory section in the gate stress application process. After a high voltage is applied for a certain period of time, a speed test of a microcomputer operation that operates while accessing a memory cell of the flash memory unit is performed in an operation speed test step, and if the operation speed is out of an allowable range, it is selected as defective.

Gate stress application and burn-in step T
In the gate stress application step of p12, by applying a stress longer than the product operation guarantee period to the control gates of all the memory cells, the threshold value of the erased memory cells rises in the charge gain mode, and the memory cell transistors , The read access time of the memory cell data is reduced, and the operating speed of the microcomputer operating while accessing the flash memory is also reduced. Since the operation immediately after the gate stress application step can be regarded as equivalent to the lapse of the product operation assurance period, an operation speed test is performed at this time, and the chip whose operation speed is within the allowable range has an operation speed during the entire product operation assurance period. Guaranteed. Here, since the burn-in step and the gate stress applying step are simultaneously performed as one step in the step Tp12, the steps for the gate stress applying step which have been conventionally independent are shortened.

In this step Tp12, in order to perform the gate stress applying step and the burn-in step at the same time, the microcomputer incorporating the flash memory according to the present embodiment applies a voltage to the gates of all the memory cells of the flash memory section in the assembly test step. And a burn-in process for burning in the microcomputer unit.
It is configured so that it can be performed simultaneously as one step.

As described above, the number of steps in the entire manufacturing process can be reduced to shorten the production time. In addition, even when ultraviolet erasing is not possible, defective memory cells can be reliably selected and inspected. Accuracy can be improved, and operation speed can be guaranteed over the entire product operation guarantee period.

[0031]

As described above, according to the first aspect of the present invention, by performing the threshold selection step in the wafer test step without performing the ultraviolet erasing step in the diffusion step, the charge is increased in the diffusion step. It is possible to select a defective chip including a memory cell having an abnormally high threshold value due to damage, and to reduce the number of steps in a diffusion step.

According to the second and fourth aspects of the present invention, since the gate stress test mode of the flash memory section is simultaneously activated in the burn-in test mode of the microcomputer, the gate of the flash memory section is simultaneously activated in the burn-in step. After performing stress application, by performing an operation speed test including threshold selection after burn-in,
Gate stress application can be performed simultaneously with the burn-in process of the microcomputer, and an independent gate stress application process can be omitted.

In addition, since burn-in is usually performed for several hours, a long voltage application time can be secured, and an applied voltage for obtaining a required acceleration can be reduced, so that an applied voltage at the time of gate stress application can be reduced. Can be prevented from occurring due to the gate stress application test itself to which is applied. According to the third aspect of the present invention, the speed test of the microcomputer operation which operates while accessing the flash memory is performed immediately after the gate stress is applied, so that the operation speed can be guaranteed over the entire product operation guarantee period. It can be.

As described above, the number of steps in the entire manufacturing process can be reduced to shorten the production time, and the memory cells that have become defective even when the ultraviolet erasing cannot be performed can be reliably selected. The inspection accuracy can be improved, and the operation speed can be guaranteed over the entire product operation guarantee period.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an inspection method of a microcomputer with embedded flash memory according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a conventional flash memory embedded microcomputer inspection method.

[Explanation of symbols]

D1 Ultraviolet erasing (UV erasing) step Tc1, Tp1 Threshold selection (VT selection) step Tc2 Gate stress application and threshold selection (VT selection) step Tc3, Tp3 Write test step Tc4, Tp4 Erase test step Tc5, Tp5 Write test step Tc6, Tp6 Wafer baking (bake) process Tc7, Tp7 Threshold selection (VT selection) and microcomputer unit test process Tc8, Tp8 Assembly process Tc9, Tp9 Erase test process Tc10, Tp10 Write test process Tc11, Tp11 Erase test process Tc12 Burn-in process Tp12 Gate stress application and burn-in process Tc13, Tp13 Burn-in selection and operation speed test process

Claims (4)

[Claims] 1. A method of inspecting a flash memory embedded microcomputer which is manufactured through at least a diffusion step, a wafer test step, and an assembly test step as a manufacturing step, and a flash memory part is added to a microcomputer part and embedded therein. In the diffusion step, a threshold value for inspecting and selecting the threshold values of all the memory cells in the wafer test step without performing an ultraviolet ray erasing step for equalizing the threshold values of all the memory cells in the flash memory unit. An inspection method of a microcomputer with embedded flash memory, wherein a selection step is performed. 2. A method for inspecting a flash memory embedded microcomputer which is manufactured through at least a diffusion step, a wafer test step, and an assembly test step as a manufacturing step, and a flash memory section is added to the microcomputer section and mixed. In the assembly test process, a gate stress application process for applying a voltage to the gates of all the memory cells of the flash memory unit and a burn-in process for burning in the microcomputer unit are simultaneously performed as one process. Inspection method of microcomputer with embedded flash memory. 3. A method for inspecting a flash memory mixed microcomputer which is manufactured through at least a diffusion step, a wafer test step, and an assembly test step as a manufacturing step, and a flash memory section is added to a microcomputer section and mixed. In the assembly test process, after performing a gate stress applying process for applying a voltage to the gates of all the memory cells of the flash memory unit, an operating speed test process for inspecting the operating speed of the flash memory unit is performed. Inspection method of microcomputer with embedded flash memory. 4. A flash memory hybrid microcomputer which is manufactured through at least a diffusion process, a wafer test process, and an assembly test process as a manufacturing process, and has a flash memory unit added to a microcomputer unit and is mixedly mounted. In the test process, a gate stress applying process for applying a voltage to the gates of all the memory cells of the flash memory unit and a burn-in process for burning in the microcomputer unit are simultaneously performed as one process. A microcontroller with embedded flash memory, characterized in that it is configured to be able to do so.