KR19990086841A - How to erase flash memory device - Google Patents

Abstract

The erase method according to the present invention comprises the steps of determining whether the erase step, the erase verify step, and the number of erase fail memory cells exceed the maximum fail allowance, and when the number of erase fail memory cells does not exceed the maximum fail allowance, Determining whether the erase-verified memory cell is a final verification target memory cell; when the verified memory cell is not the last verification target memory cell, erasing verification of a next target memory cell of the memory cell; When the number of memory cells exceeds the maximum fail tolerance and the erase operation time is equal to the erase operation maximum time, determining an erase fail and the number of erase failed memory cells do not exceed the maximum fail tolerance and erase operation When the time is not equal to the erase operation maximum time, the erase Is small is performed in the order of steps to continue.

Description

METHOD FOR ERASING OF FLASH MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory devices, and more particularly to a method of erasing a flash memory device.

1 is a cross-sectional view of a typical flash memory cell. Referring to FIG. 1, a flash memory cell includes a current pass formed between a source 3 and a drain 4 on a semiconductor substrate 2, and insulating layers 7 and 9 on the semiconductor substrate 2. And a floating gate 9 and a control gate 8 connected therebetween. The program operation of the memory cell grounds the source region 3 and the semiconductor substrate, that is, the bulk region 2, and applies a positive high voltage (10V) to the control gate 8 as shown in the following table. And by applying a voltage (5 to 6V) for programming to the drain (4) to generate hot carriers. The hot carriers accumulate electrons in the bulk region 2 in the floating gate 6 by an electric field of the high voltage 10V applied to the control gate 8, and the drain region 4. The voltages supplied to () continue to accumulate.

In the erase operation of the flash memory cell, a negative high voltage (-10V) is applied to the control gate 8 and a predetermined voltage (5V) is applied to the bulk region 2 as shown in the following table. By generating FN tunneling, FN tunneling is performed simultaneously in sectors sharing the bulk region 2. The FN tunneling releases the electrons accumulated in the floating gate 6 into the source region 3 so that the memory cells have an erase threshold voltage distribution from about '1V' to '3V'. To have. The cell in which the threshold voltage is increased by the program operation appears to be off because a current is prevented from being injected from the drain region 4 to the source region 3 during a read operation. The cell in which the threshold voltage is lowered by the erase operation appears to be turned on with current injected from the drain region 4 into the source region 3.

Table

Operation mode Vg Vd Vs Vb Program + 10V + 5V to + 6V 0 V 0 V Cattle -10V Floating Floating + 6V Sojeong Chung + 3V + 5V to + 6V 0 V 0 V Reading + 4.5V + 1V 0 V 0 V

Since the memory cells are configured to share the bulk area 2 for high integration in the configuration of a flash memory array, the memory cells included in one sector are erased simultaneously. In this case, when the memory cells of the sector are simultaneously erased, some of the memory cells may be out of the erase threshold voltage range (1 to 3V) due to uniformity with respect to the threshold voltage. Among the cells outside the erase threshold voltage range, memory cells having a threshold voltage less than or equal to '0 V' are called over erase memory cells, and a threshold voltage is distributed within the erase threshold voltage range for them. A series of over erase repairs must be performed.

The read operation of the memory cells may ground the source region 3 and the bulk region 2, apply a predetermined voltage (4.5V) to the control gate 8, and drain the drain region as shown in Table 1 above. This is performed by applying a predetermined voltage 1V to the terminal 4. The over erase recovery operation of the over erased memory cells grounds the source region 3 and the bulk region 2, applies a predetermined voltage (3V) to the control gate 8, as shown in the table above. This is performed by applying a predetermined voltage (5V to 6V) to the drain terminal 4. The erased memory cell may cause a failure of the memory cells normally erased in the read operation.

2 is a diagram illustrating a threshold voltage distribution of a memory cell according to program and erase operations.

Referring to FIG. 2, the erase operation is caused by the programmed voltage of each of the memory cells and characteristics of the devices during the erase operation and the program operation. The over-erasing occurs because a negative high voltage (-10V) is applied to the control gate 8 for a predetermined time and the erase operation is performed, whereby the electrons are accumulated in the floating gates 6 of the memory cells differently. do. The non-uniform thickness of the insulating layer 7 between the bulk region 2 and the floating gate 6 causes the floating gate 6 of the memory cells during the FN tunneling of the erase operation. These electrons are accumulated differently in the field. As a result, over erase occurs when the threshold voltages of the memory cells that are erased during the erase operation are lowered below '0 V'.

3 is a flow chart for a general erase operation of a NOR flash memory cell.

Referring to FIG. 3, a general erase method of a NOR flash memory cell initializes an address counter for counting an address for designating each of the memory cells and a pulse counter for counting a pulse for specifying an erase time of an erase operation ( S105). When the address counter and the pulse counter are initialized (S105), an erase operation of the memory cells is performed (S110). The erase operation is performed in units of sectors to which the bulk 2 shared by the memory cells is a reference. As a result, each of the threshold voltages of the memory cells is distributed within the erase threshold voltage range.

After the erase operation S110, whether the respective threshold voltages of the memory cells is lower than the maximum voltage of the erase threshold voltage range is verified, and verification data is output (S115). After the erase verification step S115, it is determined whether all of the verification data are '0' (S120). When the verification data are all '0', the threshold voltages of the memory cells are distributed lower than the maximum voltage. When at least one of the verification data is '1', the threshold voltage of at least one memory cell is distributed higher than the maximum voltage.

If all of the verification data are '0', it is determined whether the address value counted by the address counter in the erase verification operation is the same as the last address value (S125). When the address value is the same as the last address value, it indicates that the erase operation and the erase verify operation of the memory cell are completed, and the erase operation is terminated. If the address value is smaller than the final address value, it means that there are unvalidated cells among the memory cells. Therefore, by counting '1' to the address value (S130), the memory cell corresponding to the counted address is counted. An erase verification operation (S115) is performed. If at least one of the verification data is '1', it is verified whether the pulse count value indicating the erase operation time is the same as the maximum pulse count value (S135). When the pulse count value and the maximum pulse count value are the same, it means that the erase operation time has been exceeded, and thus the erase operation becomes a fail (S145). When the pulse count value is smaller than the maximum pulse count value, it means that the erase operation time is insufficient, and counts '1' to the pulse value (S140) to perform the erase operation (S110) again.

When an erase operation is performed, there may be a case in which a memory cell is not erased by a defect. The defect of the memory cell occurs when the drain terminal 4 is cut and when the drain terminal 4 and the control gate 8 of the memory cell are not insulated. In the case where the defective memory cell exists, in the conventional erase method, the erase operation of the defective memory cells is not completed until the pulse value is equal to the pulse maximum value, that is, the erase operation time is exceeded. Since the erase operation time is exceeded by the defective cell during the erase operation, an over erasure occurs in which the threshold voltages of the memory cells in which the defect does not occur are distributed below '0 V'. There is a problem in that the erase time due to the over erasure increases and the time for recovering the over erased memory cells increases.

Accordingly, an object of the present invention is to provide an erase method of a flash memory device which prevents over erasing of memory cells during an erase operation.

1 is a cross-sectional view of a typical flash memory cell;

2 is a diagram illustrating a threshold voltage distribution of a memory cell according to program and erase operations;

3 is a flow chart for an erase operation of a typical NOR flash memory cell; And

4 is a flowchart for an erase operation of the NOR flash memory cell of the present invention.

(Configuration)

According to one aspect of the present invention for achieving the above object, an erase method of a flash memory device includes the step of making each discharge voltage of the memory cells have a predetermined erase threshold voltage distribution and each discharge of the memory cells; Verifying whether a solder voltage is lower than a maximum voltage in the erase threshold voltage distribution; Determining whether the number of erase fail memory cells of which the memory voltage of the memory cells is higher than the maximum voltage exceeds a maximum fail tolerance; When the number of erase-failed memory cells does not exceed the maximum fail tolerance, determining whether the erase-verified memory cell is the last verified memory cell and when the verified memory cell is not the last verified memory cell. Erasing and verifying a next target memory cell of the memory cell; Determining whether an erase operation time is equal to an erase operation maximum time by determining whether an erase operation time is equal to an erase operation maximum time when the number of erase fail memory cells exceeds the maximum fail tolerance, and determining an erase fail when the erase operation time is equal to an erase operation maximum time; and Continuing the erase operation when the number of erase failed memory cells does not exceed the maximum fail tolerance and the erase operation time is not equal to the erase operation maximum time.

(Action)

By this method, by failing defective memory cells, it is possible to prevent over erasure of memory cells in which defects have not occurred.

(Example)

Hereinafter, the present invention will be described in detail with reference to FIG. 4.

4 sequentially illustrates the erase operation of the NOR flash memory device of the present invention.

Referring to FIG. 4, the erase method of the flash memory device may include initializing a pulse counter (S205), initializing an address counter and a fail counter (S210), an erase step (S215), an erase verification step (S220), and data. A determination step (S225), a step of counting up a fail count value (S226), a step of determining whether a fail count value exceeds a fail maximum count value (S227), and a step of determining whether an address count value and a final address value are the same. (S230), the step of up counting the address counter (S235), the step of determining whether the pulse count value and the maximum pulse count value is the same (S240) and the step of up counting the pulse counter (S245).

In the erasing method of the present invention, a pulse counter informing the erasing operation time is initialized (S205). After the pulse counter is initialized (S205), an address counter that counts addresses input to designate each of the memory cells and a fail counter that counts erased fail memory cells during the erase operation are initialized (S210). Thereafter, an erase operation of the memory cells is performed (S215). The erase operation is performed in a unit of a sector in which the bulk 2 shared by the memory cells is a reference, and respective dress voltages of the memory cells are distributed within the erase dress voltage range (1V to 3V).

After the erase operation (S215), it is verified whether each of the threshold voltages of the memory cells is lower than the maximum voltage (3V) of the erase threshold voltage range, and the verification data is output (S220). Then, it is determined whether all of the verification data are '0' (S225). When the verification data are all '0', the threshold voltages of the memory cells are distributed lower than the maximum voltage. At least one verification data of the verification data is '1' indicating that at least one threshold voltage of the threshold voltages of the memory cells is distributed higher than the maximum voltage.

If the verification data is '1', an up count operation in which the fail counter counts '1' to the fail count value is performed (S226). It is determined whether the up counted fail count value is greater than the maximum fail tolerance value (S227). When the fail count value is smaller than the maximum fail allowance value, it is determined whether the address count value is the same as the last address value (S230). When the address count value is smaller than the last address value, an up count operation of counting '1' to the address count value is performed (S235). When the up count operation is performed, verification is performed on a memory cell corresponding to the up counted address (S220). When the address count value and the last address value are the same, the erase operation is terminated.

When the fail count value is larger than the maximum fail tolerance, it means that the defective memory cells exceed a predetermined number of defective memory cells. When the pulse count value and the maximum fail allowance value are the same, an erase operation of the memory cells indicates a fail (S240). If the fail count value is smaller than the maximum fail allowable value, the erase operation time is insufficient. Thus, the address counter and the fail counter are initialized again by counting '1' to the fail count value (S210) and again. Operation S215 is performed. According to the above-described method of erasing a flash memory, when a defective cell exists below the maximum fail tolerance in an erase operation, the defective cell is failed. Therefore, it is possible to prevent the predetermined erase operation time from exceeding, and to prevent the over erasing of the memory cells caused by the defective cells. As a result, the erase operation time is reduced than before, and the repair operation time of the over erased memory cells is also reduced.

As described above, the erase operation time can be reduced by failing the defective memory cells to prevent over erasing of the defective memory cells.

Claims (1)

In a method of erasing a flash memory device: Causing each threshold voltage of the memory cells to have a predetermined erase threshold voltage distribution; Verifying that each threshold voltage of the memory cells is lower than a maximum voltage in the erase threshold voltage distribution; Determining whether the number of erase fail memory cells of which the memory voltage of the memory cells is higher than the maximum voltage exceeds a maximum fail tolerance; When the number of erase fail memory cells does not exceed the maximum fail tolerance, determining whether the erase verified memory cell is the last memory cell to be verified; Verifying a next target memory cell of the memory cell when the verified memory cell is not the last verification target memory cell; Determining whether an erase operation time is equal to an erase operation maximum time by determining whether an erase operation time is equal to an erase operation maximum time when the number of erase fail memory cells exceeds the maximum fail tolerance, and determining an erase fail when the erase operation time is equal to an erase operation maximum time; and ; Continuing the erase operation when the number of erase failed memory cells does not exceed the maximum fail tolerance and the erase operation time is not equal to the erase operation maximum time.