JP2000222892A - Threshold value control method and screening method for semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a rewritable semiconductor memory in which a cell of degraded reliability can be detected accurately with low stress in a short time. SOLUTION: In a semiconductor memory comprising a plurality of electrically writable and erasable memory cells as a memory medium, the voltage and/or the pulse width is controlled at the time of writing such that the threshold voltage distribution width is decreased after writing in the plurality of memory cells. Information of various threshold value distributions before application of stress for screening is written for each device and it is compared with remeasurements taken after application of stress thus sorting the good from the bad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a threshold control method and a screening method for a semiconductor memory device having a floating gate and a control gate and capable of writing and erasing data.

[0002]

2. Description of the Related Art A floating gate for storing charges is formed on a semiconductor substrate via a first insulating film, and a control gate is formed on the floating gate via a second insulating film. By forming source / drain regions on the substrate on both sides of the floating gate, electrically writable and erasable memory cells are formed. Further, by arranging the memory cells in a matrix, the memory cell A non-volatile semiconductor storage device using a storage medium as a storage medium is known. In such a non-volatile semiconductor memory device, the amount of change in the threshold voltage due to the neglected stress of each memory cell charge amount stored in the floating gate after writing, the voltage stress of the control gate, or the voltage stress of the drain is guaranteed. If there is one or more memory cells that do not satisfy the condition, the semiconductor storage device has poor reliability.

Therefore, a memory cell in which the amount of change in the threshold voltage due to the standing stress of the charge amount of each memory cell stored in the floating gate after writing, the voltage stress of the control gate, or the voltage stress of the drain does not satisfy the guarantee criterion. When one or more exists, screening at the time of examination is required.

A method that has been widely used in the past as a method for determining and screening for the existence of a memory cell that does not satisfy such a guarantee criterion is described below.

FIG. 7 shows a flow of a conventional inspection process for screening a nonvolatile semiconductor memory device for defective reliability.

In this conventional inspection process, the voltage V at the time of writing for a plurality of memory cells to be screened is
DD and the write pulse width tPW are, for example, VDD =
A, Step 1 for setting tPW = B, Step 2 for writing to the plurality of memory cells, and Applying a leaving stress, a voltage stress of a control gate, or a voltage stress of a drain to the plurality of memory cells Step 2
1 and a step 60 of determining whether the threshold voltage after the application of the stress is distributed above the reference value. If there is at least one bit or more of memory cells that are defective (NG) in the process 60 when a leaving stress is applied, it is regarded that the amount of charge stored in the floating gate has changed, and is determined to be defective. judge.

The content of the applied stress in step 21 differs depending on the purpose of the screening, but the determination method is the same.

[0008]

However, such a conventional method for screening for poor reliability has the following problems.

FIG. 8 shows a threshold distribution of a plurality of memory cells to be screened in a conventional screening method.

Here, the threshold voltage distribution 70 after a normal write for a plurality of memory cells to be screened becomes a write level 71 or more and,
2 is distributed. The write level 71 and the threshold voltage distribution width 72 change for each rewrite, and the threshold voltage after write for each rewrite is not reproduced even in memory cell units. For this reason, in one screening test, it is determined whether or not there is a memory cell in which the charge amount of the floating gate changes, that is, whether or not there is a reliability-degraded cell.
In order to detect at any level, it is necessary to take measures to detect any deterioration of the threshold distribution state 70 after this writing, at every rewriting of the reliability-deteriorated cell. In FIG. 8, reference numerals 73, 74, 75, and 76 denote the permissible fluctuation amounts of the threshold when stress is applied, and the permissible fluctuation amounts 73, 74, 75, and 76 have a level difference as shown. Exists. For this reason, it is necessary to perform screening with an excessive acceleration stress longer than the product guarantee stress time in consideration of the worst-case variation allowable amount 76, the variation of the write level for each rewrite, and the variation of the threshold voltage distribution width for each rewrite. Become.

As a result, it takes time to apply the stress in the screening, which increases the inspection time and the inspection cost. Further, there is a problem that an excessive stress causes an increase in a defective rate, and furthermore, an excessive stress damage is given to a non-defective product at the time of inspection, so that the original ability is impaired.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to make it possible to accurately detect a reliability-reduced cell in a short time and with low stress.

[0013]

SUMMARY OF THE INVENTION In order to achieve this object, the present invention relates to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium. The voltage at the time of writing and / or the pulse width are controlled so as to reduce the threshold voltage distribution width.

Thus, the threshold voltage distribution after writing can be suppressed to a smaller width than the threshold voltage distribution during normal writing.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of controlling a threshold value of a semiconductor memory device according to the present invention is directed to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium. The voltage and / or pulse width at the time of writing is controlled so as to reduce the threshold voltage distribution width.

In this way, the threshold voltage distribution after writing can be suppressed to a smaller width than the threshold voltage distribution during normal writing.

Further, according to the threshold control method for a semiconductor memory device of the present invention, a step of setting a voltage and a pulse width at the time of writing, a step of performing writing to a plurality of memory cells, and a step of performing writing to the plurality of memory cells are performed. Determining whether the threshold voltage distribution after writing is less than a predetermined distribution width; and, if the threshold voltage distribution is not less than the distribution width, once erasing the plurality of memory cells; To reduce the threshold voltage distribution width after writing of the cell, the voltage at the time of writing after once erasing and / or the pulse width is set to the voltage at the time of previous writing and
Alternatively, it is provided with a step of changing the pulse width and writing again.

In this case, the threshold voltage distribution after writing can be suppressed to a smaller width than the threshold voltage distribution during normal writing.

In the step of writing data to a plurality of memory cells at the time of screening, by performing writing with this configuration, it is possible to detect a reliability-reduced cell in a shorter time and with lower stress than in the conventional method.

That is, the method of screening a semiconductor memory device according to the present invention comprises the steps of: setting a voltage and a pulse width at the time of writing to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium; Performing writing to the plurality of memory cells; determining whether a threshold voltage distribution after writing to the plurality of memory cells is smaller than a predetermined distribution width; If the distribution width is not less than the step of once erasing the plurality of memory cells, and to reduce the threshold voltage distribution width after writing of the plurality of memory cells,
A step of changing the voltage and / or pulse width at the time of writing after once erasing compared to the voltage and / or pulse width at the time of previous writing, and writing again; and a threshold after writing to the plurality of memory cells. When the voltage distribution is less than the predetermined distribution width, writing information obtained by measuring the upper limit value and the lower limit value in the threshold voltage distribution after the writing to a memory cell other than the plurality of memory cells; and Applying stress to the
The upper limit value and the lower limit value of the threshold voltage distribution are measured again after the application of the stress, and the measured upper limit value and the lower limit value are written to memory cells other than the plurality of memory cells before the stress is applied. A step of classifying non-defective products and non-defective products by comparing information on the upper limit value and the lower limit value of the value voltage distribution.

This makes it possible to detect the reliability-degraded cells in a shorter time and with a lower stress, and it is possible to eliminate an increase in the defective rate due to the excessive stress.

The screening method of a semiconductor memory device according to the present invention further comprises the steps of: setting a voltage and a pulse width when writing to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium; A step of performing writing to the plurality of memory cells, a step of measuring the upper limit value and the lower limit value of the threshold voltage distribution after the writing of the plurality of memory cells, and information of the measured upper limit value and lower limit value. A step of writing to memory cells other than the plurality of memory cells, a step of applying stress to the plurality of memory cells, and measuring the upper limit value and the lower limit value of the threshold voltage distribution again after the application of the stress. The upper limit value and the lower limit value of the threshold voltage distribution written in the memory cells other than the plurality of memory cells before the stress application are described. Compared to, those where the structure and a step of classifying the molded product is good or defective.

This makes it possible to detect the reliability-degraded cells in a short time and with a low stress, and it is possible to eliminate an increase in the defective rate due to the excessive stress.

The screening method of a semiconductor memory device according to the present invention further comprises the steps of: setting a voltage and a pulse width when writing to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium; A step of performing writing to the plurality of memory cells and, after the writing step, measuring the number of memory cells for each threshold value a plurality of times in the threshold voltage distribution range while changing the threshold value A step of writing information measured in the measuring step to memory cells other than the plurality of memory cells, and a step of applying a stress to the plurality of memory cells;
After the application of the stress, a step of measuring the number of memory cells for each threshold value a plurality of times again by changing the threshold value in the distribution range of the threshold voltage; Comparing the number of memory cells with information written in memory cells other than the plurality of memory cells before applying the stress to classify non-defective products and defective products.

This makes it possible to detect the reliability-deteriorated cells in a short time and with low stress, and it is possible to eliminate the increase in the defective rate due to excessive stress.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

The semiconductor memory device to which the present invention is directed is a semiconductor memory device in which memory cells as electrically writable and erasable storage media are arranged in a matrix. A floating gate formed thereon via a first insulating film to accumulate electric charges; a control gate formed on the floating gate via a second insulating film; and a control gate formed on both sides of the floating gate. The structure includes a source / drain region formed on a substrate.

FIG. 1 shows a write process flow in the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a voltage VDD and a write pulse width t during writing with respect to a plurality of memory cells to be screened.
PW is set to, for example, VDD = A and tPW = B. Step 2 is a step of writing data into a plurality of memory cells to be screened. 3 is a step of externally reading and judging whether or not the threshold voltage distribution after writing of the plurality of memory cells is equal to or smaller than an arbitrary distribution width. The maximum threshold voltage Vtmax and the minimum threshold voltage Vtmi
It is determined whether or not the difference from n is less than a fixed value C. 4
Is a step of temporarily erasing the plurality of memory cells. Step 5 is a step 5 of changing the voltage and / or pulse width when rewriting is performed after erasing in step 4 with respect to the voltage and / or pulse width at the previous writing.

The operation of the above-structured writing process flow will be described below.

First, in step 1, the voltage V at the time of writing is
DD and the write pulse width tPW are initialized (VDD =
A, tPW = B), and in step 2, writing to a plurality of memory cells to be screened is performed using the initially set voltage and write pulse width. Next, in step 3, it is read and determined whether or not the distribution of the threshold voltages after writing in the plurality of memory cells is smaller than a predetermined distribution width C. If it is not smaller than the required threshold voltage distribution width C, the plurality of memory cells are temporarily erased in step 4. Then, in step 5, the convergence of the threshold voltage distribution after writing is checked in step 2.
In order to increase the voltage and / or pulse width at the time of the previous writing, the voltage and / or the pulse width at the time of the previous writing are changed and reset. Then, returning to the step 2, the writing to the memory cells to be screened is performed again. By repeating this series of operations until the threshold voltage distribution width becomes smaller than the arbitrary threshold voltage distribution width C, the threshold voltage distribution after writing of the plurality of memory cells is suppressed to less than the arbitrary distribution width C.

FIG. 2 shows that a plurality of memory cells to be screened become smaller than the threshold voltage distribution width C after three times of writing by the writing process flow of FIG. 1 according to the embodiment of the present invention. Is shown as an example. In FIG. 2, reference numeral 10 denotes a write operation (step 2) with an initial setting voltage and a write pulse width, and 11
Shows the threshold distribution after writing at the initial setting voltage and writing pulse width. At this stage, the threshold distribution 1
No. 1 has not yet satisfied the condition of being less than the arbitrary distribution width C. Therefore, the state is returned to the erased state 18 once by the erase operation 12 corresponding to the step 4. Then, the voltage and / or pulse width at the time of the next writing is changed and reset with respect to the voltage and / or pulse width at the time of the previous writing (Step 5), and the flow returns to Step 2 to perform the writing 13 again. However, since the resulting threshold distribution 14 does not yet satisfy the condition that the distribution width is smaller than the arbitrary distribution width C, the threshold distribution 14 is returned to the erased state 18 by the erase operation 15 again. Next, the voltage and / or pulse width at the time of writing is changed three times with respect to the voltage and / or pulse width at the time of previous writing, and writing 16 is performed. As a result, the threshold distribution 17 satisfies the condition that it is less than an arbitrary distribution width C.

As described above, according to the present embodiment, the step 5 of changing the voltage and / or the pulse width at the time of rewriting after erasing to the voltage and / or the pulse width at the time of the previous writing and resetting is performed. Is provided, the threshold voltage distribution after the rewriting can be suppressed to a width smaller than that in the normal writing.

Further, by using the writing method according to the present embodiment, it is possible to detect the reliability-deteriorated cells in a short time and with low stress at the time of screening.

FIG. 3 shows an inspection process flow for screening for a reliability failure based on the second embodiment of the present invention. In FIG. 3, reference numeral 1 denotes a step of setting a write voltage and a write pulse width;
Is a step of performing writing to a plurality of memory cells to be screened; and 3 is a step of externally reading and determining whether or not the threshold voltage distribution after writing of the plurality of memory cells is smaller than an arbitrary distribution width C. Is a step of once erasing the plurality of memory cells, and 5 is a step of changing the voltage and / or pulse width at the time of writing according to the voltage and / or pulse width at the time of previous writing. The above is the same as the configuration of FIG. Things.

The following steps are different from the configuration shown in FIG. That is, reference numeral 20 denotes an upper limit value Vtmax and a lower limit value Vtmi of the threshold voltage distribution after writing when the threshold voltage distribution is equal to or more than an arbitrary distribution width C in step 3.
This is a step of writing information obtained by measuring n into memory cells other than the plurality of memory cells. Reference numeral 21 denotes a step of applying a leaving stress, a control gate voltage stress, or a drain voltage stress to the plurality of memory cells to which writing has been performed as described above. 22 is the upper limit value Vtmax of the threshold voltage distribution again after the application of the stress.
And the step of measuring the lower limit value Vtmin. And 2
3 is the information of the upper limit value Vtmax and the lower limit value Vtmin of the threshold voltage distribution written in the memory cells other than the plurality of memory cells in the step 20 before the application of the stress, and the information in the step 22 again after the stress is applied. This is a step of comparing the measurement results of the upper limit value Vtmax and the lower limit value Vtmin of the threshold voltage distribution to classify non-defective products and defective products.

The operation of the inspection process flow for screening for the reliability failure configured as described above will be described below.

First, in step 1, the voltage V at the time of writing is
DD and the write pulse width tPW are initialized (VDD =
A, tPW = B), and in step 2, writing is performed on a plurality of memory cells to be screened with the initially set voltage and write pulse width. Next, in step 3, it is read and determined whether or not the threshold voltage distribution after writing of the plurality of memory cells is smaller than a predetermined distribution width C. If the threshold voltage distribution width is not less than the arbitrary threshold voltage distribution width C, the plurality of memory cells are once erased in step 4, and in step 5, the convergence of the threshold voltage distribution after further writing than in the previous writing is improved. , The voltage and / or pulse width at the time of writing is changed with respect to the voltage and / or pulse width at the time of previous writing and reset. Then, in step 2, rewriting of the plurality of memory cells to be screened is performed. Also,
By repeating this operation until the threshold voltage distribution width becomes smaller than the arbitrary threshold voltage distribution width C, the threshold voltage distribution after writing of the plurality of memory cells is suppressed to less than the arbitrary distribution width C.
The above is the same as the operation of the above-described first embodiment.

Next, in step 20, the upper limit value Vtmax and the lower limit value Vtm of the threshold voltage distribution of the plurality of memory cells are obtained.
The information obtained by measuring "in" is written to memory cells other than the plurality of memory cells. Then, in step 21, a leaving stress, a control gate voltage stress, or a drain voltage stress is applied to the plurality of memory cells. Then, in step 22, the upper limit value Vtmax and the lower limit value Vtmin of the threshold voltage distribution are measured again.
Finally, in step 23, the information of the upper limit and lower limit of the threshold voltage distribution written in the memory cells other than the plurality of memory cells before the application of the stress, and the upper limit of the threshold voltage distribution again after the stress. By comparing the result of the measurement with the lower limit value, the amount of change in the threshold value due to the change in the charge stored in the floating gate is determined and screened.

FIG. 4 shows a threshold distribution after writing of a plurality of memory cells to be screened in the process of FIG. 3 and a determination method after stress is applied. In FIG. 4, reference numeral 17 denotes a threshold voltage distribution after writing is performed based on steps 1 to 5 in FIG. 3, which is similar to that shown in FIG. Where 3
1 is the writing distribution lower limit, and 32 is the writing distribution upper limit. Reference numeral 30 denotes a judgment level that is acceptable even if the charge stored in the floating gate changes after the stress is applied and the threshold value fluctuates. Reference numeral 33 denotes a threshold variation allowable amount when the charge stored in the floating gate changes due to the application of the stress.

As described above, according to the present embodiment, by providing the step 5 of changing the voltage and / or pulse width at the time of writing to the voltage and / or pulse width at the time of previous writing and resetting it. The threshold voltage distribution after writing is suppressed to a width smaller than that at the time of normal writing, and the upper limit value and lower limit value of the threshold voltage distribution before stress application are stored for each sample, so that the upper limit value before and after stress application and By screening by comparing the lower limit values, it is possible to accurately detect the reliability-degraded cells in a short time and with low stress, and it is possible to eliminate an increase in the defective rate due to excessive stress.

FIG. 5 shows a flow of an inspection process for screening for reliability failure based on the third embodiment of the present invention. In FIG. 5, 1 is a step of setting a voltage and a pulse width at the time of writing, and 2 is a step of writing a plurality of memory cells to be screened, which are steps shown in FIGS. Is similar to Step 40 is a step of measuring the number Vt of memory cells for each threshold value a plurality of times in the distribution range of the threshold voltage by changing the threshold value after the writing of the plurality of memory cells. Step 41 is a step of writing the information measured in step 40 to memory cells other than the plurality of memory cells.

Step 21 is a step of applying a leaving stress, a control gate voltage stress, or a drain voltage stress to the plurality of memory cells. 42 is
After the stress is applied in step 21, the number Vt of memory cells for each threshold value is again measured a plurality of times by changing the threshold value in the threshold voltage distribution range. 43 is a step of comparing the information written in the memory cells other than the plurality of memory cells before the application of the stress with the result of measuring the number of memory cells again after the application of the stress to classify non-defective products and defective products. is there.

The operation of the inspection process flow for screening for the reliability failure configured as described above will be described below.

First, in step 1, the voltage V at the time of writing is
DD and the write pulse width tPW are initialized (VDD =
A, tPW = B), and in step 2, writing is performed on a plurality of memory cells to be screened with the initially set voltage and write pulse width. Next, in step 40, in the threshold voltage distribution range after writing of the plurality of memory cells, the number Vt of memory cells for each threshold value
Is measured a plurality of times while changing the threshold value. Then, in step 41, the measured information is written into memory cells other than the plurality of memory cells.

Next, in step 21, after applying a leaving stress, a control gate voltage stress, or a drain voltage stress to the plurality of memory cells,
In step 42, the number Vt of memory cells for each threshold value is measured a plurality of times in the threshold voltage distribution range while changing the threshold value. Further, in step 43, the number of memory cells for each threshold value written in the memory cells other than the plurality of memory cells before the stress application is changed plural times by changing the threshold value, and the threshold value is again measured after the stress application. The number of memory cells for each value is measured a plurality of times while changing the threshold value, and the result is compared with the result of the threshold value change amount due to the change in the charge stored in the floating gate to perform screening.

FIG. 6 shows a threshold distribution after writing in a plurality of memory cells to be screened and a determination method after stress application in the process of FIG. In FIG. 6, reference numeral 50 denotes a threshold voltage distribution after writing, and reference numeral 51 denotes a threshold fluctuation amount allowed when the charge stored in the floating gate changes after stress is applied.

As described above, according to the present embodiment, the number of memory cells Vt for each threshold value is measured a plurality of times while changing the threshold value in the threshold voltage distribution range before the application of stress. The information can be stored for each sample, and the number of memory cells for each threshold value before and after stress application can be compared for screening. By doing so, it is not necessary to control the threshold value at the time of writing, so that it is possible to accurately detect the reliability-degraded cells in a short time and with low stress, and to eliminate an increase in the defective rate due to excessive stress. it can.

In the second and third embodiments, the present invention is directed to a method of screening for a change in the threshold value of a memory cell, and the content of the stress on the memory cell does not matter.

As the stress, any one of the leaving stress, the voltage stress of the control gate, and the voltage stress of the drain can be applied alone, or two or more of them can be applied simultaneously or continuously.

In the third embodiment, the threshold voltage change screening after writing by stress application is used. However, it goes without saying that the threshold voltage change screening after erasing by stress application may be used.

[0051]

As described above, according to the present invention, in a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium, the threshold voltage distribution width of the plurality of memory cells after writing is obtained. To make
By controlling the voltage and / or pulse width during writing, the threshold voltage distribution after writing can be suppressed to a width smaller than that during normal writing.

Further, the upper limit value and the lower limit value of the threshold voltage distribution before the stress application are stored for each sample, and the upper limit value and the lower limit value before and after the stress application are compared to perform screening, so that a short time and low stress can be obtained. It is possible to detect the reliability-deteriorated cells with high accuracy, and it is possible to eliminate an increase in the defective rate due to excessive stress.

After the writing step, in the threshold voltage distribution range, the number of memory cells for each threshold value is measured a plurality of times while changing the threshold value, and the information is stored for each sample. By comparing the number of memory cells for each threshold value before and after stress application and performing screening, it is not necessary to control the threshold value in writing, so that the reliability-deteriorated cells can be accurately detected in a short time and with low stress. It is possible to eliminate the increase in the defective rate due to excessive stress.

[Brief description of the drawings]

FIG. 1 is a process flowchart of a threshold control method for a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating an example of a distribution of a write threshold voltage in the process of FIG. 1;

FIG. 3 is a process flow chart of a semiconductor memory device screening method according to a second embodiment of the present invention;

FIG. 4 is a diagram showing a threshold distribution after writing and a determination method after stress application in the process of FIG. 3;

FIG. 5 is a process flowchart of a method for screening a semiconductor memory device according to a third embodiment of the present invention.

6 is a diagram showing a threshold distribution after writing and a determination method after stress application in the process of FIG. 5;

FIG. 7 is a process flow chart of a conventional semiconductor memory device screening method.

8 is a diagram showing a threshold distribution after writing and a determination method after stress application based on the screening method of FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 voltage and write pulse width setting step 2 writing step 3 threshold distribution width determination step 4 erasing step 5 voltage and write pulse width resetting step

Claims (6)

[Claims] In a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium, a write operation is performed so that a threshold voltage distribution width of the plurality of memory cells after writing is reduced. A method of controlling a threshold value of a semiconductor memory device, comprising controlling a voltage and / or a pulse width. 2. A step of setting a voltage and a pulse width at the time of writing, a step of executing writing to a plurality of memory cells, and a step wherein a threshold voltage distribution after writing to the plurality of memory cells is less than a predetermined distribution width. Determining whether or not the threshold voltage distribution is not less than the distribution width, temporarily erasing the plurality of memory cells, and reducing the threshold voltage distribution width after writing of the plurality of memory cells. Thus, the voltage at the time of writing after once erasing and / or the pulse width is changed to the voltage at the time of previous writing and
2. The method according to claim 1, further comprising the step of writing again after changing the pulse width compared with the pulse width. 3. A step of setting a voltage and a pulse width at the time of writing to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium, and performing writing to the plurality of memory cells. Measuring the upper limit value and the lower limit value of the threshold voltage distribution after writing of the plurality of memory cells, and writing information of the measured upper limit value and lower limit value to memory cells other than the plurality of memory cells Applying a stress to the plurality of memory cells, measuring the upper and lower limits of the threshold voltage distribution again after the application of the stress, and determining the measured upper and lower limits before applying the stress. Comparing the information on the upper limit value and the lower limit value of the threshold voltage distribution written in the memory cells other than the plurality of memory cells to classify non-defective products and defective products. And a method of screening a semiconductor memory device. 4. A step of setting a voltage and a pulse width at the time of writing to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium, and performing writing to the plurality of memory cells. Determining whether the threshold voltage distribution after writing to the plurality of memory cells is less than a predetermined distribution width; and determining whether the threshold voltage distribution is less than the predetermined distribution width, A step of once erasing the cell, and changing the voltage at the time of writing after the once erasing and / or the pulse width to the voltage at the time of the previous writing so as to reduce the threshold voltage distribution width after the writing of the plurality of memory cells. And / or a step of writing again with a change in comparison with the pulse width, and a step of changing the threshold voltage distribution after the writing to the plurality of memory cells is smaller than the predetermined distribution width. In this case, a step of writing information obtained by measuring the upper limit value and the lower limit value in the threshold voltage distribution after the writing to a memory cell other than the plurality of memory cells,
Applying a stress to the plurality of memory cells; measuring the upper and lower limits of the threshold voltage distribution again after the application of the stress; and determining the measured upper and lower limits before applying the stress. Screening of a semiconductor memory device, comprising a step of comparing information on upper and lower limits of a threshold voltage distribution written in a memory cell other than a memory cell to classify a non-defective product and a defective product. Method. 5. A step of setting a voltage and a pulse width at the time of writing to a semiconductor memory device using a plurality of electrically rewritable and erasable memory cells as a storage medium, and performing writing to the plurality of memory cells. A step of, after the writing step, measuring the number of memory cells for each threshold in the threshold voltage distribution range a plurality of times while changing the threshold, and Writing information to memory cells other than the plurality of memory cells, applying stress to the plurality of memory cells,
After the application of the stress, a step of measuring the number of memory cells for each threshold value a plurality of times again by changing the threshold value in the distribution range of the threshold voltage; A step of comparing the number of memory cells with information written in memory cells other than the plurality of memory cells before applying the stress, and classifying non-defective products and defective products. Method. 6. A memory cell is formed on a semiconductor substrate via a first insulating film, and accumulates charge by accumulating the charge. The memory cell is formed on the floating gate via a second insulating film. A control gate, and a source / drain region formed on the substrate on both sides of the floating gate, wherein the stress is any one of a standing stress on the floating gate, a voltage stress on the control gate, and a voltage stress on the drain. 6. The method for screening a semiconductor memory device according to claim 3, wherein the voltage is applied or two or more voltages are applied simultaneously or successively.