JP2000227899A - Resource dividing method and bus connecting mechanism in bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resource dividing method and a bus connecting device which do not need a register for system resource allocation, are of simple hardware constitution and facilitates system extension. SOLUTION: When response signals are returned from plural I/O systems 8-12 with time lag at an access request made by a CPU 1, I/O buses 3 and 4 which are connected with bus connection devices 5 and 6 of the I/O system having quickly responded are validated and the I/O buses which are connected with the other bus connection devices are invalidated. When the response signals are returned at the same time, the bus connecting device of some I/O system outputs a data validation signal to a CPU bus 2 and other bus connecting devices outputs CPU interruption signals. The CPU detects inconsistency being generated in an I/O cycle by receiving a contrary signal and when the response signal is not returned from any I/O system, a timer 7 sends time-out signals to the respective bus connecting devices make all the I/O buses ineffective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a CPU bus connected to a CPU, and a plurality of I / O buses connected to an arbitrary number of I / O systems. And a bus connection mechanism in a bus system having a bus connection mechanism between the two.

[0002]

2. Description of the Related Art In a conventional resource dividing method in a bus (BUS) connection mechanism, when an address duplication or the like occurs,
For one access request, two resources (I / O
In order to prevent redundant activation of the I / O system such as a space and a memory, resources allocated to the I / O buses controlled by each BUS connection mechanism are stored in a register or the like. By referring to the contents of this register, the I / O request can be made only when the access request is for a resource connected to the I / O bus controlled by the access request.
The I / O bus is controlled to return a response to the CPU.

[0003]

However, in the case of the above-mentioned conventional system, when the system is initialized, all resources are checked by an initialization program, the resources allocated to each BUS control mechanism are calculated, and then each BUS control mechanism is calculated. The contents of the resources must be recorded in the register in the control mechanism, which causes a problem that the system initialization program becomes complicated. Also, registers are required in the BUS connection mechanism by the number of I / O systems connected to the I / O bus, and there is a problem that the hardware configuration is complicated and the size is increased. Further, when the system is expanded, it is necessary to add a register, and there is a problem that the system expansion is not easy.

Therefore, the present invention has been made in view of the above problem, and by devising a method of processing resource division, a register for system resource allocation conventionally provided in each BUS connection mechanism is provided. It is an object of the present invention to provide a resource dividing method and a bus connection mechanism in a bus system, which is unnecessary, has a simple hardware configuration, and can be easily expanded.

[0005]

The resource dividing method of the present invention comprises a CPU bus connected to a CPU, and an arbitrary number of I / Os.
A plurality of I / O buses connected to the O system;
In a bus system in which a BUS connection mechanism is provided between a PU bus and each I / O bus, when a response signal is returned with a time lag from a plurality of I / O systems to an access request by a CPU. Is the response I
The I / O bus connected to the BUS connection mechanism of the I / O system is enabled, and the BUS connection mechanism of the I / O system that has responded quickly responds to the other BUS connection mechanism.
When an I / O bus interruption signal is output to invalidate an I / O bus connected to another BUS connection mechanism, and a response signal is returned simultaneously from a plurality of I / O systems to an access request from the CPU, , BU of any I / O system
A data valid signal is output from the S connection mechanism to the CPU bus, and a CPU interrupt signal is output from the BUS connection mechanism of another I / O system to the CPU bus.
The PU detects the occurrence of inconsistency in the I / O cycle by receiving the contradictory signal, and if no response signal is returned from any of the I / O systems in response to the access request by the CPU, the specified time is reached. Is sent to each BUS connection mechanism from a timer that counts the number of buses, and all I / O buses are invalidated.

A first BUS connection mechanism of the present invention for realizing the above resource dividing method receives an address valid signal and an address / command signal from a CPU bus, and adjusts the I / O bus in accordance with I / O timing. An address timing generation circuit for outputting an I / O cycle start signal and an address / command signal, and receiving a response signal from the I / O system, outputting a data valid signal to the CPU bus, and processing the I / O system. When the data is read from the CPU, a data timing generation circuit for flowing data to the CPU bus and an I / O bus stop command signal input via a control signal line from the other BUS connection mechanism are monitored. And outputs an I / O bus interruption signal to the I / O bus when the signal becomes valid, and a control signal line based on a response signal received from the I / O bus. Through and to the other BUS connection mechanism I /
An I / O bus stop timing generation circuit for outputting an O bus stop command signal, a response signal from the I / O bus, and an I / O bus
A circuit for performing a logical product of the bus stop command signal, a circuit for performing a logical sum of an output from the logical product circuit and a time-out signal from a timer, and a CPU based on the output from the logical sum circuit
And a CPU bus stop timing generation circuit for outputting a CPU bus interruption signal for instructing the bus to interrupt the transfer cycle of the CPU bus.

A second BUS connection mechanism of the present invention for realizing the above resource dividing method receives an address signal and an address / command signal from a CPU bus, and receives an I / O signal in accordance with the timing of the I / O bus. An address timing generation circuit that outputs a bus cycle start signal and an address / command signal (A / C); and a data valid signal that is output to the CPU bus in response to a response signal from the I / O system. If it was read from the system,
A data timing generation circuit for flowing data to the CPU bus and a response signal of the I / O bus input from the other BUS connection mechanism through a control signal line are monitored, and when the signal becomes valid, the signal is transmitted to the I / O bus. An I / O bus stop timing generation circuit that outputs an I / O bus interruption signal and outputs a response signal received from the I / O bus to the other BUS connection mechanism via a signal line, and a response signal from the I / O bus A circuit for performing an AND operation on a response signal from the other BUS connection mechanism, a circuit for performing an OR operation on an output from the AND circuit and a time-out signal from a timer, and a circuit based on an output from the OR circuit. And a CPU bus stop timing generation circuit for outputting a CPU bus interruption signal for instructing the CPU bus to interrupt the transfer cycle of the CPU bus.

Then, the resource dividing method having the above configuration and B
When the US connection mechanism is used, a plurality of I / Os can be provided without providing a register for allocating resources such as I / Os and memories.
The access to the I / O system of the bus system having the bus can be controlled, and the system can be prevented from being frozen when the address is duplicated.

Further, in the case of the second BUS connection mechanism, the number of control signal lines output from the BUS connection mechanism can be reduced, and the BUS connection mechanism can be configured more simply.

[0010]

Next, a specific example of an embodiment of the present invention will be described with reference to the drawings. 1 and 2
FIG. 1 shows an embodiment of the present invention. FIG. 1 is a block diagram showing an entire configuration of a bus system to which the present invention is applied, and FIG. 2 is a block diagram showing a configuration of a BUS connection mechanism in FIG. is there.

As shown in FIG. 1, the bus system shown in FIG. 1 has a CPU 1, a CPU bus 2, and a first bus system.
A first BUS connection mechanism 5 for connecting the CPU bus 2 to the first I / O bus 3; a second BUS connection mechanism 5 for connecting the CPU bus 2 to the first I / O bus 3; A second BUS connection mechanism 6 for connecting with the I / O bus 4, a timer 7, and a plurality of I / O systems 8 connected to each of the first and second I / O buses 3, 4 ~ 12.

The BUS connection mechanisms 5 and 6 receive an access request to any one of the I / O systems 8 to 12 sent from the CPU 1 and send the access request to the first or second I / O bus 3 or 4. It outputs necessary signals. Thereby, the data from the CPU 1 is transferred to the I / O systems 8 to 1
2 to any one of the I / O systems 8 to
12 can be sent to the CPU 1. The BUS connection mechanisms 5 and 6 are connected via the control signal line 13 to the BUS connection mechanisms 5 and 6 on the other side.
By receiving an I / O cycle interrupt request from
Interrupt the O cycle.

The timer 7 is turned on when a data transfer cycle on the first I / O bus 3 or the second I / O bus 4 is started, and the timer 7 transfers data on the I / O bus within a specified time. Is not completed, a time-out signal notifying the time-out is output to each of the BUS connection mechanisms 5 and 6 through a signal line.

Addresses are individually assigned to each of the I / O systems 8-12. This address is
It can be changed by a special instruction from U1. Each I /
The O systems 8 to 12 are independent and can have the same address as other I / O systems.

FIG. 2 shows a circuit example of the first and second BUS connection mechanisms 5 and 6. The first and second BUS connection mechanisms 5 and 6 have the same circuit configuration, and include an address timing generation circuit 101 and a data timing generation circuit 10 respectively.
2. It comprises an I / O bus stop timing generation circuit 103, an AND circuit 104, an OR circuit 105, and a CPU bus stop timing generation circuit 106.

The address timing generation circuit 101
Upon receiving an address valid signal (ADS) and an address / command signal (A / C) from the PU bus 1, the I / O buses 3, 4
Is a circuit for outputting an I / O cycle start signal (CST) and an address / command signal (A / C) to the I / O buses 3 and 4 at the same timing.

The data timing generation circuit 102 has an I / O
When a response signal (ACK) from the O system 8 to 12 is received and a data valid signal (D-ACT) is output to the CPU bus 2, and the processing is data reading from the I / O system 8 to 12 Is a circuit having a function of flowing data to the CPU bus 2.

I / O bus stop timing generation circuit 1
03 is a control signal line 13 from the BUS connection mechanism on the other side.
A / I bus stop command signal (STO
PRQ-IN) and a function of outputting an I / O bus interruption signal (STOP) to the I / O bus when the signal becomes valid, and a response signal ( AC
K), the I / O bus stop command signal (STOPRQ-OU) is sent to the other BUS connection mechanism through the control signal line 13b.
T) is a circuit having a function of outputting T).

The AND circuit 104 receives a response signal (ACK) from the I / O buses 3 and 4 and an I / O bus stop command signal (S
TOPRQ-IN).

The OR circuit 105 is connected to the AND circuit 10.
4 and the time-out signal (TO) from the timer 7
UT).

CPU bus stop timing generation circuit 1
06 is a CP based on the output from the OR circuit 105.
This circuit has a function of outputting a CPU bus interruption signal (STOP) for instructing the U bus 2 to interrupt the transfer cycle of the CPU bus 2.

An access request from the CPU bus 2 to the I / O buses 3 and 4 is activated by the address timing generation circuit 101 as a transfer cycle of the I / O bus, and
In response to a response signal (ACK) from the O device, the data timing circuit 102 outputs data (DATA) and a data valid signal (D-ACT) to the CPU bus 2 to transmit and receive data from the CPU to the I / O system. Can do it.

Further, based on an I / O bus stop command signal (STOPRQ-IN) sent from the other BUS connection mechanism via the control signal line 13a, the I / O bus stop timing generation circuit 103 generates a control signal. The I / O bus stop command signal (S
By outputting (TOPRQ-OUT), the I / O bus can be interrupted.

Further, a time-out signal (T-OUT) indicating a time-out of an I / O cycle or an external I / O cycle
I / O cycle interrupt request and connected I / O
If the response signal (ACK) of the O bus is valid,
A CPU bus interrupt signal (STOP) for instructing the CPU bus cycle to be interrupted can be output to the PU bus 2.

Next, the operation of the bus system having the above configuration will be described. First, a normal reading operation from the CPU to the I / O system will be described with reference to the timing chart of FIG. Note that the L level of each control signal in the timing chart of FIG. 3 indicates that the signal is valid.

The CPU 1 first outputs an address signal (ADS) indicating the start of a transfer cycle to the CPU bus 2. At the same time, it outputs an address / command signal (A / C).

Each of the BUS connection mechanisms 5 and 6 has an I / O generated by each address timing generation circuit 101.
A cycle start signal (CST) indicating a cycle start and an address / command signal (A / C) are transmitted to each I / O bus 3,
4 is output.

Here, the I / O system 8 corresponding to the address is connected to the first I / O bus 3 and the second I / O bus 3 is connected to the first I / O bus 3.
When the I / O system corresponding to the address is not connected to the I / O bus 4, only the I / O system 8 connected to the first I / O bus 3 controls the first I / O bus 3. The response signal (ACK) and the data corresponding to the address (DAT
A) is output. At this time, since there is no corresponding I / O system on the second I / O bus 4, no change occurs.

BU connected to first I / O bus 3
The S connection mechanism 5 makes the I / O bus stop command signal (STOPRQ-OUT) valid by the I / O bus stop timing generation circuit 103 in the BUS connection mechanism 5.

BU connected to second I / O bus 4
In the S connection mechanism 6, the I / O bus stop timing generation circuit 103 in the BUS connection mechanism 6 causes the second I / O
An I / O bus interruption signal (STOP) is sent to the bus 4 and the second
Of the transfer cycle of the I / O bus 4 is forcibly terminated.

In the BUS connection mechanism 5, the internal data timing generation circuit 102 controls the I / O system 8
And outputs a data valid signal (D-ACT) indicating that the data is valid, and terminates the normal reading operation from the CPU 1 to the I / O system 8. I do.

Next, a normal write operation from the CPU to the I / O system will be described with reference to the timing chart of FIG. The CPU 1 first sends an address signal (ADS) indicating the start of a transfer cycle to the CPU bus 2.
Output to At the same time, an address / command signal (A / C) and data (DATA) are output.

Each of the BUS connection mechanisms 5 and 6 has an I / O generated by each address timing generation circuit 101.
A cycle start signal (CST) indicating a cycle start, an address / command signal (A / C), and data (DAT) generated by the data timing generation circuit 102
A) is output to each I / O bus 3, 4.

Here, the I / O system 8 corresponding to the address is connected to the first I / O bus 3 and the second I / O bus 3 is connected to the first I / O bus 3.
When the I / O system corresponding to the address is not connected to the I / O bus 4, only the I / O system 8 connected to the first I / O bus 3 controls the first I / O bus 3. The response signal (ACK) and the data corresponding to the address (DAT
A) is output. At this time, since there is no corresponding I / O system on the second I / O bus 4, no change occurs.

BU connected to the first I / O bus 3
The S connection mechanism 5 makes the I / O bus stop command signal (STOPRQ-OUT) valid by the I / O bus stop timing generation circuit 103 in the BUS connection mechanism 5.

BU connected to second I / O bus 4
In the S connection mechanism 6, the I / O bus stop timing generation circuit 103 in the BUS connection mechanism 6 causes the second I / O
An I / O bus interruption signal (STOP) is sent to the bus 4 and the second
Of the transfer cycle of the I / O bus 4 is forcibly terminated, and the output of the data (DATA) output on the second I / O bus 4 is also terminated.

In the BUS connection mechanism 5, a data valid signal (D-ACT) indicating that data is valid based on a response signal (ACK) from the I / O system 8 is transmitted to the CPU.
The data is output to the bus 2 and the normal write operation from the CPU 1 to the I / O system 8 ends.

Next, the operation in the case where no I / O system responds when the CPU accesses the I / O system will be described with reference to the timing chart of FIG.

The CPU 1 first outputs an address signal (ADS) indicating the start of a transfer cycle to the CPU bus 2. At the same time, the address / command signal (A /
C) is also output. Each of the BUS connection mechanisms 5 and 6 outputs the I
/ O cycle start signal (CS)
T) and an address / command signal (A / C) are transmitted to each I / O
Output to buses 3 and 4.

Here, since each of the I / O systems 8 to 12 does not correspond to the address, a response signal (AC
Do not return K).

When the specified time has elapsed, the timer 7 connected to the BUS connection mechanisms 5 and 6 detects a time-out, and a time-out signal (T-OUT) is sent to each BUS connection mechanism 5 and 6 through the signal line 14. Notice.

In each of the BUS connection mechanisms 5 and 6,
The I / O bus stop timing generation circuit 103 receives the time-out signal (T-OUT), and
For the O buses 3 and 4, I representing the interruption of the I / O cycle
/ O bus interrupt signal (STOP) is output.

Thus, the cycle of the I / O bus is interrupted. Further, the CPU bus stop timing generation circuits in the BUS connection mechanisms 5 and 6 output a CPU bus interruption signal (STOP) to the CPU bus 2 in response to the time-out signal (T-OUT) signal. Break the cycle. Thus, the CPU 1 can know that the I / O cycle has failed.

Next, a case where a plurality of I / O systems respond when the CPU accesses the I / O system will be described.

First, a case where the responses of a plurality of I / O systems are shifted in time will be described. For example, the second I
If the I / O system 10 connected to the I / O bus 4 has a slower response than the I / O system 8 connected to the first I / O bus 3, the I / O system 10 terminates the transfer cycle first. BUS connection mechanism 5 of the I / O bus 3 is connected to the control signal line 13
, The interrupt request is notified to the BUS connection mechanism 6 of the second I / O bus 4, the slower response is ignored, and a contradictory transfer cycle occurs on the CPU bus 2. Never.

Next, the I / O connected to the first I / O bus 3
/ O system 8 and an I / O system connected to the second I / O bus 4
The operation when the / O system 10 simultaneously returns the response signal (ACK) will be described with reference to the timing chart of FIG.

First, the CPU 1 outputs an address signal (ADS) indicating the start of a transfer cycle to the CPU bus 2. At the same time, the address / command signal (A /
C) is also output.

Then, an I / O system 8 connected to the first I / O bus 3 and an I / O system connected to the second I / O bus 4
Since the / O system 10 can respond to the address, it returns an acknowledgment signal (ACK) at the same time. At this time,
The BUS connection mechanism 5 notifies the other BUS connection mechanisms 6 of the interruption request through the control signal line 13.

However, in the BUS connection mechanism 6, the response signal (AC) is simultaneously sent to the second I / O bus 4 managed by the BUS connection mechanism 6.
K) is returned, the AND circuit 104 causes the response signal (ACK) from the second I / O bus 4 and the I / O bus stop command signal (STOPRQ) from the BUS connection mechanism 5 to be output.
−IN) is taken, sent to the CPU bus stop timing generation circuit 106 through the OR circuit 105, and outputs a CPU bus interruption signal (STOP) to the CPU bus 2 from the CPU bus stop timing generation circuit 106.

At the same time, inside the BUS connection mechanism 5, the data timing generation circuit 102 uses the response signal (ACK) from the first I / O bus 3 to indicate that the data is valid. A signal (D-ACT) is output to the CPU bus 2.

Therefore, a data valid signal (D-ACT) and a CPU bus interruption signal (STOP) are provided on the CPU bus 2.
Both signals are output at the same time, whereby the CPU 1 can know that an inconsistency has occurred in the I / O cycle.

FIG. 7 shows another configuration example of the BUS connection mechanisms 5 and 6. In the example of FIG. 7, the part for sending the interruption request to the BUS control mechanism on the other side is further devised, and the BU shown in FIG.
One of the two control signal lines 13a and 13b in the S connection mechanism is not required, and the number of control signal lines output from the BUS connection mechanisms 5 and 6 is reduced.

The BUS connection mechanisms 5 and 6 in FIG. 7 respectively include an address timing generation circuit 201, a data timing generation circuit 202, an I / O bus stop timing generation circuit 203, a logical product circuit 204, and a logical sum. Circuit 205 and CPU bus stop timing generation circuit 20
6.

The address timing generation circuit 201
Upon receiving an address signal (ADS) and an address / command signal (A / C) from the PU bus, the cycle start signal (CST) of the I / O buses 3 and 4 is synchronized with the timing of the I / O buses 3 and 4. And the address / command signal (A /
C) is a circuit for performing the output.

The data timing generation circuit 202 generates the I /
Upon receiving a response signal (ACK) from the O system 8 to 12, it outputs a data valid signal (D-ACT) to the CPU bus 2, and in the case of reading from the I / O system 8 to 12, This is a circuit having a function of flowing data (DATA) to the CPU bus 2.

I / O bus stop timing generation circuit 2
03 is a response signal (ACK-I) of the I / O bus input from the other BUS connection mechanism through the control signal line 13a.
N), a function of monitoring the response signal and outputting an I / O bus interruption signal (STOP) to the I / O bus when the signal becomes valid, and receiving the signal from the I / O buses 3 and 4. The response signal (ACK-OUT) is transmitted through the signal line 207 to the other BU.
This is a circuit having a function of outputting to the S connection mechanism.

The logical product circuit 204 is a circuit that performs a logical product of the response signal (ACK) from the I / O bus and the response signal (ACK-IN) from the other BUS connection mechanism.

The OR circuit 205 is provided for the AND circuit 20.
4 and the time-out signal (TO) from the timer 7
UT).

CPU bus stop timing generation circuit 2
06 is a CP based on the output from the OR circuit 205.
This circuit has a function of outputting a CPU bus interruption signal (STOP) for instructing the U bus 2 to interrupt the transfer cycle of the CPU bus.

The BUS connection mechanisms 5 and 6 having the above configuration are
As shown in a timing chart of the operation in FIG.
An access request from the PU bus 2 to the I / O buses 3 and 4 is:
It is started as a transfer cycle of the I / O bus by the address timing generation circuit 201, and data (DATA) and data are valid from the data timing generation circuit 202 to the CPU bus 2 by a response signal (ACK) from the I / O buses 3 and 4. By outputting a signal (D-ACT), C
Data can be transmitted and received from the PU 1 to the I / O systems 8 to 12.

Further, upon receiving a response signal (ACK-IN) of the other I / O bus given from the other BUS connection mechanism through the control signal line 13a, the I / O bus stop timing generation circuit 103 causes the I / O bus By outputting an I / O bus interruption signal (STOP) to the I / O bus, the I / O bus can be interrupted.

Further, an I / O cycle time-out signal (T-OUT) from the timer 7 via the signal line 14 or an I / O cycle interruption request (ACK) from the other BUS connection mechanism via the control signal line 13a. −IN),
If the response signal (ACK) of the I / O bus connected to the I / O bus is valid, the CPU bus stop timing generation circuit 106 interrupts the CPU bus cycle to the CPU bus 2. The CPU bus interruption signal (STOP) to be instructed is output.

As described above, when the BUS connection mechanism of FIG. 8 is used, one of the two control signal lines 13a and 13b in the BUS connection mechanism shown in FIG. 2 is used.
Since b is unnecessary and the number of control signal lines can be reduced, the configuration of the device can be further simplified.

[0064]

As described above, according to the method and apparatus of the present invention, a plurality of I / Os can be provided without providing a register for allocating system resources such as I / O and memory in a bus (BUS) connection mechanism. A system having a bus can control access to the I / O system, and can avoid freezing of the system in the event of address duplication or the like.

Even when the I / O systems have the same address, a contradiction on the CPU bus occurs and the
A situation in which the U bus cycle freezes can be avoided.

Further, in the system initialization program for initializing the system, since the register of the BUS connection mechanism can be omitted, the system can be initialized with a simpler initialization program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a bus system configured by applying the present invention.

FIG. 2 is a block diagram illustrating a configuration of a BUS connection mechanism in FIG. 1;

FIG. 3 is a timing chart of a normal reading operation from a CPU to an I / O system.

FIG. 4 is a timing chart of a normal write operation from the CPU to the I / O system.

FIG. 5 is a timing chart of an operation when no responding I / O system exists.

FIG. 6 is a timing chart of an operation when response signals are returned simultaneously from I / O systems connected to different I / O buses.

FIG. 7 is a block diagram showing another configuration example of the BUS connection mechanism.

FIG. 8 is a timing chart showing the operation of the BUS connection mechanism of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 CPU bus 3 1st I / O bus 4 2nd I / O bus 5 1st BUS connection mechanism 6 2nd BUS connection mechanism 7 Timer 8-12 I / O system 14 Signal line 13 Control signal Line 101 Address timing generation circuit 102 Data timing generation circuit 103 I / O bus stop timing generation circuit 104 Logical product circuit 105 Logical OR circuit 106 CPU bus stop timing generation circuit 201 Address timing generation circuit 202 Data timing generation circuit 203 I / O bus Stop timing generation circuit 204 logical product circuit 205 logical sum circuit 206 CPU bus stop timing generation circuit

Claims (3)

[Claims] 1. A system comprising: a CPU bus connected to a CPU; and a plurality of I / O buses connected to an arbitrary number of I / O systems, each having a bus between the CPU bus and each I / O bus. In a bus system provided with a connection mechanism, when a response signal is returned with a time lag from a plurality of I / O systems in response to an access request from a CPU, the bus connection mechanism of the I / O system which has a quick response. The I / O bus connected to the I / O bus is enabled, and an I / O bus interruption signal is output from the bus connection mechanism of the I / O system that has responded quickly to the other bus connection mechanism, thereby enabling another bus connection. If the I / O bus connected to the mechanism is invalidated and response signals are returned from a plurality of I / O systems simultaneously to an access request from the CPU, the bus connection mechanism of one of the I / O systems CP A data valid signal is output to the bus, and a CPU interrupt signal is output to the CPU bus from the bus connection mechanism of another I / O system. If a response signal is not returned from any of the I / O systems in response to an access request from the CPU, an expiration signal is sent from a timer that counts a specified time to each bus connection mechanism. And disabling all I / O buses in the bus system. 2. An address timing generator for receiving an address valid signal and an address / command signal from a CPU bus and outputting an I / O cycle start signal and an address / command signal to the I / O bus in accordance with I / O timing. A data valid signal is output to the CPU bus in response to the response signal from the circuit and the I / O system, and if the processing is data reading from the I / O system, the data is passed to the CPU bus. A timing generation circuit monitors an I / O bus stop command signal input from a bus connection mechanism on the other side via a control signal line, and when the signal becomes valid, an I / O bus is transmitted to the I / O bus. An I / O that outputs a bus interruption signal and outputs an I / O bus stop command signal to the other bus connection mechanism through a control signal line based on a response signal received from the I / O bus. A bus stop timing generation circuit, a circuit for performing a logical product of a response signal from the I / O bus and an I / O bus stop command signal, and a logical sum of an output from the logical product circuit and a time-out signal from a timer And a CP to the CPU bus based on the output from the OR circuit.
A bus connection mechanism comprising: a CPU bus stop timing generation circuit that outputs a CPU bus interruption signal for instructing interruption of a U bus transfer cycle. 3. Upon receiving an address signal and an address / command signal from the CPU bus, output a cycle start signal and an address / command signal (A / C) of the I / O bus in accordance with the timing of the I / O bus. An address timing generating circuit, receiving a response signal from the I / O system, outputting a data valid signal to the CPU bus, and transmitting data to the CPU bus when reading from the I / O system A timing generation circuit monitors an I / O bus response signal input from the other bus connection mechanism through a control signal line, and outputs an I / O bus interruption signal to the I / O bus when the signal becomes valid. An I / O bus stop timing generating circuit for outputting a response signal received from the I / O bus to the other bus connection mechanism via a signal line; A circuit for performing an AND operation on a response signal from the bus and a response signal from the other bus connection mechanism, a circuit for performing an OR operation on an output from the AND circuit and a time-out signal from a timer, and the OR circuit To the CPU bus based on the output from
A bus connection mechanism comprising: a CPU bus stop timing generation circuit that outputs a CPU bus interruption signal for instructing interruption of a U bus transfer cycle.