JP2000227857A - Information processor for branch destination associative storage system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide accurate branch prediction by performing an appropriate amount of registration/deletion by independently performing the registration/ deletion to/from first and second branch destination associative memories. SOLUTION: This device is provided with means 15-1 and 15-2 for respectively and independently holding the results of reference to a first low-speed large- capacity branch destination associative memory 12 and a second high-speed small-capacity branch destination associative memory 13 for storing, respectively, the instruction address and branch destination address of a branching instruction according to the execution history of branching instructions in the past, means 17-1 and 17-2 for respectively and independently discriminating branch establishment/non-establishment according to held predictive information and means 18-1 and 18-2 for respectively and independently performing the registration/deletion to/from the first and second branch destination associative memories 12 and 13 according to the discriminated result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for prefetching an instruction word such as a pipeline control, and more particularly, to speed up processing of a branch instruction by reading out a branch instruction in advance using a branch associative memory. The present invention relates to a branch destination associative storage type information processing apparatus.

[0002]

2. Description of the Related Art Conventionally, in a pipeline-controlled information processing device or the like, in order to process a branch instruction at a high speed, a branch destination storing a pair of an address of a previously executed branch instruction and a branch destination address is stored. Control is performed using associative memory to reduce the disturbance of the read pipeline ahead of the branch destination instruction.

[0003] The branch destination associative memory requires a large number of registrations, and is often constituted by a large-capacity RAM. But,
RAM takes longer to access than registers,
In addition to the first branch destination associative memory composed of a large-capacity RAM, a second branch destination associative memory having a small capacity but composed of registers is provided, and the second branch destination associative memory is operated at high speed. A method of reading a branch destination instruction is employed. The hierarchization of the branch destination associative memory is described in, for example,
No. 3726.

A high-speed processing of a branch instruction by a conventional information processing apparatus of a branch destination associative memory system will be described below with reference to FIGS.

FIG. 8 is a general block diagram of a conventional branch destination associative memory type information processing apparatus for speeding up the reading of a branch destination instruction. 8, 1 is an address register A, 2 is an address register B, 3 is a branch instruction address register, 4 is a branch destination address register, 5 is an address comparison circuit A, 6 is a priority control circuit, and 7 is a branch destination address selection. Circuit, 8 is a branch instruction address array, 9 is a branch destination address array, 10 is an address comparison circuit B, 11 is a branch destination address array register, 12 is a first branch destination associative memory, and 13 is a second branch destination associative memory. , 14 is an instruction read control circuit, 15 is a prediction information holding circuit, 16 is a branch control circuit, 17 is a branch determination comparison circuit, 18 is a registration deletion control circuit, and 19 is a branch instruction address selection circuit. here,
The first branch destination associative memory 12 is composed of a RAM, and its branch instruction address array 8 stores instruction addresses for past instructions, and the branch instruction address array 9 corresponds to the instruction addresses of the branch instruction address array 8. Then, the branch destination address is stored. Second branch destination associative memory 1
Reference numeral 3 denotes a register. The branch instruction address register 3 stores, for example, the instruction address of the latest branch instruction. The branch destination address register stores the branch destination address corresponding to the instruction address of the branch instruction address register 3. The address is stored.

First, the case where the instruction address information of the branch instruction is not registered in the second branch destination associative memory 13 and the instruction address information of the branch instruction is registered only in the first branch destination associative memory 12 is described. The reading of the branch destination instruction will be described with reference to the time chart of FIG.

[0009] In FIG. 9, the horizontal axis at the top indicates the execution cycle of the pipeline, and indicates the cycle number given for convenience in order to make it possible to refer to the sequential cycles 1 to 17. D, A, T, B,
L, E, Di, and Ai, Ti, Bi, Li represent pipeline stages, D is instruction decoding, A is address calculation, T is address conversion, B is memory access, L is memory access,
Is transfer of memory read data, E is instruction execution, Di
Fetches address information for generating the instruction address of the instruction word to be read, Ai generates the instruction address of the instruction word to be read and issues a read request, Ti is the address conversion at the time of reading the instruction, Bi is the memory access at the time of reading the instruction, and Li is This indicates that the memory read data is transferred when the instruction is read.

[0009] In FIG. 9, the instruction processing by the pipeline control is such that the branch instruction 1 is taken and the branch instruction 2 continues. Cycle 1 in the instruction read control circuit 14
The instruction reading process of the instruction word including the branch instruction 1 is started, the instruction address of the instruction word to be read in cycle 2 is generated, and the instruction address generated in cycle 2 is received from the line 100 to the address register A1 in cycle 3. The branch instruction address selection circuit 19 stores the first branch destination associative memory 12
When the instruction address of the branch instruction is referred to from, the address of the address register A1 is selected, and when registration or deletion to the first branch destination associative memory 12 is performed, the registration / deletion control circuit 1
8 selects the instruction address sent out. In this case, the selection circuit 19 selects the instruction address of the address register A1 and sends it to the address register B2. In cycle 4, the instruction address of the address register A1 is received by the address register B2 in the first branch destination associative memory 13,
The branch instruction address is read from the branch instruction address array 8 as a part of the address register B2 indicating the location where the first branch destination associative memory 12 is to be read, and the instruction address of the address register B2 and the branch instruction address array 8 are read. The branch instruction address is compared by the address comparison circuit B10 to detect whether the instruction address of the branch instruction 1 is registered in the branch instruction address array 8,
When the registration is detected, a detection signal is transmitted to the priority control circuit 6 via the line 101, and a branch destination address corresponding to the detected branch instruction 1 is read from the branch destination address array 9. . In cycle 5, the branch destination address read from the branch destination address array 9 in cycle 4 is received by the branch destination address array register 11, and the line 1
The branch destination address is sent to the branch destination address selection circuit 7 through the line 02. In the priority control circuit 6, a signal for selecting the branch destination address read from the first branch destination associative memory 12 is supplied via the line 103 to the branch destination address selection circuit based on the detection signal received via the line 101 in the cycle 4. 7, and sends the detection signal received via the line 101 to the command readout control circuit 14. Branch destination address selection circuit 7
The instruction read control circuit 1 reads the branch destination address from the branch instruction address array register 11 on the line 102 according to the selection signal received from the priority control circuit 6 via the line 103.
4 Thus, under the control of the instruction read control circuit 14, the reading of the branch destination instruction 2 is completed in cycle 8, the decoding of the branch destination instruction 2 is started in cycle 9, and the processing of the branch destination instruction 2 is completed in cycle 14. .

Next, a case where the address information of the branch instruction 1 is registered only in the second branch destination associative memory 13 will be described with reference to a time chart of FIG.

The instruction reading process of the instruction word including the branch instruction 1 is started in cycle 1, the instruction address of the instruction word to be read in cycle 2 is generated, and in cycle 3, the instruction address generated in cycle 2 is transferred from the line 100 to the address. The contents of the address register A1 and the second
Branch instruction address register 3 in the branch destination associative memory 13
Is compared by the address comparison circuit A5 to detect whether or not the instruction address of the branch instruction 1 is registered in the branch instruction address register 3. If it is detected that the instruction address is registered, the detection signal is prioritized. Line 10 to degree control circuit 6
4, the branch destination address corresponding to the detected branch instruction 1 is read from the branch destination address register 4, and transmitted to the branch destination address selection circuit 7 via the line 105. The priority control circuit 6 sends a signal for selecting a branch destination address read from the second branch associative memory 13 to the branch destination address selection circuit 7 via the line 103 based on the detection signal received via the line 104. Then, the detection signal received via the line 105 is sent to the command readout control circuit 14. The branch destination address selection circuit 7 includes a priority control circuit 6
The branch destination address of the branch destination address register 4 on the line 105 is sent to the instruction read control circuit 14 in response to the selection signal from. Thus, the reading of the branch destination instruction is completed in cycle 6, the decoding of the branch destination instruction is started in cycle 7, and the processing of the branch destination instruction is completed in cycle 12.

As described above, by having the high-speed second branch destination associative memory 13 having a register configuration, in the prior art,
The speed of detecting whether the instruction address of the branch instruction included in the instruction word to be read is registered in the branch destination associative memory is increased, and the processing time of the branch instruction is reduced by reading the branch destination instruction at high speed. ing.

Next, the operation of registering an instruction address and a branch destination address in the branch destination associative memory will be described with reference to FIG.

In the processing of an instruction by pipeline control, a branch instruction 1 is taken and a branch is taken, and a branch is made to a branch instruction. The branch instruction is also a branch instruction 2, and the branch instruction 2 is taken and a branch instruction is taken. Branch to The first branch destination associative memory 12 stores the address information of the branch instruction 1 and the branch instruction 2
Are not registered, and only the address information of the branch instruction 2 is registered in the second branch destination associative memory 13.

In cycle 1, the instruction reading process of the instruction word including the branch instruction 1 is started. In cycle 3, the instruction address generated in cycle 2 is received by the address register A1 from the line 100, and the contents of the address register A1 and the second The content of the branch instruction address register 3 in the branch destination associative memory 13 is compared by the address comparison circuit A5, and the instruction address of the branch instruction 1 included in the instruction word to be read is registered in the branch instruction address register 3. To detect In this case, since the registration is not detected, a signal indicating that the registration has not been detected is sent to the prediction information holding circuit 15 via the line 106. The instruction address is sent from the address register A1 to the address register B2 in the first branch destination associative memory 12. Cycle 4
Then, the branch instruction address is read from the branch instruction address array 8 as a part of the address register B2 indicating the position where the first branch destination associative memory 12 is read, and the instruction address of the address register B2 and the branch instruction address array 8 are read. The address comparison circuit B10 compares the branch instruction addresses thus obtained, and detects whether the instruction address of the branch instruction 1 is registered in the branch instruction address array 8. In this case, since the registration is not detected, a signal indicating that the registration has not been detected is sent to the prediction information holding circuit 15 via the line 108. The prediction information holding circuit 15 predicts whether a branch is not taken in accordance with the detection signal received from the line 106 and the detection signal received from the line 108, and in this case, generates a branch not taken prediction signal. From cycle 5, the branch not-taken prediction signal is held in the prediction information holding circuit 15 corresponding to the pipeline stage of the branch instruction 1,
In FIG. 11, the instruction is held until the E stage of the branch instruction 1 (cycle 11).

In cycle 11, it is determined whether the result of executing branch instruction 1 in branch control circuit 16 is whether the branch is taken or not taken. In this case, since the branch is taken, the branch control circuit 16 generates a branch taken signal, sends the branch taken signal to the branch determination / comparison circuit 17 via the line 110, and further outputs the instruction address of the branch instruction 1 and the branch destination. The address is sent to the registration / deletion control circuit 18 via the lines 111 and 112. Further, the prediction information holding circuit 15 sends a branch failure prediction signal of the branch instruction 1 to the branch determination / comparison circuit 17 via the line 114. The branch determination / comparison circuit 17 determines that the prediction has been missed by the branch not taken prediction signal by the line 114 and the branch taken signal by the line 110, and stores the first branch destination associative memory 12 and the second branch destination associative memory 13. A registration signal for registering the branch instruction 1 is generated for both, and sent to the registration deletion control circuit 18. The registration deletion circuit 18 sends the registration signal received from the line 113, the branch instruction address and the branch destination address received from the line 111 to the first branch destination associative memory 12 and the second branch destination associative memory 13.

In the cycle 12, the branch instruction address and the branch destination address are registered in the branch instruction register 3 and the branch destination address register 4 in the second branch destination associative memory 13 by the registration signal from the registration and deletion control circuit 18. . The address register B in the first branch destination associative memory 12
2 receives the branch instruction address sent from the registration / deletion control circuit 18. In cycle 13, address register B
2 is an address indicating a registration location of the first branch destination associative memory 12, the instruction address of the branch instruction 1 is stored in the branch instruction address array 8 indicated by the address, and the branch instruction is stored in the branch destination address array 9. 1 are registered.

Thus, the first branch destination associative memory 1
2 and the second branch destination associative memory 13 both branch instruction 1
Is not registered, the instruction address and the branch destination address of the branch instruction 1 are registered in both the first branch destination associative memory 12 and the second branch destination associative memory 13.

On the other hand, the decoding of the branch instruction 1 starts in cycle 6, the branch destination address of branch instruction 1 (address of branch instruction 2) is generated in cycle 7, and the branch destination address generated in cycle 8 is The address comparison circuit A5 compares the contents of the address register A1 with the contents of the branch instruction address register 3 in the second branch destination associative memory 13 by the address comparison circuit A5, and reads the branch instruction 2 included in the instruction word to be read. Is detected in the branch instruction address register 3. In this case, since the registration is detected, a signal indicating the detection is transmitted to the prediction information holding circuit 15 via the line 106. Further, the first address register A1
The instruction address (the address of the branch instruction 2) is sent to the address register B2 in the branch destination associative memory 12. In cycle 9, the branch instruction address is read from the branch instruction address array 8 as a part of the address register B2 indicating the location to be read from the first branch destination associative memory 12, and the instruction address of the address register B2 and the branch instruction address array 8 are read. Is compared by the address comparison circuit B10 to detect whether the instruction address of the branch instruction 2 is registered in the branch instruction address register 3. In this case, since the registration has not been detected, a signal indicating that the registration has not been detected is indicated by line 1.
08 to the prediction information holding circuit 15. In accordance with the detection signal received from the line 106 and the detection signal received from the line 108, the prediction information holding circuit 15 branches if any of the first and second branch destination associative memories is detected. In this case, a branch taken prediction signal is generated to predict the taken. From cycle 10, the branch taken prediction signal is held in the prediction information holding circuit 15 corresponding to the pipeline stage of the branch instruction 2, and is held up to the E stage (cycle 16) of the branch instruction 2 in FIG.

In cycle 16, it is determined whether the result of executing branch instruction 2 by branch control circuit 16 is whether the branch is taken or not taken. In this case, since the branch is taken, the branch control circuit 6 generates a branch taken signal, sends a branch taken signal to the branch determination / comparison circuit 17 via the line 110, and further outputs the instruction address of the branch instruction 2 and the branch destination. The address is sent to the registration / deletion control circuit 18 via the lines 111 and 112. Further, the prediction information holding circuit 15 sends the branch taken prediction signal of the branch instruction 2 to the line 11.
4 and transmitted to the branch determination / comparison circuit 17. The branch determination / comparison circuit 17 determines that the prediction was successful based on the branch taken prediction signal by the line 114 and the branch taken signal by the line 110, and does not need to register the instruction address and the branch destination address of the branch instruction 2 again. Therefore, neither the first branch destination associative memory 12 nor the second branch destination associative memory 13 generates a registration signal, and the instruction address of the branch instruction 2 and the branch destination address are not registered.

As described above, the branch instruction is registered in the second branch destination associative memory 13 and the first branch destination associative memory 12 is registered.
If no branch instruction is registered in the first branch destination associative memory 13, the branch prediction is not performed in the first branch destination associative memory 12 again. When the branch instruction is registered in the first branch destination associative memory 12 and the branch instruction is not registered in the second branch destination associative memory 13, the first branch destination associative memory 1 is stored.
Since the branch prediction by 2 is prioritized, the registration is not performed again in the second branch destination associative memory 13.

Next, the operation of deleting from the branch destination associative memory will be described with reference to FIG. In the instruction processing by the pipeline control, it is assumed that the branch instruction 1 is not taken and the instruction 2 is executed. Further, the instruction address of the branch instruction 1 is not registered in the first branch destination associative memory 12,
It is assumed that the instruction address of the branch instruction 1 is registered in the branch destination associative memory 13.

Under the control of the instruction read control circuit 14, the instruction read processing of the instruction word including the branch instruction 1 is started in cycle 1, and in cycle 3, the instruction address generated in cycle 2 is received from the line 100 to the address register A1. ,
Address register A1 contents and second branch destination associative memory 1
The contents of the branch instruction address register 3 are compared with the contents of the branch instruction address register 3 by the address comparison circuit A5, and it is detected whether or not the instruction address of the branch instruction 1 included in the instruction word to be read is registered in the branch instruction address register 3. In this case, since the registration is detected, a signal indicating the detection is transmitted to the prediction information holding circuit 15 via the line 106. The instruction address is sent from the address register A1 to the address register B2 in the first branch destination associative memory 12. In cycle 4, the branch instruction address is read from the branch instruction address array 8 as a part of the address register B2 indicating the location to be read from the first branch destination associative memory 12, and the instruction address of the address register B2 and the branch instruction address array 8 are read. The address of the branch instruction read from is compared by the address comparison circuit B10 to detect whether the instruction address of the branch instruction 1 is registered in the branch instruction address array 8. In this case, since the registration is not detected, a signal indicating that the registration has not been detected is sent to the prediction information holding circuit 15 via the line 108. In accordance with the detection signal received from the line 106 and the detection signal received from the line 108, the prediction information holding circuit 15 branches if any of the first and second branch destination associative memories is detected. In order to predict the establishment, a branch establishment prediction signal is generated. From cycle 5, the branch taken prediction signal is held in the prediction information holding circuit 15 corresponding to the pipeline stage of the branch instruction 1, and is held up to the E stage (cycle 11) of the branch instruction 1 in FIG.

In cycle 11, it is determined whether the result of executing branch instruction 1 in branch control circuit 16 is whether the branch is taken or not taken. In this case, since the branch is not taken, the branch control circuit 16
Generates a branch-not-taken signal, sends a branch-not-taken signal to the branch determination / comparison circuit 17 via the line 110, and sends the instruction address of the branch instruction 1 to the registration / deletion control circuit 18 via the line 111. Further, the prediction information holding circuit 15 sends a branch establishment prediction signal of the branch instruction 1 to the branch determination / comparison circuit 17 via the line 114. The branch determination / comparison circuit 17 determines that the prediction has failed based on the branch taken prediction signal by the line 114 and the branch not taken signal by the line 110, and deletes the instruction address and the branch destination address of the branch instruction 1. A delete signal is generated for both the first branch destination associative memory 12 and the second branch destination associative memory 13 and sent to the registration / deletion control circuit 18. The registration delete circuit 18
The delete signal received from the line 15 and the branch instruction address received from the line 111 are sent to the first branch destination associative memory 12 and the second branch destination associative memory 13.

In cycle 12, second associative branch destination memory 13 deletes the instruction address of branch instruction 1 from branch instruction address register 3, and deletes the branch destination address of branch instruction 1 from branch destination address register 4. The address register B2 in the first branch destination associative memory 12 receives the branch instruction address sent from the registration / deletion control circuit 18. In the cycle 13, the branch instruction address to be deleted is not registered in the first branch destination associative memory 12 by the deletion signal from the registration deletion circuit 18, but a part of the address of the address register B2 is changed to the first. An address indicating the location where the branch destination associative memory 12 is to be deleted is set, and the registered contents of the branch instruction address array 8 and the registered contents of the branch destination address array 9 indicated by the address are deleted.

[0025]

According to the above prior art, for example, the instruction address of a branch instruction is registered in the second branch destination associative memory, and the instruction address of the branch instruction is stored in the first branch destination associative memory. If the branch is not registered, the branch prediction is a branch taken prediction if the branch prediction is registered in either the first branch destination associative memory or the second branch destination associative memory. The prediction information in the first branch destination associative memory is not used, and the prediction is successful, and no registration is performed in the first branch destination associative memory. If the registration in the second branch destination associative memory is performed many times and the number of registrations exceeds the capacity of the second branch destination associative memory, the branch instruction already registered in the second branch destination associative memory. Instruction address is overwritten by another branch instruction address. At this time,
Since it is not registered in the first branch destination associative memory for the above-described reason, a problem occurs that the subsequent branch prediction is not performed correctly.

When the branch instruction is registered only in the second branch destination associative memory, if the branch prediction is registered in either the first branch destination associative memory or the second branch destination associative memory. Since the branch is taken, if the branch determination is not taken, the prediction fails and the second branch destination associative memory is deleted. At this time, unnecessary deletion of the first branch destination associative memory is also performed at the same time, and a part of the branch instruction address is deleted as an address indicating the deletion location of the first branch destination associative memory. The problem is that the instruction address information of the branch instruction which is not to be used is deleted, and the subsequent branch prediction is not correctly performed.

Accordingly, a first object of the present invention is to hold prediction information of a first branch destination associative memory and prediction information of a second branch destination associative memory independently, and to determine whether branch prediction has succeeded or failed. 1
Of the branch destination associative memory and the second branch destination associative memory, and independently registering or deleting the branch associative memory, thereby enabling highly accurate branch prediction. An object of the present invention is to provide a storage-type information processing device.

When the first branch destination associative memory and the second branch destination associative memory are independently registered, the address information of the branch instruction is stored in both the first branch destination associative memory and the second branch destination associative memory. Registered in. Therefore, when prefetching an instruction,
The instruction address of the same branch instruction is detected in the first branch destination associative memory and the second branch destination associative memory. In this case, the instruction is read using the branch destination address read from the second branch destination associative memory, and the instruction is read using the branch destination address read from the first branch destination associative memory. The problem occurs.

Accordingly, a second object of the present invention is to provide a method for reading instructions which are performed in duplicate when the instruction address of the same branch instruction is detected in the second branch destination associative memory and the first branch destination associative memory. Another object of the present invention is to provide an information processing apparatus of a branch destination associative memory system that can suppress one of the processes and prevent unnecessary instruction reading.

The second branch destination associative memory has a smaller number of registrations than the first branch destination associative memory.
When the capacity of the branch destination associative memory is exceeded, overwriting of the registration occurs, so that the registered contents of the first branch destination associative memory and the second branch destination associative memory do not match. In this case, when the instruction is prefetched, the branch instruction address detected in the first branch destination associative memory and the branch instruction address detected in the second branch destination associative memory are detected at different addresses. If the branch instruction address detected in the first branch destination associative memory is smaller than the branch instruction address detected in the second branch destination associative memory, the branch predicted in the first branch destination associative memory is considered in consideration of the execution order of the instructions. If the instruction is executed first and the prediction of the first branch destination associative memory is successful, the branch instruction predicted by the second branch destination associative memory is not executed and the instruction is read out by the second branch destination associative memory. The branch instruction is not executed. However, when the first branch destination associative memory and the second branch destination associative memory are independently controlled, the branch destination address read from the second branch destination associative memory and the branch destination read from the first branch destination associative memory. Since both instructions at the destination address are read, there is a problem that a branch destination instruction is also read for a branch instruction that is unlikely to be executed.

Accordingly, a third object of the present invention is to provide a method for detecting the first branch destination associative memory and the first branch destination associative memory when the second and third branch associative memories are registered at different branch instruction addresses.
Of the branch instruction address read from the second branch destination associative memory and the branch instruction address read from the second branch destination associative memory to determine the execution order, and to read the instruction by the already started second branch destination associative memory. The present invention is to provide an information processing apparatus of a branch destination associative memory system capable of suspending the processing of the above and not reading a branch destination instruction of a branch instruction which is unlikely to be executed.

[0032]

In order to achieve the first object, an information processing apparatus according to the present invention comprises a first branch destination associative memory having a low speed and a large capacity and a second branch destination associative memory having a high speed and a small capacity. Means for detecting whether or not the instruction address of a branch instruction contained in the prefetched instruction word in prefetching the instruction word is registered in the first branch destination associative memory; Prediction is performed by means for detecting whether or not the information has been registered, and the prediction information is held independently.
When a branch instruction not registered in the branch destination associative memory is taken, the instruction address and the branch destination address of the branch instruction are registered in the first branch destination associative memory and registered in the second branch destination associative memory. When a branch instruction that has not been taken is taken, the instruction address and the branch destination address of the branch instruction are registered in the second branch destination associative memory, and the branch instruction registered in the second branch destination associative memory is branched. Means for deleting the registration of the second branch destination associative memory when the branch is not taken, and deleting the registration of the first branch destination associative memory when the branch instruction registered in the first branch destination associative memory is not taken. Thus, unnecessary registration / deletion is suppressed, and highly accurate branch prediction is performed.

In order to achieve the second object, an information processing apparatus according to the present invention is arranged such that the instruction address information of the branch instruction included in the prefetched instruction word in the prefetching of the instruction word is the first address.
If the registration is detected by both of the means for detecting whether or not the branch instruction is registered in the branch destination associative memory and the means for detecting whether or not the branch instruction is stored in the second branch associative memory, the detected branch instruction address is deleted. Each of them is held independently, and it is compared whether the branch instruction address detected in the first branch destination associative memory matches the branch instruction address detected in the second branch destination associative memory, and the comparison results are identical. First
Means for suppressing instruction reading by the associative memory of the branch destination, so that unnecessary instruction reading is not performed.

In order to achieve the third object, an information processing apparatus according to the present invention is arranged such that the instruction address information of the branch instruction included in the prefetched instruction word in the prefetching of the instruction word is the first address.
If the registration is detected in both of the branch destination associative memory and the means for detecting whether or not the branch instruction is registered in the second branch associative memory, the detected branch instruction addresses are respectively The branch instruction address detected in the first branch destination associative memory is compared with the branch instruction address detected in the second branch destination associative memory. Means for interrupting the instruction read processing of the branch instruction by the second branch address associative memory when the address is smaller than the branch instruction address detected in the second branch address associative memory. It is characterized by not being performed.

[0035]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described in more detail with reference to FIGS. FIG. 1 is a block diagram of an information processing apparatus of a branch destination associative memory system that speeds up processing of a branch instruction by branch prediction according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an address register A for storing an instruction address of an instruction word to be read, and reference numeral 2 denotes an address register B for receiving the contents of the address register A1. 3 is a branch instruction address register for storing an instruction address for a past branch instruction, and 4 is a branch instruction address register 3.
A branch destination address register 5 for storing the branch destination address corresponding to the branch instruction address 5 is an address comparison circuit A for comparing the instruction address of the address register A1 with the branch instruction address of the branch instruction address register 3. Similarly, reference numeral 8 denotes a branch instruction address array in which an instruction address corresponding to a past branch instruction is stored, 9 denotes a branch destination address array in which the branch destination address corresponding to the branch instruction address of the branch instruction address array 8 is stored, 10 Is an address comparison circuit B for comparing the instruction address of the address register B2 with the branch instruction address of the branch instruction address array 8, and 11 is a branch destination address array register for receiving the branch destination address read from the branch destination address array 9. Reference numeral 12 denotes a large-capacity first associative memory having a RAM structure, which comprises an address register B2, a branch instruction address array 8, and a branch instruction address array 9.
Reference numeral 13 denotes a small-capacity second branch-address associative memory having a register configuration, which comprises a branch instruction address register 3 and a branch destination address register 4.

Reference numeral 14 denotes an instruction read control circuit for performing prefetch control of instruction words, and 16 denotes a branch control circuit for performing instruction branch control. Reference numeral 15-1 denotes a prediction information holding circuit A for holding branch prediction information in the second branch destination associative memory 13 corresponding to a pipeline stage of a branch instruction, and 17-1 denotes prediction information in the second branch destination associative memory 13. And a branch determination comparison circuit A 18-1 for comparing whether or not the branch determination matches with the branch determination is a registration deletion control circuit A for the second branch destination associative memory 13. 15-2 is a prediction information holding circuit B for holding branch prediction information in the first branch destination associative memory 12 corresponding to a pipeline stage of a branch instruction, and 17-2 is prediction information in the first branch destination associative memory 12. A branch determination comparison circuit B 18-2 for comparing whether or not the branch determination matches with the branch determination is a registration deletion control circuit B for the first branch destination associative memory 12. 19 is a branch instruction address selection circuit for selecting an address from the address register A1 or the registration / deletion control circuit B18-2.

Next, the registration control of the first branch destination associative memory and the second branch destination associative memory in the information processing apparatus according to the embodiment of the present invention shown in FIG. 1 will be described with reference to the time chart of FIG. . FIG. 2 is a time chart of a pipeline control flow for explaining the operation of the information processing apparatus according to the present embodiment. In the processing of the instructions by the pipeline control, it is assumed that the branch instruction 1 is taken and the instruction sequence following the branch destination instruction 2 is processed. The illustrated example is the first branch destination associative memory 1
Although the instruction address of the branch instruction 1 is not registered in both the second and the second branch destination associative memories 13, when the branch instruction 1 is taken, the second branch destination associative memory and the first branch destination associative memory are stored. Registration operation.

Under the control of the instruction read control circuit 14, the instruction reading of the instruction word including the branch instruction 1 is started in cycle 1, and the instruction address of the instruction word to be read is generated in cycle 2. In cycle 3, the instruction address generated in cycle 2 is received from line 100 by address register A1,
The contents of the address register A1 and the contents of the branch instruction address register 3 in the second branch destination associative memory 13 are compared by an address comparison circuit A5, and the instruction address of the branch instruction 1 is registered in the branch instruction address register 3. Is detected. In this case, since it is not detected that the branch instruction 1 has been registered, the address comparing circuit A5 sends the branch failure prediction signal to the prediction information holding circuit A15-1 by the line 121.
Out via. In cycle 4, the prediction information holding circuit A15-1 receives the branch failure prediction signal of the line 121, and in accordance with the pipeline stage of the branch instruction 1, sends the branch failure prediction signal in cycle 11 (E stage of branch instruction 1).
Hold up to

On the other hand, in cycle 4, the instruction address of the instruction word to be read is received from the address register A1 by the address register B2, and the address of the address register B2 and the first
Is compared with the branch address of the branch instruction address array 8 in the branch destination associative memory 12 by the address comparison circuit B10 to detect whether the instruction address of the branch instruction 1 is registered in the branch instruction address array 11. In this case, since the branch instruction 1 is not registered in the branch instruction address array 11, the address comparison circuit B10 sends out a branch failure prediction signal to the prediction information holding circuit B15-2 via the line 122. In cycle 5, the prediction information holding circuit B15-2 receives the branch failure prediction signal of the line 122 and outputs the branch instruction 1
Is held until cycle 11 (E stage of branch instruction 1).

In cycle 11, the branch control circuit 16 determines whether the branch of the branch instruction 1 is taken or not. In this case, the branch is taken.
6 is sent to the branch judgment / comparison circuit A17-1. Similarly, a branch establishment signal is sent to the branch judgment / comparison circuit B17-2. The branch determination / comparison circuit A17-1 receives, via the line 123, the branch failure prediction signal held by the prediction information holding circuit A15-1 until cycle 11, and receives the branch determination signal and the branch failure prediction signal received from the branch control circuit 16. Is compared. In this case, the branch is not taken. However, since the branch is taken, the prediction fails, and it is necessary to register the instruction address of the branch instruction 1 and the branch destination address in the second branch destination associative memory 13. A17-1 generates a registration signal of the second branch destination associative memory 13, and sends it to the registration deletion control circuit A18-1. Further, the branch determination comparison circuit B
17-2 is a cycle 1 in the prediction information holding circuit B15-2.
The branch not taken prediction signal held to 1 is received via the line 124, and the branch taken signal received from the branch control circuit 16 is compared with the branch not taken prediction signal. In this case, the branch is not taken. However, since the branch is taken, the prediction fails, and it is necessary to register the instruction address and the branch destination address of the branch instruction 1 in the first branch destination associative memory 12. 17-2 generates a registration signal for the first branch destination associative memory and sends it to the registration deletion control circuit B18-2.

The registration / deletion control circuit A18-1 receives the registration signal from the branch determination / comparison circuit 17-1, receives the instruction address of the branch instruction 1 and the branch destination address from the branch control circuit 16, and stores the registration signal of the branch instruction 1 The branch instruction address and the branch destination address are sent to the second branch destination associative memory 13.
Further, the registration / deletion control circuit B18-2 receives the registration signal from the branch determination / comparison circuit B17-2, receives the instruction address and the branch destination address of the branch instruction 1 from the branch control circuit 16, and receives the registration signal of the branch instruction 1 and the branch signal. The instruction address and the branch destination address are sent to the first branch destination associative memory 12. Then, in cycle 14, the branch instruction address register 3 and the branch destination address register 4 in the second branch destination associative memory 13 are read.
Then, the writing of the instruction address of the branch instruction 1 and the branch destination address are completed. Further, in the first branch destination associative memory 12, the instruction address of the branch instruction 1 is received in the address register B2, and a part of the branch instruction address is used as an address indicating a location to be registered in the first branch destination associative memory 12. The branch instruction address and the branch destination address are written to the branch instruction address array 8 and the branch destination address array 9, and the writing of the branch instruction address and the branch destination address to the first branch destination associative memory 12 is completed in cycle 15.

As described above, in the embodiment of the present invention, the first
Is written to the branch destination associative memory 12 and the second branch destination associative memory 13 according to the prediction information of the first branch destination associative memory 12 and the second branch destination associative memory 13, respectively.
Registration is performed without being affected by the other prediction.

Next, the operation of deleting the first branch destination associative memory 12 and the second branch destination associative memory 13 in the information processing apparatus of this embodiment of FIG. 1 will be described with reference to the time chart of FIG. . Instruction processing by pipeline control is to process an instruction sequence following instruction 2 when branch instruction 1 is not taken. In the example of FIG. 3, when the branch instruction 1 registered in both the first branch destination associative memory 12 and the second branch destination associative memory 13 is not taken, the first branch destination associative memory 12 and The second branch destination associative memory 13 is deleted.

In cycle 1, the instruction reading of the instruction word including the branch instruction 1 is started, the instruction address of the instruction word to be read in cycle 2 is generated, and in cycle 3, the instruction address generated in cycle 2 is sent from the line 100 to the address. The address received by the register A1, the address of the address register A1 and the address of the branch instruction address register 3 in the second branch destination associative memory 13 are compared by an address comparison circuit A5. Detect if it is registered in. In this case, it is detected that the branch instruction 1 is registered, and the address comparison circuit A5
Sends a branch taken prediction signal to the prediction information holding circuit A15-1 via the line 121. In cycle 4, the branch taken prediction signal of the line 121 is received by the prediction information holding circuit A15-1,
The branch taken prediction signal is held until cycle 11 (E stage of branch instruction 1) in accordance with the pipeline stage of branch instruction 1.

On the other hand, in cycle 4, the instruction address of the instruction word read from the address register A1 is received by the address register B2, and the address of the address register B2 and the branch instruction address array 8 in the first branch destination associative memory 12 are read.
Is compared with the address in the address comparison circuit B10.
The instruction address of the branch instruction 1 is the branch instruction address array 8
Detects whether it is registered in. In this case, it is detected that the branch instruction 1 is registered in the branch instruction address array 8, and the address comparison circuit B10 sends a branch establishment prediction signal to the prediction information holding circuit B15-2 via the line 122. In cycle 5, the branch taken prediction signal of line 122 is received by the prediction information holding circuit B15-2, and the branch taken prediction signal is sent to cycle 11 (E stage of branch instruction 1) in accordance with the pipeline stage of branch instruction 1. Hold.

In cycle 11, the branch control circuit 16 determines whether the branch instruction 1 is taken or not. In this case, the branch is not taken. Therefore, the branch not-taken signal is sent from the branch control circuit 16 to the branch judgment comparison circuit A17. -1. Similarly, a branch failure signal is also sent to the branch determination / comparison circuit B17-2. The branch determination / comparison circuit A17-1 receives via the line 1234 the branch taken prediction signal held by the prediction information holding circuit A15-1 up to cycle 11, and receives the branch not taken signal from the branch control circuit 16, and A comparison is made with the establishment prediction signal. This case is a branch taken prediction,
Since the branch was not taken, the prediction failed, and it was necessary to delete the instruction address and the branch destination address of the branch instruction 1 from the second branch destination associative memory 13, and the branch determination comparison circuit A1
At 7-1, a delete signal of the second branch destination associative memory 13 is generated and sent to the registration / deletion control circuit A18-1. Further, the branch determination comparison circuit B17-2 includes a prediction information holding circuit B15.
At -2, the branch taken prediction signal held up to the cycle 11 is received via the line 124, and the branch not taken signal is received from the branch control circuit 16, and is compared with the branch taken prediction signal. This case is a branch taken prediction, but the prediction fails because the branch was not taken, and the instruction address and the branch destination address of the branch instruction 1 need to be deleted from the first branch destination associative memory 12. At 17-2, a delete signal for the first branch destination associative memory 12 is generated and sent to the registration / deletion control circuit B18-2.

The registration / deletion control circuit A18-1 receives the deletion signal from the branch judgment / comparison circuit A17-1, and outputs the instruction address of the branch instruction 1 and the branch destination address to the branch control circuit 16-1.
And sends a delete signal of the branch instruction 1 to the second branch destination associative memory 13. Also, the registration deletion control circuit B18-2
Receives the delete signal from the branch determination / comparison circuit B17-2, receives the instruction address of the branch instruction 1 from the branch control circuit 16,
The delete signal of the branch instruction 1 and the branch instruction address are sent to the first branch destination associative memory 12. Then, in cycle 12,
The deletion of the instruction address of the branch instruction 1 and the branch destination address from the second branch destination associative memory 13 is completed. Also,
In the first branch destination associative memory 12, the address register B2
Receives the instruction address of the branch instruction 1 and deletes the branch instruction address and the branch destination address using the branch instruction address as the delete address of the first branch destination associative memory 12. The deletion of the branch instruction address and the branch destination address for is completed.

As described above, in the embodiment of the present invention, the first
Is deleted from the branch destination associative memory 12 and the second branch destination associative memory 13 in accordance with the prediction information of the first branch destination associative memory 12 and the second branch destination associative memory 13, thereby affecting the other prediction. The deletion is performed without any excess or shortage.

FIG. 4 shows another embodiment of the present invention. In the case where the first branch destination associative memory and the second branch destination associative memory are detected at the same branch instruction address, the reading of one instruction is suppressed. FIG. 9 is a block diagram of an information processing apparatus characterized by accelerating instruction processing. In FIG. 4, reference numeral 20 denotes a read processing suppressing circuit provided in the present embodiment, and the other configuration is the same as that of FIG.

FIG. 5 shows the first branch destination associative memory 12 and the first branch destination associative memory 12.
5 is a time chart of the instruction processing in the information processing apparatus of FIG. 4 including a circuit 20 for suppressing reading of one instruction when a branch instruction is detected at the same branch instruction address in the branch destination associative memory 13 of FIG. In FIG. 5, the instruction processing by the pipeline control is such that the branch instruction 1 is taken and the branch destination instruction 2 is taken.
It is assumed that the branch instruction 1 is registered in both the first branch destination associative memory 12 and the second branch destination associative memory 13.

In cycle 1, a process of reading an instruction sequence including the branch instruction 1 is started. In cycle 3, the instruction address of the instruction word to be read from the line 100 to the address register A1 is received, and the contents of the address register A1 and the second branch are received. The contents of the branch instruction address register 3 in the associative memory 13 are compared by the address comparison circuit A5, and it is detected whether or not the instruction address of the branch instruction 1 is registered in the branch instruction address register 3. In this case, since it is detected that the branch instruction 1 is registered, the address comparison circuit A5 sends the detection signal to the instruction read control circuit 14, and the branch destination address corresponding to the branch instruction detected at the same time is It is read from the branch destination address register 4 and sent to the instruction read control circuit 14. Further, the address comparison circuit A5
Sends the detection signal and the detected branch instruction address to the read processing inhibiting circuit 20. In cycle 4, the instruction read address is received by the address register B2, and the contents of the address register B2 and the contents of the branch instruction address array 8 in the first branch destination associative memory 12 are compared with the address comparison circuit B.
A comparison is made at 10 to detect whether the instruction address of the branch instruction 1 is registered in the branch instruction address array 8. In this case, since it is detected that the branch instruction 1 has been registered, the address comparison circuit B10 compares the detection signal and the detected branch instruction address with the read processing suppression circuit 2
Send to 0.

The read processing suppressing circuit 20 compares the branch instruction address received from the address comparison circuit A5 in cycle 3 with the branch instruction address received from the address comparison circuit B10 in cycle 4. In this case, since the branch instruction address received from the address comparison circuit A5 matches the branch instruction address received from the address comparison circuit B10, the instruction read processing by the second branch destination associative memory 13 has already been performed. And the read processing suppression circuit 20 generates a read processing suppression signal for suppressing the instruction read processing by the first branch destination associative memory 12, and detects the branch instruction 1 by the first branch destination associative memory 12. The transmission of the signal to the instruction read control circuit 14 is suppressed.

As described above, in this embodiment, when it is detected that the instruction address of the same branch instruction is registered in both the first branch destination associative memory 12 and the second branch destination associative memory 13 , The first in the instruction read control circuit 14
The reading processing of the branch destination instruction by the branch destination associative memory 12 is suppressed, and unnecessary instruction reading is not performed, so that the number of accesses to the memory can be reduced.

FIG. 6 shows still another embodiment of the present invention.
When the first branch destination associative memory and the second branch destination associative memory are detected at different branch instruction addresses, the execution order of the instructions is determined, instruction reading of a later executed branch instruction is suppressed, and instruction processing is performed. FIG. 2 is a block diagram of an information processing apparatus characterized by speeding up the processing. In FIG. 6, reference numeral 21 denotes a read processing interruption circuit particularly provided in the present embodiment, and other configurations are the same as those in FIG.

FIG. 7 shows the first branch destination associative memory 12 and the second branch destination associative memory 12.
If the branch instruction address of a different branch instruction is detected in the branch destination associative memory 13, the execution order of the branch instruction is determined,
7 is a time chart of instruction processing in the information processing apparatus of FIG. 6 having a circuit 21 for interrupting one instruction read. In FIG. 7, in the processing of the instruction by the pipeline control, the branch instruction 1 is taken and the branch instruction 1 is executed.
The instruction address and the branch destination address of the branch instruction 1 are registered in the branch destination associative memory 12, and the instruction address and the branch destination address of the branch instruction 1 are not registered in the second branch destination associative memory 13. It is assumed that the instruction address and the branch destination address of the branch instruction having the branch instruction address larger than the instruction address of the branch instruction 1 are registered.

In cycle 1, the process of reading an instruction string including branch instruction 1 is started. In cycle 3, the instruction address of the instruction word to be read from line 100 to address register A1 is received, and the contents of address register A1 and the second branch destination are read. The contents of the branch instruction address register 3 in the associative memory 13 are compared by the address comparison circuit A5 to detect whether the instruction address of the branch instruction 1 is registered in the branch instruction address register 3. In this case, it is detected that a branch instruction different from the branch instruction 1 is registered, and the address comparison circuit A5 sends the detection signal to the instruction read control circuit 14. At the same time, the branch destination address corresponding to the detected branch instruction is read from the branch destination address register 4, and
The instruction is sent to the instruction read control circuit 14. Further, the address comparison circuit A5 sends the detection signal and the detected branch instruction address to the read processing inhibition circuit 20 and the read processing interruption circuit 21. In cycle 4, the instruction address of the instruction read from the address register A1 is received in the address register B2, and the contents of the address register B2 and the first address are read.
The content of the branch instruction address array 8 in the branch destination associative memory 12 is compared by the address comparison circuit B10 to detect whether the instruction address of the branch instruction 1 is registered in the branch instruction address array 8. In this case, since it is detected that the branch instruction 1 is registered, the address comparison circuit B10 sends the detection signal and the detected branch instruction address to the read processing inhibition circuit 20 and the read processing inhibition circuit 21, respectively. I do. Also, the detected branch instruction 1
Is read from the branch destination address array 9 and sent to the branch destination address array register 14.

The read processing suppression circuit 20 compares the branch instruction address received from the address comparison circuit A5 in cycle 3 with the branch instruction address received from the address comparison circuit B10 in cycle 4, and confirms that the comparison results are not identical. To detect this, the detection signal that detects that the instruction address of the branch instruction 1 is registered in the first branch destination associative memory 12 is sent to the instruction readout control circuit 14 without suppression.

The read processing inhibiting circuit 21 compares the branch instruction address received from the address comparison circuit A5 in cycle 3 with the branch instruction address received from the address comparison circuit B10 in cycle 4. In this case, since the branch instruction address received from the address comparison circuit B10 is smaller than the branch instruction address received from the address comparison circuit A5, the execution order of the branch instructions is the first branch destination associative memory 12
The branch instruction registered in the second branch destination associative memory 13 in which the branch instruction registered in the second branch destination associative memory 13 in which the reading process of the branch destination instruction has already been started is less likely to be executed. Therefore, the read processing interruption circuit 21 generates a read processing interruption signal for interrupting the instruction read processing by the second branch destination associative memory 13, and sends the read processing interruption signal to the instruction read control circuit 14.
In cycle 5, the instruction read control circuit 14
The second branch destination associative memory 13 is read by the read processing interruption signal.
Interrupts the instruction reading process. Further, the instruction read control circuit 14 controls the branch destination address array register 11
The branch destination instruction of the branch instruction 1 is read based on the branch destination address received from.

As described above, in the present embodiment, when it is detected that the instruction addresses of different branch instructions are registered in the first branch destination associative memory 12 and the second branch destination associative memory 13, the first The first branch destination associative memory 1 is compared with the branch instruction address detected in the branch destination associative memory 12 and the branch instruction address detected in the second branch destination associative memory 13.
If the branch instruction address detected in step 2 is smaller, the process of reading the branch destination instruction by the second branch destination associative memory 13 is interrupted, and only the reading of the branch target instruction by the first branch destination associative memory 12 is performed. By doing so, unnecessary instruction reading is not performed, and the number of accesses to the memory can be reduced.

[0060]

As described above, according to the present invention, registration and deletion of the first branch destination associative memory and the second branch destination associative memory are independently performed, so that the other branch is not affected by the prediction. It is possible to perform registration deletion without excess / shortage, unnecessary registration / deletion is suppressed, and highly accurate branch prediction can be performed.

According to the present invention, it is detected that the instruction address of the branch instruction is registered in both the first branch destination associative memory and the second branch destination associative memory, and the detected branch instruction address is detected. Is suppressed in the first branch destination associative memory and the second branch destination associative memory, and the number of accesses to the memory can be suppressed by not reading out unnecessary instructions. Can be reduced.

Further, according to the present invention, it is detected that the instruction address of the branch instruction is registered in both the first branch destination associative memory and the second branch destination associative memory, and the first branch destination associative memory is detected. Comparing the branch instruction address detected in the storage with the branch instruction address detected in the second branch destination associative memory;
When the branch instruction address detected in the first branch destination associative memory is smaller, the instruction read processing by the second branch destination associative memory is interrupted, and unnecessary instruction read processing is not performed. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart in a case where registration to a branch destination associative memory is performed in the first embodiment.

FIG. 3 is a time chart when deleting a branch destination associative memory in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a time chart when an instruction is read out by a branch destination associative memory in the second embodiment.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a time chart when an instruction is read out by associative storage of a branch destination in the third embodiment.

FIG. 8 is a general block diagram of a conventional example of a branch destination associative storage type information processing apparatus.

FIG. 9 is a time chart for performing an instruction read when an instruction address of a branch instruction is registered only in the first branch destination associative memory in the conventional example.

FIG. 10 is a time chart for performing an instruction read when an instruction address of a branch instruction is registered in a second branch destination associative memory in a conventional example.

FIG. 11 is a time chart when registering in a branch destination associative memory in a conventional example.

FIG. 12 is a time chart when deleting a branch destination associative memory in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address register A 2 Address register B 3 Branch instruction address register 4 Branch destination address register 5 Address comparison circuit A 8 Branch instruction address array 9 Branch destination address array 10 Address comparison circuit B 11 Branch destination address array register 12 First branch destination Associative memory 13 Second branch destination associative memory 14 Instruction reading control circuit 15-1, 15-2 Prediction information holding circuits A, B 17-1, 17-2 Branch judgment comparing circuits A, B 18-1, 18-2 Registration / deletion control circuits A and B 19 Branch instruction address selection circuit 20 Read processing suppression circuit 21 Read processing interruption circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Hiraoka 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Ultra-SII Systems Co., Ltd. (72) Inventor Kazuo Ojima Kanagawa 1 Horiyamashita, Hadano-shi, General-purpose Computer Business Division, Hitachi, Ltd. (72) Inventor Tomonaga Itoi 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture, General-purpose Computer Business Division, Hitachi, Ltd. 1 Ichihoriyamashita F-term in the General-purpose Computer Division, Hitachi, Ltd. 5B013 BB11 BB15

Claims (3)

[Claims] 1. An information processing apparatus for reading a branch instruction ahead of time by using a branch destination associative memory to speed up the processing of the branch instruction. First branch destination associative storage means for storing a branch destination address of a branch instruction; second branch destination associative storage means smaller in size but faster than the first branch destination associative storage means; A first detecting means for detecting whether or not the instruction address of the branch instruction included in the prefetched instruction word is registered in the first branch destination associative memory; Second detecting means for detecting whether or not the instruction address of the branch instruction which has been registered is registered in the second branch destination associative memory; and Instruction add When it is detected that the branch instruction is registered, first detection means for comparing the detection result with a branch determination result indicating whether the branch instruction is taken or not taken; Is detected in the associative memory of the branch destination, the result of the detection is compared with a branch determination result indicating whether the branch instruction is taken or not taken. Means, first registration / deletion means for registering / deleting the first branch destination associative memory according to the comparison result of the first comparison means, and second branch destination associative memory according to the comparison result of the second comparison means. Information on a branch destination associative memory system, comprising a second registration / deletion means for performing registration / deletion, wherein registration / deletion to / from the first branch destination associative memory and the second branch destination associative memory is performed independently. Processing equipment. 2. The method according to claim 1, wherein the prefetching of the instruction word detects that the instruction address of the branch instruction included in the prefetched instruction word is registered in both the first branch destination associative memory and the second branch destination associative memory. In this case, the branch instruction address detected in the first branch destination associative memory is compared with the branch instruction address detected in the second branch destination associative memory. 2. The information processing apparatus according to claim 1, further comprising means for suppressing reading of an instruction by a branch destination address read from the first associative memory, and suppressing duplicate instruction reading. 3. The method according to claim 1, wherein the prefetching of the instruction word detects that the instruction address of the branch instruction included in the prefetched instruction word is registered in both the first branch destination associative memory and the second branch destination associative memory. In this case, the branch instruction address detected in the first branch destination associative memory is compared with the branch instruction address detected in the second branch destination associative memory, and the comparison result is stored in the first branch destination associative memory. 2. The method according to claim 1, further comprising: means for interrupting the instruction read by the branch destination address read from the second branch destination associative memory when the detected branch instruction address is smaller, thereby suppressing unnecessary instruction read. An information processing apparatus using a branch destination associative storage method according to claim 1.