JP2000223635A - Semiconductor element package - Google Patents
Semiconductor element packageInfo
- Publication number
- JP2000223635A JP2000223635A JP11356438A JP35643899A JP2000223635A JP 2000223635 A JP2000223635 A JP 2000223635A JP 11356438 A JP11356438 A JP 11356438A JP 35643899 A JP35643899 A JP 35643899A JP 2000223635 A JP2000223635 A JP 2000223635A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- lower terminal
- semiconductor die
- semiconductor
- insulating housing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子パッケ
ージに関し、より詳細にはプラスチックハウジングと導
電性タブとを有する新奇なパッケージに関する。The present invention relates to a semiconductor device package, and more particularly, to a novel package having a plastic housing and a conductive tab.
【０００２】なお、この出願は米国特許出願第６０／１
１２３２６号を基礎とする優先権主張を伴うものであ
り、その開示内容の全体がこれを参照することによっ
て、本明細書に組み入れられる。This application is disclosed in US Patent Application No. 60/1.
No. 12326, the disclosure of which is hereby incorporated by reference in its entirety.
【０００３】[0003]
【従来の技術】ダイオードの如き個々の半導体素子は、
高電流用途に対して種々のパッケージスタイルで利用可
能である。例えば、Ｔ０−２４７パッケージとして知ら
れている標準パッケージは、高電流用途に対して低コス
トで利用可能であるが、高電流素子はより高価な金属ケ
ースや電源モジュール内に概ね収納されている。2. Description of the Related Art Individual semiconductor devices, such as diodes,
Available in various package styles for high current applications. For example, the standard package, known as the T0-247 package, is available at low cost for high current applications, but the high current elements are generally housed in more expensive metal cases or power modules.
【０００４】[0004]
【発明が解決しようとする課題】金属パッケージや電源
モジュールよりも低コストな高電流用パッケージおよび
Ｔ０−２４７パッケージよりも高電流容量の低コストな
パッケージに対する要求がある。特に、およそ４５ボル
トの定格電圧と１００から１７５のアンペアの定格電流
を有するショットキーダイオードのための低コストのパ
ッケージに対する要求がある。同様に、およそ１２００
ボルトまでか、あるいはそれ以上の逆電圧と、７０から
８５アンペアの順方向電流とを有する高速回復ダイオー
ドおよび標準整流器のためのこのようなパッケージに対
する要求がある。There is a need for a high-current package lower in cost than a metal package or a power supply module, and a low-cost package having a higher current capacity than the T0-247 package. In particular, there is a need for a low cost package for a Schottky diode having a rated voltage of approximately 45 volts and a rated current of 100 to 175 amps. Similarly, about 1200
There is a need for such packages for fast recovery diodes and standard rectifiers with reverse voltages up to or higher than volts and forward currents of 70 to 85 amps.
【０００５】[0005]
【発明の目的】本発明の目的は、かさばらず、優れた半
導体ダイ−フットプリント比を有し、頑丈で低コストな
高電流用途に適した半導体素子パッケージを提供するこ
とにある。OBJECTS OF THE INVENTION It is an object of the present invention to provide a semiconductor device package which is not bulky, has an excellent semiconductor die-to-footprint ratio, is robust and is suitable for low-current high-current applications.
【０００６】[0006]
【課題を解決するための手段】本発明による半導体素子
パッケージは、第１の平面上に配された厚みがほぼ均一
な導電性の下部端子と、この下部端子の上面に支持され
て電気的に接続する下面を有する少なくとも１つの半導
体ダイと、前記下部端子よりも厚みが薄く、前記下部端
子の前記第１の平面の上方のこれと平行な平面上に配さ
れると共に下部端子から電気的に絶縁され、当該下部端
子の幅とほぼ等しい幅を有すると共に該下部端子の本体
の少なくとも一部からその長手方向に延在する平坦なタ
ブと、導電性の前記タブに対して前記半導体ダイの上面
を接続する接続手段と、前記半導体ダイの上面および前
記接続手段および前記半導体タブの前記下部端子に隣接
する第１の部分のみおよび前記下部導電性端子の少なく
とも一部を取り囲んで成形されてこれらを封入する絶縁
ハウジングとを具え、前記下部端子および前記タブが前
記半導体ダイの外部端子を形成することを特徴とするも
のである。A semiconductor device package according to the present invention comprises a conductive lower terminal having a substantially uniform thickness disposed on a first plane, and an electrically supported lower terminal supported on the upper surface of the lower terminal. At least one semiconductor die having a lower surface to be connected, and having a thickness smaller than the lower terminal, disposed on a plane above and parallel to the first plane of the lower terminal, and electrically connected to the lower terminal. A flat tab that is insulated, has a width approximately equal to the width of the lower terminal, and extends longitudinally from at least a portion of the body of the lower terminal; and a top surface of the semiconductor die relative to the conductive tab. Connecting only the first portion of the upper surface of the semiconductor die and the connecting portion and the semiconductor tab adjacent to the lower terminal and at least a portion of the lower conductive terminal. In is formed comprising an insulating housing enclosing these, the lower terminals and the tabs are characterized in that to form the external terminals of the semiconductor die.
【０００７】この新奇な半導体素子パッケージは、１つ
あるいはそれ以上の半導体ダイを受容するヒートシンク
部と、このヒートシンク部の反対側に延在してヒートシ
ンク部の平面から変位した平面上の薄く平坦なタブとを
有するリードフレームに設けられる。ヒートシンク部お
よびその上に設けられる半導体ダイは、プラスチックハ
ウジングの一つの壁面を貫通する延在部およびこれと反
対側の絶縁ハウジングの壁面から突出する薄く平坦なタ
ブとを持ったヒートシンクと共にプラスチックにより封
入される。絶縁ハウジングから露出状態で突出する薄い
タブは、高電流能力の最適な接続と効率的な熱の引き込
みとをもたらす。[0007] The novel semiconductor device package includes a heat sink portion for receiving one or more semiconductor dies, and a thin, flat surface extending on the opposite side of the heat sink portion and displaced from the plane of the heat sink portion. It is provided on a lead frame having a tab. The heatsink part and the semiconductor die provided thereon are encapsulated in plastic with a heatsink with an extension extending through one wall of the plastic housing and a thin flat tab protruding from the wall of the insulating housing on the opposite side. Is done. The thin tabs projecting out of the insulated housing provide optimal connection of high current capability and efficient heat draw.
【０００８】[0008]
【発明の実施の形態】本発明による半導体素子パッケー
ジにおいて、タブの第１の部分を覆って成形される絶縁
ハウジングの側面に隣接する位置の両側に第１および第
２の応力緩和用切欠を設け、タブから絶縁ハウジングへ
の応力の伝達を減少させるようにしてもよい。DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device package according to the present invention, first and second stress relief notches are provided on both sides of a position adjacent to a side surface of an insulating housing formed over a first portion of a tab. The transmission of stress from the tub to the insulating housing may be reduced.
【０００９】また、下部端子の一部を絶縁ハウジングか
ら突出させ、この下部端子の一部の中央部分および絶縁
ハウジング空突出するタブの中央部にこれらを貫通する
開口をそれぞれ設けるようにしてもよい。Further, a part of the lower terminal may be protruded from the insulating housing, and a central portion of the part of the lower terminal and a central part of the tab protruding from the insulating housing may be provided with openings therethrough. .
【００１０】タブの自由端にここから突出する複数のプ
ラグ−イン差し込みフィンガを設けるようにしてもよ
い。The free end of the tab may be provided with a plurality of plug-in insertion fingers projecting therefrom.
【００１１】半導体ダイがダイオードとＭＯＳゲート素
子とサイリスタとからなるグループから選択される素子
であってよい。[0011] The semiconductor die may be an element selected from the group consisting of a diode, a MOS gate element, and a thyristor.
【００１２】タブがこれと同一平面上で当該タブおよび
下部端子から絶縁された接続フィンガをその側方に有
し、半導体ダイがその上面にゲート電極を有するＭＯＳ
ゲート素子と、ゲート電極に接続フィンガを電気的に接
続する絶縁ハウジング内に配置された第２の接続手段と
を設けるようにしてもよい。A MOS transistor having, on the same side thereof, connection fingers insulated from the tab and the lower terminal on the same plane, and a semiconductor die having a gate electrode on an upper surface thereof;
A gate element and second connection means arranged in an insulating housing for electrically connecting the connection finger to the gate electrode may be provided.
【００１３】さらに、半導体ダイがダイオードであって
もよい。Further, the semiconductor die may be a diode.
【００１４】[0014]
【実施例】本発明による半導体素子パッケージの実施例
について、図１〜図１７を参照しながら詳細に説明する
が、本発明はこのような実施例に限らず、これらをさら
に組み合わせたり、この明細書の特許請求の範囲に記載
された本発明の概念に包含されるべき他の技術にも応用
することができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device package according to the present invention will be described in detail with reference to FIGS. 1 to 17. However, the present invention is not limited to such embodiments, and they may be further combined or described. It is also applicable to other technologies that are to be encompassed by the inventive concept described in the appended claims.
【００１５】図１および図２をまず参照すると、本実施
例における半導体素子パッケージ３０が示されており、
これはトランスファー成形による絶縁ハウジング（以
下、プラスチックハウジングともいう）３３の側面３２
を超えて延在する大容量の導電性下部端子（以下、電極
ともいう）３１を有する。平坦なタブ形式の第２の電極
（以下、タブともいう）３４は、側面３２の反対側にあ
って、これと平行な絶縁ハウジング３３の側面３５から
延在している。タブ３４は、絶縁ハウジング３３の側面
３５とほぼ同じ幅を持ち、そこに取り付け開口部３６
と、その外側の自由端にプリント回路板差し込みフィン
ガ（以下、プラグ−インフィンガともいう）３７ａ,３
７ｂ,３７ｃとを有する。後述するように、電極３１,３
４は、絶縁ハウジング３３内に収容される半導体ダイの
上面および下面にそれぞれ連結される。この半導体ダイ
は、任意の希望する半導体素子、例えばショットキーダ
イオード、あるいは別な任意の２つの端末素子であって
もよい。しかしながら、後述するように、この半導体ダ
イはコントロール電極、例えば絶縁ハウジング３３から
同様に突出するコントロール電極を覆うパワーＭＯＳＦ
ＥＴダイを有することも可能である。端子３１は、そこ
に取り付け開口部３９を有する。Referring first to FIGS. 1 and 2, there is shown a semiconductor device package 30 in the present embodiment.
This is a side surface 32 of an insulating housing (hereinafter also referred to as a plastic housing) 33 formed by transfer molding.
And a large-capacity conductive lower terminal (hereinafter, also referred to as an electrode) 31 extending beyond. A flat tab-shaped second electrode (hereinafter, also referred to as a tab) 34 is opposite to the side surface 32 and extends from a side surface 35 of the insulating housing 33 parallel to the side surface 32. The tab 34 has approximately the same width as the side surface 35 of the insulating housing 33 and has a mounting opening 36 therein.
And a printed circuit board insertion finger (hereinafter, also referred to as a plug-in finger) 37a, 3
7b and 37c. As described later, the electrodes 31, 3
4 are respectively connected to the upper and lower surfaces of the semiconductor die housed in the insulating housing 33. The semiconductor die may be any desired semiconductor device, such as a Schottky diode, or any other two terminal devices. However, as will be described later, this semiconductor die is a power MOSF which covers a control electrode, for example a control electrode which also protrudes from the insulating housing 33.
It is also possible to have an ET die. Terminal 31 has a mounting opening 39 therein.
【００１６】タブ３４の重要な特長として、プラスチッ
クハウジング３３に接近して隣接する２つの応力緩和用
切欠４０,４１があり、これらはタブ３４からプラスチ
ックハウジング３３への応力の伝達を減少させる。An important feature of the tab 34 is the two stress relief notches 40, 41 adjacent and adjacent the plastic housing 33, which reduce the transmission of stress from the tab 34 to the plastic housing 33.
【００１７】図１および図２に示した半導体素子パッケ
ージ３０は、図３,図４,図５に示すように、その形状を
変更することが可能である。図３〜図５において、先の
実施例と同一機能の要素には、これと対応する参照符号
が記される。それで、図３の半導体素子パッケージ３０
においては、タブ３４が短くされ、図４におけるタブ３
４は細長いプラグ−インフィンガ３７ａ,３７ｂ,３７ｃ
を有する。図５の半導体素子パッケージ３０は、絶縁ハ
ウジング３３内のＭＯＳＦＥＴダイのゲート電極に内部
結合可能なコントロール電極フィンガ６０を有するもの
であり、タブ部６１はプラグ−インフィンガ６２,６３
を有するソース電極である。図５におけるタブ３１は、
絶縁ハウジング３３内のＭＯＳＦＥＴダイの下部ドレン
電極に接続される。The shape of the semiconductor element package 30 shown in FIGS. 1 and 2 can be changed as shown in FIGS. 3, 4, and 5. 3 to 5, elements having the same functions as those of the previous embodiment are denoted by the corresponding reference numerals. Therefore, the semiconductor device package 30 of FIG.
In FIG. 4, the tab 34 is shortened, and the tab 3 in FIG.
4 is an elongated plug-in finger 37a, 37b, 37c
Having. The semiconductor device package 30 of FIG. 5 has a control electrode finger 60 that can be internally coupled to a gate electrode of a MOSFET die in an insulating housing 33, and a tab portion 61 has plug-in fingers 62, 63.
Is a source electrode having: The tab 31 in FIG.
It is connected to the lower drain electrode of the MOSFET die in the insulating housing 33.
【００１８】図６,図７および図８は、図１および図２
の実施例に対するリードフレームおよび半導体ダイの詳
細を示している。それで、図６および図８のリードフレ
ーム７０は、下部端子３１およびタブ３４をもたらす。
リードフレーム７０のより頑丈な部分は、一体的に延在
するダイ受容部７１を有し、これらは図６および図７に
示すように、はんだ付け、あるいは他の方法でそれに電
気的に接続されることにより、半導体ダイ７２の下部電
極を受容する。半導体ダイ７２は、ショットキーダイオ
ードダイであってもよい。その上側の電極は、タブ３４
に対して６本のワイヤボンド７３により結合される。そ
れで、プラスチックハウジング３３が図７中の破線で示
されるように形成され、リードフレームが直線８０〜８
４の部分で切断されて厚みのある部分３１〜７１および
タブ３４が切り離される。FIGS. 6, 7 and 8 show FIGS. 1 and 2 respectively.
5 shows details of a lead frame and a semiconductor die for the embodiment of FIG. Thus, the lead frame 70 of FIGS. 6 and 8 provides the lower terminal 31 and the tab 34.
The sturdier portion of the lead frame 70 has an integrally extending die receiving portion 71, which is soldered or otherwise electrically connected thereto, as shown in FIGS. Thereby, the lower electrode of the semiconductor die 72 is received. Semiconductor die 72 may be a Schottky diode die. The upper electrode is a tab 34
Are connected by six wire bonds 73. Thus, the plastic housing 33 is formed as shown by the broken line in FIG.
4, the thick portions 31 to 71 and the tab 34 are cut off.
【００１９】図９,図１０および図１１は、タブ３４が
プラグ−イン接続ではなく、開口部３６を介してボルト
により接続される半導体素子パッケージ３０におけるさ
らに他の実施例のそれぞれ平面図,側面図および底面図
を示す。FIGS. 9, 10 and 11 are plan and side views, respectively, of still another embodiment of a semiconductor device package 30 in which tabs 34 are not plug-in connections but are connected by bolts through openings 36. Figures and bottom view are shown.
【００２０】上述したように、用途や使用方法に応じた
パッケージのための多くの選択が考えられる。いくつか
の選択が図１２〜図１７に示される。それで、図１４〜
図１７は、タブ３７から絶縁される中央コントロール電
極５０を持った半導体素子パッケージ３０を示してい
る。図１５は、ボルト５１によって接続可能なタブ３４
のための最適な構造を示している。As mentioned above, there are many possible choices for the package depending on the application and method of use. Several options are shown in FIGS. So, FIG.
FIG. 17 shows the semiconductor device package 30 having the central control electrode 50 insulated from the tab 37. FIG. 15 shows a tab 34 connectable by bolts 51.
The optimal structure for is shown.
【００２１】なお、これらの実施例において、先の実施
例と同一機能の要素には、これと同一の符号を記してあ
る。In these embodiments, elements having the same functions as those in the previous embodiment are denoted by the same reference numerals.
【００２２】[0022]
【発明の効果】本発明によると、コンパクトでかさばら
ず、優れた半導体ダイ−フットプリント比を持った頑丈
で低コストな高電流用途に適した半導体素子パッケージ
を提供することができる。また、絶縁ハウジングから露
出状態で突出する薄いタブは、高電流能力の最適な接続
と効率的な熱の引き込みとをもたらす。さらに、大きな
沿面距離および低い内部抵抗および低い迷走インダクタ
ンスによって、低電圧用途において最適な性能が保証さ
れる。According to the present invention, it is possible to provide a semiconductor device package which is compact, not bulky, has an excellent semiconductor die-to-footprint ratio, and is suitable for high-current applications at low cost at low cost. Also, the thin tabs that protrude out of the insulated housing provide optimal connection with high current capability and efficient heat draw. In addition, large creepage and low internal resistance and low stray inductance ensure optimal performance in low voltage applications.
【００２３】プリント回路板差し込みフィンガを設けた
場合には、使用中の回路の電力密度をプリント回路板の
わずかな交換で、あるいはプリント回路板の交換を行わ
ずに増大させることが容易となる。The provision of printed circuit board insertion fingers facilitates increasing the power density of the circuit in use with little or no replacement of the printed circuit board.
【００２４】絶縁ハウジングの壁面からわずかに隙間を
隔てた一対のスロットをタブに設けた場合には、タブか
ら絶縁ハウジングへの応力の伝達を制限して絶縁ハウジ
ングの欠損や亀裂が発生しないようにすることができ
る。When the tab is provided with a pair of slots slightly spaced from the wall surface of the insulating housing, the transmission of stress from the tab to the insulating housing is restricted to prevent the insulating housing from being broken or cracked. can do.
【図１】本発明による半導体素子パッケージの一実施例
の外観を表す斜視図である。FIG. 1 is a perspective view illustrating an appearance of an embodiment of a semiconductor device package according to the present invention.
【図２】図１に示した半導体素子パッケージの平面図で
ある。FIG. 2 is a plan view of the semiconductor device package shown in FIG. 1;
【図３】本発明による半導体素子パッケージの他の実施
例の概略構造を表す平面図である。FIG. 3 is a plan view illustrating a schematic structure of another embodiment of a semiconductor device package according to the present invention.
【図４】本発明による半導体素子パッケージの別な実施
例の概略構造を表す平面図である。FIG. 4 is a plan view illustrating a schematic structure of another embodiment of a semiconductor device package according to the present invention.
【図５】本発明による半導体素子パッケージのさらに他
の実施例の概略構造を表す平面図である。FIG. 5 is a plan view illustrating a schematic structure of still another embodiment of a semiconductor device package according to the present invention.
【図６】図１に示した実施例におけるリードフレームの
平面図であり、ショットキーダイオードダイをリードフ
レームに接合した状態を示す。FIG. 6 is a plan view of the lead frame in the embodiment shown in FIG. 1, showing a state where a Schottky diode die is joined to the lead frame.
【図７】図６に対する右側面図である。FIG. 7 is a right side view of FIG.
【図８】半導体ダイの接合およびリードフレーム部分の
分離前の図５および図６に示したリードフレームの側面
図である。FIG. 8 is a side view of the lead frame shown in FIGS. 5 and 6 before bonding of the semiconductor die and separation of the lead frame portion.
【図９】本発明による半導体素子パッケージのさらに別
な実施例の外観を表す平面図である。FIG. 9 is a plan view illustrating an appearance of still another embodiment of a semiconductor device package according to the present invention.
【図１０】図９に示した実施例の右側面図である。FIG. 10 is a right side view of the embodiment shown in FIG. 9;
【図１１】図９に示した実施例の底面図である。FIG. 11 is a bottom view of the embodiment shown in FIG. 9;
【図１２】本発明のさらなる実施例の外観を表す斜視図
である。FIG. 12 is a perspective view illustrating an appearance of a further embodiment of the present invention.
【図１３】本発明のさらなる他の実施例の外観を表す斜
視図である。FIG. 13 is a perspective view showing the appearance of still another embodiment of the present invention.
【図１４】本発明のさらなる別な実施例の外観を表す斜
視図である。FIG. 14 is a perspective view showing the appearance of still another embodiment of the present invention.
【図１５】本発明の異なる実施例の外観を表す斜視図で
ある。FIG. 15 is a perspective view illustrating an appearance of a different embodiment of the present invention.
【図１６】本発明の異なる他の実施例の外観を表す斜視
図である。FIG. 16 is a perspective view showing the appearance of another embodiment of the present invention.
【図１７】本発明の異なる別な他の実施例の外観を表す
斜視図である。FIG. 17 is a perspective view showing the appearance of another different embodiment of the present invention.
３０ パッケージ ３１ 下部端子（電極） ３２ 側面 ３３ 絶縁ハウジング（プラスチックハウジング） ３４ 第２の電極（タブ） ３５ 側面 ３６ 開口部 ３７ タブ ３７ａ,３７ｂ,３７ｃ プリント回路板差し込みフィン
ガ ３９ 取り付け開口部 ４０,４１ 応力緩和用切欠 ５０ 中央コントロール電極 ５１ ボルト ６０ コントロール電極フィンガ ６１ タブ部 ６２,６３ プラグ−インフィンガ ７０ リードフレーム ７１ ダイ受容部 ７２ 半導体ダイ ７３ ワイヤボンド ８０〜８４ 切断線Reference Signs List 30 package 31 lower terminal (electrode) 32 side surface 33 insulating housing (plastic housing) 34 second electrode (tab) 35 side surface 36 opening 37 tab 37a, 37b, 37c printed circuit board insertion finger 39 mounting opening 40, 41 stress Notch for relaxation 50 Central control electrode 51 Bolt 60 Control electrode finger 61 Tab part 62, 63 Plug-in finger 70 Lead frame 71 Die receiving part 72 Semiconductor die 73 Wire bond 80-84 Cutting line
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ポール シー． ウエストマーランド 英国 シーアール６ ９ジェージー サリ ー ワーリンハム サコムズ ヒル グレ ードサイド コート 17 (72)発明者 ピーター アール． ジューア 英国 アールエイチ８ ９ディーディー サリー ハースト グリーン オクステッ ド ミル レーン 122 (72)発明者 アルバート ゲラ アメリカ合衆国 90274 カリフォルニア 州 パロス ヴァーデス エステイテス アディソン ロード 1720 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Paul C. Westmarland United Kingdom C Earl 69 Jersey Sally Warlingham Sacomes Hill Gradeside Court 17 (72) Inventor Peter Earl. Jewish United Kingdom Earl H8 9 D.D. Sally Hearst Green Octext Mill Lane 122 (72) Inventor Albert Gera United States 90274 Paros Verdes Estates Addison Road 1720 California 1720
Claims (7)
な導電性の下部端子と、 この下部端子の上面に支持されて電気的に接続する下面
を有する少なくとも１つの半導体ダイと、 前記下部端子よりも厚みが薄く、前記下部端子の前記第
１の平面の上方のこれと平行な平面上に配されると共に
下部端子から電気的に絶縁され、当該下部端子の幅とほ
ぼ等しい幅を有すると共に該下部端子の本体の少なくと
も一部からその長手方向に延在する平坦なタブと、 導電性の前記タブに対して前記半導体ダイの上面を接続
する接続手段と、 前記半導体ダイの上面および前記接続手段および前記半
導体タブの前記下部端子に隣接する第１の部分のみおよ
び前記下部導電性端子の少なくとも一部を取り囲んで成
形されてこれらを封入する絶縁ハウジングとを具え、前
記下部端子および前記タブが前記半導体ダイの外部端子
を形成することを特徴とする半導体素子パッケージ。1. A conductive lower terminal having a substantially uniform thickness disposed on a first plane, and at least one semiconductor die having a lower surface supported and electrically connected to an upper surface of the lower terminal; A width smaller than the lower terminal, arranged on a plane above and parallel to the first plane of the lower terminal, electrically insulated from the lower terminal, and substantially equal in width to the lower terminal; And a flat tab extending longitudinally from at least a portion of the body of the lower terminal, connecting means for connecting an upper surface of the semiconductor die to the conductive tab, and an upper surface of the semiconductor die And an insulating housing molded around and enclosing only the first portion of the connection means and the semiconductor tab adjacent to the lower terminal and at least a portion of the lower conductive terminal. For example, a semiconductor device package, wherein the lower terminal and said tabs to form the external terminals of the semiconductor die.
成形される前記絶縁ハウジングの側面に隣接して前記タ
ブの両側に第１および第２の応力緩和用切欠を有し、前
記タブから前記絶縁ハウジングへの応力の伝達を減少さ
せるようにしたことを特徴とする請求項１に記載の半導
体素子パッケージ。2. A first and a second stress relief notch on both sides of the tab adjacent to a side of the insulating housing formed surrounding the first portion of the tab, wherein the notch extends from the tab. The semiconductor device package according to claim 1, wherein transmission of stress to the insulating housing is reduced.
グから突出し、この下部端子の前記一部の中央部分およ
び前記絶縁ハウジングから突出する前記タブの中央部
は、それぞれこれらを貫通する開口部を個々に有するこ
とを特徴とする請求項１または請求項２に記載の半導体
素子パッケージ。3. A part of the lower terminal protrudes from the insulating housing, and a central part of the part of the lower terminal and a central part of the tab protruding from the insulating housing have openings formed therethrough. The semiconductor device package according to claim 1, wherein the semiconductor device package is provided individually.
複数のプラグ−イン差し込みフィンガを有することを特
徴とする請求項１から請求項３の何れかに記載の半導体
素子パッケージ。4. The semiconductor device package according to claim 1, wherein the free end of the tab has a plurality of plug-in insertion fingers extending therefrom.
ゲート素子とサイリスタとからなるグループから選択さ
れる素子であることを特徴とする請求項１から請求項４
の何れかに記載の半導体素子パッケージ。5. The semiconductor die includes a diode and a MOS.
5. An element selected from the group consisting of a gate element and a thyristor.
The semiconductor element package according to any one of the above.
ブおよび前記下部端子から絶縁された接続フィンガをそ
の側方に有し、前記半導体ダイは、その上面にゲート電
極を有するＭＯＳゲート素子と、前記ゲート電極に前記
接続フィンガを電気的に接続する前記絶縁ハウジング内
に配置された第２の接続手段とを具えていることを特徴
とする請求項１から請求項３の何れかに記載の半導体素
子パッケージ。6. A MOS gate device having a tab on the side thereof having connection fingers insulated from the tab and the lower terminal on the same plane, and the semiconductor die having a gate electrode on an upper surface thereof. 4. A device according to claim 1, further comprising a second connection means disposed in said insulating housing for electrically connecting said connection finger to said gate electrode. Semiconductor element package.
を特徴とする請求項１から請求項４の何れかに記載の半
導体素子パッケージ。7. The semiconductor device package according to claim 1, wherein said semiconductor die is a diode.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11232698P | 1998-12-15 | 1998-12-15 | |
| US60/112,326 | 1998-12-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000223635A true JP2000223635A (en) | 2000-08-11 |
| JP4616954B2 JP4616954B2 (en) | 2011-01-19 |
Family
ID=22343296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35643899A Expired - Fee Related JP4616954B2 (en) | 1998-12-15 | 1999-12-15 | Semiconductor device package |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6348727B1 (en) |
| JP (1) | JP4616954B2 (en) |
| DE (1) | DE19960013A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008500863A (en) * | 2004-06-01 | 2008-01-17 | シンセス ゲーエムベーハー | Osteosynthesis plate |
| JP2015026725A (en) * | 2013-07-26 | 2015-02-05 | 京セラ株式会社 | Semiconductor element housing package and mounting structure body equipped with the same |
| KR20190106783A (en) * | 2018-03-08 | 2019-09-18 | 캐논 가부시끼가이샤 | Vibration damping apparatus, lithography apparatus, and method of manufacturing article |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4054137B2 (en) * | 1999-06-03 | 2008-02-27 | 株式会社東京アールアンドデー | Power semiconductor element power supply and heat dissipation device |
| DE10100882A1 (en) * | 2001-01-11 | 2002-08-01 | Bosch Gmbh Robert | Method for assembling a semiconductor component and semiconductor component |
| EP1316999A1 (en) * | 2001-11-28 | 2003-06-04 | Continental ISAD Electronic Systems GmbH & Co. oHG | Method and device of contacting power electronic devices |
| DE10303933B4 (en) * | 2003-01-31 | 2005-08-04 | Infineon Technologies Ag | Semiconductor device with reduced connection-induced parasitic inductance and / or capacitance |
| US20060151868A1 (en) * | 2005-01-10 | 2006-07-13 | Zhu Tinggang | Package for gallium nitride semiconductor devices |
| US20070013053A1 (en) * | 2005-07-12 | 2007-01-18 | Peter Chou | Semiconductor device and method for manufacturing a semiconductor device |
| JP5106528B2 (en) * | 2007-05-29 | 2012-12-26 | 京セラ株式会社 | Electronic component storage package and electronic device |
| JPWO2010004609A1 (en) * | 2008-07-07 | 2011-12-22 | 三菱電機株式会社 | Power semiconductor device |
| US10367125B2 (en) * | 2012-07-30 | 2019-07-30 | Lumileds, LLC | Strengthened LED package and method therefor |
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| JPS62163352A (en) * | 1986-01-14 | 1987-07-20 | Toshiba Corp | Semiconductor device |
| JPH021862U (en) * | 1988-06-16 | 1990-01-09 | ||
| JPH02304877A (en) * | 1989-05-17 | 1990-12-18 | Seiko Epson Corp | Flexible substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3893161A (en) * | 1974-02-04 | 1975-07-01 | Jr Albert Pesak | Frictionally engageable heat sink for solid state devices |
| IT7821073V0 (en) * | 1978-03-09 | 1978-03-09 | Ates Componenti Elettron | CLAMP FOR FIXING A SEMICONDUCTOR DEVICE TO A HEAT SINK. |
| JPH08139113A (en) * | 1994-11-09 | 1996-05-31 | Mitsubishi Electric Corp | Resin sealed semiconductor device |
-
1999
- 1999-12-07 US US09/455,699 patent/US6348727B1/en not_active Expired - Lifetime
- 1999-12-13 DE DE19960013A patent/DE19960013A1/en not_active Withdrawn
- 1999-12-15 JP JP35643899A patent/JP4616954B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62163352A (en) * | 1986-01-14 | 1987-07-20 | Toshiba Corp | Semiconductor device |
| JPH021862U (en) * | 1988-06-16 | 1990-01-09 | ||
| JPH02304877A (en) * | 1989-05-17 | 1990-12-18 | Seiko Epson Corp | Flexible substrate |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008500863A (en) * | 2004-06-01 | 2008-01-17 | シンセス ゲーエムベーハー | Osteosynthesis plate |
| JP4657293B2 (en) * | 2004-06-01 | 2011-03-23 | シンセス ゲーエムベーハー | Osteosynthesis plate |
| JP2015026725A (en) * | 2013-07-26 | 2015-02-05 | 京セラ株式会社 | Semiconductor element housing package and mounting structure body equipped with the same |
| KR20190106783A (en) * | 2018-03-08 | 2019-09-18 | 캐논 가부시끼가이샤 | Vibration damping apparatus, lithography apparatus, and method of manufacturing article |
| KR102502898B1 (en) | 2018-03-08 | 2023-02-24 | 캐논 가부시끼가이샤 | Vibration damping apparatus, lithography apparatus, and method of manufacturing article |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4616954B2 (en) | 2011-01-19 |
| US6348727B1 (en) | 2002-02-19 |
| DE19960013A1 (en) | 2000-06-29 |
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