JP2000223507A - Stage for mounting semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve manufacturing yield and reliability, without lowering throughput by suppressing generation of various damages on a semiconductor chip in tentatively placing a semiconductor chip on a stage for chip mounting for purpose of position alignment or the like of the semiconductor chip, in an intermediate step of die bonding process for the semiconductor chip. SOLUTION: A recessed trench 12 is formed on the upper face of an interim stage 10 used for mounting a semiconductor chip. Because of this structure, in tentatively placing an extra long and narrow semiconductor chip 14 such as a linear sensor or the like on the upper face of the interim stage 10 with a side chuck 16, stresses generated when the bottom face of the semiconductor chip 14 contacts the upper face of the interim stage 10 escapes to the direction of the recessed trench 12, and the contact area between the bottom face of the semiconductor chip 14 and the upper face of the interim stage 10 is reduced. Therefore, the stresses applied from the contact plane to the bottom face of the semiconductor chip 14 are reduced. Consequently, generation of damages to the semiconductor chip 14 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stage for mounting a semiconductor chip, and more particularly, to a method for die bonding an ultrafine semiconductor chip such as a linear sensor to a package.
The present invention relates to a semiconductor chip mounting stage which is temporarily placed in order to position a semiconductor chip in the middle.

[0002]

2. Description of the Related Art When a normal semiconductor chip is die-bonded to a package, generally, individual semiconductor chips diced from a wafer are picked up and then picked up.
A so-called direct die bonding method is adopted in which the material is moved to a package, placed on a die pad portion to which an adhesive is applied in advance, and fixed.

However, when a semiconductor chip of an extremely thin type such as a linear sensor is die-bonded to a package, it is unstable to pick up the semiconductor chip and move it directly to the package. It is difficult to do.

Therefore, as shown in FIG. 5, after picking up the semiconductor chip 14 using, for example, a side chuck 16, the semiconductor chip 14 is temporarily placed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip. Then, chip alignment for correcting the attitude of the semiconductor chip 14 is performed on the upper surface of the intermediate stage 10. Thereafter, the semiconductor chip 14 on which the chip alignment has been performed is performed.
Is picked up again using the side chuck 16, moved to a package, and placed and fixed on a die pad portion to which an adhesive has been applied in advance. In this way, the ultra-small semiconductor chip 14 such as a linear sensor is die-bonded to the package.

At this time, a method of using the side chuck 16 as a means for picking up the semiconductor chip 14 and temporarily placing the semiconductor chip 14 on the upper surface of the intermediate stage 10 is generally called a side chuck method. Specifically, as shown in FIG. 6, two arms of the side chuck 16 are used to chuck the semiconductor chip 14 from both sides with a pattern-free side wall portion interposed therebetween, as indicated by arrows in the figure. is there. Then, an extra-fine semiconductor chip 14 such as a linear sensor
When picking up the semiconductor chip, the side chuck method is adopted to prevent the surface of the semiconductor chip 14 on which the pattern is formed from being damaged.

The chip alignment for correcting the attitude of the semiconductor chip 14 temporarily placed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip includes, for example, soft alignment using image processing of the semiconductor chip 14, a side check 16, and the like. There is a mechanical alignment performed by using.

[0007]

However, when the semiconductor chip 14 is picked up by using the side chuck 16, a load is applied horizontally from both side walls of the semiconductor chip 14 via two arms of the side chuck 16. Is applied, but the semiconductor chip 14 is placed on the intermediate stage 1 with both side walls sandwiched by the side chuck 16.
When the semiconductor chip 14 is temporarily placed on the upper surface, the semiconductor chip 1
The load applied to 4 propagates as stress in various directions.

That is, depending on the cutting state of the semiconductor chip 14, both side walls are not necessarily formed in a vertical shape, or the semiconductor chip 14 when such inclined side walls are picked up by the side chuck 16. The semiconductor chip 14 may be tilted due to various factors, such as inclination, and the bottom surface of the semiconductor chip 14 sandwiched between the side chucks 16 and the upper surface of the intermediate stage 10 may not maintain a parallel positional relationship. When the semiconductor chip 14 comes into contact with the upper surface of the intermediate stage 10, loads are applied to the semiconductor chip 14 in various directions from the contact surface of the upper surface of the intermediate stage 10.

FIG. 7 is an enlarged view of part A of FIG.
As shown in FIG. 7, the maximum stress is applied to the vicinity of the contact surface of the bottom surface of the semiconductor chip 14 with the top surface of the intermediate stage 10, that is, the region indicated by oblique lines in the drawing, whereby various types of damage are likely to occur.

For example, at this time, the damage occurring near the bottom of the semiconductor chip 14 is as shown in FIG.
As shown in (b) and (c), a chip (break) 18 in which a part of the bottom surface of the semiconductor chip 14 is lost, a crack 20 running from the bottom surface of the semiconductor chip 14 into the bulk, and a side surface of the semiconductor chip 14 There are scratches 22 and the like.

As described above, when the semiconductor chip 14 is temporarily placed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip in a state where both side walls are sandwiched by the side chucks 16, damage occurs near the bottom of the semiconductor chip 14. As described above, such a situation is caused by performing chip alignment for correcting the attitude of the semiconductor chip 14 on the upper surface of the intermediate stage 10 and then holding the side walls of the semiconductor chip 14 on which the chip alignment has been performed again to the side chuck 1.
6 also occurs when chucking, picking up, and moving to a package.

That is, when picking up both side walls of the semiconductor chip 14 on the upper surface of the intermediate stage 10 for mounting the semiconductor chip again by the side chuck 16, the lower surface of the semiconductor chip 14 near the contact surface with the upper surface of the intermediate stage 10. , A large stress is applied, and damage is likely to occur.

When the semiconductor chips 14 sandwiching both side walls by the side chuck 16 are temporarily placed on the upper surface of the intermediate stage 10, the side walls of the semiconductor chip 14 on the upper surface of the intermediate stage 10 are again
Various damages that occur in the semiconductor chip 14 when the semiconductor chip 14 is chucked by being sandwiched between the semiconductor chips 14 are a major cause of lowering the manufacturing yield and the reliability.

The rate of occurrence of such various types of damage on the semiconductor chip 14 tends to increase as the speed of a series of die bonding processes on the semiconductor chip 14 increases. When the speed of the bonding process is reduced, the throughput of the die bonding process is reduced.

Furthermore, the rate at which such various types of damage occur in the semiconductor chip 14 also depends on the skill and skill of the die bonding operator, and thus a large downtime occurs depending on the skill and skill of the operator. Will be.

The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-described problems. In the process of die-bonding an ultra-fine type semiconductor chip such as a linear sensor to a package, the semiconductor is used for positioning the semiconductor chip in the middle. It suppresses various damages to the semiconductor chip when the semiconductor chip is temporarily placed on the chip mounting stage, improves the production yield and reliability without lowering the throughput of the die bonding process, and improves the worker's It is an object of the present invention to provide a semiconductor chip mounting stage that enables die bonding processing independent of skill and skill.

[0017]

The above object is achieved by the following semiconductor chip mounting stage according to the present invention. That is, the semiconductor chip mounting stage according to claim 1 is a semiconductor chip mounting stage for temporarily placing a semiconductor chip when the semiconductor chip is die-bonded to a package. It is characterized in that a concave groove is formed on the upper surface for mounting.

In the semiconductor chip mounting stage according to the first aspect of the present invention, since the concave groove is formed on the upper surface on which the semiconductor chip is mounted, the semiconductor chip whose both side walls are sandwiched by the side chuck can be used. When temporarily placed on the top surface of the stage for mounting a semiconductor chip, the stress generated when the bottom surface of the semiconductor chip comes into contact with the top surface of the stage for mounting a semiconductor chip escapes in the direction of the concave groove. Since the stress applied to the bottom surface of the semiconductor chip from the contact surface on the top surface of the mounting stage for semiconductor chips is also reduced, damage to the vicinity of the contact surface of the bottom surface of the semiconductor chip with the top surface of the mounting stage for semiconductor chips is suppressed. You.

Similarly, after performing chip alignment for correcting the attitude of the semiconductor chip on the upper surface of the semiconductor chip mounting stage, the semiconductor chip on which the chip alignment has been performed is again picked up with the side chucks sandwiching both side walls. In addition, the stress applied to the bottom surface of the semiconductor chip from the contact surface of the top surface of the stage for mounting a semiconductor chip, which has a reduced area due to the formation of the concave groove, is reduced. The occurrence of damage in the vicinity of the contact surface is suppressed.

The semiconductor chip mounting stage according to a second aspect of the present invention is a semiconductor chip mounting stage for temporarily placing the semiconductor chip when the semiconductor chip is die-bonded to a package. The upper surface on which the semiconductor chip is mounted is mirror-finished.

In the semiconductor chip mounting stage according to the second aspect of the present invention, since the upper surface on which the semiconductor chip is mounted is mirror-finished, the semiconductor chip whose side walls are sandwiched by the side chuck can be mounted. When the semiconductor chip is temporarily placed on the top surface, the friction at the time of contact between the bottom surface of the semiconductor chip and the top surface of the semiconductor chip mounting stage is greatly reduced. Is suppressed.

Similarly, after performing chip alignment for correcting the posture of the semiconductor chip on the upper surface of the stage for mounting the semiconductor chip, the semiconductor chip on which the chip alignment has been performed is again picked up by the side chuck with both side walls interposed therebetween. In addition, since the friction at the contact surface between the bottom surface of the semiconductor chip and the top surface of the stage for mounting a semiconductor chip is greatly reduced, damage to the vicinity of the contact surface of the bottom surface of the semiconductor chip with the top surface of the stage for mounting a semiconductor chip is suppressed. You.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. (First Embodiment) FIG. 1 is a sectional view showing an intermediate stage for mounting a semiconductor chip according to a first embodiment of the present invention, and FIG. It is sectional drawing which shows the state which mounted the semiconductor chip.

As shown in FIG. 1, the intermediate stage 10 for mounting a semiconductor chip according to the first embodiment is characterized in that a concave groove 12 is provided on the upper surface on which the semiconductor chip is mounted. is there. And this concave groove 12
It has a rectangular planar shape slightly smaller than the outer shape of the semiconductor chip mounted on the upper surface of the intermediate stage 10 and a rectangular cross-sectional shape of a predetermined depth.

For this reason, as shown in FIG. 2, an ultrafine semiconductor chip 14 such as a linear sensor diced from a wafer is picked up using a side chuck 16, and is temporarily placed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip. When placing, the stress generated when the bottom surface of the semiconductor chip 14 comes into contact with the top surface of the intermediate stage 10 escapes in the direction of the lower concave groove 12 as indicated by the arrow in the figure. Further, since the contact area between the bottom surface of the semiconductor chip 14 and the top surface of the intermediate stage 10 is reduced by the provision of the concave groove 12 on the top surface of the intermediate stage 10, the stress applied to the bottom surface of the semiconductor chip 14 from the contact surface is also reduced. Decrease.

Therefore, the semiconductor chip 14 sandwiched between the side walls by the side chuck 16 is moved to the intermediate stage 1.
When the semiconductor chip 14 is temporarily placed on the upper surface, the lower surface of the semiconductor chip 14 is placed near the contact surface with the upper surface of the intermediate stage 10 as shown in FIG.
Missing (cut) 1 as shown in (b) and (c) respectively
8, cracks 20 and scratches 22 are suppressed from occurring.

After the chip alignment for correcting the attitude of the semiconductor chip 14 temporarily placed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip is performed, the side walls of the semiconductor chip 14 on which the chip alignment has been performed are again side-chucked. Since the concave groove 12 is provided on the upper surface of the intermediate stage 10 when picking up from the upper surface of the intermediate stage 10 while being sandwiched between the semiconductor chip 14 and the upper surface of the intermediate stage 10 by the area of the concave groove 12. And the stress applied from the contact surface to the bottom surface of the semiconductor chip 14 decreases.

Therefore, in order to move the semiconductor chip 14 from the upper surface of the intermediate stage 10 to the package, the semiconductor chip 14 is again chucked by sandwiching both side walls of the semiconductor chip 14 by the side chuck 16 and picked up from the upper surface of the intermediate stage 10. The occurrence of various types of damage near the contact surface with the upper surface of the intermediate stage 10 is suppressed.

As described above, according to the first embodiment, the concave groove 1 is formed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip.
When the semiconductor chip 14 having both side walls sandwiched by the side chuck 16 is temporarily placed on the upper surface of the intermediate stage 10, the side chuck 16 is provided again.
When the semiconductor chip 14 is picked up from the upper surface of the intermediate stage 10 across both side walls of the semiconductor chip 14, the stress applied to the bottom surface of the semiconductor chip 14 is reduced due to the contact area with the upper surface of the intermediate stage 10. The occurrence of damage can be suppressed.

Therefore, it is possible to prevent a reduction in the manufacturing yield and reliability due to various types of damage occurring in the semiconductor chip 14, and to realize an improvement in the manufacturing yield and reliability more than before. In addition, since it is not necessary to reduce the speed of a series of die bonding processes in order to suppress the occurrence of various types of damage to the semiconductor chip 14, it is possible to improve the throughput of the die bonding process. Furthermore, since high skill and skill for the die bonding operator are no longer required to suppress the occurrence of various damages to the semiconductor chip 14, a large downtime is caused by the skill and skill of the ordinary worker. This makes it possible to easily perform the die bonding operation without using a die.

In the first embodiment,
The concave groove 12 provided on the upper surface of the intermediate stage 10 for mounting the semiconductor chip has a rectangular planar shape and a rectangular cross-sectional shape slightly smaller than the outer shape corresponding to the shape of the semiconductor chip mounted on the intermediate stage 10. However, the shape need not be limited to this. For example, instead of this concave groove 12, as shown in FIG. 3, a rectangular planar shape slightly smaller than the outer shape and an arc shape having a predetermined curvature corresponding to the shape of the semiconductor chip mounted on the upper surface of the intermediate stage 10 are provided. Groove 12a having a cross-sectional shape of
May be used. Also in this case, the same operation and effect as in the case of the concave groove 12 shown in FIG. 2 can be obtained.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 5 is a cross-sectional view showing an intermediate stage for mounting a semiconductor chip according to the embodiment.

As shown in FIG. 4, an intermediate stage 10 for mounting a semiconductor chip according to the second embodiment is characterized in that the upper surface on which the semiconductor chip is mounted is mirror-finished.

For this reason, when the ultrafine semiconductor chip 14 such as a linear sensor diced from a wafer is picked up using the side chuck 16 and temporarily placed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip, the bottom surface of the semiconductor chip 14 is required. Is significantly reduced when contacting the upper surface of the intermediate stage 10.

Accordingly, the semiconductor chip 14 sandwiched between the side walls by the side chuck 16 is moved to the intermediate stage 1.
When the semiconductor chip 14 is temporarily placed on the upper surface, the occurrence of damage near the contact surface of the bottom surface of the semiconductor chip 14 with the upper surface of the intermediate stage 10 is suppressed.

After the chip alignment for correcting the attitude of the semiconductor chip 14 temporarily placed on the upper surface of the intermediate stage 10 for mounting the semiconductor chip is performed, the side walls of the semiconductor chip 14 on which the chip alignment has been performed are again subjected to the side chuck. Even when the semiconductor chip 14 is picked up from the upper surface of the intermediate stage 10 by being sandwiched by 16, the friction at the contact surface between the semiconductor chip 14 and the upper surface of the intermediate stage 10 is greatly reduced.

Therefore, in order to move the semiconductor chip 14 from the upper surface of the intermediate stage 10 to the package, the semiconductor chip 14 is again chucked by sandwiching both side walls of the semiconductor chip 14 by the side chuck 16. The occurrence of various types of damage near the contact surface with the upper surface of the intermediate stage 10 is suppressed.

As described above, according to the second embodiment, since the upper surface of the intermediate stage 10 for mounting the semiconductor chip is mirror-finished, the semiconductor chip 14 sandwiching both side walls by the side chuck 16 can be moved to the intermediate stage. The contact between the semiconductor chip 14 and the upper surface of the intermediate stage 10 when the semiconductor chip 14 is temporarily placed on the upper surface of the intermediate stage 10 or when the side walls of the semiconductor chip 14 on the upper surface of the intermediate stage 10 are again sandwiched by the side chuck 16 and picked up from the upper surface of the intermediate stage 10. Since the friction on the surface is greatly reduced, the semiconductor chip 1
4 can be prevented from causing various damages.

Therefore, as in the case of the first embodiment, it is possible to achieve an improvement in the production yield and reliability more than before, and to achieve an improvement in the throughput of the die bonding step. Furthermore, the die bonding operation can be easily performed without a large downtime due to the skill and skill of a normal worker.

[0040]

As described above in detail, according to the semiconductor chip mounting stage of the present invention, the following effects can be obtained. In other words, according to the semiconductor chip mounting stage of the first aspect, since the concave groove is formed on the upper surface on which the semiconductor chip is mounted, the semiconductor chip whose both side walls are sandwiched by the side chuck is mounted on the semiconductor chip. When the semiconductor chip is temporarily placed on the upper surface of the stage, the stress generated when the semiconductor chip comes into contact with the upper surface of the stage for mounting the semiconductor chip escapes in the direction of the concave groove, and the area of the semiconductor is reduced compared to the conventional semiconductor device due to the formation of the concave groove. Since the stress applied to the bottom surface of the semiconductor chip from the contact surface on the top surface of the chip mounting stage is also reduced, it is possible to suppress the occurrence of damage near the contact surface of the bottom surface of the semiconductor chip with the top surface of the semiconductor chip mounting stage.

Similarly, when the semiconductor chip mounting stage is picked up from the upper surface of the semiconductor chip mounting stage by sandwiching both side walls of the semiconductor chip with side chucks, the semiconductor chip mounting stage whose area is reduced as compared with the prior art by forming concave grooves. Since the stress applied to the bottom surface of the semiconductor chip from the contact surface on the top surface is reduced, it is possible to suppress the damage near the contact surface of the bottom surface of the semiconductor chip with the top surface of the stage for mounting a semiconductor chip.

Accordingly, it is possible to prevent a reduction in the manufacturing yield and reliability due to various types of damage occurring in the semiconductor chip, and to realize an improvement in the manufacturing yield and reliability more than before. In addition, since it is not necessary to reduce the speed of a series of die bonding processes in order to suppress the occurrence of various types of damage to the semiconductor chip, it is possible to improve the throughput of the die bonding process. Furthermore, since high skills and proficiency for die bonding workers are no longer required to suppress the occurrence of various damages to the semiconductor chip, a large downtime is caused by the skills and proficiency of ordinary workers. It is possible to easily perform the die bonding operation without any additional steps.

According to the semiconductor chip mounting stage of the present invention, since the upper surface for mounting the semiconductor chip is mirror-finished, the semiconductor chip sandwiched on both side walls by the side chuck can be mounted on the semiconductor chip. When the semiconductor chip is temporarily placed on the upper surface of the stage, the friction when the semiconductor chip contacts the upper surface of the stage for mounting the semiconductor chip is greatly reduced. The occurrence can be suppressed.

Similarly, when the semiconductor chip is picked up from the upper surface of the stage for mounting the semiconductor chip by sandwiching both side walls of the semiconductor chip with the side chuck, the friction at the contact surface between the semiconductor chip and the upper surface of the stage for mounting the semiconductor chip is significantly increased. Due to the reduction, it is possible to suppress the occurrence of damage near the contact surface of the bottom surface of the semiconductor chip with the top surface of the stage for mounting a semiconductor chip.

Therefore, the same effects as those of the first aspect can be obtained, and the production yield and the reliability can be improved more than before, and the throughput of the die bonding step can be improved. Furthermore, the die bonding operation can be easily performed without a large downtime due to the skill and skill of a normal worker.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an intermediate stage for mounting a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state where a semiconductor chip is mounted on an intermediate stage for mounting the semiconductor chip of FIG. 1;

FIG. 3 is a sectional view showing a modification of the intermediate stage for mounting a semiconductor chip according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing an intermediate stage for mounting a semiconductor chip according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a state where a conventional semiconductor chip is temporarily placed on an upper surface of an intermediate stage for mounting a semiconductor chip using a side chuck.

FIG. 6 is a cross-sectional view for explaining a side chuck system in which a side wall of a semiconductor chip is sandwiched from both sides using two arms of the side chuck.

FIG. 7 is a partially enlarged view of a portion A in FIG. 5;

FIG. 8 is a cross-sectional view illustrating damage that occurs in a semiconductor chip.

[Explanation of symbols]

10: Intermediate stage for mounting semiconductor chip, 12, 1
2a: concave groove, 14: semiconductor chip, 16: side chuck, 18: chipped, 20: crack, 22: scratch.

Claims (2)

[Claims] 1. A semiconductor chip mounting stage for temporarily placing a semiconductor chip when the semiconductor chip is die-bonded to a package, wherein the semiconductor chip mounting stage has a concave surface on an upper surface on which the semiconductor chip is mounted. A stage for mounting a semiconductor chip, wherein a groove is formed. 2. A semiconductor chip mounting stage for temporarily placing the semiconductor chip when the semiconductor chip is die-bonded to a package, wherein an upper surface of the semiconductor chip mounting stage on which the semiconductor chip is mounted has a mirror finish. Stage for mounting a semiconductor chip.