JP2000216548A - Electronic circuit board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily raise the density of an electronic circuit by forming a layer insulation film on a first wiring layer on a base, forming wiring trenches thereinto, filling the wiring trenches with a plating film, and removing a conductive film on the layer insulation film to separate patterns, by leaving the plating film in the wiring trenches, thus forming a second wiring layer. SOLUTION: A first wiring layer 2 is formed on a base 1, a layer insulation film 3 is formed on the wiring layer 2, wiring trenches are formed into the insulation film 3, a plating feed film 4 covers the surface of the insulation film 3 including the wiring trench bottoms, a conductive film 6 covers the wiring trench bottoms, the electric plating is made to grow a plating film from the trenches, thus forming an electric Cu plating film 7, the plating feed film 4 on the insulation film 3 is removed to separate patterns, by leaving the plating film 7 in the wiring trenches, and a second wiring layer 8 is formed so as to be electrically connected to the trenches.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic circuit board by an electroplating method and an electronic circuit board manufactured by using the method. The present invention relates to a method for manufacturing an electronic circuit board suitable for filling, and particularly to a multilayer wiring board having a high wiring density and a method for manufacturing the same.

[0002] The present invention also relates to a semiconductor device such as an LSI and a method of forming a wiring or an interlayer connection thereof.

[0003] Furthermore, the present invention relates to a method of manufacturing a thermal via not only for electrical connection in an electronic circuit board but also for heat conduction.

[0004]

2. Description of the Related Art In order to improve the performance and reduce the size of electronic devices, it is necessary to mount electronic components such as LSI devices on electronic circuit boards at high density. A multilayer wiring is required. Various proposals have already been made as a method for forming such fine wiring and fine interlayer connection portions, and the following methods are known as conventional techniques.

[0005] First, after a first wiring layer, an interlayer insulating film and a via are formed on a substrate as in the technique [Example 1] described in JP-A-7-58201 (FIG. 7A). ), The entire surface of the substrate is covered with a conductive film (FIG. 7 (b)), and using this conductive film as an electrode, a thick plating film is formed in the concave portion, and electroplating is performed under such conditions that a flat surface is obtained. (FIG. 7 (c)), the plating film on the interlayer insulating film is removed by etching, while the plating film in the via is selectively left (FIG. 7 (d) and (e)). Then, a second wiring layer is formed so as to be in contact with the plating film (FIG. 7 (f)).

The second is a method of controlling a plating current, such as pulse plating or current reversal plating. This includes the technique [Example 2] described in JP-A-7-336017.

The third is an electroless plating method [Example 3]. Electroless Plating-Basics and Applications-edited by the Electroplating Study Group, Nikkan Kogyo Shimbun, 1994, p.101-130, edited by the Electroplating Research Group, Plating Textbook Nikkan Kogyo Shimbun 1991 p.207-218, Minoru Toyonaga Plating technology for printed wiring boards Maki Shoten 1996
pp. 102-153 and Toshiki Suzube Plating technology for printed wiring boards Nikkan Kogyo Shimbun, 1995, pp. 61-75. In the electroless plating method, the concentration of the lines of electric force does not significantly increase the growth of the plating film on the projections, so that the openings of the vias or the wiring grooves are closed, and there is little chance that "spot" can be formed.

[0008]

In order to realize a multilayer wiring having a high wiring density, a via or a wiring having a high aspect ratio and an angle between the bottom of the via or the wiring groove and the side wall being substantially 90 ° is used. It is necessary to fill and flatten the inside of the groove with a metal having good conductivity, and to electrically connect the layers.

However, when the above conventional technique is used, there are the following problems.

In Example 1 of the prior art, when the opening size of the via or wiring groove is large and the aspect ratio is as low as 1 or less, it is possible to fill the via or wiring groove with an electroplating film. However, when the via or wiring groove is miniaturized and the aspect ratio is increased (for example, the aspect ratio is 1.5 or more), the concentration of the lines of electric force causes the growth of the plating film around the opening faster than the bottom of the via or wiring groove. Therefore, the opening of the via or the wiring groove is blocked, and an unfilled defect called “s” occurs in the via or the wiring groove.
In fact, when the aspect ratio becomes 1.5 or more,
Observation of the cross section revealed that the occurrence of cracks occurred.
When an unfilled defect called "su" occurs, the wiring cross-sectional area decreases and the electrical resistance increases, or a corrosive plating solution remains in the "su" and the via swells when heated and the via corrodes. There is a problem that reliability is reduced.

If the angle between the bottom of the via or the wiring groove and the side wall is made larger than 90 ° and the via or the wiring groove is tapered, the opening is blocked by the growth of the plating film around the opening of the via or the wiring groove. However, if the angle is too large, there is a problem that the width of the via or the wiring groove becomes large and the wiring density cannot be increased. Further, when the via or the wiring groove is miniaturized and has a high aspect ratio, there is a problem that it is not possible to suppress the closing of the opening only by providing a slight taper.

Further, in order to determine a plating solution composition and an additive which can suppress the clogging of the openings of vias or wiring trenches having a finer and higher aspect ratio and completely eliminate the generation of "spots", it is necessary to determine parameters such as: There is a problem that the selection is difficult because the number is very large.

In Example 2, not only the parameters of the plating conditions (the types of the components in the plating solution and their concentrations, the current density, the energizing time, etc.) are very large, but also the optimization of the plating conditions and the verification thereof are conducted by experiments. In a short period of time,
It is difficult to find optimal plating conditions at low cost.
If the optimum conditions cannot be found, "spots" are generated in the vias or the wiring grooves, so that there is a problem that it is difficult to produce a multilayer wiring board having good electrical characteristics and high reliability in a short time.

In Example 3, since the plating speed of electroless plating is considerably lower than 1/5 to 1/10 of that of electroplating, it takes a long time to fill the via or the wiring groove when increasing the plating film thickness. In addition, since the plating solution is high temperature and strong alkali, there are problems such as that the interlayer insulating film is easily damaged and that the stability of the plating solution and the quality of the plating film are inferior to those of electroplating.

[0015]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art.
In a manufacturing process of a high-density multilayer electronic circuit board, it is an object of the present invention to provide a method of filling a metal conductor evenly into a wiring, a via or a wiring groove without any gap. In addition, it is to realize high-density and multi-layer electronic circuits, as well as high performance and high reliability.

According to the present invention, the object can be easily achieved when the aspect ratio is small, and up to an aspect ratio of 5, the metal conductor is filled flat without any gap such as "su" in the via or wiring groove. It is possible. Aspect ratio is
If it exceeds 5, it becomes difficult to form a conductive film for plating power supply to the via or the wiring groove bottom by a vacuum film forming method,
Plating current does not flow to the via or the bottom of the wiring groove, and electroplating cannot be performed.

In order to achieve the above object, a first method of manufacturing an electronic circuit board according to the present invention and an electronic circuit board manufactured by using the method include a first wiring formed on a base material. Forming an interlayer insulating film on the layer, forming a via or a wiring groove in the interlayer insulating film, and covering the surface of the interlayer insulating film including the bottom of the via or the wiring groove with a conductive film (1); Alternatively, a step of covering the bottom of the wiring groove with a conductive film (2), and under the condition that a plated film grows from a via or a wiring groove, using the conductive film (1) and the conductive film (2) as a power supply film for plating. Electroplating, filling the via or wiring groove with a plating film, and leaving the plating film in the via or wiring groove after plating, and conducting the conductive film on the interlayer insulating film (1).
And a step of forming a second wiring layer so as to be electrically connected to the via or the wiring groove.

The insulating layer is made of polyimide resin formed by liquid coating or film sticking or SiO2, SiN formed by a coating method, a chemical vapor deposition method, or a sputtering method.
A film or the like is used.

The angle between the bottom of the via or the wiring groove and the side wall is preferably 90 ° in order to make the wiring finer and higher in density, and it is desirable that the hole shape be a well type with a vertically dug hole. However, in order to reduce the stress at the interface between the base material / insulating film, the interface between the lower wiring / insulating film, and the interface between the insulating film / plating power supply film and to prevent cracks from occurring, and to prevent disconnection during the formation of the plating power supply film, the angle is set to May be greater than 90 ° to taper the via or wiring groove.

More specifically, in the step of covering the bottom of the via or wiring groove with the conductive film (2), light irradiation into the via or wiring groove, pretreatment for electroless plating and electroless plating are performed. Conductive film using a method combining
(2) is formed.

More specifically, the conductive film (1) is made of Cr, Ti, N
i, V, Nb, Ta, Mo, W, Al and at least one of their alloys, oxides and nitrides, or conductive film (1) / Cu / conductive film
(1), conductive film (1) / Al / conductive film (1), conductive film (1) / Au / conductive film (1)
The conductive film (2) is made of Cu, Al, Ni, Au, Pt,
It consists of at least one of Pd and their alloys.

More preferably, the conductive film (1) has a higher electric resistance than the conductive film (2) and uses a substance which forms a chemically and mechanically stable passive film on the surface. In the conductive film (1), since the electric resistance of the passivation film itself or on the surface is higher than that of the conductive film (2), the plating current flowing through the conductive film (1) is smaller than that flowing through the conductive film (2). Also, a material is used in which the deposition thickness on the conductive film (1) is smaller than that on the conductive film (2).

Alternatively, in a portion of the conductive film (1) where the conductive film (2) does not adhere to the surface and the conductive film (1) itself is exposed, the passivation film on the surface becomes an insulator. Use a material that does not deposit plating. Conductive film (2) is conductive film (1)
Use a substance that has lower electric resistance and good adhesion to the metal deposited by plating. Examples of these are the materials described above.

The conductive film (1) not only enhances the adhesion between the interlayer insulating film and the conductive film (2), but also has a function of suppressing a diffusion reaction between them. The conductive film (1) and the conductive film (2) are vapor deposition method, sputtering method, ion plating method, chemical vapor deposition method, vacuum film forming method such as molecular beam epitaxy method or fine particle application, fine particle spraying, The film is formed using at least one of photodecomposition, thermal decomposition, a sol-gel method, electroless plating, and direct plating used in a printed wiring board manufacturing process.

Further, in order to achieve the above object, a method of manufacturing an electronic circuit board according to the present invention and a second configuration of the electronic circuit board manufactured by using the method include a first structure formed on a base material. Forming an interlayer insulating film on the wiring layer of the above, forming a via or a wiring groove in the interlayer insulating film, and forming the interlayer insulating film including the bottom of the via or the wiring groove on the surface of the interlayer insulating film.
(1), the upper layer is covered with a conductive film (2), and then the bottom surface of the via or wiring groove is covered with the conductive film (2),
The conductive film (2) on the side surface in the via or wiring groove and on the interlayer insulating film is removed, and the conductive film on the bottom of the via or wiring groove is removed.
(2) leaving the conductive film (1) and the conductive film (2) as a power supply film for plating, and performing electroplating under conditions such that the plated film grows from the inside of the via or the wiring groove. Filling the groove with a plating film, leaving a plating film in the via or wiring groove after plating, removing the conductive film (1) on the interlayer insulating film and separating the pattern, and forming the via or wiring groove. Forming a second wiring layer for electrical connection.

In the step of removing the side surface in the via or wiring groove and the conductive film (2) on the interlayer insulating film, a resist is applied to the surface of the interlayer insulating film including the bottom of the via or wiring groove, and polishing or dry etching is performed. After the resist is left at the bottom of the via or wiring groove, the conductive film (2) on the side surface inside the via or wiring groove and the interlayer insulating film is removed by wet etching or the like, and the bottom of the via or wiring groove is removed. After the conductive film (2) is left, the resist at the bottom of the via or wiring groove is removed.

More specifically, the conductive film (1) is made of Cr, Ti, N
i, V, Nb, Ta, Mo, W, Al and at least one of their alloys, oxides and nitrides, or conductive film (1) / Cu / conductive film
(1), conductive film (1) / Al / conductive film (1), conductive film (1) / Au / conductive film (1)
The conductive film (2) is made of Cu, Al, Ni, Au, Pt,
It consists of at least one of Pd and their alloys.

In order to achieve the above object, a third method of manufacturing an electronic circuit board according to the present invention and an electronic circuit board manufactured by using the method include a first structure formed on a base material. Forming an interlayer insulating film on the wiring layer, forming a via or a wiring groove in the interlayer insulating film, and forming the entire surface of the substrate including the bottom of the via or the wiring groove.
(1), the upper layer is covered with a conductive film (2), and then the bottom surface of the via or wiring groove is covered with the conductive film (2),
A step of covering the side surface in the via or the wiring groove and the interlayer insulating film with the film (3), and forming a plating film from the inside of the via or the wiring groove using the conductive film (1) and the conductive film (2) as a plating power supply film. Electroplating under conditions such as growth, filling the via or wiring groove with a plating film, and leaving the plating film in the via or wiring groove after plating, coating (3) on the interlayer insulating film and conductive The method includes a step of removing the film (1) to perform pattern separation, and a step of forming a second wiring layer so as to be electrically connected to the via or the wiring groove.

The side surface in the via or the wiring groove and the surface of the interlayer insulating film were covered with the film (3), and the bottom surface of the via or the wiring groove was covered with the conductive film (2) without the film (3). In order to achieve the state, a film is formed by using evaporation, ion plating, CVD or highly directional sputtering while tilting the substrate. When the film (3) is an organic material, there are methods such as coating, transfer and film sticking.

More specifically, the conductive film (1) is made of Cr, T
i, Ni, V, Nb, Ta, Mo, W, Al and at least one of their alloys, oxides and nitrides, or conductive film (1) / Cu / conductive film
(1), conductive film (1) / Al / conductive film (1), conductive film (1) / Au / conductive film (1)
The conductive film (2) is made of Cu, Al, Ni, Au, Pt,
A coating comprising at least one of Pd and their alloys
(3) is made of a metal, an organic substance, an inorganic oxide, or an inorganic nitride having a higher electric resistance than the conductive film (2).

According to the above-described method, the first plating power supply film and the second plating power supply film are formed in the interlayer insulating film and the via or the wiring groove, and the first power supply film is more electric than the second power supply film. Since the plating film grows from the bottom of the via or wiring groove by using a material having high resistance and easily forming a chemically stable passivation film on the surface, the plating film grows around the opening of the via or wiring groove. This prevents the opening from being clogged, and prevents the occurrence of unfilled defects such as "su".

Further, unnecessary plating power supply films can be removed after plating without breaking the interlayer insulating film, and power can be supplied to isolated patterns to perform plating.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described in detail with reference to the drawings.

Example 1 A first wiring layer is formed on a substrate. In this example, the substrate is made of glass, and the first wiring layer is made of a Cr / Cu / Cr film formed by a sputtering method.

A first insulating layer is formed by applying polyimide thereon and forming a via by photolithography. The thickness of the insulating layer is about 20 mm, and the opening of the via is 20 mm square or 20 mm in diameter (Fig. 1 (a)).

A plating power supply film (conductive film (1)) made of Cr (0.05 mm thick) / Cu (0.5 mm thick) / Cr (0.1 mm thick) is formed on the surface of the first insulating layer and in the vias by sputtering. (Fig. 1 (b)).

Next, the substrate is immersed in a Pd activating solution for electroless Cu plating. In order to remove air bubbles in the via so that the inside of the via is filled with the activating solution and the plating solution, pure substrate is used. It is desirable to perform vacuum defoaming in water, an activating solution or an electroless plating solution.

While this substrate is immersed in a Pd activating solution for electroless Cu plating, finely squeezed ultraviolet light or laser light is applied only inside the via to deposit Pd on the bottom of the via (FIG. 1 (c)). )).

Subsequently, the substrate is immersed in an electroless Cu plating solution, and a Cu film (conductive film (2)) having a thickness of about 0.1 mm is formed on the bottom of the via with Pd as a nucleus (FIG. 1 (d)).

Next, it is immersed in an electric Cu plating solution, a current is applied to the plating power supply film from around the periphery of the substrate, a Cu film having a thickness of about 20 mm is applied, and the inside of the via is filled with Cu (FIG. 1 (e)). .

Immediately before immersion in the electrolytic Cu plating solution, it is desirable to perform vacuum defoaming in pure water or a plating solution to remove bubbles in the via so that the inside of the via is filled with the plating solution.

Cathode locking during plating, so that the plating solution can easily enter and exit the via or wiring groove,
A method such as jet flow plating and ultrasonic irradiation may be used in combination.

Subsequently, Cr / Cu / Cr on the insulating layer (conductive film (1))
Is removed. Consists of alkaline potassium permanganate
Cr is etched using a Cr etchant, then Cu is etched using a Cu etchant made of sodium persulfate, and Cr is etched using the Cr etchant to separate patterns (FIG. 1 (f)). Electroplating Cu for plating power supply film
Since it is very thin compared to Cu, it can be etched with little damage to electroplated Cu.

Thereafter, a Cr / Cu film of a second wiring layer is formed on the surface of the first insulating layer and over the filled vias by using a sputtering method and photolithography. Two insulating layers are formed (FIG. 1 (g)).

By repeating the above process,
It is possible to increase the number of wiring layers. Since the upper part of the via is almost flat, the next via can be formed just above the via.

Although the number of steps is large, plating growth is carried out from the bottom of the via or wiring groove, so that unfilled defects such as "su" formed in the via or wiring groove, which could not be solved by the prior art, can be surely eliminated. I can do it.

Example 2 A first wiring layer is formed on a substrate. In this example, the substrate is made of glass ceramic, and the first wiring layer is made of a Cr / Cu / Cr film formed by a sputtering method.

A photosensitive polyimide is applied thereon, and a via is formed by photolithography to form a first insulating layer. The thickness of the insulating layer is about 15 mm, and the opening of the via is 15 mm square or 15 mm diameter (Fig. 2 (a)).

A plating power supply film (conductive film (1)) made of Cr (0.05 mm thick) / Cu (0.05 mm thick) / Al (0.05 mm thick) is formed on the surface of the first insulating layer and in the via by sputtering. (Figure 2
(b)).

While this substrate is immersed in an electroless Cu plating solution, a thinly squeezed ultraviolet ray or laser beam is applied only to the inside of the via, and a Cu film (conductive film (2)) having a thickness of about 0.1 mm is formed on the bottom of the via.
(Fig. 2 (c)).

Next, the substrate is immersed in an electric Cu plating solution, a current is applied to the plating power supply film from around the periphery of the substrate, a Cu film having a thickness of about 15 mm is applied, and the via is filled with Cu (FIG. 2 (d)). .

Subsequently, Cr / Cu / Al on the insulating layer (conductive film (1))
Is removed. Al is etched using an Al etchant composed of sodium hydroxide, Cu is etched using a Cu etchant composed of sodium persulfate, and Cr is further etched using a Cr etchant composed of alkaline potassium permanganate to separate patterns. (Figure 2 (e)). Since the Cu of the plating power supply film is much thinner than the electroplated Cu, etching can be performed with little damage to the electroplated Cu.

Thereafter, a Cr / Cu film of a second wiring layer is formed on the surface of the first insulating layer and on the filled vias by using a sputtering method and photolithography. Two insulating layers are formed (FIG. 2 (f)).

By repeating the above process,
It is possible to increase the number of wiring layers. Since the upper part of the via is almost flat, the next via can be formed just above the via.

(Example 3) A first wiring layer is formed on a base material. In this example, the substrate is made of polyimide, and the first wiring layer is made of a Cr / Cu / Cr film formed by a sputtering method.

A first insulating layer is formed by applying polyimide thereon and forming a via by laser. The thickness of the insulating layer is about 10 mm, and the opening of the via is 10 mm square or 10 mm in diameter (FIG. 3A).

A plating power supply film (conductive film) made of Cr (0.05 mm thick) is formed on the surface of the first insulating layer and in the via by sputtering.
(1)) is formed (FIG. 3 (b)).

After immersing this substrate in an electroless Cu plating solution, tilt the substrate or rotate it at a low speed of 300 rpm or less, and then wipe the plating solution on the surface of the first insulating layer with a squeegee to remove the plating solution on the substrate surface. After removing the plating solution so that the plating solution remains at the bottom of the via (FIG. 3C), the entire surface of the first insulating layer and the via is irradiated with ultraviolet light or laser light, and Cu is applied only to the bottom of the via. Precipitate.

Subsequently, the substrate is immersed in an electroless Cu plating solution, and a Cu film (conductive film (2)) having a thickness of about 0.1 mm is formed on the bottom of the via with Cu as a core (FIG. 3 (d)).

Although the electroless Cu plating solution was used here,
Use Pd activation solution for electroless Cu plating instead of Pd
And then immersed in an electroless Cu plating solution to form a Cu film with a thickness of about 0.1 mm on the bottom of the via with Pd as a nucleus.

Next, it is immersed in an electric Cu plating solution, a current is applied to the plating power supply film from the vicinity of the outer periphery of the substrate, a Cu film having a thickness of about 10 mm is formed, and the via is filled with Cu (FIG. 3 (e)). .

Subsequently, Cr / Cu / Cr on the insulating layer (conductive film (1))
Is removed. Consists of alkaline potassium permanganate
Cr is etched using a Cr etchant to separate patterns (FIG. 3 (f)). Thereafter, a Cr / Cu film of a second wiring layer is formed on the surface of the first insulating layer and over the filled vias by using a sputtering method and photolithography, and then polyimide is applied to those surfaces to form a second insulating layer. Form (Figure
3 (g)).

By repeating the above process,
It is possible to increase the number of wiring layers. Since the upper part of the via is almost flat, the next via can be formed just above the via.

(Example 4) A first wiring layer is formed on a base material. In this example, the substrate is made of polyimide, and the first wiring layer is made of a Cr / Cu / Cr film formed by a sputtering method.

A polyimide is applied thereon, and a via is formed by a laser to form a first insulating layer. The thickness of the insulating layer is about 25 mm, and the opening of the via is about 5 mm square or 5 mm in diameter (FIG. 4A).

A plating power supply film (conductive film (1)) made of Cr (0.05 mm thick) / Cu (0.1 mm thick) / Al (0.05 mm thick) is formed on the surface of the first insulating layer and in the vias by sputtering. (Figure 4
(b)).

While the substrate was immersed in a Pd activating solution for an electroless Cu plating solution, finely squeezed ultraviolet or laser light was applied only inside the via to deposit Pd on the bottom of the via (FIG. 4 ( c)) Then, it is immersed in an electroless Cu plating solution, and a Cu film having a thickness of about 0.1 mm is formed on the bottom of the via with Pd as a nucleus. About 0.1 mm
A thick Cu film (conductive film (2)) is applied (FIG. 4D).

Here, a Pd activating solution for electroless Cu plating was used. Instead, Cu was deposited on the bottom of the via using an electroless Cu plating solution, and the Cu was used as a nucleus to form a copper on the bottom of the via.
A 0.1 mm thick Cu film can also be applied.

Next, the substrate is immersed in an electric Cu plating solution, a current is applied to the plating power supply film from around the periphery of the substrate, a Cu film having a thickness of about 25 mm is formed, and the inside of the via is filled with Cu (FIG. 4 (e)). .

Subsequently, in order to form a second wiring layer on the surface of the first insulating layer and on the via, while the substrate is immersed in the electroless Cu plating solution, finely squeezed ultraviolet light or laser light is applied to the surface of the first insulating layer. Irradiate the upper portion and the portion to be the second wiring layer on the via to form a Cu film (conductive film (2)) having a thickness of about 0.1 mm (FIG. 4 (f)). Next, the substrate is immersed in an electric Cu plating solution, and a current is applied to the plating power supply film from the vicinity of the outer periphery of the substrate to attach a Cu film having a thickness of about 10 mm to form a second wiring layer (FIG. 4 (g)).

Here, the via filling and the formation of the second wiring layer are performed separately, but they can be performed simultaneously as follows. While the substrate after the formation of the conductive film (1) is immersed in a Pd activating solution for an electroless Cu plating solution, finely squeezed ultraviolet light or laser light is applied to the second wiring layer on the surface of the first insulating layer. Irradiation is performed on the portion to be formed and inside the via to deposit Pd on the portion to be the second wiring layer and the bottom of the via. Subsequently, the substrate is immersed in an electroless Cu plating solution, and a Cu film (conductive film (2)) having a thickness of about 0.1 mm is applied to a portion serving as the second wiring layer with Pd as a nucleus and a bottom of the via. Next, the substrate is immersed in an electric Cu plating solution, and a current is applied to the plating power supply film from the vicinity of the outer periphery of the substrate to attach the Cu film to form a second wiring layer and a via.

Subsequently, Cr / Cu / Cr on the insulating layer (conductive film (1))
Is removed. Al is etched using an Al etchant composed of sodium hydroxide, Cu is etched using a Cu etchant composed of sodium persulfate, and Cr is further etched using a Cr etchant composed of alkaline potassium permanganate to separate patterns. (Figure 4 (h)). Since the Cu of the plating power supply film is much thinner than the electroplated Cu, etching can be performed with little damage to the electroplated Cu.

Thereafter, polyimide is applied on the surfaces of the first insulating layer and the second wiring layer and on the filled via to form a second insulating layer (FIG. 4 (i)).

By repeating the above process,
It is possible to increase the number of wiring layers. Since the upper part of the via is almost flat, the next via can be formed just above the via.

(Example 5) A first wiring layer is formed on a base material. In this example, the substrate is made of glass, and the first wiring layer is made of a Cr / Cu / Cr film formed by a sputtering method.

A photosensitive polyimide is applied thereon, a via is formed by photolithography, and a first insulating layer is formed. The thickness of the insulating layer is about 20 mm, and the opening of the via is 20 mm square or 20 mm diameter (FIG. 5 (a)).

The Cr (0.05 mm thick) / Cu (0.1 mm thick) / Cr (0.1 mm thick) / Cu (0.1 mm thick)
Then, a plating power supply film (conductive films (1) and (2)) having a thickness of 2 mm is formed (FIG. 5B).

Next, a liquid resist is applied to the surface of the first insulating layer and the inside of the via (FIG. 5C). Subsequently, by using mechanical polishing or dry etching, the resist in the via is left, and the resist on the surface of the first insulating layer is removed (FIG. 5D).

Next, the uppermost Cu (conductive film (2)) of the plating power supply film on the surface of the first insulating layer is removed using a Cu etchant made of sodium persulfate. The etching is performed slightly excessively, and the uppermost Cu (conductive film (2)) of the plating power supply film on the side surface near the opening in the via is also removed. In this way, Cu (conductive film (2)) is attached to the top layer of the plating power supply film only at the bottom of the via (FIG. 5).
(e)).

Subsequently, the resist remaining in the via is stripped with a resist stripper, and oxygen plasma ashing is performed to remove the resist residue at the bottom (FIG. 5 (f)).

Next, the substrate is immersed in an electric Cu plating solution, a current is applied to the plating power supply film from around the periphery of the substrate, a Cu film having a thickness of about 20 mm is formed, and the via is filled with Cu (FIG. 5 (g)). .

Subsequently, Cr / Cu / Cr on the insulating layer (conductive film (1))
Is removed. Consists of alkaline potassium permanganate
Cr is etched using a Cr etchant, then Cu is etched using a Cu etchant made of sodium persulfate, and Cr is etched using the Cr etchant to perform pattern separation (FIG. 5 (h)). Electroplating Cu for plating power supply film
Since it is very thin compared to Cu, it can be etched with little damage to electroplated Cu.

Thereafter, a Cr / Cu film of a second wiring layer is formed on the surface of the first insulating layer and on the filled vias by using a sputtering method and photolithography. Two insulating layers are formed (FIG. 5 (i)).

By repeating the above process,
It is possible to increase the number of wiring layers. Since the upper part of the via is almost flat, the next via can be formed just above the via.

Example 6 A first wiring layer is formed on a base material. In this example, the base material is a Si wafer, and the first wiring layer is a TiN / Cu film formed by a sputtering method.

Then, a SiN film is formed thereon by a CVD method, a via is formed by photolithography and dry etching, and a first insulating layer is formed. The thickness of the insulating layer is about 1 mm, and the opening of the via is about 0.2 mm square or 0.2 mm in diameter (FIG. 6 (a)).

A plating power supply film (conductive films (1) and (2)) made of TaN (0.01 mm thick) / Cu (0.05 mm thick) is formed on the surface of the first insulating layer and in the via by sputtering (FIG. 6 (b)).

Subsequently, the bottom surface of the via or wiring groove is covered with the conductive film (2), while the side surface in the via or wiring groove and the conductive film (2) on the interlayer insulating film are not exposed to the surface. Next, the side surface in the via or wiring groove and the interlayer insulating film are covered with a film (3).

In this example, the conductive film (2) is made of Cu and the film (3) is made of Cu.
Is used for Cr. Since the film (3) only needs to be a plating resist that is easy to remove, it has etching selectivity with the conductive film (2), such as Al, has a higher electrical resistance than the conductive film (2), and has a poor surface. Other metals that can be used to form the active film or Al2O
3, metal oxides such as TiN, metal nitrides, inorganic oxides such as SiO2 and SiN, inorganic nitrides, and organic materials such as polyimide may be used. When the vapor deposition or ion plating described below is used, it is preferable to use Cr, Al, Ti, W, etc. for the film (3).

In order to prevent the film (3) from being attached to the bottom of the via or the wiring groove, the film is formed by using highly directional sputtering, vapor deposition or ion plating while tilting the substrate. In vapor deposition or ion plating, the pressure at the time of film formation is reduced to about 10 −4 to 10 −6 Pa to increase the mean free path of the film formed particles and to enhance the straightness of the film formed particles. Also,
A collimator is placed between the evaporation source or target and the substrate, and the flight direction of the film-forming particles is aligned.

In order to form a film evenly on the side surface in the via or wiring groove and on the interlayer insulating film, the inclined substrate is formed while rotating and revolving.

According to the above method, the bottom surface of the via or wiring groove is covered with the conductive film (2), while the side surface in the via or wiring groove and the conductive film (2) on the interlayer insulating film are covered with the conductive film (2). The side surface in the via or wiring groove and the interlayer insulating film are covered with a film (3) so as not to be exposed (FIG. 6 (c)).

Next, a portion immersed in an electro-Cu plating solution and flowing a current from the vicinity of the outer periphery of the substrate to the plating power supply film to form a Cu film having a thickness of about 1 mm to form a second wiring layer on the surface of the first insulating layer Then, the inside of the via is filled with Cu (FIG. 6D).

Subsequently, Cr / Cu / Cr on the insulating layer (conductive film (1))
Is removed. Consists of alkaline potassium permanganate
Cr is etched using a Cr etchant, then Cu is etched using a Cu etchant composed of sodium persulfate, and then TaN is etched using an etchant composed of alkaline potassium permanganate, and chemical mechanical polishing or Ar sputter etch. The power supply film is removed to perform pattern separation (FIG. 6 (e)). Since the Cu of the plating power supply film is much thinner than the electroplated Cu, etching can be performed with little damage to the electroplated Cu.

Thereafter, a Cr / Cu film of a second wiring layer is formed on the surface of the first insulating layer and on the filled vias by using a sputtering method and photolithography. Two insulating layers are formed (FIG. 6 (f)).

By repeating the above process,
It is possible to increase the number of wiring layers. Since the upper part of the via is almost flat, the next via can be formed just above the via.

Recently, even in semiconductor devices such as LSIs,
Since it is necessary to lower the wiring resistance in order to miniaturize the wiring, it has been studied to replace the conventional wiring material with Al instead of Cu, and to use a plating method for the film formation method.
Semiconductor World December 1997 p.107-111. By using the method of the present invention, it is possible to form a Cu wiring of a semiconductor element or to make an interlayer connection using a Cu via.

[0098]

As described above, according to the present invention, it is possible to fill a via or a wiring groove with a metal conductor without any defect and to form a high-density, high-reliability, fine multilayer wiring. Become.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing the order of manufacturing steps of an electronic circuit board according to Embodiment 1 of the present invention.

FIG. 2 is a side sectional view showing the order of manufacturing steps of an electronic circuit board according to Embodiment 2 of the present invention.

FIG. 3 is a side sectional view showing the order of manufacturing steps of an electronic circuit board according to Embodiment 3 of the present invention.

FIG. 4 is a side sectional view showing the order of manufacturing steps of an electronic circuit board according to Embodiment 4 of the present invention.

FIG. 5 is a side sectional view showing the order of manufacturing steps of an electronic circuit board according to Embodiment 5 of the present invention.

FIG. 6 is a side sectional view showing the order of manufacturing steps of an electronic circuit board according to Embodiment 6 of the present invention.

FIG. 7 is a side sectional view showing the order of manufacturing steps of the multilayer wiring board in Example 1 of the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... 1st wiring layer, 3 ... Interlayer insulating film, 4 ... Plating power supply film (conductive film (1)), 5 ... Pd activating liquid, 6 ... Conductive film
(2), 7: Electric Cu plating film, 8: Second wiring layer, 9: Electroless Cu plating solution, 10: Resist, 11: Film (3), 12
... conductive film.

Continued on the front page (72) Inventor Yoshihide Yamaguchi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd.Production Technology Laboratory (72) Inventor Yasunori Narizuka 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company (72) Eiji Matsuzaki, Inventor, Hitachi, Ltd.292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Japan Inside (72) Inventor Masashi Nishigame, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Japan Address F-term in Hitachi, Ltd. Production Research Laboratory 5E317 AA24 BB01 BB03 BB12 BB15 BB16 BB17 CC32 CC33 CC52 CD12 CD15 CD18 CD25 CD32 GG01 GG05 GG14 5E346 AA12 AA15 AA35 AA43 BB01 CC10 CC16 CC32 EE33 FF02 FF05 FF07 FF10 FF13 FF14 FF17 GG15 GG17 GG19 GG22 HH07 HH21 HH25 HH26

Claims (9)

[Claims] A step of forming an interlayer insulating film on a first wiring layer formed on a substrate and forming a via or a wiring groove therein; and forming an interlayer insulating film including a bottom of the via or the wiring groove. A step of covering the surface of the insulating film with the conductive film (1), and subsequently covering the bottom of the via or wiring groove with the conductive film (2), and using the conductive film (1) and the conductive film (2) as a power supply film for plating. Performing electroplating under conditions such that a plating film grows from inside the via or wiring groove, filling the via or wiring groove with the plating film, and leaving a plating film in the via or wiring groove after plating, An electronic device comprising: a step of removing a conductive film (1) on an insulating film to separate a pattern; and a step of forming a second wiring layer so as to be electrically connected to the via or the wiring groove. A method for manufacturing a circuit board. 2. The conductive film (1) is made of Cr, Ti, Ni, V, Nb, Ta, Mo,
W, Al and at least one of their alloys, oxides and nitrides, or conductive film (1) / Cu / conductive film (1), conductive film (1) / Al /
A conductive film (1), a conductive film (1) / Au / a multilayer film such as a conductive film (1), and the conductive film (2) includes at least Cu, Al, Ni, Au, Pt, Pd and an alloy thereof. 2. The method according to claim 1, wherein the first element comprises one.
A manufacturing method of the electronic circuit board according to the above. 3. An electronic circuit board manufactured by using the method according to claim 1. 4. A step of forming an interlayer insulating film on a first wiring layer formed on a base material, forming a via or a wiring groove in the interlayer insulating film, and forming an interlayer including a bottom of the via or the wiring groove. The surface of the insulating film is covered with the conductive film (1) for the lower layer and the conductive film (2) for the upper layer, and then the conductive film (2) covers the bottom surface of the via or wiring groove.
Removing the conductive film (2) on the side surfaces in the via or wiring groove and the interlayer insulating film so as to leave the conductive film (2) on the bottom of the via or wiring groove as covered by the conductive film; (1)
Using the conductive film (2) and the conductive film (2) as a power supply film for plating, performing electroplating under conditions such that the plating film grows from inside the via or wiring groove, filling the via or wiring groove with the plating film, and forming the via hole after plating. Alternatively, a step of removing the conductive film (1) on the interlayer insulating film and separating the pattern while leaving the plating film in the wiring groove, and forming a second wiring layer so as to be electrically connected to the via or the wiring groove. Forming an electronic circuit board. 5. The conductive film (1) is made of Cr, Ti, Ni, V, Nb, Ta, Mo, W, A
l and at least one of their alloys, oxides and nitrides
Or a multilayer film such as conductive film (1) / Cu / conductive film (1), conductive film (1) / Al / conductive film (1), conductive film (1) / Au / conductive film (1). The method according to claim 4, wherein the conductive film (2) is made of at least one of Cu, Al, Ni, Au, Pt, Pd and an alloy thereof. 6. An electronic circuit board manufactured by using the method according to claim 4. 7. A step of forming an interlayer insulating film on a first wiring layer formed on a base material, forming a via or a wiring groove in the interlayer insulating film, and forming a base including the bottom of the via or the wiring groove. The entire material surface is covered with the conductive film (1) for the lower layer and the conductive film (2) for the upper layer, and then the conductive film (2) covers the bottom surface of the via or wiring groove.
Covering the side surface in the via or wiring groove and the interlayer insulating film with the film (3) so as to be covered with the conductive film (1) and the conductive film (2) as a plating power supply film so as to be covered with a via. Alternatively, electroplating is performed under conditions such that a plating film grows from inside the wiring groove, and a step of filling the via or the wiring groove with the plating film, and leaving the plating film in the via or the wiring groove after plating, Upper film (3) and conductive film
A method for manufacturing an electronic circuit board, comprising: a step of removing a pattern by removing (1); and a step of forming a second wiring layer so as to be electrically connected to the via or the wiring groove. 8. The conductive film (1) is made of Cr, Ti, Ni, V, Nb, Ta, Mo, W, A
l and at least one of their alloys, oxides and nitrides
Or a multilayer film such as conductive film (1) / Cu / conductive film (1), conductive film (1) / Al / conductive film (1), conductive film (1) / Au / conductive film (1). The conductive film (2) is composed of at least one of Cu, Al, Ni, Au, Pt, Pd and an alloy thereof, and the film (3) is a metal, an organic material having a higher electric resistance than the conductive film (2), 8. The method for manufacturing an electronic circuit board according to claim 7, comprising an inorganic oxide and an inorganic nitride. 9. An electronic circuit board manufactured by using the method according to claim 7.