JP2000216294A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of an air hole which is easily formed at the corner part of a metal post, used for a chip-size package. SOLUTION: Before forming an insulating resin layer R which coats a wiring layer 7 of Cu and a metal post 8 in a first slot, a coating material H is formed over the entire surface of a wafer. The rigidity deterioration occurring from formation of a first slot TC, as well as the occurrence of a blow hole are prevented with the insulating resin layer R. By forming a dicing blade DC of narrow width, the interface exposed at dicing is protected with the coating material H and the insulating resin layer R.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a chip size package and a method for manufacturing the same. The chip size package (Chip Size Package) is also referred to as a CSP, and is a general term for packages having a size equal to or slightly larger than the chip size, and is a package for high-density mounting. The present invention relates to a metal post used in a CSP and a resin covering the metal post.

[0002]

2. Description of the Related Art Conventionally, in this field, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, a fine pitch BGA, a structure in which the ball pitch of the BGA is further narrowed and the outer shape is close to the chip size, etc. Are known.

Recently, there is a wafer CSP described in “Nikkei Microdevice”, August 1998, pp. 44-71. This wafer CSP is basically a CSP in which wiring or array-like pads are formed by a wafer process (pre-process) before dicing a chip.
It is expected that this technology will integrate the wafer process and the package process (post-process), thereby greatly reducing the package cost.

There are two types of wafer CSP: a sealing resin type and a rewiring type. The sealing resin mold has a structure in which the surface is covered with a sealing resin, similarly to a conventional package, and has a structure in which metal posts are formed on a wiring layer on the chip surface and the periphery thereof is solidified with the sealing resin.

It is generally said that when a package is mounted on a printed circuit board, stress generated due to a difference in thermal expansion between the printed circuit board and the printed circuit board is concentrated on the metal posts. It is believed to be decentralized.

On the other hand, in the rewiring type, as shown in FIG.
This is a structure in which rewiring is formed without using a sealing resin. That is, the Al electrode 52, the wiring layer 53, and the insulating layer 54 are stacked on the surface of the chip 51, and the metal posts 55 are formed on the wiring layer 53.
Is formed, and a solder bump 56 is formed thereon. The wiring layer 53 is used as rewiring for arranging the solder bumps 56 on the chip in a predetermined array.

[0007] The sealing resin mold has a metal post of 100 μm.
By lengthening it and reinforcing it with sealing resin,
High reliability is obtained. However, the process of forming the sealing resin needs to be performed using a mold in a later step, and the process becomes complicated.

On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, there is a need to relieve stress in some way to increase reliability.

FIG. 11 omits the wiring layer 53 of FIG. 10 and forms an opening exposing the Al electrode 52, and the metal post 55 and the Al electrode 52 are formed in this opening.
, A barrier metal 58 is formed at least one layer, and a solder ball 56 is formed on the metal post 55.

[0010]

However, in FIG. 10, since the insulating layer 54 is made of a resin, there is a problem that a contact is formed at a contact portion of the metal post 55.

This is, as shown in FIG.
The resin 63 is put into the first and the second 62 and melted under pressure. The semiconductor chip 51 is placed in a mold with a large number of metal posts 55 erected, and the resin 63 is pressed by the mold to cover the entire surface of the wafer. Here, reference numeral 64 is a sheet for peeling from the mold.

However, the resin 63 does not reach the corners around the metal post 55 and the abutment portion under the metal post 55, so that black (black circles in the drawing) is easily formed. Therefore, there is also a problem that the element is destroyed due to a decrease in moisture resistance, a deterioration in environmental resistance, or an explosion caused by the external atmosphere or the heat of the element itself.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is firstly achieved by providing a coating material for smoothing a corner formed around a contact portion of a lower layer of a metal post. Things.

For example, a resin dissolved in a solvent, a low-viscosity SO
When G is applied and melted, it is formed at the corners as if it were a spacer. In particular, the resin is difficult to be injected into the corners, but is formed like a spacer at the corners, so that the generation of the dust can be prevented.

Second, a coating material is provided to smooth the corner formed around the contact portion of the lower layer of the metal post, and a resin layer covering the side wall around the chip and the corner formed at the bottom of the side wall are provided. The problem can be solved by providing the covering material between them.

When cutting into individual chips, a resin is embedded in the first dicing groove of the half-cut, and then full-cut with a blade smaller than the dicing width.

Therefore, when forming the coating material, if the coating material is formed also in the first dicing groove, the formation of the coating material can be suppressed.

Third, if the covering material is formed so as to cover also the interface exposed on the side wall, it is possible to prevent water vapor and the like entering from this interface and to form a material having excellent environmental resistance.

Fourth, a wiring layer made of a metal is in contact with the lower layer of the metal post, and the covering material is also provided on a corner formed around the contact portion of the lower layer of the wiring layer, so that the wiring layer is in contact with the wiring layer. The interface with the lower layer can be covered, and a product excellent in environmental resistance can be formed. Fifth, the coating can be realized in a very simple way with spin-on materials,
Cost merit increases.

[0020]

Next, an embodiment of the present invention will be described.

In FIG. 9, reference numeral 1 denotes a portion of the uppermost metal layer (which also functions as a bonding pad) in a normal wire bonding type IC chip. The interlayer insulating film in which the hole C is formed is shown in FIG. Here, the reference numeral 1 is named Al electrode, but the material is Au, and recently, Cu electrode is used.
Is also conceivable. The material is not particularly limited as long as it is a material that can be bonded.

In the lower layer of the contact hole C,
Metal is formed in a plurality of layers, for example, a transistor (MO
S type transistor or BIP type transistor),
It is in contact with a diffusion region, a poly-Si gate, poly-Si or the like.

Here, it is needless to say that the present embodiment can be carried out with a MOS type or a BIP.

This structure is an IC generally called a one-layer metal, a two-layer metal, or the like.

That is, although not shown, as the number of metals increases to two, three,.
A metal and an insulating layer of each layer are formed, and their interfaces are exposed in a first groove TC described later.

FIG. 3 shows a passivation film. Here, the passivation film 3 is made of a Si nitride film, epoxy resin, polyimide, or the like.
The insulating resin layer r is covered.

When a resin is used as the passivation film, the same material as the insulating resin layer r may be used. This insulating resin layer r is coated with a relatively low viscosity by spin-on or the like as described later, and the surface thereof can be made flat by leaving it to stand. Therefore, the wiring layer 7 can be made flat, and the height of the solder ball can be made constant.

When a resin with a sheet is used as shown in FIG. 12, when the film is pressed with a mold before curing, the height of the metal post 8 is uniform, so that all metal post heads are used. Can be brought into contact with the film 64, and highly accurate metal exposure can be performed. Details will be described in the process.

On the Al electrode 1, a Ti nitride film 5 is formed.

An opening K exposing the TiN film 5 is formed in the passivation film 3 and the insulating resin layer r, and a Cu thin film layer 6 is formed here as a plating electrode (seed layer) of the wiring layer 7. Is done. Then, a wiring layer 7 formed by Cu plating is formed thereon.

Then, on the entire surface of the chip including the wiring layer 7,
A resin layer R made of resin is formed. However, although omitted in the drawing, an Si3N4 film may be provided at the interface between the resin layer R and the wiring layer 7 and between the resin layer R and the metal post 8.

The resin layer R can be implemented as long as it is a thermosetting or thermoplastic resin. In particular, as the thermosetting resin, an amic acid film, a polyimide resin, or an epoxy resin is preferable. Further, if it is a thermoplastic resin, a thermoplastic polymer (Hitachi Chemical Co., Ltd .: Himal) or the like is preferable. The amic acid film has a shrinkage of 30 to 50%.

Here, as the resin R, one containing liquid amic acid as a main material is prepared, and the resin R is spun on the entire surface of the wafer. The thickness is about 50 to 150 μm. Thereafter, the resin R is polymerized by a thermosetting reaction. The temperature is 30
0 ° C. or higher. However, the resin composed of amic acid before thermosetting becomes active under the above-mentioned temperature, reacts with Cu,
There is a problem of deteriorating the interface. However, the reaction with Cu can be prevented by covering the surface of the wiring layer with the Si3N4 film. Here, the thickness of the Si3N4 film is
It is about 1,000 to 10,000 °.

The Si 3 N 4 film is an insulating film having excellent barrier properties, and the SiO 2 film is inferior to the Si 3 N 4 film in barrier properties. However, when the SiO2 film is used, it is necessary to make the film thickness thicker than the Si3N4 film. Further, since the Si3N4 film can be formed by the plasma CVD method, its step coverage is excellent and is preferable. Further, since the resin layer R is coated after the formation of the metal post 8, the formation of the Si3N4 film not only prevents the reaction between the wiring layer 7 made of Cu and the resin layer containing amic acid as a main material, but also prevents the Cu layer from reacting. Between the metal post 8 and the resin layer R containing amic acid as a main material can also be prevented.

When the resin layer R in a state having fluidity before curing is cured, the resin R contracts during the curing, and as shown in FIG.
The film thickness is greatly reduced as shown in FIG. Therefore, the surface of the resin layer R is located at the lower end of the metal post 8 from the head, and the metal post 8 is exposed. Therefore, there is no need to remove the resin layer R and expose the head. In order to expose the head uniformly in this polishing step, very difficult control is required, but the head can be easily exposed by contraction of the resin.

In this step, of course, the resin R having a small shrinkage
May be applied and polished to expose the head of the metal post 8 after curing.

Therefore, the metal post 8 is provided at the end of the wiring layer 7.
Of the metal post 8 can form a barrier metal on the head of the metal post 8. Here, Ni10, Au
11 is formed by electroless plating.

If the solder ball is formed directly on the metal post 8 made of Cu, the connection strength with the solder ball is deteriorated due to the oxidized Cu. When Au is directly formed to prevent oxidation, Au is diffused, so that N
i is inserted. Ni prevents oxidation of Cu, and Au prevents oxidation of Ni. Therefore, deterioration of the solder ball and deterioration of the strength are suppressed.

A solder ball 12 is formed on the head of the metal post 8.

Here, the difference between the solder ball and the solder bump will be described. The solder ball is prepared by separately preparing ball-shaped solder in advance and fixed to the metal post 8.
The solder bump is formed by electrolytic plating via the wiring layer 7 and the metal post 8. The solder bump is initially formed as a thick film, and is formed into a spherical shape by post-heating.

In this case, since the seed layer is removed in the step of FIG. 6, electrolytic plating cannot be employed, and solder balls are actually prepared.

Finally, a first groove indicated by TC is formed around each chip prepared in a wafer state, and an insulating resin layer is embedded in this groove. Here, the same layer as the resin layer R is formed for simplification of the process, but it is not necessary to be the same unless the simplification of the process is considered.

The groove TC and the resin layer are features of the present invention, and are fully cut by a dicing blade DC narrower than the first groove TC. That is, the first
A resin layer is disposed between the groove TC and the full cut line DL, and can cover the interface end of each layer that causes moisture resistance deterioration, thereby preventing element deterioration.

The second characteristic lies in the provision of the coating material H. As described with reference to FIG. 13, in particular, a corner is easily formed at the corner where the metal post 8 is in contact with the wiring layer 7 (the location indicated by the symbol H in FIG. 9). This is because the resin layer R does not reach the depth of the corner H. For this reason, if low-viscosity SOG or resin is applied to the entire surface of the wafer, the corners can be filled in smoothly, and if the resin layer R is coated thereafter, dust can be prevented.

This covering material can also be formed in the first groove TC. In particular, since the plurality of interfaces are exposed on the side wall of the first groove TC, the interfaces can be covered, and the environmental resistance of the chip can be improved in combination with the resin layer R.

Next, a method of manufacturing the structure of FIG. 9 will be described with reference to FIG.

First, a semiconductor substrate (wafer) in which an LSI having up to the Al electrode 1 is formed in a matrix is prepared. Here, as described above, a one-layer metal, two-layer metal, IC, for example, a source electrode of a transistor,
The drain electrode is formed as a first layer metal, and the Al electrode 1 in contact with the drain electrode is formed as a second layer metal.

Here, after an opening C of the interlayer insulating film 2 from which the drain electrode is exposed is formed, an electrode material mainly composed of Al and a Ti nitride film 5 are formed on the entire surface of the wafer, and an Al electrode is formed using a photoresist as a mask. 1 and the TiN film 5 are dry-etched into a predetermined shape.

Here, a passivation film 3 is formed,
Unlike the case where a barrier metal is formed from above the opening C which is opened thereafter, the barrier metal can be formed at once including a TiN film as a barrier metal, and the number of steps can be simplified.

The Ti nitride film 5 functions as a barrier metal for a Cu thin film layer 6 to be formed later. Moreover, attention is paid to the fact that the TiN film is effective as an antireflection film. That is, it is also effective for preventing halation of the resist used in patterning. To prevent halation, a minimum of about 1200 ° to 1300 ° is required, and in order to provide a barrier metal function, it is preferably about 2000 ° to 3000 °. If the film is formed to be thicker than this, a stress occurs due to the Ti nitride film. Also, the contact with the resin layer r is not preferable because the TiN film has poor adhesion to the resin.

After the Al electrode 1 and the TiN film 5 are patterned, the entire surface is covered with a passivation film 3. Although a Si3N4 film is employed here as the passivation film, polyimide or the like can be used. (See FIG. 1 above.) Subsequently, the surface of the passivation film 3 is coated with an insulating resin layer r. In this case, a positive photosensitive polyimide film is employed for the insulating resin layer, and the insulating resin layer is covered by about 3 to 5 μm. Then, an opening K is formed.

By employing this photosensitive polyimide film, it is not necessary to separately form a photoresist to form the opening K in the patterning of the opening K in FIG. By adopting the method, the process can be simplified. Of course, photoresist is also possible.

Moreover, this polyimide film is also used for the purpose of flattening. That is, in order for the height of the solder ball 12 to be uniform in all regions, the height of the metal post 8 needs to be uniform in all regions, and the wiring layer 7 also needs to be formed flat and accurately. . For this reason, a polyimide resin is applied and the resin has a certain viscosity and has fluidity, so that it has an advantage that its surface can be flattened by being left for a desired time before curing.

Here, the Al electrode 1 also functions as a pad for external connection of the LSI, and functions as a wire bonding pad when it is not formed as a chip size package composed of solder balls (solder bumps). (The above figure 2
Next, a Cu thin film layer 6 is formed on the entire surface. The Cu thin film layer 6 will later become a plating electrode for the wiring layer 7, and is formed to a thickness of about 1000 to 2000 ° by sputtering, for example.

Subsequently, for example, a photoresist layer PR is formed on the entire surface.
1 is applied, and the photoresist PR1 corresponding to the wiring layer 7 is removed. (See FIG. 3 above.) Subsequently, C exposed at the opening of the photoresist PR1
The wiring layer 7 is formed by using the thin film layer 6 of u as a plating electrode.
This wiring layer 7 has a thickness of 2 to 5 μm in order to secure mechanical strength.
It must be formed as thick as possible. Here, it is formed using a plating method, but may be formed by vapor deposition, sputtering, or the like. When using this evaporation or sputtering,
Since the seed layer is not required, the Cu thin film layer 6 is unnecessary.

Thereafter, the photoresist layer PR1 is removed. (See FIG. 4 above.) Subsequently, a photoresist PR2 exposing a region where the metal post 8 is to be formed is formed, and a Cu metal post 8 is formed on this exposed portion by electrolytic plating. Also in this case, the Cu thin film layer 6 is used as a plating electrode. This metal post is formed at a height of about 30 to 150 μm. The height of the metal post 8 is adjusted by the coefficient of thermal expansion of the mounting substrate to which the chip size package is fixed. That is, as the height of the post is higher, the stress of the mounting board due to expansion can be absorbed by the post.

Here, sputtering can be considered as a method other than the electrolytic plating.

Here, the formation timing of the first groove TC is as follows.
Although it can be considered in various ways, the first timing may be after the metal post is formed. Here, if a line for forming the first groove TC is formed in the photoresist PR2, dicing can be performed along the exposed portion of the planned TC. In addition, if a photoresist that exposes only the first groove TC is separately formed, it can be formed by etching or dicing.

Subsequently, the photoresist PR2 is removed, and the thin film layer 6 of Cu is removed using the wiring layer 7 as a mask. Then, a low-viscosity SOG film or a liquid resist is formed on the entire surface of the wafer by, for example, spin-on. At this time, a covering portion H is formed at a corner where the edge is likely to be formed. The interface exposed on the side wall of the first trench TC is also covered with an extremely thin film.

Although spin-on is employed here as a simple manufacturing method, an SiO 2 film or a TEOS film may be formed by plasma CVD capable of forming a film at a low temperature and then etched back. (See FIG. 6 above.) Further, this coating film may be formed after the Si3N4 film is applied to all surfaces including the wiring layer 7 and the metal posts 8 by the plasma CVD method.

This is because the unhardened coating film H formed in a later step reacts with Cu by heat. Therefore, there is a problem that this interface is deteriorated. Therefore, it is necessary to cover the wiring layer 7 and the metal posts 8 with this Si3N4 film. This Si3N4 film can be omitted if the interface does not deteriorate.

After the metal post 8 is formed,
If the i3N4 film is formed, the wiring layer 7 and the metal posts 8 can be covered. It is also necessary to protect the exposed side surface M together, but here, since both are patterned and then covered with the Si3N4 film, the side surface M is also protected.

As described above, the timing for forming the first trench TC may be after the Si3N4 film is formed.

That is, since the entire surface is protected by the Si 3 N 4 film, the first trench TC can be diced or etched in this state. Further, since the Si3N4 film is formed on the entire surface of the wafer, oxidation of the metal posts 8 can be prevented.

Even when the Si3N4 film is not provided,
Since it is necessary to embed the resin layer R in the first groove, it is necessary to form the first groove TC before covering the resin layer R.

Subsequently, a resin layer R is applied to the entire surface.

This resin is initially fluid,
When the thermosetting reaction is completed, the film thickness is greatly reduced.

This resin has a fluidity so that flatness can be realized before curing, and the resin is located at the lower end from the head of the metal post due to a decrease in film thickness.

The insulating resin layers R and r also have the following merits. In general, when a viscous resin is applied with a dispenser, there is a problem that bubbles are taken in even if defoamed. If sintering is performed with the air bubbles taken in, there is a problem that the air bubbles burst in the future process or in a high-temperature atmosphere used by the user.

In this step, spin-on coating is performed, and its viscosity is adjusted so that a film thickness of about 20 to 30 μm can be formed by one spin. As a result, bubbles larger than this film thickness pop and disappear because the film is thin. Also, bubbles smaller than this thickness are blown out together with the resin blown out by the spin-on centrifugal force, and a film without bubbles can be formed.

The insulating resin layer R has a thickness of 50 μm.
Approximately 100 μm is required. In this case, the above-described principle can be adopted, and application can be performed in a plurality of times by spin-on to form while removing bubbles.

Of course, instead of employing spin-on, the coating may be performed with a dispenser.

Further, the point of the present insulating resin layer R is that it contracts during curing. Generally, the resin shrinks to some extent after curing. However, the insulating resin layer R contracts during baking, and the surface of the insulating resin layer R is located at the lower end of the metal post 8 relative to the head. Therefore, the head of the metal post 8 is exposed, so that the solder ball can be fixed.

In order to increase the strength of the solder ball,
Although it is necessary to increase the exposure ratio including the side surface of the metal post 8, the exposure ratio can also be controlled by controlling the amount of the insulating resin layer R applied.

After curing, an extremely thin film may remain on the top of the metal post 8, but in this case, the surface may be simply polished or plasma-ashed.
In particular, since the height of the metal posts is uniform as described above, all heads can be cleaned by using a flat polishing plate.

After coating the insulating resin layer R, the metal post 8 may be semi-cured to the extent that it can be polished, polished to the vicinity of the head of the metal post 8, and then completely cured. In this case, since only an extremely thin film remains on the head of the metal post 8, even if the contraction rate of the insulating resin layer R is small, the metal post can be exposed by the contraction of the insulating resin layer. That is, since the film thickness that can be arranged on the metal post 8 is determined by the shrinkage ratio of the resin, it is necessary to determine whether to polish or not to polish the metal post 8 and how much to polish it, and to expose the metal post. Good.

When the coating film H and the Si3N4 film are formed, the films are formed on the heads of the metal posts. In this case, the film is removed by wet etching, dry etching or polishing.

As for the resin layer R, as shown in FIG. 12, the wafer in the state of FIG. 6 may be mounted on dies 60, 61, and 62, and the resin layer R may be pressed and sealed by the dies. . In this case, the sheet 6 having a very small adhesiveness in consideration of the releasability.
4 are provided.

In this case, as described in the subject section,
However, this problem can be solved because the coating material H is formed in the present invention. Further, in this case, the head of the metal post 8 can be exposed by cutting or contacting the head with the sheet.

The exposed metal posts 8 are plated with Ni10 and Au. Here, since the thin film layer 6 of Cu is removed using the wiring layer 7 as a mask, electroless plating is adopted, Ni is about 1 to 3 μm, and Au11 is about 100 μm.
It is formed at 0-10000 °.

When the insulating resin layer is applied to the upper portion of the metal post head and polished, it is very difficult to find the head of the metal post. Au is 1000-10000Å
If the flat polishing is not realized, Au is exposed on one post, another post is covered with an insulating resin layer on Au, and another post is not. This creates a state in which Au is shaved. In other words, since it also serves to prevent the oxidation of Ni, there are places where the solder balls are fixed, places where they are weak, and places where they cannot be formed at all.

In the present invention, since the metal posts 8 are exposed, the barrier metals 10 and 11 can be finally formed with high accuracy, and the solder balls 12 can be fixed well.

Although the resin layer R has been described as a shrinkable type, it may be polished as described above. That is, the metal post 8 may be completely covered with the resin layer R, and then polished until the metal post 8 is exposed. In this polishing step, the resin layer R
Fills the first groove, it is possible to prevent cracks and the like caused by the first groove. (See FIG. 7 above.) Although not shown, the wafer surface is covered with a protective sheet,
Back grinding is performed as shown by the arrow to reduce the thickness of the wafer. (See FIG. 8 above.) Finally, the prepared solder balls 12 are aligned and mounted, and reflowed. Then, the semiconductor substrate is divided into chips along scribe lines by a dicing process,
Completed as chip size package.

The timing for melting the solder is before the dicing.

This dicing is a characteristic feature. The dicing blade DC has a width smaller than that of the first groove TC.
Is prepared, and a full cut is made substantially at the center of the first groove by using this. Since the first groove TC is realized by, for example, a half cut reaching the semiconductor substrate, the interface end of each layer formed above the semiconductor substrate is protected by the coating resin H and the resin layer R. CSP.

Further, it has the following features. That is, in the chip size package realized in FIGS. 12 and 13, an extremely thin wafer is mounted in a mold, and the resin 63 is pressed and sealed. However, when small particles are present on the back surface of the wafer, there is a problem that the wafer is broken with the particles as fulcrums. However, this problem is eliminated when the resin layer R is formed by spin-on.

Although the present invention has been described with reference to the rewiring type, it goes without saying that the present invention can also be implemented with a resin-sealed type.

[0088]

According to the present invention, firstly, the corner formed around the contact portion of the lower layer of the metal post is provided with a coating material which makes the corner smooth, so that generation of dust can be prevented.

Secondly, a coating material for smoothing the corner formed around the contact portion of the lower layer of the metal post is provided, and a resin layer covering the side wall around the chip and the corner formed at the bottom of the side wall are provided. Since the covering material is also provided between the first dicing grooves, it is possible to suppress the formation of the first dicing groove.

Third, if the covering material is formed so as to cover the interface exposed on the side wall, it is possible to prevent water vapor and the like entering from the interface, and to form a material having excellent environmental resistance.

Fourthly, a wiring layer made of metal is in contact with the lower layer of the metal post, and the covering material is also provided on the corner formed around the contact portion of the lower layer of the wiring layer, so that the wiring layer is in contact with the wiring layer. An interface with the lower layer can be covered, and a material having excellent environmental resistance can be formed. Fifth, the coating can be realized in a very simple way with spin-on materials, thus increasing the cost advantage.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a diagram illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a diagram illustrating a conventional chip size package.

FIG. 11 is a diagram illustrating a conventional chip size package.

FIG. 12 is a diagram illustrating a method for manufacturing a semiconductor device using a mold.

FIG. 13 is a diagram illustrating a method for manufacturing a semiconductor device using a mold.

Continued on the front page (72) Inventor Hiroyuki Shinoki 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. 4M109 AA01 BA07 CA04 DB17 EA02 EA08 EA11 EA12 EC01 EC03 ED02 ED03 ED05 EE01 EE03

Claims (5)

[Claims] 1. A semiconductor device having a metal post electrically connected to an electrode of an LSI, a resin covering a periphery of the metal post, and a solder ball or a solder bump connected to the metal post. A semiconductor device, comprising: a coating material for smoothing a corner formed around a contact portion of the metal post lower layer. 2. A semiconductor device comprising: a metal post electrically connected to an electrode of an LSI; a resin surrounding the metal post; and a solder ball or a solder bump connected to the metal post. A coating material is formed around the contact portion of the lower layer of the metal post to smooth the corner portion, and the coating material is provided between the resin layer covering the side wall around the chip and the corner portion formed at the bottom of the side wall. A semiconductor device comprising a material. 3. The semiconductor device according to claim 2, wherein said covering material covers an interface exposed on said side wall. 4. A wiring layer made of metal abuts on the lower layer of the metal post, and the covering material is provided at a corner formed around a contact portion of the lower layer of the wiring layer. Alternatively, the semiconductor device according to claim 3. 5. The semiconductor device according to claim 1, wherein said coating material is made of a material that can be turned on.