JP2000243774A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To substantially equalize heights of metal post head parts, when a chip size package is manufactured. SOLUTION: If an insulated resin layer (r) is coated with a resin having flowability, after a predetermined leaving time elapses, the surface of the insulated resin layer (r) is flattened. For this reason, if the size of a metal post 8 is equalized, it is possible to substantially equalize heights (the height from the back face of a wafer to a metal post head part) of head parts of the metal posts 8 dotted over the entire wafer. Accordingly, the heights of the head parts of solder balls also become uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a chip size package and a method for manufacturing the same. The chip size package (Chip Size Package) is also referred to as a CSP, and is a general term for packages having a size equal to or slightly larger than the chip size, and is a package for high-density mounting. The present invention relates to a metal post used in a CSP and a resin covering the metal post.

[0002]

2. Description of the Related Art Conventionally, in this field, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, a fine pitch BGA, a structure in which the ball pitch of the BGA is further narrowed and the outer shape is close to the chip size, etc. Are known.

Recently, there is a wafer CSP described in “Nikkei Microdevice”, August 1998, pp. 44-71. This wafer CSP is basically a CSP in which wiring or array-like pads are formed by a wafer process (pre-process) before dicing a chip.
It is expected that this technology will integrate the wafer process and the package process (post-process), thereby greatly reducing the package cost.

There are two types of wafer CSP: a sealing resin type and a rewiring type. The sealing resin mold has a structure in which the surface is covered with a sealing resin, similarly to a conventional package, and has a structure in which metal posts are formed on a wiring layer on the chip surface and the periphery thereof is solidified with the sealing resin.

It is generally said that when a package is mounted on a printed circuit board, stress generated due to a difference in thermal expansion between the printed circuit board and the printed circuit board is concentrated on the metal posts. It is believed to be decentralized.

On the other hand, in the rewiring type, as shown in FIG.
This is a structure in which rewiring is formed without using a sealing resin. That is, the Al electrode 52, the wiring layer 53, and the insulating layer 54 are stacked on the surface of the chip 51, and the metal posts 55 are formed on the wiring layer 53.
Is formed, and a solder bump 56 is formed thereon. The wiring layer 53 is used as rewiring for arranging the solder bumps 56 on the chip in a predetermined array.

[0007] The sealing resin mold has a metal post of 100 μm.
By lengthening it and reinforcing it with sealing resin,
High reliability is obtained. However, the process of forming the sealing resin needs to be performed using a mold in a later step, and the process becomes complicated.

On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, there is a need to relieve stress in some way to increase reliability.

FIG. 11 omits the wiring layer 53 of FIG. 10 and forms an opening exposing the Al electrode 52, and the metal post 55 and the Al electrode 52 are formed in this opening.
, A barrier metal 58 is formed at least one layer, and a solder ball 56 is formed on the metal post 55.

[0010]

However, in FIG. 10, since the insulating film under the wiring layer 53 is formed by tracing the unevenness of the underlying film substantially as it is, the wiring layer formed over the entire chip is formed. 53 is formed according to the irregularities. Therefore, even if the height of the metal post 55 is constant,
Since irregularities are formed on the entire surface of the wafer, the height from the back surface of the semiconductor substrate to the metal posts 55 varies.

FIG. 10 shows an example in which the semiconductor device is soldered to a mounting substrate such as a printed circuit board or a ceramic substrate. Since the height from the semiconductor substrate varies, the solder balls are electrically connected to the conductive patterns on the mounting substrate. There was a problem that some were not connected and some were not connected.

Further, the back surface of the wafer may be shaved due to the tendency to be light, thin and small. In this case, there is a problem that the wafer is broken when it is mounted on a mold described with reference to FIGS.

As shown in FIG. 12, after mounting the semiconductor wafer, a resin 63 is placed in dies 60, 61 and 62.
And melt under pressure. The semiconductor chip 51 is placed in a mold with a large number of metal posts 55 erected, and the resin 63 is pressed by the mold to cover the entire surface of the wafer.
Here, reference numeral 64 is a sheet for peeling from the mold.

However, if all the metal post heads are pressed so as to be in contact with the mold and the sheet 64, there is a problem that the wafer is distorted and the wafer is broken. In particular, dust (metal particles of several μm to several tens of μm) and the like may be present on the back surface of the wafer.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. First, a first insulating layer which is in contact with a wiring layer is made of a fluid material and is adhered to the wafer. rear,
The problem is solved by forming the wiring layer after the first insulating layer is flattened after a predetermined time has passed, the surface of which is made of a material having substantially flatness.

For example, the passivation film 3 traces irregularities on the silicon substrate. However, if a resin having a predetermined viscosity before curing is coated thereon with a film thickness that completely exceeds the head of the passivation film, the surface thereof is flat over the entire wafer because of the fluidity. Can be Therefore, since the wiring layer is formed on the cured flat resin layer r, even if a plurality of metal posts are formed on the semiconductor chip, the height from the back surface of the substrate to the top of the metal posts is all uniform.

Further, the problem is solved by forming the material by spin-on.

Spin-on is a technique that has been widely adopted in a normal semiconductor device manufacturing method, and can be easily performed without additional equipment.

The insulating layer made of the resin is made of a fluid material, and is applied to the wafer by spin-on.
The problem is solved by making the surface of the material having a substantially flat property after a predetermined time elapse.

As described above, the height of the metal post head can all be uniform from the back surface of the wafer, but the wafer may be warped. But without adopting the mold method,
Since it is formed by spin-on, solidification by pressing is not required, and wafer cracks can be prevented.

Instead of spin-on, resin can be applied to the wafer with a dispenser.

[0022]

Next, an embodiment of the present invention will be described.

In FIG. 9, reference numeral 1 denotes the uppermost layer of metal (a part which also functions as a bonding pad) in a normal wire bonding type IC chip. The interlayer insulating film in which the hole C is formed is shown in FIG. Here, the reference numeral 1 is named Al electrode, but the material is Au, and recently, Cu electrode is used.
Is also conceivable. The material is not particularly limited as long as it is a material that can be bonded.

In the lower layer of the contact hole C,
Metal is formed in a plurality of layers, for example, a transistor (MO
S type transistor or BIP type transistor),
It is in contact with a diffusion region, a poly-Si gate, poly-Si or the like.

Here, it is needless to say that the present embodiment can be carried out with a MOS type or a BIP.

This structure is an IC generally called a one-layer metal, a two-layer metal, or the like.

That is, although not shown, as the number of metals increases to two, three,.
A metal and an insulating layer of each layer are formed, and their interfaces are exposed in a first groove TC described later.

FIG. 3 shows a passivation film. Here, the passivation film 3 is made of a Si nitride film, epoxy resin, polyimide, or the like.
The insulating resin layer r is covered.

When a resin is used as the passivation film, the same material as the insulating resin layer r may be used.

The feature of the present invention resides in the insulating resin layer r. As described later, since the resin before curing having fluidity is covered, the surface of the insulating resin layer r can be flattened by leaving the resin for a predetermined time.

For example, as described later, the insulating resin layer r is coated with a relatively low viscosity by spin-on or the like, and the surface thereof can be made flat by leaving it to stand. for that reason,
The wiring layer 7 can be made flat, and the height from the back surface of the wafer to the solder balls can be made constant.

When a resin with a sheet is used as shown in FIG. 12, when the film is pressed with a mold before curing, the height of the metal post 8 is uniform, so that all metal post heads are used. Can be brought into contact with the film 64, and highly accurate metal exposure can be performed. In addition, if all the metal posts do not contact the film, the entire metal posts will not be exposed. Therefore, a certain amount of pressure is required, but the insulating resin layer r becomes flat, and the distance between the metal post head and the wafer back surface becomes substantially uniform, so that the pressing force of the mold can be small. .

The details of the metal post will be described in the process.

On the Al electrode 1, a Ti nitride film 5 is formed.

An opening K exposing the TiN film 5 is formed in the passivation film 3 and the insulating resin layer r, and a Cu thin film layer 6 is formed here as a plating electrode (seed layer) of the wiring layer 7. Is done. Then, a wiring layer 7 formed by Cu plating is formed thereon.

Then, on the entire surface of the chip including the wiring layer 7,
A resin layer R made of resin is formed. However, although omitted in the drawing, an Si3N4 film may be provided at the interface between the resin layer R and the wiring layer 7 and between the resin layer R and the metal post 8.

As described in FIG. 12, the resin layer R may be sealed with a mold. In addition, since the wafer is easily broken due to dust in the mold (described in the section of the problem to be solved by the present invention), like the insulating resin layer r, it is made of a fluid resin, and its surface is left by leaving. It may be flat.

In this case, both methods can be used as long as the resin is a thermosetting resin or a thermoplastic resin. In particular, as the thermosetting resin, an amic acid film, a polyimide resin, or an epoxy resin is preferable. Further, if it is a thermoplastic resin, a thermoplastic polymer (Hitachi Chemical Co., Ltd .: Himal) or the like is preferable. The amic acid film has a shrinkage of 30 to 50%.

Here, the resin R is prepared mainly from liquid amic acid, and is spin-on or laminated (vacuum) over the entire surface of the wafer. The thickness is 50-150μm
It is about. Thereafter, the resin R is polymerized by a thermosetting reaction. The temperature is at least 300 ° C. However, there is a problem that the resin made of amic acid before thermosetting becomes active under the above-mentioned temperature, reacts with Cu, and deteriorates the interface. However, the reaction with Cu can be prevented by covering the surface of the wiring layer with the Si3N4 film. Here, the thickness of the Si3N4 film is about 1000 to 3000 degrees.

The Si 3 N 4 film is an insulating film having excellent barrier properties, and the SiO 2 film is inferior to the Si 3 N 4 film in barrier properties. However, when the SiO2 film is used, it is necessary to make the film thickness thicker than the Si3N4 film. Further, since the Si3N4 film can be formed by the plasma CVD method, its step coverage is excellent and is preferable. Further, since the resin layer R is coated after the formation of the metal post 8, the formation of the Si3N4 film not only prevents the reaction between the wiring layer 7 made of Cu and the resin layer containing amic acid as a main material, but also prevents the Cu layer from reacting. Between the metal post 8 and the resin layer R containing amic acid as a main material can also be prevented.

When the resin R is cured, the resin layer R in a state having fluidity before curing contracts during the curing, and as shown in FIG.
The film thickness is greatly reduced as shown in FIG. Therefore, the surface of the resin layer R is located at the lower end of the metal post 8 from the head, and the metal post 8 is exposed. Therefore, there is no need to remove the resin layer R and expose the head. In order to expose the head uniformly in this polishing step, very difficult control is required, but the head can be easily exposed by contraction of the resin.

In this step, the resin R having a small shrinkage
May be applied and polished to expose the head of the metal post 8 after curing.

Accordingly, the metal post 8 is provided at the end of the wiring layer 7.
Of the metal post 8 can form a barrier metal on the head of the metal post 8. Here, Ni10, Au
11 is formed by electroless plating.

If the solder ball is formed directly on the metal post 8 made of Cu, the connection strength with the solder ball is deteriorated due to the oxidized Cu. When Au is directly formed to prevent oxidation, Au is diffused, so that N
i is inserted. Ni prevents oxidation of Cu, and Au prevents oxidation of Ni. Therefore, deterioration of the solder ball and deterioration of the strength are suppressed.

On the head of the metal post 8, a solder ball 12 or a solder bump is formed.

Here, the difference between the solder ball and the solder bump will be described. The solder ball is prepared by separately preparing ball-shaped solder in advance and fixed to the metal post 8.
The solder bump is formed by electrolytic plating via the wiring layer 7 and the metal post 8. The solder bump is initially formed as a thick film, and is formed into a spherical shape by post-heating.

In this case, since the seed layer is removed in the step of FIG. 6, electrolytic plating cannot be employed, and solder balls are actually prepared.

Finally, a first groove indicated by TC is formed around each chip prepared in a wafer state, and an insulating resin layer R is embedded in this groove. Here, the same material as the resin layer R is formed for simplification of the process,
They need not be the same unless the process is simplified.

The groove TC and the resin layer are features and are fully cut by a dicing blade DC narrower than the first groove TC. That is, the first groove TC
And a resin layer is arranged between the full cut line DL and
The interface end of each layer that causes moisture resistance deterioration can be covered, and element deterioration can be prevented.

The second characteristic lies in the provision of the coating material H. In the corners where the metal posts 8 are in contact with the wiring layer 7 (indicated by the reference numeral H in FIG. 9), it is inevitable that a metal is formed. This is because the resin layer R does not reach the depth of the corner H. For this reason, if low-viscosity SOG or resin is applied to the entire surface of the wafer, the corners can be filled in smoothly, and if the resin layer R is coated thereafter, dust can be prevented.

This covering material can also be formed in the first groove TC. In particular, since the plurality of interfaces are exposed on the side wall of the first groove TC, the interfaces can be covered, and the environmental resistance of the chip can be improved in combination with the resin layer R.

Next, a method of manufacturing the structure of FIG. 9 will be described with reference to FIG.

First, a semiconductor substrate (wafer) in which an LSI having up to the Al electrode 1 is formed in a matrix is prepared. Here, as described above, a one-layer metal, two-layer metal, IC, for example, a source electrode of a transistor,
The drain electrode is formed as a first layer metal, and the Al electrode 1 in contact with the drain electrode is formed as a second layer metal.

Here, after the opening C of the interlayer insulating film 2 from which the drain electrode is exposed is formed, an electrode material mainly composed of Al and a Ti nitride film 5 are formed on the entire surface of the wafer, and the Al electrode is formed using a photoresist as a mask. 1 and the TiN film 5 are dry-etched into a predetermined shape.

Here, a passivation film 3 is formed,
Unlike the case where a barrier metal is formed from above the opening C which is opened thereafter, the barrier metal can be formed at once including a TiN film as a barrier metal, and the number of steps can be simplified.

The Ti nitride film 5 functions as a barrier metal for a Cu thin film layer 6 to be formed later. Moreover, attention is paid to the fact that the TiN film is effective as an antireflection film. That is, it is also effective for preventing halation of the resist used in patterning. To prevent halation, a minimum of about 1200 ° to 1300 ° is required, and in order to provide a barrier metal function, it is preferably about 2000 ° to 3000 °. If it is formed thicker than this, a stress is generated due to the Ti nitride film. Also, the contact with the resin layer r is not preferable because the TiN film has poor adhesion to the resin.

After the Al electrode 1 and the TiN film 5 are patterned, the entire surface is covered with a passivation film 3. Although a Si3N4 film is employed here as the passivation film, polyimide or the like can be used. (See FIG. 1 above.) Subsequently, the surface of the passivation film 3 is coated with an insulating resin layer r. In this case, a positive photosensitive polyimide film is employed for the insulating resin layer, and the insulating resin layer is covered by about 3 to 5 μm. Then, an opening K is formed.

By employing this photosensitive polyimide film, it is not necessary to form a separate photoresist to form the opening K in the patterning of the opening K in FIG. 2, so that a glass photomask and metal mask can be used. By adopting the method, the process can be simplified. Of course, photoresist is also possible.

Moreover, this polyimide film is formed as shown in FIG.
As shown in (b), it is also used for the purpose of flattening.
That is, in order for the height of the solder ball 12 to be uniform in all regions, the height of the metal post 8 needs to be uniform in all regions, and the wiring layer 7 also needs to be formed flat and accurately. . For that, apply polyimide resin,
Since it is a fluid resin having a certain viscosity, it has an advantage that its surface can be flattened by being left for a desired time before curing.

That is, as shown in (a), a resin having fluidity and having a flat surface when left for a predetermined time is coated. This may be applied by spin-on or by a dispenser. The resin coated by this method is the resin layer r immediately before the application in the figure.

The resin layer r is coated with a film thickness that completely exceeds the highest part of the unevenness of the wafer, and its surface becomes flat due to its fluidity when left for a predetermined time. This is the insulating resin layer r after being left as shown in FIG.

Therefore, the wiring layer 7 is formed flat by making the insulating resin layer r flat.

Here, the Al electrode 1 also serves as a pad for external connection of the LSI, and functions as a wire bonding pad when it is not formed as a chip size package composed of solder balls (solder bumps). (The above figure 2
Next, a Cu thin film layer 6 is formed on the entire surface. The Cu thin film layer 6 will later become a plating electrode for the wiring layer 7, and is formed to a thickness of about 1000 to 2000 ° by sputtering, for example.

Subsequently, for example, a photoresist layer PR is formed on the entire surface.
1 is applied, and the photoresist PR1 corresponding to the region where the wiring layer 7 is formed is removed. (See FIG. 3 above.) Subsequently, C exposed at the opening of the photoresist PR1
The wiring layer 7 is formed by using the thin film layer 6 of u as a plating electrode.
This wiring layer 7 has a thickness of 2 to 5 μm in order to secure mechanical strength.
It must be formed as thick as possible. Here, it is formed using a plating method, but may be formed by vapor deposition, sputtering, or the like. When using this evaporation or sputtering,
Since the seed layer is not required, the Cu thin film layer 6 is unnecessary.

Thereafter, the photoresist layer PR1 is removed. As described above, since the insulating resin layer r is flat, all the wiring layers 7 scattered on the wafer are all flat. (See FIG. 4 above.) Subsequently, a photoresist PR2 exposing a region where the metal post 8 is to be formed is formed, and a Cu metal post 8 is formed on this exposed portion by electrolytic plating. Also in this case, the Cu thin film layer 6 is used as a plating electrode. This metal post is formed at a height of about 30 to 150 μm. The height of the metal post 8 is adjusted by the coefficient of thermal expansion of the mounting substrate to which the chip size package is fixed. In other words, the higher the height of the post, the more the stress of the mounting board caused by expansion can be absorbed.

Here, sputtering can be considered as a method other than the electrolytic plating.

Here, the formation timing of the first groove TC is as follows.
Although it can be considered in various ways, the first timing may be after the metal post is formed. Here, if a line for forming the first groove TC is formed in the photoresist PR2, dicing can be performed along the exposed portion of the planned TC. In addition, if a photoresist that exposes only the first trench TC is separately formed, since the metal post 8 is protected by the resist, it can be formed by etching or dicing. Subsequently, the photoresist PR2 is removed, and the thin film layer 6 of Cu is removed using the wiring layer 7 as a mask. Here, a low-viscosity SOG film or a liquid resist may be formed on the entire surface of the wafer by, for example, spin-on. At this time, a covering portion H is formed at a corner where the edge is likely to be formed. Also, the interface exposed on the side wall of the first trench TC is covered with an extremely thin film.

Although spin-on is employed here as a simple manufacturing method, an SiO 2 film or a TEOS film may be formed by plasma CVD capable of forming a film at a low temperature and then etched back.

Further, this coating film may be formed after the Si3N4 film is applied to all surfaces including the wiring layer 7 and the metal posts 8 by the plasma CVD method. This is because the unhardened coating film H and Cu formed in a later step react by heat. Therefore, there is a problem that this interface is deteriorated. Therefore, it is necessary to cover the wiring layer 7 and the metal posts 8 with this Si3N4 film. This Si3N4 film can be omitted if the interface does not deteriorate.

After the metal post 8 is formed, S
If the i3N4 film is formed, the wiring layer 7 and the metal posts 8 can be covered. It is also necessary to protect the exposed side surface M together, but here, since both are patterned and then covered with the Si3N4 film, the side surface M is also protected.

As described above, the timing of forming the first trench TC may be after the Si3N4 film is formed.

That is, since the entire surface is protected by the Si3N4 film, the first trench TC can be diced or etched in this state. Further, since the Si3N4 film is formed on the entire surface of the wafer, oxidation of the metal posts 8 can be prevented.

Even when the Si3N4 film is not provided,
Since it is necessary to embed the resin layer R in the first groove, it is necessary to form the first groove TC before covering the resin layer R. (See FIG. 6 above.) Subsequently, a resin layer R is applied to the entire surface.

This resin is initially fluid,
As shown in FIG. 7A, the surface of the insulating resin layer R has irregularities, but becomes flat when left for a predetermined time.

As shown in FIG. 7 (b), a film whose thickness is greatly reduced after the completion of the thermosetting reaction may be employed.

This resin has a fluidity so that flatness can be realized before curing, and the resin is located at the lower end from the head of the metal post due to a decrease in film thickness.

The insulating resin layers R and r also have the following merits. In general, when a viscous resin is applied with a dispenser, there is a problem that air bubbles are taken in even if the resin is defoamed in advance. When thermosetting with air bubbles,
There is a problem that bubbles will burst in the future process or in the use of a high-temperature atmosphere on the user side.

In this step, spin-on coating is performed, and its viscosity is adjusted so that a film thickness of about 20 to 30 μm can be formed by one spin. As a result, bubbles larger than this film thickness pop and disappear because the film is thin. Also, bubbles smaller than this thickness are blown out together with the resin blown out by the spin-on centrifugal force, and a film without bubbles can be formed.

The insulating resin layer R has a thickness of 50 μm.
Approximately 100 μm is required. In this case, the above-described principle can be adopted, and application can be performed in a plurality of times by spin-on to form while removing bubbles.

Of course, instead of employing spin-on, the coating may be performed with a dispenser.

Further, the point of the present insulating resin layer R is that it contracts during curing. Generally, the resin shrinks to some extent after curing. However, the insulating resin layer R contracts during baking, and the surface of the insulating resin layer R is located at the lower end of the metal post 8 relative to the head. Therefore, the head of the metal post 8 is exposed, so that the solder ball can be fixed.

In order to increase the strength of the solder ball,
It is necessary to increase the exposure ratio of the metal post head including the side surfaces of the metal posts 8, but this can also be controlled by controlling the amount of the insulating resin layer R applied.

After curing, a very thin film may remain on the head of the metal post 8, but in this case, the surface may be simply polished or plasma-ashed.
In particular, since the height of the metal posts is uniform as described above, all heads can be cleaned by using a flat polishing plate.

Further, after the insulating resin layer R is coated, it may be semi-cured to the extent that it can be polished, polished to the vicinity of the head of the metal post 8, and then completely cured. In this case, since only an extremely thin film remains on the head of the metal post 8, even if the contraction rate of the insulating resin layer R is small, the metal post can be exposed by the contraction of the insulating resin layer. That is, since the film thickness that can be arranged on the metal post 8 is determined by the shrinkage ratio of the resin, it is necessary to determine whether to polish or not to polish the metal post 8 and how much to polish it, and to expose the metal post. Good.

When the covering film H and the Si3N4 film are formed, the film is formed on the top of the metal post. In this case, the film is removed by wet etching, dry etching or polishing.

As shown in FIG. 12, the resin layer R may be formed by mounting the wafer in the state shown in FIG. 6 on dies 60, 61, and 62, and sealing the resin layer R with the dies. . In this case, the sheet 6 having a very small adhesiveness in consideration of the releasability.
4 are provided.

In this case, as described in the subject section,
Since the insulating resin layer r is flat, the head of the metal post 8 also has a uniform height over the entire area. Therefore, all the heads of the metal posts 8 are brought into contact with the film, or they can be brought into contact with a small pressing force without being brought into contact with the film. Can be.

The exposed metal posts 8 are plated with Ni10 and Au. Here, since the thin film layer 6 of Cu is removed using the wiring layer 7 as a mask, electroless plating is adopted, Ni is about 1 μm, and Au11 is about 5000 °.
Is formed.

If an insulating resin layer is applied to the upper portion of the metal post head and polished, it is very difficult to find the head of the metal post. Also, Au is in the uppermost layer with a film thickness of about 5000 °, so if flat polishing is not realized, some posts have Au and another post has
An insulating resin layer covers Au and another post is A
This creates a state in which u is shaved. In other words, since it also serves to prevent the oxidation of Ni, there are places where the solder balls are fixed, places where they are weak, and places where they cannot be formed at all.

In the present invention, since the metal posts 8 are exposed, the barrier metals 10 and 11 can be formed with high accuracy and the solder balls 12 can be fixed well.

Although the resin layer R has been described as a shrinkable type, it may be polished as described above. That is, the metal post 8 may be completely covered with the resin layer R, and then polished until the metal post 8 is exposed. In this polishing step, the resin layer R
Fills the first groove, it is possible to prevent cracks and the like caused by the first groove. (See FIG. 7 above.) Although not shown, the wafer surface is covered with a protective sheet,
Back grinding is performed as shown by the arrow to reduce the thickness of the wafer. (See FIG. 8 above.) Finally, the prepared solder balls 12 are aligned and mounted, and reflowed. Then, the semiconductor substrate is divided into chips along scribe lines by a dicing process,
Completed as chip size package.

Here, the timing of melting the solder is before the dicing.

This dicing is a characteristic feature. The dicing blade DC has a width smaller than that of the first groove TC.
Is prepared, and a full cut is made substantially at the center of the first groove by using this. Since the first groove TC is realized by, for example, a half cut reaching the semiconductor substrate, the interface end of each layer formed above the semiconductor substrate is protected by the coating resin H and the resin layer R. CSP.

Further, it has the following features. That is, in the chip size package realized in FIGS. 12 and 13, an extremely thin wafer is mounted in a mold, and the resin 63 is pressed and sealed. However, when small particles are present on the back surface of the wafer, there is a problem that the wafer is broken with the particles as fulcrums. However, this problem is eliminated when the resin layer R is formed by spin-on. (Refer to FIG. 9 above.) Although the present invention has been described with reference to the rewiring type, it goes without saying that the present invention can also be implemented with a resin-sealed type.

[0095]

According to the present invention, first, the first insulating layer which is in contact with the wiring layer is made of a fluid material, and the surface of the first insulating layer is formed when a predetermined time elapses after being attached to the wafer. By forming the wiring layer after the first insulating layer is flattened, even if a plurality of metal posts are formed on the semiconductor chip, the metal posts are formed from the back surface of the substrate. The height to the head is all uniform.

Further, by forming the material by spin-on, the material can be simplified without additional facilities.

Further, since the insulating layer made of the resin is formed by spin-on without using a mold method, pressing and solidifying becomes unnecessary, and a wafer crack can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a diagram illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a diagram illustrating a conventional chip size package.

FIG. 11 is a diagram illustrating a conventional chip size package.

FIG. 12 is a diagram illustrating a method for manufacturing a semiconductor device using a mold.

FIG. 13 is a diagram illustrating a method for manufacturing a semiconductor device using a mold.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/92 604S (72) Inventor Yukihiro Takao 2-5-5 Keihanhondori, Moriguchi-shi, Osaka, Sanyo Inside Electric Co., Ltd. (72) Inventor Hiroyuki Shinoki 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) 4M104 BB02 BB04 BB05 BB09 BB30 DD52 DD53 EE05 EE14 EE17 EE18 HH20 5F033 HH08 HH11 HH33 JJ01 JJ07 JJ08 JJ11 JJ13 KK01 KK08 MM05 MM08 NN01 NN06 NN12 PP15 PP27 PP28 QQ09 QQ10 QQ12 QQ37 QQ42 QQ46 QQ73 QQ74 QQ75 RR04 RR06 RR21 RR22 SS15 SS21 TT04XXV XXXXX

Claims (3)

[Claims] 1. A first insulating layer having a first opening exposing a part of a metal electrode pad is formed on a wafer, the first insulating layer being connected to the metal electrode pad exposing from the first opening, Forming a wiring layer made of Cu extending on the surface of the wafer, covering the surface of the wafer including the first insulating layer and the wiring layer with an insulating layer made of resin, and soldering the metal posts exposed from the insulating layer; In a method of manufacturing a semiconductor device in which balls (or solder bumps) are formed and the wafer is cut into individual semiconductor devices, the first insulating layer in contact with the wiring layer is made of a fluid material. A semiconductor having a surface substantially made of a material having a substantially flat surface after a lapse of a predetermined time after being attached to the wafer, and forming the wiring layer after the first insulating layer is flattened; Equipment manufacturing method . 2. The method according to claim 1, wherein the material is formed by spin-on. 3. The method according to claim 1, wherein the insulating layer made of the resin is made of a fluid material, and the surface thereof is made of a material having a substantially flat surface after a predetermined time elapses after being applied to the wafer by spin-on. Item 3. A method for manufacturing a semiconductor device according to Item 2.