JP2000216275A - Nonvolatile semiconductor storage device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dispersion in a threshold voltage at writing/erasing of a nonvolatile semiconductor device by optimizing both tunnel insulating film characteristics and gate insulating film characteristics, between a floating gate and control gate with a process which is relatively simplified. SOLUTION: A floating gate 14 formed on a semiconductor substrate 11 via a tunnel insulating film 13 and a control gate 16 formed on the floating gate 14 via a gate insulating film 15 are provided. Here, the floating gate 14 is formed of first and second impurity concentration layers 14a and 14b with a phosphorus which is single impurity doped at different concentrations, respectively, while the particle size of the first impurity concentration layer 14a on the side of tunnel insulating film 13 is smaller than that of the second impurity concentration layer 14b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, an EPR
The present invention relates to a nonvolatile semiconductor memory device such as an OM, an E ² PROM, and a flash type E ² PROM and a method of manufacturing the same, and more particularly, to a structure and a method of forming a floating gate of the nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art A typical EPROM of a nonvolatile semiconductor memory device is, for example, a source region 106 of an element forming region formed by a field oxide film 102 of a semiconductor substrate 101 as shown in FIG. A floating gate 104 made of, for example, polysilicon on a channel region between drain and drain region 107 via tunnel oxide film 103, and a control gate formed on insulating film 105 on floating gate 104. 108. EP of the above configuration
In the ROM, a positive voltage is applied to the control gate 108 and the drain region 107 so that the drain region 10
Electrons having high energy generated near 7 are injected into the floating gate 104 through the tunnel oxide film 103. Thus, the threshold voltage of the EPROM cell is changed by the electric charge injected into the floating gate 104, and data can be written. Further, the floating gate 10 is formed through the tunnel oxide film 103.
By extracting the charge from No. 4, data can be erased. As a method of forming a floating gate of a nonvolatile semiconductor memory device such as the above-described EPROM, E ² PROM, flash type E ² PROM, etc., CVD (C
Chemical Vapor Deposition (PDAS) (Phospho
rus Doped AmorphousSilicon) and DOPOS (Phosphorus
Doped Poly Silicon) is known. PDAS or DOPOS by CVD is a technique of doping phosphorus during a process of forming amorphous silicon or polysilicon by CVD.

In PDAS and DOPOS by the CVD method, for example, the reliability of the oxide film is improved by reducing the heat history as compared with the method of doping impurities in a diffusion furnace after forming a polysilicon film by the CVD method. The retention characteristics (charge release characteristics on the low potential side), disturb characteristics (charge release characteristics on the high potential side), and endurance characteristics (repetitive write / erase characteristics) of the nonvolatile semiconductor memory device are improved.

[0004]

However, in practice, it is difficult to greatly improve each of the above-mentioned characteristics by simply using PDAS or DOPOS by the CVD method for simply forming the floating gate. It has also been difficult to stably control characteristics (variation in threshold voltage during writing / erasing).

In the above nonvolatile semiconductor memory device, electrons tunnel from the semiconductor substrate to the floating gate via the tunnel oxide film. For this reason, it is indispensable that the tunnel current flows stably without variation. This tunnel current largely depends on the grain size of the polysilicon constituting the floating gate. It is known that the smaller the grain size is, the more stable the tunnel current flows. On the other hand, when considering the leakage current between the floating gate and the control gate, it is known that the larger the grain size at the interface of the floating gate, the smaller the leakage current, and the better the withstand voltage and data retention characteristics.

For this reason, a technique for optimizing both the characteristics of the tunnel insulating film and the characteristics of the inter-gate insulating film between the floating gate and the control gate is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-99256. This publication states that the floating gate is formed of two layers of polysilicon film, the polysilicon film on the tunnel insulating film side is doped with phosphorus as an impurity, and the polysilicon film on the control gate side is doped with arsenic as an impurity. Thus, a technique is disclosed in which the grain size of the polysilicon film on the tunnel insulating film side is reduced and the grain size of the polysilicon film on the control gate side is increased. In this technique, after forming a polysilicon film on the tunnel insulating film side, phosphorus is doped by ion implantation or diffusion to reduce the grain size, and a polysilicon film is further formed on the polysilicon film to form a polysilicon film. The silicon film is doped with arsenic by ion implantation or diffusion to increase the grain size. However, in this technique, impurities are implanted after forming a polysilicon film,
After that, it is necessary to perform an annealing treatment, so that the number of steps increases, and there is a disadvantage that the steps are complicated because different impurities are used for controlling the grain size.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has both characteristics of a tunnel insulating film and characteristics of an inter-gate insulating film between a floating gate and a control gate by a relatively simplified process. It is an object of the present invention to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can optimize the characteristics of the nonvolatile semiconductor device and improve the characteristics of the nonvolatile semiconductor device.

[0008]

The present invention has a floating gate formed on a semiconductor substrate via a tunnel insulating film, and a control gate formed on the floating gate via an inter-gate insulating film. In the nonvolatile semiconductor memory device, the floating gate is formed from first and second impurity concentration layers each doped with a single impurity at a different concentration, and a first impurity on a side of the tunnel insulating film is formed. The particle diameter of the impurity concentration layer is smaller than the particle diameter of the second impurity concentration layer.

The floating gate is made of polysilicon.

The floating gate is made of amorphous silicon.

[0011] The impurity comprises phosphorus.

The particle diameter of the first impurity concentration layer located on the tunnel insulating film side of the floating gate is 3
The particle diameter of the second impurity concentration layer is about 60 to 300 nm.

The first and second impurity concentration layers have a higher impurity concentration in the first impurity concentration layer located on the tunnel insulating film side than in the second impurity concentration layer.

The thickness of the first impurity concentration layer is smaller than the thickness of the second impurity concentration layer.

Further, the present invention provides a nonvolatile semiconductor memory having a floating gate formed on a semiconductor substrate via a tunnel insulating film, and a control gate formed on the floating gate via an inter-gate insulating film. A method for manufacturing a device, comprising: a first impurity concentration layer forming a part of the floating gate by doping an impurity at a predetermined concentration while depositing a material for forming a floating gate on the tunnel insulating film by a chemical reaction; Forming the floating gate on the first impurity concentration layer, and doping the impurity at a higher concentration than the first impurity concentration layer while depositing a material for forming the floating gate by a chemical reaction to remove the remainder of the floating gate. Forming a second impurity concentration layer to be formed.

The impurity is phosphorus.

The step of forming the first impurity concentration layer comprises:
The step is performed at a higher temperature than the step of forming the second impurity concentration layer.

The step of forming the first impurity concentration layer comprises:
The step of forming the second impurity concentration layer is performed at a temperature of about 620 ° C., and the step of forming the second impurity concentration layer is performed at a temperature of about 530 ° C.

The step of forming the first and second impurity concentration layers is performed under reduced pressure.

The step of forming the first impurity concentration layer is performed under a higher pressure than the step of forming the second impurity concentration layer.

In the step of forming the first and second impurity concentration layers, a mixture of PH ₃ and SiH ₄ is used.

Further, the present invention provides a nonvolatile semiconductor memory having a floating gate formed on a semiconductor substrate via a tunnel insulating film and a control gate formed on the floating gate via an inter-gate insulating film. In the method of manufacturing a device, in the step of forming the floating gate, a particle diameter of the floating gate is controlled by a concentration of an impurity doped into the floating gate.

In the present invention, the floating gate is composed of the first impurity concentration layer on the side of the tunnel insulating film having a small particle diameter and the second impurity concentration layer on the side of the control gate having a large particle diameter. Between the impurity concentration layer 1 and the tunnel insulating film, the threshold voltage at the time of writing / erasing is stabilized, and the writing / erasing characteristics are improved. On the other hand, the second
In the impurity concentration layer side, the leakage current at the interface between the floating gate and the inter-gate insulating film is reduced, and the withstand voltage and data retention characteristics are improved.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. First, before describing the structure and the manufacturing method of the nonvolatile semiconductor device according to the present invention, the impurity concentration and the grain size of the floating gate, the withstand voltage and the threshold voltage of the inter-gate insulating film having the structure shown in FIG. The relationship with the variation width will be described with reference to FIG. As shown in FIG. 1, it can be seen that the grain size of the floating gate can be controlled by changing the concentration of phosphorus doped in the floating gate. That is, when the concentration of phosphorus is reduced, the grain size is reduced, and when the concentration of phosphorus is increased, the grain size is increased.

As can be seen from FIG. 1, the insulation resistance of the inter-gate insulating film between the floating gate and the control gate and the variation width of the threshold voltage are correlated with the phosphorus concentration. It can be seen that there is a trade-off between the insulation resistance and the variation width of the threshold voltage. That is, when the phosphorus concentration is low, the grain size becomes small and the variation width of the threshold voltage becomes small, but the insulation resistance of the inter-gate insulating film becomes small, and when the phosphorus concentration is high, the grain size becomes large. Although the variation width of the threshold voltage increases, the insulation resistance of the inter-gate insulating film increases.

When the variation width of the threshold voltage can be reduced, the variation of the threshold voltage at the time of writing / erasing is improved, and the writing / erasing characteristics are improved. In addition, if the insulation resistance of the inter-gate insulating film can be increased, retention characteristics (charge escape characteristics on the low potential side), disturb characteristics (charge escape characteristics on the high potential side), and endurance characteristics (repeated write / erase characteristics) Is improved. However, as described above, since there is a trade-off relationship between the variation width of the threshold voltage and the insulation resistance of the inter-gate insulating film, in the present invention, the floating gate is doped with impurities at different concentrations. And a second impurity concentration layer, the variation in threshold voltage is improved by reducing the grain size of one impurity concentration layer of the floating gate, and the grain size of the other impurity concentration layer is increased by reducing the grain size of the other impurity concentration layer. The configuration is such that the insulation resistance of the inter-gate insulating film is improved.

FIG. 6 is a sectional view showing a configuration of one embodiment of the nonvolatile semiconductor memory device of the present invention. In FIG. 6, a P-type well region 11 is formed on a P-type silicon substrate 11.
a, a field oxide film 12 made of silicon oxide is formed in a well region 11a, and an element region is formed. A tunnel insulating film 13 made of silicon oxide is formed on the element region. Tunnel insulating film 13
On the upper side, a floating gate 14 composed of a first impurity concentration layer 14a and a second impurity concentration layer 14b in which polysilicon or amorphous silicon is doped with phosphorus (P) as an impurity is formed. On the floating gate 14, for example, an inter-gate insulating film 15 made of silicon oxide and a control gate 16 made of polysilicon are sequentially laminated, and the periphery of the floating gate 14 and the inter-gate insulating film 15 is insulated from silicon oxide. It is covered with a film 17.

In the first impurity concentration layer 14a and the second impurity concentration layer 14b of the floating gate 14, the concentration of phosphorus in the first impurity concentration layer 14a is lower than the concentration of phosphorus in the second impurity concentration layer 14b. The grain size of the first impurity concentration layer 14a is smaller in the first impurity concentration layer 14a than in the second impurity concentration layer 14b.
Is several tens of nm, for example, and the second
The grain size of impurity concentration layer 14b is, for example, several tens to several hundreds nm.

In the nonvolatile semiconductor memory device having the above configuration,
The grain size of the first impurity concentration layer 14a of the floating gate 14 is as small as several tens of nm, and therefore, the number of crystal grains per unit area is relatively large, and the variation in the number of crystal grains is small. From this, the variation of the threshold voltage at the time of writing / erasing is suppressed, and the writing / erasing is suppressed.
Erasure characteristics are improved. On the other hand, the floating gate 14
The grain size of the second impurity concentration layer 14b is as large as several tens to several hundreds of nm.
Gate insulating film 15 between the gate and the control gate 16
Withstand voltage increases. Therefore, the retention characteristics (charge elimination characteristics on the low potential side), the disturb characteristics (charge elimination characteristics on the high potential side), and the endurance characteristics (repeated writing / erasing characteristics) are improved.

Next, an example of a method of manufacturing the nonvolatile semiconductor memory device having the above configuration will be described with reference to FIGS. First, as shown in FIG.
A P-type well region 11a is formed on the
After a field oxide film 12 and a tunnel insulating film 13 made of silicon oxide are formed on a, a polysilicon film 21 for forming a first impurity concentration layer 14a of a floating gate 14a is formed. The polysilicon film 21 is formed under reduced pressure CVD (Chemical Vapor Deposited) under the film forming conditions of Step 1 shown in Table 1 below.
on) method.

[0031]

[Table 1]

When a film is formed under the film forming conditions in step 1 of Table 1, a polysilicon film 2 doped with phosphorus at a predetermined concentration is formed.
1 is formed. The size of the grain size of the polysilicon film 21 is controlled by the concentration of phosphorus. That is, by adjusting the flow rate of PH ₃ with respect to SiH ₄ and adjusting the doping amount of phosphorus with respect to polysilicon within the range of step 1 in Table 1, a relatively small desired grain size of, for example, about 30 nm is obtained. Obtainable.

Next, as shown in FIG. 3, an amorphous silicon film 22 for forming the second impurity concentration layer 14b of the floating gate 14 is formed on the polysilicon film 21 under the film forming conditions of Step 2 in Table 1. I do. This amorphous silicon film 22 is formed under reduced pressure CVD (Chemical Vapor Deposited) under the film forming conditions of Step 2 shown in Table 1 above.
on) method. When the film is formed under the film forming conditions of Step 2 in Table 1, an amorphous silicon film 22 in which amorphous silicon is doped with phosphorus at a predetermined concentration is formed. By adjusting the flow rate of PH ₃ with respect to SiH ₄ and adjusting the doping amount of phosphorus with respect to amorphous silicon in the range of step 2 in Table 1, for example, 60 to 3
A relatively large desired grain size of about 00 nm can be obtained.

Next, as shown in FIG. 4, for example, a part of the second impurity concentration layer 14b is oxidized to a predetermined thickness by a thermal oxidation method to form an inter-gate insulating film 15 made of a thermal oxide film. I do. Next, as shown in FIG. 5, a polysilicon film 23 is formed on the inter-gate insulating film 15, for example. The polysilicon film 23 is formed by a CVD method while doping phosphorus as an impurity. After the formation of the polysilicon film 23, the polysilicon film 21, the amorphous silicon film 22, the inter-gate insulating film 15, and the polysilicon film 23 are patterned into a predetermined pattern.
After forming the insulating film 17 made of the thermal oxide film shown in FIG.
A source region 18 and a drain region 19 are formed on a silicon substrate 11.
Is formed, the structure shown in FIG. 6 is obtained.

As described above, according to the present embodiment, the floating gate 14 is formed by stacking the first and second impurity concentration layers 14a and 14b having different grain sizes, whereby the first gate having the smaller grain size is formed. On the side of the impurity concentration layer 14a, variation in threshold voltage during writing / erasing is suppressed, and the writing / erasing characteristics can be improved. On the side of the second impurity concentration layer 14b having a large grain size, the floating gate The dielectric strength of the inter-gate insulating film 15 between the gate insulating film 14 and the control gate 16 can be improved.
, And the characteristics of the inter-gate insulating film 15 can be simultaneously improved. Also, the first and second impurity concentration layers 1 of the floating gate 14 of the present embodiment
In 4a and 14b, since the grain size is controlled by the same impurity concentration, the process of forming the floating gate 14 can be simplified. Further, in the step of forming the floating gate 14 of the present embodiment, the polysilicon which forms the first and second impurity concentration layers 14a and 14b or the amorphous silicon is deposited by the CVD method while the impurity phosphorus is doped. There is no need to dope impurities into the floating gate 14 by ion implantation or diffusion in a later step, and it is not necessary to perform annealing required after ion implantation. Also,
According to the present embodiment, the first of the floating gates 14
Since the temperature in the step of forming the second impurity concentration layer 14b is lower than the temperature in the step of forming the impurity concentration layer 14a, phosphorus as an impurity is present between the first impurity concentration layer 14a and the second impurity concentration layer 14b. Can be suppressed from spreading.

[0036]

According to the present invention, both the characteristics of the tunnel insulating film and the characteristics of the inter-gate insulating film between the floating gate and the control gate can be optimized by a relatively simplified process. The write / erase characteristics, retention characteristics, disturb characteristics, and endurance characteristics of the semiconductor device can be simultaneously improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between an impurity concentration of a floating gate and a grain size, a withstand voltage of an inter-gate insulating film, and a variation width of a threshold voltage.

FIG. 2 is a sectional view illustrating an example of a manufacturing process of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process following FIG. 2;

FIG. 4 is a cross-sectional view showing the manufacturing process following FIG. 3;

FIG. 5 is a cross-sectional view showing the manufacturing process continued from FIG. 4;

FIG. 6 is a cross-sectional view showing the structure of one embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a sectional view showing an example of the structure of an EPROM.

[Explanation of symbols]

11 silicon substrate, 12 field oxide film, 13
Tunnel insulating film, 14 ... Floating gate, 14a
... first impurity concentration layer, 14b ... second impurity concentration layer, 15
... Intergate insulating film.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA04 AA30 AB08 AC02 AC06 AD12 AF06 AF07 AF25 AG02 AG21 5F083 EP04 EP06 EP07 EP23 ER02 ER05 ER09 ER14 ER15 ER16 ER19 ER22 GA15 GA16 GA17 GA21 GA24 JA33 PR21

Claims (15)

[Claims] 1. A non-volatile semiconductor memory device comprising: a floating gate formed on a semiconductor substrate via a tunnel insulating film; and a control gate formed on the floating gate via an inter-gate insulating film. The floating gate is formed of first and second impurity concentration layers each doped with a single impurity at a different concentration, and the particle diameter of the first impurity concentration layer on the side of the tunnel insulating film is smaller than the first impurity concentration layer. 2. A nonvolatile semiconductor memory device smaller than the particle diameter of the impurity concentration layer of No. 2. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said floating gate is made of polysilicon. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said floating gate is made of amorphous silicon. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said impurity comprises phosphorus. 5. A particle diameter of a first impurity concentration layer located on the side of the tunnel insulating film of the floating gate is 3
2. The nonvolatile semiconductor memory device according to claim 1, wherein the second impurity concentration layer has a particle diameter of about 60 nm to about 300 nm. 6. The impurity concentration of each of the first and second impurity concentration layers is higher in the first impurity concentration layer located on the tunnel insulating film side than in the second impurity concentration layer. 3. The nonvolatile semiconductor memory device according to 1. 7. The nonvolatile semiconductor memory device according to claim 1, wherein a thickness of said first impurity concentration layer is smaller than a thickness of said second impurity concentration layer. 8. A method of manufacturing a nonvolatile semiconductor memory device having a floating gate formed on a semiconductor substrate via a tunnel insulating film and a control gate formed on the floating gate via an inter-gate insulating film. Forming a first impurity concentration layer constituting a part of the floating gate by doping an impurity at a predetermined concentration while depositing a material for forming a floating gate on the tunnel insulating film by a chemical reaction; A second material forming the remainder of the floating gate by doping the impurity at a higher concentration than the first impurity concentration layer while depositing a material for forming the floating gate on the first impurity concentration layer by a chemical reaction; Forming an impurity concentration layer. 9. The method according to claim 8, wherein the impurity is phosphorus. 10. The method according to claim 8, wherein the step of forming the first impurity concentration layer is performed at a higher temperature than the step of forming the second impurity concentration layer. 11. The step of forming the first impurity concentration layer is performed at a temperature of about 620 ° C., and the step of forming the second impurity concentration layer is performed at a temperature of about 530 ° C. 9. The method for manufacturing a nonvolatile semiconductor memory device according to item 8. 12. The method according to claim 8, wherein the step of forming the first and second impurity concentration layers is performed under reduced pressure. 13. The method according to claim 8, wherein the step of forming the first impurity concentration layer is performed under a higher pressure than the step of forming the second impurity concentration layer. . 14. The method according to claim 8, wherein the step of forming the first and second impurity concentration layers uses a mixture of PH ₃ and SiH ₄ . 15. A method for manufacturing a nonvolatile semiconductor memory device having a floating gate formed on a semiconductor substrate via a tunnel insulating film and a control gate formed on the floating gate via an inter-gate insulating film. A method of manufacturing a nonvolatile semiconductor memory device, wherein in the step of forming the floating gate, a particle diameter of the floating gate is controlled by a concentration of an impurity doped into the floating gate.