JP2000216204A - Needle probe card and wafer checking - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously perform an optical property checking for a plurality of solid imaging element chips by a plurality of needle probe groups formed on a same card plate so arranging in a staggered shape as each needle tip not to cross each other and by the needle tips providing at a predetermined distance separating from adjacent needle probe group. SOLUTION: Each needle probe group that constitutes a needle probe group A2 and a needle probe group B2 is so arranged in a staggered shape as needle tips not to cross each other. Further, the needle probes of which each needle tip is arranged at a distance of few tens to hundreds μm is so arranged as to have a structure where each needle tip of the needle probe group to constitute the needle probe group A2 does not cross each needle tip of the needle probe group to constitute the needle probe group B3. An optical property checking for a plurality of chips at a step of wafer level of solid imaging element chips A15 and B16 is simultaneously performed under the condition of checking pads which are formed on a plurality of the arranged solid imaging element chips being contacted at the same time by using the needle probe groups.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a probe card and a wafer inspection method for simultaneously performing an optical characteristic inspection on a plurality of wafer-level solid-state imaging device chips.

[0002]

2. Description of the Related Art In recent years, product prices of solid-state imaging device chips have been decreasing year by year, and it is important to reduce product costs. Further, the ratio of the cost cost generated in the inspection process of the solid-state imaging device chip to the product cost cannot be ignored, and it is required to reduce the inspection time of the solid-state imaging device chip.
Therefore, it is necessary to reduce the inspection time required for one pellet. However, unless the number of inspection items is reduced, the effect of reducing the inspection time by improving the test program is 80% to 9%.
The cost is about 0%, and the cost cost generated in the inspection process of the solid-state imaging device chip is reduced to only about 80 to 90% of the conventional one, and the fundamental solution has not been reached.

FIG. 7 is a top view for explaining a first conventional probe probe card. FIG. 13 is a top view for explaining an inspection pad structure limited to only one row of solid-state imaging devices. Simultaneous inspection of a plurality (n ≧ 2) of solid-state imaging device chips has been considered as a method of shortening the inspection time. This is a method in which output signals from a plurality of solid-state imaging element chips are detected in parallel (parallel), and inspection of device characteristics and the like is performed by a parallel processing method (first conventional technique). In the first related art, when the inspection and measurement times are compared, output signals from three solid-state imaging device chips are simultaneously detected in parallel, and an inspection is performed by an inspection machine having a two-channel parallel processing function. In the case where one chip is independently inspected by an inspection machine having a processing function, the inspection time from the start of the inspection to the end of the inspection is almost equal. Therefore, when simultaneously inspecting three solid-state imaging device chips, 1
Since the inspection time required for each chip is 50 to 60% of the inspection and measurement time for inspecting one solid-state imaging device chip independently, the cost cost generated in the inspection process of the solid-state imaging device chip is reduced by 50 to 60% of the conventional cost. It has the effect of reducing to the extent.

FIG. 12 is a top view of a chip showing a state in which a plurality of solid-state imaging devices having test pads of a two-row structure are arranged in parallel. FIG. 11 shows a wafer inspection method using the probe probe card of the second prior art. DRAM
In (random access memory) and the like, the solid-state imaging device chips A15, B16, and C17 are short in length, so that a plurality of solid-state imaging device chips A15, B16, and C17 can be arranged horizontally. There is a problem that the width is long and a light source for irradiating the solid-state imaging device chips A15, B16, and C17 reaches only a limited area, and it is impossible to arrange a plurality of light emitting devices horizontally. As a conventional technique aiming at solving such a technical problem, as shown in FIGS.
5, B16 and C17 are arranged in tandem (second prior art).

FIG. 8 shows a wafer inspection method using a third conventional probe probe card. 9 and 1
0 is a top view for explaining a probe probe arrangement structure of a two-stage structure in the probe probe card of the third prior art. As a prior art aiming at solving the technical problem of the second prior art, as shown in FIGS. 8, 9 and 10, the first stage 2A of the probe probe group A2 and the second stage 2A of the probe probe group A2 are used.
There is disclosed a method of forming a two-stage structure of a stage 2B, a first stage 3A of the probe group B3, and a second stage 3B of the probe group B3 (third prior art). In the third prior art, FIG.
The wafer on which the solid-state imaging device chips A15 and B16 in which the test pads A11 are two rows as shown in FIG.
In order to measure the pellet simultaneously, one of the probe groups A2
It has a two-stage structure of a stage 2A, a second stage 2B of the probe probe group A2, a first stage 3A of the probe probe group B3, and a second stage 3B of the probe probe group B3. In the third prior art, FIG.
As shown in (1), it is possible to prevent the needle tips from contacting each other, and when the probe group A2 and the probe group B3 are illuminated, the shadow projected on the solid-state imaging device chips A15 and B16 becomes invisible. , The first solid-state imaging device chip A15,
B16 or the second solid-state imaging device chip A15, B
There is an effect that it does not affect the 16 photodiode units 10.

[0006]

However, in the first prior art, as shown in FIGS.
2. A method for simultaneously inspecting two solid-state imaging device chips A15 and B16 formed on a wafer with a card 4 on which a probe probe group B3 is formed on the same plane is realized by a solid-state imaging device chip. The test pads A15, B16 have test pad structures A11, B12, C1 shown in FIG.
3, a row of solid-state imaging device chips A15 such as D14,
There is a problem in that it is limited to only B16, C17, and D18.

In the second prior art, the solid-state imaging device chips A15, B16, and C17 having two rows of test pads A11, B12, and C13 as shown in FIG.
When simultaneous pellet measurement is to be realized using a probe array structure in which the probe group A2 and the probe group B3 are formed on the same plane, as shown in FIG. Since the tips of the probe group B3 cross over the solid-state imaging device chips A15 and B16, the tips may come into contact with each other, making it impossible to implement in terms of manufacturing. was there.

In the third prior art, the probe is a first probe 2A of the probe probe group A2, a second probe 2B of the probe probe group A2, a first probe 3A of the probe probe group B3, and a probe probe. Since it is composed of the second stage 3B of the group B3, if the fixed strength for preventing the deformation of the probe probe group and giving the accuracy is maintained, the probe probe card becomes thick,
In addition, the arrangement of the probe is complicated. For this reason,
The production cost is 1,000,000 yen or more, and there is a problem that the production cost is 10 times or more as compared with the conventional method of arranging the probe probes on a plane. The present invention has been made in view of such a problem, and an object of the present invention is to provide a probe probe for simultaneously performing optical property inspection on a plurality of wafer-level solid-state imaging device chips in a short time and at low cost. Another object of the present invention is to provide a card and wafer inspection method.

[0009]

The gist of the present invention resides in that an inspection chip having an elongated chip shape and having a one-row configuration or a two-row configuration is formed on one or both of the end sides of the chip. A probe probe card for simultaneously performing an optical property test on a plurality of solid-state imaging device chips at a wafer level, the probe card having a plurality of probe probes formed on the same plane of the card, wherein the plurality of probe probes The probe probes constituting each of the groups are staggered so that the tips do not intersect with each other, and each of the plurality of probe probes is arranged such that the adjacent probe group does not intersect with the probe tip. A probe probe card, which is provided with a probe probe arrangement structure separated by a predetermined distance. According to another aspect of the present invention, there is provided a probe in which a counterbore hole having an opening for simultaneously inspecting optical characteristics of each of the solid-state imaging device chips at a wafer level is formed near a central portion of the card. The probe probe card according to claim 1, further comprising a probe arrangement structure. The gist of the third aspect of the present invention resides in the probe card according to the first or second aspect, wherein the separation distance is several tens to several hundreds μm. The gist of claim 4 of the present invention is that a shadow of each of the probe groups projected onto each of the solid-state imaging device chips is not projected on a photodiode provided on the solid-state imaging device chip. 4. The probe probe card according to claim 3, wherein each of the probe groups is arranged on the same plane. According to a fifth aspect of the present invention, there is provided a plurality of wafer-level solid-state imaging devices each having an elongated chip shape and having one or two rows of test pads formed on one or both of the ends of the chip. A step of simultaneously contacting test pads formed on the chip using a group of probe probes, and in a state where the test pads are simultaneously contacted using each of the probe groups, each of the solid-state image sensor chips And a step of simultaneously inspecting a plurality of chips at the wafer level. The gist of claim 6 of the present invention is a step of independently inputting a predetermined signal to each of the solid-state imaging device chips via each of the probe groups, and each of the solid-state imaging device chips Independently sampling the output signal from each of the probe groups,
The method according to claim 5, further comprising the step of: performing an arithmetic processing on output signals sampled independently from each of the probe probes in a parallel manner by using an inspection machine having a multi-channel parallel processing function. In the wafer inspection method.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of each embodiment described below are as follows.
In order to inspect a plurality of solid-state image sensor chips (solid-state image sensor chip A15 and solid-state image sensor chip B16) in a wafer state at the same time, a plurality of probe probes are arranged on the same plane. A plurality of probe probe cards each having a probe probe arrangement structure arranged in a staggered arrangement (stacker) on the
2, n is the number of solid-state imaging device chips) The inspection pads formed on the arranged solid-state imaging device chips (solid-state imaging device chip A15 and solid-state imaging device chip B16, respectively) are simultaneously tested using a probe group. In a wafer inspection method, a plurality of chips (solid-state image sensor chips A15 and B16) are simultaneously inspected at a wafer level (optical characteristic inspection) in a state where they are in contact with each other. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) A first embodiment of a probe probe card for simultaneously inspecting two wafers of a solid-state image sensor chip (each of a solid-state image sensor chip A15 and a solid-state image sensor chip B16) in a wafer state will be described. It is shown below. FIG. 1 is a probe probe arrangement structure diagram for explaining a first embodiment of a probe probe card according to the present invention. FIG. 2 shows a first embodiment of a wafer inspection method according to the present invention using the probe card of FIG.

The solid-state image sensor chips (solid-state image sensor chip A15 and solid-state image sensor chip B16) are shown in FIG.
As shown in the figure, a pad is formed on one or both of the end sides of the solid-state imaging device chip (each of the solid-state imaging device chip A15 and the solid-state imaging device chip B16) and has a two-row structure. Inspection pads (inspection pads A11 and B12) for inspecting the solid-state imaging device chips (each of the solid-state imaging device chip A15 and the solid-state imaging device chip B16) are formed. As shown in FIG. 1, the probe card of the first embodiment is connected to a probe group A2 for connecting to a test pad A11 of a solid-state image sensor chip A15 and to a test pad B12 of a solid-state image sensor chip B16. And a probe group B3 are connected on the same plane on the card 4, and a solid-state image sensor chip (solid-state image sensor chip A15, solid-state image sensor chip B
16), a counterbore 1 having an opening for simultaneous inspection (in this embodiment, two-chip simultaneous inspection) of light response (optical characteristics) at the wafer level is formed at the center of the card 4. And a probe probe arrangement structure.

The inspection light emitted from above the card 4
When a plurality of solid-state imaging device chips (solid-state imaging device chip A15 and solid-state imaging device chip B16) are simultaneously inspected at a wafer level (optical characteristic inspection), the counterbore hole 1 is formed.
Through the solid-state imaging device chip (solid-state imaging device chip A
15, the solid-state imaging device chip B16).

Each of the solid-state image sensor chips (the solid-state image sensor chip A15 and the solid-state image sensor chip B16) has a horizontal one that generates electrons proportional to the intensity of incident light (inspection light).
A photodiode section 10 having photodiodes arranged in a row, a charge detection section for converting electrons generated by the photodiode into an analog signal, and an amplifier amplification circuit section (not shown) for amplifying and outputting the analog signal converted by the charge detection section. (Shown).

In the probe probe card of the first embodiment,
When a response (optical characteristic) due to light in the solid-state imaging device chips (the solid-state imaging device chip A15 and the solid-state imaging device chip B16) is simultaneously inspected using a wafer level, a shadow occurs in a part of the photodiode unit 10. In order to avoid the case where simultaneous inspection of a plurality of chips (optical characteristic inspection) cannot be performed accurately at the wafer level, the probe projected on the solid-state imaging device chips (the solid-state imaging device chips A15 and B16). Needle probe group A
2. In order that the shadow of the probe group B3 does not fall on the photodiode section 10 of the solid-state image sensor chip (the solid-state image sensor chip A15 and the solid-state image sensor chip B16),
The probe group A2 and the probe group B3 are
It is located on both sides of.

For example, as shown in FIGS. 1 and 2, the probe of the probe group A2 projected onto the solid-state image pickup device chip A15 is set so that the shadow does not fall on the photodiode section 10 of the solid-state image pickup device chip A15. The probe group A2 is arranged on one side of the card 4 (upper side in FIGS. 1 and 2). Similarly, the shadow of the probe group B3 projected onto the solid-state image sensor chip B16 is changed to the solid-state image sensor chip B1.
The probe group B3 is arranged on the other end side of the card 4 (the lower side in FIG. 1 and FIG. 2) so as not to cover the photodiode section 10 of FIG.

In the probe card according to the first embodiment,
A plurality of (n ≧ 2, n is the number of solid-state imaging device chips) arranged solid-state imaging device chips (solid-state imaging device chip A15,
Inspection pads formed on each of the solid-state imaging device chips B16) are simultaneously contacted by using a probe group, and
In this state, the solid-state imaging device chip (solid-state imaging device chip A
15, each of the solid-state imaging device chips B16) has a probe probe arrangement structure capable of simultaneously inspecting optical characteristics at a wafer level. More specifically, as shown in FIG. 1, the probe group A2 is brought into contact with an inspection pad A11 formed on the solid-state image sensor chip A15, and formed on the solid-state image sensor chip B16. The probe probe group B3 is brought into contact with the inspection pad B12, and in this state, the first solid-state imaging device chip A15 is simultaneously inspected (optical characteristic inspection) using the wafer level using the probe probe group A2. Simultaneous inspection of multiple chips at the wafer level of the second solid-state image sensor chip B16 using the probe group B3 (optical characteristic inspection)
It has a probe probe arrangement structure that can be used. Further, each of the probe groups constituting the probe group A2 is arranged in a staggered arrangement so that the tips do not cross each other. The tips are arranged in a staggered arrangement (stacked) so that the tips do not cross each other. Further, each tip of the probe groups constituting the probe group A2 constitutes a probe group B3. The probe tips of the probe probe group (each of the probe probe group A2 and the probe probe group B3) are arranged at a distance of several tens to several hundreds μm so as not to intersect with each of the probe tips of the probe probe group. It has a probe probe arrangement structure.

In the wafer inspection method of the first embodiment using such a probe card, a plurality (n ≧ 2, n
Are the number of the solid-state image sensor chips) The test pads formed on the arranged solid-state image sensor chips (the solid-state image sensor chip A15 and the solid-state image sensor chip B16) were simultaneously brought into contact using a probe group. In this state, the solid-state image sensor chips (the solid-state image sensor chip A15 and the solid-state image sensor chip B16) are simultaneously inspected at a wafer level (optical characteristic inspection). More specifically, as shown in FIG. 1, the probe group A2 is brought into contact with an inspection pad A11 formed on the solid-state image sensor chip A15, and formed on the solid-state image sensor chip B16. While the probe probe group B3 is in contact with the inspection pad B12, the first solid-state imaging device chip A15 is simultaneously inspected (optical characteristic inspection) using the wafer level using the probe probe group A2, Second solid-state imaging device chip B using probe group B3
16 are being inspected.

Input signals to the solid-state image sensor chips (the solid-state image sensor chip A15 and the solid-state image sensor chip B16) are applied independently from the probe group A2 and the probe group B3, respectively. Solid-state image sensor chip (solid-state image sensor chip A15, solid-state image sensor chip B1
6) are output from the probe probe group A2 and the probe probe group B3, respectively. Output signals output from each of the probe group A2 and the probe group B3 are simultaneously processed in parallel using an inspection machine having a two-channel parallel processing function.

Next, a wafer inspection method according to the first embodiment will be described with reference to the drawings. In the wafer inspection method according to the first embodiment, the solid-state imaging device chip (solid-state imaging device chip A1
5. When the response (optical characteristics) of light in each of the solid-state imaging device chips B16) is simultaneously inspected using a wafer level, if a shadow occurs in a part of the photodiode unit 10, a plurality of chips at an accurate wafer level are obtained. A probe group A2 and a probe group projected on a solid-state image sensor chip (solid-state image sensor chip A15 and solid-state image sensor chip B16) so as to avoid a case where simultaneous inspection (optical characteristic inspection) cannot be performed. The shadow of B3 is a solid-state image sensor chip (solid-state image sensor chip A15, solid-state image sensor chip B1
6) The probe response A (optical characteristics) in a state where the probe group A2 and the probe group B3 are arranged on both sides of the card 4 so as not to cover the photodiode section 10).
Are inspected simultaneously using the wafer level.

In the wafer inspection method according to the first embodiment, a plurality of (n ≧ 2) solid-state imaging device chips (each of the solid-state imaging device chip A15 and the solid-state imaging device chip B16) formed on the wafer are measured at a wafer level. Probe group (probe probe group A2, probe probe) on the solid-state imaging device chips (solid-state imaging device chip A15 and solid-state imaging device chip B16) to simultaneously execute the multiple chip simultaneous inspection (optical characteristic inspection). When each of the groups B3) is brought into contact, as shown in FIG. 2, the probe group A2 is brought into contact with the inspection pad A11 formed on the solid-state imaging device chip A15, and the solid-state imaging device chip B is contacted.
The wafer-level optics of the solid-state imaging device chips (solid-state imaging device chip A15 and solid-state imaging device chip B16) in a state where the probe group B3 is in contact with the inspection pad B12 formed on the 16 chips. Perform a characteristic inspection. At this time, input signals are applied to the solid-state imaging device chips (the solid-state imaging device chip A15 and the solid-state imaging device chip B16, respectively) from the probe probe group A2 side and the probe probe group B3 side independently, and the probe probe group Output signals from the solid-state image sensor chips (the solid-state image sensor chip A15 and the solid-state image sensor chip B16) are received via the A2 side and the probe probe group B3 side, respectively. Subsequently, the received output signal is given to an inspection machine having a two-channel parallel processing function to perform arithmetic processing in parallel. Thus, at the wafer-level optical characteristic inspection of the solid-state image sensor chips (the solid-state image sensor chip A15 and the solid-state image sensor chip B16), the probe probe group A2 and the probe group B3 are arranged from the upper surface of the card 4. Even when the inspection light is irradiated,
A photodiode section 10 formed in a horizontal line on a solid-state imaging element chip (each of the solid-state imaging element chip A15 and the solid-state imaging element chip B16) includes a solid-state imaging element chip (solid-state imaging element chip A15, solid-state imaging element chip). B1
6) can avoid the case where the shadow projected on the wafer is projected on the optical characteristics inspection at the wafer level.

As described above, according to the first embodiment, first, the solid state imaging device chip A15 in the wafer state
Of the probe group A2 on the test pad A11 of FIG.
In the state where the probe group B3 is in contact with the probe group 2, a simultaneous inspection of a plurality of chips (optical characteristic inspection) at the wafer level can be performed simultaneously. Secondly, independent output signals from a plurality of (n ≧ 2) solid-state imaging device chips (each of the solid-state imaging device chip A15 and the solid-state imaging device chip B16) are detected in parallel, and device characteristics and the like are detected. Since the inspection is performed by the parallel processing method, it is effective to reduce the inspection time. At the same time, the output signals from the two solid-state imaging device chips (solid-state imaging device chip A15 and solid-state imaging device chip B16) are detected in parallel, and the inspection is performed using an inspection machine having a two-channel parallel processing function. Comparing the times, when one chip is independently inspected using an inspection machine having a one-channel processing function, the inspection times from the start of the inspection to the end of the inspection are almost the same, so that two solid-state imaging element chips (solid-state imaging element chip A15) are used. , The simultaneous inspection of the solid-state image sensor chips B16) requires a single solid-state image sensor chip (each of the solid-state image sensor chip A15 and the solid-state image sensor chip B16) at the wafer level. Only 50 to 60% of the inspection measurement time for optical characteristic inspection is required. Therefore, the solid-state imaging device chip (solid-state imaging device chip A15,
There is an effect that the cost cost generated during the inspection time of each of the solid-state imaging element chips B16 can be reduced to 50 to 60% of the conventional cost. Thirdly, since the conventional probe probe group (each of the probe group A2 and the probe group B3) is arranged on the same plane in terms of manufacturing cost, the conventional probe arrangement is used. The production cost is the same as that of the needle probe card.

(Second Embodiment) FIG. 3 is a diagram showing a probe probe arrangement structure for explaining a probe probe card according to a second embodiment of the present invention, and FIG. 4 is a diagram showing the probe probe card of FIG. The second of the wafer inspection method according to the present invention used
1 shows an embodiment. Note that the same parts as those already described in the first embodiment are denoted by the same reference numerals, and redundant description will be omitted. The probe card of the second embodiment has a simultaneous inspection of a plurality of chips at a wafer level (optical characteristic inspection, three-chip simultaneous inspection in this embodiment).
The inspection pads (the inspection pad A11, the inspection pad B12, the inspection pad) formed on the solid-state imaging device chips (the solid-state imaging device chip A15, the solid-state imaging device chip B16, and the solid-state imaging device chip C17, respectively) so that the inspection can be performed. Each of the pads C13 is moved to a probe group (probe probe group A).
2, each of the probe groups B3) is provided with a probe probe arrangement structure that can be brought into contact simultaneously.

The probe card according to the second embodiment has an inspection pad (solid state imaging element chip A15, solid state imaging element chip B16, and solid state imaging element chip C17) for inspecting the optical characteristics of the solid state imaging element chip. A probe group (probe probe group A2, probe group A2) that contacts the test pad A11, the test pad B12, and the test pad C13.
Each of the probe groups B3) has a probe probe arrangement structure formed on the same plane on the card 4. In this state, the probe group (each of the probe group A2 and the probe group B3) is connected to the inspection pad (the inspection pad A1).
1, each of the test pad B12 and the test pad C13). In order to simultaneously inspect the optical characteristics of the solid-state image sensor chips (the solid-state image sensor chip A15, the solid-state image sensor chip B16, and the solid-state image sensor chip C17), a counterbore having an opening is formed at the center of the card 4. 1 is formed.

The probe group A2 inspects the pads of the third solid-state image sensor chip C17 and the upper half pad of the first solid-state image sensor chip A15, and the probe group B3 examines the first solid-state image sensor chip C15. A probe probe arrangement for inspecting the lower half pad of the element chip A15 and the pad of the second solid-state imaging element chip B16 is provided. Further, each of the probe groups constituting the probe group A2 is arranged in a staggered arrangement so that the tips do not cross each other. The tips are arranged in a staggered arrangement (stacked) so that the tips do not cross each other. Further, each tip of the probe groups constituting the probe group A2 constitutes a probe group B3. The probe tips of the probe probe group (each of the probe probe group A2 and the probe probe group B3) are arranged at a distance of several tens to several hundreds μm so as not to intersect with each of the probe tips of the probe probe group. It has a probe probe arrangement structure.

Next, a solid-state image pickup device chip (solid-state image pickup device chip A15, solid-state image pickup device chip B16, solid-state image pickup device chip C17) in which test pads A11, B12, and C13 for inspection have a two-row structure. FIG. 4 shows an operation according to the present invention for simultaneously inspecting three wafers. In the wafer inspection method according to the second embodiment, a solid-state image sensor chip (solid-state image sensor chip A15, solid-state image sensor chip A15, A test pad (each of the test pad A11, the test pad B12, and the test pad C13) formed on the image pickup device chip B16 and the solid-state image pickup device chip C17) is probed with a probe group (probe probe group A2, probe). Performing simultaneous inspection (optical characteristic inspection) of a plurality of chips at the wafer level in the state of simultaneous contact using each of the needle probe groups B3);
And the probe group A2 is the pad of the third solid-state imaging device chip C17 and the first solid-state imaging device chip A15.
The upper half pad of the first solid-state image sensing device chip A15 is inspected, and the probe
It is characterized in that the pads of the second solid-state imaging device chip B16 are inspected.

As described above, according to the second embodiment, first, the probe probe group is placed on the pad of the third solid-state image sensor chip C17 and the upper half pad of the first solid-state image sensor chip A15. A2 is abutted, and a plurality of chips are simultaneously inspected at the wafer level in a state in which the probe group B3 is in contact with the lower half pad of the first solid-state image sensor chip A15 and the pad of the second solid-state image sensor chip B16 ( Optical property inspection) can be performed simultaneously.
Second, independent output signals from a plurality of (n ≧ 2) solid-state imaging device chips (solid-state imaging device chip A15, solid-state imaging device chip B16, and solid-state imaging device chip C17) are detected in parallel. In addition, since the inspection of the device characteristics and the like is performed by the parallel processing method, it is effective to reduce the inspection time. At the same time, output signals from three solid-state imaging device chips (solid-state imaging device chip A15, solid-state imaging device chip B16, and solid-state imaging device chip C17) are detected in parallel, and an inspection machine having a three-channel parallel processing function is used. When the inspection time is compared with the case of the inspection, three solid-state imaging device chips are used because the inspection time from the start of the inspection to the end of the inspection is almost the same when one chip is independently inspected using an inspection machine having a one-channel processing function. The inspection time required per chip in the simultaneous inspection of each of the solid-state imaging device chip A15, the solid-state imaging device chip B16, and the solid-state imaging device chip C17 is one solid-state imaging device chip (solid-state imaging device chip A15, solid-state imaging device Chip B1
6. 30 to 4 times of the inspection measurement time for individually inspecting the optical characteristics of the solid-state imaging device chip C17) at the wafer level.
It will be 0%. Therefore, the solid-state imaging device chips (solid-state imaging device chip A15, solid-state imaging device chip B1
6. The effect that the cost cost generated in the inspection time of each of the solid-state imaging device chips C17) can be reduced to 30 to 40% of the conventional cost. Thirdly, since the conventional probe probe group (each of the probe probe group A2 and the probe probe group B3) is arranged on the same plane in terms of manufacturing cost, the conventional probe is used. The production cost is the same as that of the needle probe card.

(Third Embodiment) FIG. 5 is a diagram showing a probe probe arrangement structure for explaining a probe probe card according to a third embodiment of the present invention, and FIG. 6 is a diagram showing the probe probe card of FIG. Third of the wafer inspection method according to the present invention used
1 shows an embodiment. The same portions as those already described in the first and second embodiments are denoted by the same reference numerals, and redundant description will be omitted. In the third embodiment,
Inspection pads for inspecting solid-state image sensor chips (each of solid-state image sensor chip A15, solid-state image sensor chip B16, solid-state image sensor chip C17, and solid-state image sensor chip D18) when n = 4 (simultaneous four-chip inspection) (Inspection pad A
The solid-state image sensor chip (solid-state image sensor chip A15, solid-state image sensor chip B16, solid-state image sensor chip C17) in which each of the test pad 11, test pad B12, test pad C13, and test pad D14 has a single-row structure as shown in FIG. , A solid-state imaging device chip D18) and a wafer inspection method for simultaneously inspecting four chips of the wafer.

The probe card according to the third embodiment shown in FIG. 5 includes a solid-state image sensor chip (solid-state image sensor chip A1).
5. Solid-state image sensor chip B16, solid-state image sensor chip C
17, each of the solid-state imaging device chips D18) (inspection pads A11, B12, C)
13, each of the test pads D14) has a probe probe arrangement structure in which a probe probe group A2 and a probe probe group B3 are formed on the same plane on the card 4. In addition, the light response (optical characteristics) of the solid-state image sensor chips (solid-state image sensor chip A15, solid-state image sensor chip B16, solid-state image sensor chip C17, and solid-state image sensor chip D18) is inspected (simultaneous inspection of four chips).
For this purpose, a counterbore 1 having an opening is formed in the center of the card 4.

The probe group A2 includes a first solid-state image sensor chip A15 and a third solid-state image sensor chip C1.
The pad No. 7 and the probe group B3 have a probe probe arrangement for inspecting the pad of the second solid-state imaging device chip B16 and the pad of the fourth solid-state imaging device chip D18. Further, each of the probe groups constituting the probe group A2 is arranged in a staggered arrangement so that the tips do not cross each other. The tips are arranged in a staggered arrangement (stacked) so that the tips do not cross each other. Further, each tip of the probe groups constituting the probe group A2 constitutes a probe group B3. The probe tips of the probe probe group (each of the probe probe group A2 and the probe probe group B3) are arranged at a distance of several tens to several hundreds μm so as not to intersect with each of the probe tips of the probe probe group. It has a probe probe arrangement structure.

As described above, according to the third embodiment, by executing the wafer inspection method as shown in FIG.
Since four solid-state imaging device chips (solid-state imaging device chip A15, solid-state imaging device chip B16, solid-state imaging device chip C17, and solid-state imaging device chip D18) can be simultaneously inspected, an inspection machine having a four-channel parallel processing function can be obtained. When the inspection is performed simultaneously and in parallel, one solid-state image sensor chip (solid-state image sensor chip A15, solid-state image sensor chip B
16, each of the solid-state imaging device chip C17 and the solid-state imaging device chip D18) independently performs an output signal process on the inspection time of 2
The inspection time is about 0 to 30%, and the measurement time can be greatly reduced. As a result, the solid-state imaging device chips (solid-state imaging device chip A15, solid-state imaging device chip B1
6. Solid-state image sensor chip C17, solid-state image sensor chip D
18) The cost required for the inspection time is 2
There is an effect that it can be reduced to about 0 to 30%.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment,
The number, position, shape, and the like suitable for carrying out the present invention can be obtained. In each drawing, the same components are denoted by the same reference numerals.

[0033]

Since the present invention is configured as described above, the following effects can be obtained. First, it is possible to simultaneously execute a wafer inspection (optical characteristic inspection) with a plurality of (n ≧ 2) solid-state imaging device chips in a wafer state in which a probe group is in contact with each inspection pad. Become.
Second, independent output signals from each of a plurality of (n ≧ 2) solid-state imaging device chips are detected in parallel (parallel), and inspection of device characteristics and the like is performed by a parallel processing method, so that inspection time is reduced. It is effective for At the same time, the output signals from each of the two solid-state imaging device chips are detected in parallel, and the inspection time is compared with a case where the inspection is performed using an inspection machine having a two-channel parallel processing function. When one chip is independently inspected by using the method, since the inspection time from the start of the inspection to the end of the inspection is almost equal, the inspection time required for one chip in the simultaneous inspection of each of the two solid-state imaging device chips is one solid-state imaging. It takes 50 to 60% of the inspection measurement time for individually inspecting the optical characteristics at the wafer level for each of the element chips. For this reason, there is an effect that the cost cost generated in each inspection time of the solid-state imaging device chip can be reduced to 50 to 60% of the conventional cost. Third, in terms of manufacturing cost, the conventional probe probe arrangement structure for arranging the conventional probe probe group on the same plane is used, so that the manufacturing cost is almost the same as the conventional probe card.

[Brief description of the drawings]

FIG. 1 is a view showing a probe probe arrangement structure for explaining a probe probe card according to a first embodiment of the present invention.

FIG. 2 shows a first embodiment of a wafer inspection method according to the present invention using the probe card of FIG.

FIG. 3 is a probe probe arrangement structure diagram for explaining a probe probe card according to a second embodiment of the present invention.

FIG. 4 shows a second embodiment of the wafer inspection method according to the present invention using the probe card of FIG.

FIG. 5 is a probe probe arrangement structure diagram for explaining a probe probe card according to a third embodiment of the present invention.

FIG. 6 shows a third embodiment of the wafer inspection method according to the present invention using the probe card of FIG.

FIG. 7 is a top view for explaining a probe probe card of the first related art.

FIG. 8 shows a wafer inspection method using a probe probe card of a third prior art.

FIG. 9 shows a second example of the probe probe card of the third prior art.
FIG. 4 is a top view for explaining a probe probe arrangement structure having a step structure.

FIG. 10 is a top view for explaining a probe probe arrangement structure of a two-stage structure in a probe probe card of a third conventional technique.

FIG. 11 shows a wafer inspection method using a probe probe card of the second prior art.

FIG. 12 is a top view of a chip showing a state in which a plurality of solid-state image pickup devices having test pads having a two-row structure are arranged in parallel.

FIG. 13 is a top view for explaining an inspection pad structure limited to only one row of solid-state imaging devices.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Counterbore hole 2 ... Probe group A 3 ... Probe group B 4 ... Card 10 ... Photodiode part 11 ... Inspection pad A 12 ... Inspection pad B 13 ... Inspection pad C14 ... Inspection pad D15 ... Solid-state imaging Element chip A 16: Solid-state image sensor chip B 17: Solid-state image sensor chip C 18: Solid-state image sensor chip D

Claims (6)

[Claims] 1. An optical characteristic test is simultaneously performed on a plurality of wafer-level solid-state image pickup device chips having an elongated chip shape and having one or two rows of test pads formed on one or both end sides of the chip. A probe probe card having a plurality of probe probes formed on the same plane of the card, wherein the probe tips constituting each of the plurality of probe probes have needle tips mutually. Each of the plurality of probe probes is staggered so as not to intersect, and each of the plurality of probe probes has a probe probe arrangement structure that is separated by a predetermined distance so that an adjacent probe probe group and a probe tip do not intersect. A probe card. 2. A probe probe arrangement structure in which a counterbore hole having an opening for simultaneously inspecting optical characteristics of each of the solid-state imaging device chips at a wafer level is formed near a central portion of a card. The probe card according to claim 1, wherein: 3. The method according to claim 1, wherein the separation distance is several tens to several hundreds μm.
The probe card according to claim 1 or 2, wherein: 4. A method according to claim 1, wherein a shadow of each of the probe groups projected onto each of the solid-state imaging device chips is not projected onto a photodiode provided on the solid-state imaging device chip. The probe card according to claim 3, wherein each of the probe groups is arranged. 5. A test in which test pads having an elongated chip shape and having a single-row configuration or a two-row configuration are formed on a plurality of wafer-level solid-state imaging device chips formed on one or both of the chip end sides. A step of simultaneously contacting pads using a probe probe group, and simultaneously inspecting each of the solid-state imaging device chips at a wafer level in a state where the inspection pads are simultaneously contacted using each of the probe probes. A wafer inspection method. 6. A step of independently inputting a predetermined signal to each of the solid-state imaging device chips via each of the probe groups, and outputting an output signal from each of the solid-state imaging device chips to the probe. Independently sampling through each of the probe groups; and simultaneously and independently processing the output signals sampled independently from each of the probe groups using an inspection machine having a multi-channel parallel processing function. 6. The method according to claim 5, further comprising the steps of: