JP2000215156A - Information processing system of hybrid equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of a job and to eliminate the need for a redundant memory area by providing a system bus bridge. SOLUTION: The system bus bridge(SBB) 402 interconnects a B bus 405, a G bus 404, an SC bus, and an MC bus by using a cross-bar switch and can establish the connections of two systems at the same time. Image data from a scanner are controlled by a scanner controller 4302 and written to a memory 403 through the G bus 404 and SBB 402. The data written to the memory 403 are sent to a printer controller 4303 through the SBB 402 and B bus 405 and printed. Simultaneously, a CPU 401 and the memory 403 can be accessed, so that the data can be outputted in parallel to the input.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system for processing information regarding a complex device such as a printer, a facsimile (FAX), and a copying machine.

[0002]

2. Description of the Related Art Conventionally, an image processing apparatus called a composite apparatus such as a copier or facsimile combining an image input apparatus such as a scanner and an image output apparatus such as a printer, or a computer system having the same as a single unit has been put to practical use. Have been. In such a device, in order to realize a composite function such as an image input function, an image output function, and a copy function, if the image input device and the image output device cannot operate synchronously, the image input The copy function has been realized by outputting the image data once taken into the memory from the device to the image output device. When the image input device and the image output device can operate in synchronization, a copy function is realized by providing a path for directly transferring an image signal from the image input device to the image output device.

Conventional digital multifunction peripherals have been developed in the form of additional functions of conventional machines, such as those in which a fax function is added to a copying machine and those in which a printer function is added to a fax machine. Only the composite operation and the parallel operation in job units could be performed. In conventional digital multifunction devices, when it is not possible to secure a sufficient bus to transmit and receive various data to be
The configuration is such that a local memory is distributed in an interface unit such as a printer.

FIG. 112 is a timing chart for explaining job processing when control is performed on a job basis.
Print job 1 and print job 2 are jobs to be processed by the multifunction peripheral. Consider a case where these jobs acquire a certain resource (for example, page memory).
At time T1, the print job 1 previously input acquires the resource. At the timing of T2, the subsequent print job 2 acquires the resource, but the print job 1 occupies the resource (locks) and cannot acquire the resource.
The resource acquisition request is queued. And T3
When the print job 1 releases the resources at the timing of (1), the print job 2 acquires the resources and performs the processing in accordance with the resource acquisition request of the queued print job 2. In other words, during the time from T1 to T3, the print job 1 exclusively uses resources, so that the processes of the print job 1 and the print job 2 become serial.

[0005]

However, in the conventional digital multi-function peripheral, a series of jobs are processed in a job-by-job order and executed. Therefore, when a plurality of jobs are input to the digital multi-function peripheral. The next job is in a standby state until the processing of the preceding job is completed, and the throughput of the job is reduced.

[0006] In some cases, a locally secured memory stores redundant information for each device, and thus requires a redundant memory area larger than a necessary area.

Further, when a single CPU is used for processing having a difference in necessity of real-time processing, processing that requires real-time processing is sacrificed by processing that does not require real-time processing. Had been lowered.

[0008]

The system according to the present invention is for solving any of the above-mentioned problems, and is characterized mainly by the following constitution.

That is, the information processing system of the multifunction device includes an interface for inputting an image signal from the image signal input means, a first bus connecting the interface to a system bus bridge, and the input bus via the system bus bridge. A memory for storing the stored image signal, an interface for outputting the image signal from the image signal output unit, and a second bus connecting the stored image signal to the interface for outputting the image signal via the system bus bridge. It is characterized by having. Further, the information processing system of the multifunction peripheral includes an interpreting unit that interprets a procedure transmitted from the information processing apparatus, a job generating unit that generates a job based on the interpretation of the procedure, and an element that configures the generated job. Dividing means, a device managing means for managing allocation and release of devices for processing the divided elements, a means for writing processing results of the allocated devices to a memory, and a means for writing to the memory. Means for outputting the inserted data to another device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a description will be given of "DoEngine" which is a single-chip scanning and printing engine including a processor core, a processor peripheral controller, a memory controller, a scanner / printer controller, a PCI interface and the like.

[0010] 1. DoEngine Overview DoEngine is an R40 from MIPS Technology.
It is a single-chip scanning and printing engine with a built-in processor core, processor peripheral controller, memory controller, scanner / printer controller, PCI interface, etc. It is implemented using high-speed parallel operation and the building block method.

In a processor shell (general term for processor peripheral circuits including a processor core), a maximum of 32 Kbytes of cache memory of 16 Kbytes each of instructions and data, an FPU (floating point arithmetic unit), an MMU (memory management unit), It is possible to incorporate a user-definable coprocessor or the like.

Since it has a PCI bus interface, it can be used with a computer system having a PCI bus slot. In addition to the PCI satellite configuration, a PCI bus configuration can be issued in a PCI host bus bridge configuration. By combining with a low-cost PCI peripheral device, a main engine of a multifunction peripheral (multifunction peripheral) can be issued. It is also possible to use as. Furthermore, it is possible to combine with a rendering engine and a compression / decompression engine having a PCI bus interface.

An IO for connecting a general-purpose IO core inside the chip
Bus (B bus) and graphic bus optimized for image data transfer (G bus: Graphics Bus)
By connecting these buses to the memory and processor via a crossbar switch, high-speed data transfer with high parallelism, which is essential for simultaneous operation in a multifunction system, is realized. I have.

The memory includes a synchronous DRAM (SDRAM) having the highest cost performance for accessing a continuous data string represented by image data.
In order to minimize the performance degradation of random access in small data units that cannot enjoy the advantages of SDRAM burst access high-speed data transfer, an 8-Kbyte 2-way set associative memory front cache is provided in the memory controller. . The memory front cache, even in a system configuration that employs a crossbar switch, in which bus snooping for all memory writes is difficult, without a complicated mechanism,
This is a system that can achieve high performance by a cache memory. In addition, it has a data interface (Video Interface) with a printer and a scanner capable of real-time data transfer (device control), and further supports hardware-to-device synchronization and image processing by hardware to separate the scanner and printer. Also in the mold configuration, a high-quality and high-speed copy operation can be realized.

In the case of DoEngine, the core is 3.3.
Operates at V and IO is 5V tolerant.

FIGS. 1, 2 and 3 show DoEngine
1 shows an example of the configuration of an apparatus or a system that uses the same.
FIG. 1 shows a personal computer 10 of a separated configuration type.
A local board 101 equipped with DoEngine is attached to 2 via a PCI interface provided therein. The local board 101 includes, in addition to DoEngine, a memory connected to DoEngine via a memory bus, which will be described later, and a color processing circuit (chip). The high-speed scanner 103 and the color / monochrome printer 104 are connected to the personal computer 102 via the local board 101. With this configuration, under the control of the personal computer, the local board 101 can process the image information input from the scanner 103 and output the image information from the printer 104.

FIGS. 2 and 3 show an example in which the scanner 203 and the printer 202 are integrated. FIG. 2 shows a configuration similar to a normal copying machine, and FIG. 3A shows a configuration of a facsimile machine and the like. ing. FIG. 3B shows a computer that controls FIG. 3A.

FIGS. 1 and 2 show DoP by an external CPU connected via a PCI interface.
FIG. 3 shows an example in which the engine is used in a slave mode in which the engine is controlled.
This is an example in which U is a main component and is used in a master mode for controlling a device connected via a PCI interface.

Table 1 shows the specifications of DoEngine. External interfaces include PCI, memory bus, video, general purpose input / output, IEEE1284, RS23
2C, 100baseT / 10baseT, LCD panel and key, but may further have USB. As a built-in block, a primary cache, a memory controller with a cache, a copy engine, an IO bus arbiter (B bus arbiter), a graphic bus arbiter (G bus arbiter), and the like are provided in addition to the CPU core. The DMA controller has five channels, and has a graphic bus (G bus) and an IO bus (B bus).
In both cases, arbitration is performed in a first-come-first-served manner with priority.

[0020]

[Table 1]

2. Configuration and operation of DoEngine In this chapter, in addition to the general description of DoEngine, a block diagram, an overview, details, a core interface, a timing diagram, and the like for each functional block are described.

2.1. DoEngine Chip Configuration FIG. 4 shows a block diagram of DoEngine. D
oEngine 400 is a next-generation multifunction peripheral (system) (MFP: Multi Function Pe
ripheral or MFS: Multi Func
Tion System) was designed and developed as the main controller.

As a CPU (processor core) 401,
Adopt MIPSR4000 core from MIPS Technology. In the processor core 401, instructions and data cache memory of 8 Kbytes each, M
MU and the like are implemented. The processor core 401 has 64
It is connected to a system bus bridge (SBB) 402 via a bit processor bus (SC bus). S
A BB 402 is a 4 × 4 64-bit crossbar switch, and is connected to a memory controller 403 for controlling an SDRAM or a ROM having a cache memory in addition to the processor core 401 by a dedicated local bus (MC bus). G bus 40 which is a graphic bus
4. Connected to the B bus 405, which is an IO bus,
Connected to two buses. System bus bridge 402
Is designed to ensure simultaneous parallel connection between these four modules as much as possible.

The G bus 404 is a G bus arbiter (GBA).
Coordinated control is performed by a control unit 406, which is connected to a scanner controller 4302 or a printer controller 4303 for connecting to a scanner or a printer. The B bus 405 is cooperatively controlled by a B bus arbiter (BBA) 407, and includes a scanner / printer controller, a power management unit (PMU) 409, an interrupt controller (IC) 410, and a serial interface controller (UART) using a UART. SIC) 411, U
SB controller 412, parallel interface controller (PIC) 41 using IEEE1284
3. LAN controller using Ethernet (LAN
C) 414, LCD panel, keys, general-purpose input / output controller (PC) 415, PCI bus interface (P
CIC) 416.

2.2. Processor shell A processor shell is an MMU in addition to a processor core.
(Memory Management Unit),
Refers to a block including an instruction cache, a data cache, a write-back buffer, and a multiplication unit.

<Cache Memory> As shown in FIG. 5, the cache memory controller is invalid (Inva
lid), valid and clean (Valid Clear)
n: the cache is not updated), and three state caches, valid and dirty (the cache is updated), are managed. The cache is controlled according to this state.

2.3. Interrupt Controller FIG. 6 shows a block diagram of the interrupt controller 410.

The interrupt controller 410 is connected to the B bus 405 via the B bus interface 605, integrates each functional block in the DoEngine chip and an interrupt from outside the chip, and has six levels of interrupts supported by the CPU core 401. Redistribute to external interrupts and non-maskable interrupts (NMI). Each functional block includes a power management unit 409,
Serial interface controller 411, USB
Controller 412, parallel interface controller 413, Ethernet controller 414, general-purpose IO controller 415, PCI interface controller 416, scanner controller 4302, printer controller 4303, and the like.

At this time, a mask register (IntMask Logic) capable of software configuration is used.
c0-5) 602 makes it possible to mask an interrupt for each factor. For the external interrupt input, the edge sensing / level sensing can be selected for each signal line by the selective edge detection circuit 601. Cause register (Detect and set C
ause Reg0-5) 603, for each level,
By indicating which interrupt is asserted and performing a write operation, it is possible to clear each level.

The interrupt signal of each level is output as a logical sum by the logical sum circuit 604 so as to output an interrupt signal if there is at least one interrupt for each level. The level assignment between a plurality of factors in each level is performed by software.

2.4. Memory Controller FIG. 7 is a block diagram of the memory controller 403. The memory controller 403 is connected via an MC bus interface 701 to an MC bus, which is a local bus dedicated to the memory controller, and supports a maximum of 1 gigabyte synchronous DRAM (SDRAM) and a 32 megabyte flash ROM or ROM.
64 (16 × 4) burst transfer is realized to take advantage of the high speed at the time of burst transfer, which is a feature of SDRAM. In consideration of single transfer of continuous addresses from the CPU and the B bus, an SRAM (memory front cache) 702 is built in the memory controller, and transfer efficiency is reduced by avoiding direct single transfer to the SDRAM as much as possible. Improve. The data bus width between the memory controllers SDRAM is determined by the signals ramData and ramPa.
r together with 72 bits (of which the signal ra of 8 bits
mPar is a parity), and the width of the data buses finromData and prglomData between the flash ROMs is 32 bits.

2.4.2. Configuration and Operation The components of the memory controller are configured as described below.

<MC bus interface (701)>
MC bus is SBB 402-memory controller 403
It is a dedicated bus between them and is used as a basic bus inside the SBB.

While the burst transfer of the dedicated bus PBus connecting the CPU 401 and the bus bridge 402 specifies only four bursts, the MC bus adds a transfer of up to 16 bursts × 4. For this purpose, mTType [6: 0] is newly defined as a signal indicating the burst length. (Definition of MC bus signal) Each signal of the MC bus is defined as follows. • mClk (output): MC bus clock • mAAddr [31: 0] (output): MC bus address 32-bit address bus, mTs MBRdy from the time when L is asserted Held until L is asserted. -MDataOut [63: 0] (output) ... MC bus data output This is a 64-bit output data bus, and mDataOe
Valid only when L is asserted.・ MDataOe L (output) ··· MC bus data output enable Indicates that mDataOut [63: 0] is valid. It also indicates that the transfer is Write. -MDataIn [63: 0] (input) ... MC bus data input This is a 64-bit input data bus, and mBRdy. It is sampled at the rising edge of mClk where L is asserted.・ MTs L (output) ... MC bus transaction start strobe Indicates that transfer has started. Asserted only during the first clock of the transfer. MTs if the transfer is completed in one clock and the next transfer can be started immediately L remains asserted. MTType [6: 0] (output) ··· MC bus transaction type Indicates the type of transfer on the MC bus. During single transfer, during the transfer, during burst transfer, the first transfer (beat)
Held for a while. The upper 3 bits represent the source (master) and the lower bits represent the single / burst length. The types are as follows.

[0035] ・ MBE L [7: 0] (output) ... MC bus transaction byte enable Indicates a valid byte lane on the 64-bit data bus during single transfer. At the time of burst transfer, it is effective only at the time of Write, and is ignored at the time of Read.・ MBRdy L (input): MC bus ready Indicates that the current transfer (beat) has been completed.・ MTPW L (output): Next transaction is In-pagewrite (in-page write) Next transfer is Wri of the same page (same Row address)
te, and up to four Writes can be continued. The page size is set in the configuration register in advance.・ MBPWA L (input): Permits intra-page write of bus Indicates whether the MC bus slave (memory controller) permits intra-page write transactions,
BRdy It is sampled at the same clock as L. At this time, mBPWA MTP if L is deasserted
W L becomes meaningless.・ MBRty L (input) ... bus retry Assert when the MC bus slave (memory controller) terminates the access without executing it, and indicates that the retry must be performed after idle for at least one cycle. (If mBRdy L and mBRty
If L is asserted simultaneously, mBRty L has priority.・ MBerr L (input): Bus error Asserted when a parity error or other bus error occurs.

The above-mentioned distinction between input and output is a definition from the viewpoint of SBB. (MC bus transaction) The following transactions are supported as transactions on the MC bus. Basic transaction (1,2,3,4,8 bytes Read / Write) mBE According to the L [7: 0] signal, a single transaction of 1, 2, 3, 4, 8 bytes is supported. Burst Transaction (from CPU) Supports transactions up to 4-doubleword burst. Supports up to 16-doubleword burst x4 transactions from the G bus. In-page write transaction mTPW For writing in the same page indicated by L, continuous Write access is supported. Bus retry If memory access is not possible due to restrictions in the memory controller, mBRty Assert the L signal to notify the bus retry.

<SDRAM Controller (705)> The memory controller 403 has the following configuration.
The DRAM is controlled as follows.

(DRAM Configuration) As a DRAM configuration, a 16/64 Mbit SDRAM of x4, x8, and x16 bit type can be controlled by eight banks with a 64-bit data bus.

[0039]

[Table 2]

(DRAM address bit configuration) DRAM
For the assignment of the address bits of
In the case of RAM, MA [13: 0] is converted to 16-bit SD
In the case of a RAM, MA [11: 0] is used.

[0041]

[Table 3]

(SDRAM Programmable Configuration (Mode Register)) The SDRAM has a mode register inside and sets the following items using a mode register setting command. Burst length The burst length can be set to 1, 2, 4, 8 or full page, but the burst transfer length from the CPU is 4
Therefore, the burst length 4 is optimal. Transfer of 16 bursts or more from the G bus is Read / Write
This is realized by issuing commands (without auto precharge) continuously. Wrap Type (Wrap Type) Sets the increment order of addresses during burst transfer. Either “sequential” or “interleave” can be set. CAS Latency The CAS latency can be set to one of 1, 2, and 3, and is determined by the grade of SDRAM to be used and the operation clock.

(SDRAM command) The following commands are supported for the SDRAM. Details of each command are described in the SDRAM data book.・ Mode register setting command ・ Active command ・ Precharge command ・ Write command ・ Read command ・ CBR (Auto) refresh command ・ Self refresh start command ・ Burst stop command ・ NOP command (SDRAM refresh) For SDRAM, 2048 cycles / 32 ms (4096) / 64ms)
A CBR refresh command is issued every 16,625 ns. The memory controller has a configurable refresh counter and automatically issues a CBR refresh command. During the transfer of the 16-burst xn from the G bus, no refresh request is accepted. Therefore,
The refresh counter must be set to a value with a margin of 16-burst × 4 transfer time. Also,
Support self refresh. When this command is issued, the power down mode (ramclke L =
At (Low), the self-refresh is continued.

(SDRAM initialization) After a power-on reset, the memory controller performs the following initialization on the SDRAM. That is, after a pause period of 100 μs after power-on, all banks are precharged by using a precharge command. Set the mode register of the SDRAM. Refresh is performed eight times using an auto-refresh command.

<Flash ROM controller (70
4)> The flash ROM controller 704 is
Addr [23: 2] address signal and four chip select (romCs L [3: 0]) signals. Address signals romAddr2 to romAddr9
Are multiplexed with the parity signals ramPar0 to ramPar7, and the address signals romAddr10 to r
omAddr23 is a DRAM address ramAddr.
It is multiplexed with 0 to ramAddr13.

<SRAM control (memory front cache)> SDRA used as main memory
M is very fast in burst transfer, but cannot exhibit high speed in single transfer. Therefore, a memory front cache is implemented in the memory controller to increase the speed of single transfer. The memory front cache includes a cache controller 706 and an SRAM.
702. MTTy defined for MC bus
Since the transfer master and the transfer length can be known from the pe [6: 0] signal, the ON / OFF of the cache can be set for each master or for each transfer length.
The cache method is as follows. Hereinafter, unless otherwise specified, the term “cache” or “cache memory” refers not to a cache built in a processor core but to a memory front cache built in a memory controller. -2 way set associative-8k byte data RAM-128x21x2 tag RAM-LRU (Least Recently Used)
Algorithm Write-through No Write Allocate Next, a detailed block diagram centering on the cache controller 706 is shown in FIG.

(Operation of Cache) The operation of the cache when a memory read / write transfer is requested from the MC bus will be described with reference to the block diagram of FIG. 8 and the flowcharts of FIGS.

When data transfer is started from the MC bus,
MTType shown on the MC bus at the beginning of the transfer
[6: 0], it is determined whether the transfer is performed with the cache on or off. In this description, it is determined that the transfer is ON if the transfer is a single transfer and OFF if the transfer is a burst transfer (step S90).
1). That is, if mTType (3) is "1" h, it indicates a single transfer, so that the cache is turned on.
If "0" h, it indicates burst transfer, so transfer is performed with cache off.

In the case of single transfer (cache on),
Given the address lmaddr [31: 0], l
maddr [11: 5] is b1 as an index t
ag ram801, b2 tag ram802, b1
data ram702-a, b2 data ra
m702-b and lru803, and
From the lock, the validity of the index
Debit "v" and b1_tag addr, valid
Bid "v" and b2 tag addr, b1 ou
t data, b2 out data, lru in
Are output (step S902).

B1 tag ram801 and b2 ta
g b1 output from ram802 tag add
r and b2 tag addr is each b1 comp
eater 804, b2 comparator80
5 is compared with the address lmaddr [31:12],
As a result, that is, whether or not the hit is b1 hit mi
ss_L, b2 hit miss The cache controller 706 is notified by the L signal and determined (step S903).

If it is a hit here, it is determined whether it is a read or a write (step S904). The hit is b1 tag addr and b2 tag addr
Is in agreement with the address lmaddr [31:12]. In the case of a hit and a lead, it is as follows. That is, if b1 is a hit and the requested transfer is a read, b1 already read out data and b2 out
b1 out of data out Select data and l
8 bytes of data indicated by maddr [4: 3]
Output to the C bus (step S905). At the same time, lru corresponding to the index is set to “0” (= b1 hit)
And the transfer ends. b2 is a hit,
If the requested transfer was a read, b1 already read out data and b2 out d
b2 out of data out Select the data, lma
The 8-byte data indicated by ddr [4: 3] is output to the MC bus (step S905). At the same time, lru corresponding to the index is rewritten to "1" h (= b2 hit), and the transfer is completed.

On the other hand, in the case of hit and write, the following is performed. That is, if b1 is a hit and the requested transfer is a write, b1 indicated by the index data lmaddr of ram702-a
MBE of the 8-byte data indicated by [4: 3]
Only the valid byte lane indicated by L [7: 0] is rewritten, and at the same time, lru corresponding to the index is rewritten to “0” h (= b1 hit). Also SDRA
M is similarly rewritten and the transfer is completed (step S90).
6). If b2 is a hit and the requested transfer is a write, b2 indicated by the index data
mBE of 8-byte data indicated by lmaddr [4: 3] of ram702-b Only valid byte lanes indicated by L [7: 0] are rewritten, and at the same time, lru corresponding to the index is rewritten to “1” h (= b2 hit). Similarly, the SDRAM is rewritten and the transfer is completed (step S906).

On the other hand, when both b1 and b2 are mistakes,
Is read or written (step S100).
1). If the requested transfer was a read, its l
8 bytes of data indicated by maddr [31: 3]
It is read from the SDRAM (step S1003), and M
The data is output to the C bus (step S1004). At the same time
Lru corresponding to the index of “0” is read, and “0” is read.
If h, b2 data SDRAM to ram
These data are written and lru is also rewritten to "1" h. lr
If u is "1" h, b1 data to ram
Write data from SDRAM and write lru to “0” h
The replacement is completed (step S1005). b1, b2 and
If an error was originally made and the requested transfer was a write
Transfer ends only by writing to SDRAM (step
Step S1002).

In the case of burst transfer (cache off) in step S901, both read and write
Performed only for AM (steps S907-S90)
9), rewriting of cache data and tags is not performed.

<ROM / RAM interface (70
7)> The configuration of the ROM / RAM controller 707 is shown in FIG.
It is shown in FIG. Blocks 1101 to 1104 multiplex the data signal, address signal, and parity signal of the SDRAM with the data signal and address signal of the flash ROM.

2.4.3. Timing Diagram The timing of processing such as data reading / writing by the memory controller 403 described above will be described with reference to FIGS.

FIG. 12 shows the timing of burst reading from the CPU. The burst length is 4, and the CAS latency is 3. This corresponds to the processing in step S909 in FIG.

FIG. 13 shows the timing of burst writing from the CPU. The burst length is 4, and the CAS latency is 3. This corresponds to the processing in step S908 in FIG.

FIG. 14 shows the timing of burst reading from the G bus device. G bus burst length is 1
6, the burst length of the SDRAM is 4, and the CAS latency is 3. This corresponds to the processing in step S909 in FIG.

FIG. 15 shows the timing of burst write from the G bus device. G bus burst length is 1
6, the burst length of the SDRAM is 4, and the CAS latency is 3. This corresponds to the processing in step S908 in FIG.

FIG. 16 shows the timing of a single read when a hit occurs in the memory front cache.
The data mDataIn [63: 0] to be read includes the cache memory b1 data ram7
02-a or b2 data b1 / b2 read from ram702-b out data is output. The burst length of the SDRAM is 4 and the CAS latency is 3. This corresponds to the processing in step S905 in FIG.

FIG. 17 shows the timing of a single read when no hit occurs in the memory front cache. Data to be read mDataIn [63: 0]
Is the data ramD read from the SDRAM
data [63: 0] is output. Also, this data is b1 / b2 in b1 which is a cache memory as data data ram702-a or b2
data Also written to ram702-b. SDR
The burst length of AM is 4, and the CAS latency is 3.
This corresponds to the processing in steps S1004 and S1005 in FIG.

FIG. 18 shows that the memory front cache is
This shows the timing of the single write in the case of setting.
The data mDataOut [63: 0] to be written is
B1 which is a cache memory data ram702
-A or b2 data Write to ram702-b
At the same time as writing to the SDRAM. SDR
The burst length of AM is 4, and the CAS latency is 3.
This corresponds to the processing in step S906 in FIG.

FIG. 19 shows the timing of a single write when no hit occurs in the memory front cache. The data to be written mDataOut [63:
0] is the cache memory b1 data ra
m702-a or b2 data ram702-
It is not written to b but written only to SDRAM. The burst length of the SDRAM is 4 and the CAS latency is 3. This corresponds to the processing in step S1002 in FIG.

Here, when the data transfer is started from the MC bus, mTType [6: 0] indicated on the MC bus at the beginning of the transfer indicates that if the transfer is a single transfer, it is turned on, and the burst transfer is performed. If the burst length is smaller than one line of the cache, the cache is turned on; if not, the cache is turned off; otherwise, the cache is turned off. You may do so.

Also, by including in the MC bus a signal indicating the identifier of the bus master that has requested data transfer to the memory, the memory controller determines the identifier and controls cache on / cache off according to the identifier. You can do it. In this case, it is also possible to prepare a rewritable table in which the identifier is associated with the cache ON / OFF, and switch the cache ON / OFF with reference to the rewritable table. This table can be made rewritable by the CPU 401 or the like by assigning a specific address, for example.

2.5. System bus bridge (SBB)
FIG. 20 is a block diagram of a system bus bridge (SBB) 402.

The SBB 402 includes a B bus (input / output bus),
A multi-channel bi-directional bus bridge that provides interconnection between a G bus (graphic bus), an SC bus (processor local bus) and an MC bus using a crossbar switch. With the crossbar switch, two systems can be simultaneously connected, and high-speed data transfer with high parallelism can be realized.

The SBB 402 includes a B bus interface 2906 for connecting to the B bus 405 and a G bus 40
G bus interface 2006 to connect to
And a CPU interface slave port 2002 for connecting to the processor core 401, a memory interface master port for connecting to the memory controller 403, an address switch 2003 for connecting an address bus, and a data switch 2004 for connecting a data bus. including. Further, a cache invalidation unit 2005 for invalidating the cache memory of the processor core is provided.

The B bus interface 2009 has B
A write buffer for speeding up DMA write from the bus device and a read prefetch queue for improving read efficiency of the B bus device are mounted. Coherency management for data temporarily existing in these queues is performed by hardware. Note that a device connected to the B bus is called a device.

The processor core supports dynamic bus sizing for a 32-bit bus.
The BB 402 does not support this. In the future, even if a processor that does not support bus sizing is used, S
This is for minimizing the modification required for the BB.

2.5.1. Configuration and Operation of SBB and Each Bus <B Bus Interface> FIG. 21 is a block diagram of the B bus interface.

The B bus interface 2009 is a bidirectional bridge circuit between the B bus and the MC bus. The B bus is a DoEngine internal general-purpose bus.

In the B bus interface 2009,
Master control block 2011, slave control block 2010, data interface 20
12, DMAC 2013, and 5 blocks of B bus buffer. In FIG. 21, the DMAC 2013 is functionally divided into three sequencers and register blocks. Of these three sequencers, the DMA memory access sequencer is the B bus slave control block 201
At 0, the DMAreg sequencer is built into the B bus master control block 2011. A DMA register as a register block is built in the B bus data interface 2012 unit.

Further, the B bus interface 2009
When writing to the memory from the bus side and when transfer from the device to the memory by DMA occurs, invalidation of both data and instruction caches in the CPU shell is controlled via the cache invalidation interface.

Although a write-back buffer for CPU write is not mounted on the B bus interface, a write buffer for external master write on the B bus is mounted. As a result, continuous writing from an external master, which is not a burst transfer, is speeded up. The flushing of the write buffer is performed when the connection to the memory by the B bus arbiter 407 is permitted. The write buffer bypass for the B bus master read is not performed.

The read prefetch queue of the external master is executed. Thus, the speed of reading the continuous data stream from the external master is increased. To invalidate the read buffer: When a new read of the B bus does not hit the buffer. 2. When writing from the CPU to the memory is performed. 3. When data is written from the G bus to the memory. 4. When data is written from the B bus to the memory. Done in

The B bus interface 2009 incorporates a DMA controller 2013 between each device on the B bus 405 and the memory. System bus bridge 4
02, a DMA controller is built in, an access request can be issued to both bridges at the same time, and efficient DMA transfer can be realized.

The B bus interface 2009 does not request the use of dynamic bus sizing in response to an access request from the processor 401. When a memory access request is issued from the B bus master, the memory controller 4
It does not correspond to the bus sizing from 03. That is,
Memory controllers should not expect bus sizing.

<B Bus> The B bus is a general-purpose IO bus in DoEngine, and has the following specifications. -Address / data separation type 32-bit bus.・ Any wait cycle can be inserted. The shortest is no wait. -Support for burst transactions.・ Maximum transfer speed is 200M when clock is 50MHz
byte / Sec. -Support for bus error and bus retry. -Support for multiple bus masters.

(B Bus Signal Definition) The definition of the bus signal will be described below. Each signal is described in the manner of “Signal name (English name): input source> output destination (, 3States)... Signal description”. Note that the three-state item is described only for three-state signals.

BAddr [31: 2] (IOBus A
address Bus): Master> Slab
e, 3State ... IO Bus address bus.

BData [31: 0] (IOBus
Data Bus): DataDriver> Dat
aReceiver, 3State ... IOBus data bus.

B (Data drive name) Da
taOeReq (IOBus Data Output)
Enable Request): Datadriv
er> DefaultDriverLogic... This is an output signal to a default driver control logic in order to realize a bidirectional IO bus described later. Da
A request signal for driving data on a bus by a device having a tadrivername. For devices that are allowed to output data, b (Datadriver)
ame) DataOe L is output. Datadr
Examples of aver: Pci, Sbb, Jpeg, Spu.

B (Data drive name) Da
taOe L (IOBus Data Output)
Enable) dfaultDriverLogic>
DataDriver… b (DataDriver
name) For the device that output DataOeReq
And the default driver logic is
B (Datadriver) when data drive is allowed
ame) DataOe L signal is returned to the device.
You.

BError L (IOBus Bus
Error): Slave> Master 3Stat
e: Indicates that the IO bus transaction ended with an error.

B (Mastername) BGnt L
(IOBus Grant): Arbiter> Mas
ter: Indicates that this master has obtained the right to use the bus by bus arbitration. Mastername
Examples: Pci, Sbb, Jpeg, Spu.

BlnstNotData (IOBus
Instruction / DataOutput In
dicator): Master> Slave, 3St
ate: Drives high when the B bus master performs instruction fetch for the B bus slave. In the case of a data transaction, drive to Low.

B (Mastername) CntOe
Req (IOBus MasterControl O
output EnableRequest): Mast
er> DefaultDriverLogic… B
If the bus master is bStart L, bTx L, bWr
L, vInstNotData and bAddr [31:
2] on a 3-state bus, the IO
Assert for Bus Output Control Logic. IOBus Output Co
control Logic is bMCnt from each master.
For masters that allow drive based on lOeReq, b
(Mastername) CntOe Returns L signal.

B (Mastername) CntOe
L (IOBus MasterControl Ou
output Enable): DefaultDrive
rLogic> Master… b (Mastern
ame) For the master that outputs CNtlOeReq,
If default driver logic allows driving b
(Mastername) CntOe Return the L signal to its master.

BRdy L (IOBus Read
y): Slave> Master, 3State ...
The B bus slave asserts this signal to indicate that the current B bus data transaction ends the current clock cycle last. The B bus master knows from this signal that the current transaction will end in this clock cycle.

B (Mastername) BReq L
(IOBus Bus Request): Maste
r> Arbiter... indicates that the B bus master issues a bus use right request to the B bus arbiter.

BRetry L (IOBus Bus
Retry): Slave> Master 3Stat
e: The B bus slave requests the master to execute the bus transaction the most.

B (Slavename) RdyOeRe
q (IOBus Slave Ready Output)
t Enable Request): Slave> D
defaultDriverLogic ... B bus slave is bRdy L, bWBurstReq L, b
BurstAck When driving L on a three-state bus, the IO Bus Output Control
Assert for Logic. IOBusDe
faultDriverLogic is the
b (Slavename) For a slave that permits driving based on RdyOeReq, b (Slavenname)
e) RdyOe Returns L signal.

B (Slavename) RdyOe L
(IOBus Slave Ready Output
Enable) DefaultDriverLogi
c> Slave ... b (Slavename) Rdy
When the default driver logic permits driving for the master that has output OeReq, b (Slavena
me) RdyOe Return the L signal to its master.

BSnoopWait (IOBus Sn
Oop Wait): SBB> NextMaster
... Indicates that the B bus interface is executing snooping of the cache to other devices connected to the B bus. Devices connected to the B bus cannot issue new transactions while this signal is asserted.

BStart L (IOBus Tran
action START): Master> Sla
ve 3State... A signal indicating that the B bus master starts the B bus transaction, and the B bus slave can know the start of the B bus transaction by monitoring this signal.

BTx L (IOBus Transac
Tion Indicator Input): Mas
ter> Slave 3State ... The B bus master asserts to the B bus slave to indicate that a B bus transaction is currently being executed.

BWBurstGnt L (IOBus
Burst Write Grant): Master
> Slave, 3State ... The B bus master drives to indicate that a burst write is to be performed in response to a B bus burst write request.

BWBurstReq L (IOBus
Burst Write Request): Slav
e> Master, 3State ... B bus slave is B
Assert when requesting a bus master for berth and write.

BWr L (IOBu Write Tr
response Indicator): Mast
er> Slave, 3State ... B bus master
Assert to the B bus slave to indicate that the current transaction is a write.

BByteEn [3: 0] (IOBus
Byte Enables): DataDriver>
DataReceiver, 3State... The agent driving data on the B bus drives High to indicate that the byte lane on bData [31: 0] corresponding to each bit is valid. Table 4 shows the correspondence between each line of this signal and the byte lane of bData.

[0102]

[Table 4]

BBurst L (IOBus Exte
nded Burst Request): Maste
r> Slave, 3State... Indicates that the B bus master wants to perform an extended burst. Assert, negate timing is bTx Same as L.

BBurstAck L (IOBus E
xended Burst Acknowledg
e): Slave> Mast, 3State ... Indicates that the B bus slave can perform an extended burst. Assert and negate timings are bRdy Same as L.

BBurstShortNotLong
L (IOBus Burst Length): Ma
ster> Slave, 3State... Indicates the burst length when the B bus master performs an extended burst. Assert, negate timing is bTx It is the same as L, and the correspondence between the signal value and the burst length is as shown in Table 5.

[0106]

[Table 5]

The B bus signal is as described above. DoEn
The B bus (and G bus), which is a bus inside the Gine, has 10 or more functional blocks to be connected.
It is difficult to connect all the blocks with the ut separation bus. DoEngine employs an on-chip bidirectional bus.

<G Bus Interface> FIG. 22 is a block diagram of the G bus interface 2006. The outline is as follows.

(Overview of G Bus) The G bus is a bus defined to execute high-speed data transfer between the image data processing units inside the MFP one-chip controller DoEngine. It has a 64-bit data bus,
Supports 4 Gbyte (128 byte boundary) address space. 16 beats (128 by
te = 64 bits × 16) is basically a transfer with one long burst, and four long bursts (512 by) are successively performed.
te = 16 beats x 4). (Transfer of 16 beats or less such as single beat is not supported.) (G bus signal definition) First, a symbol used for signal definition is determined. Immediately after the signal name, the direction of the signal is described as necessary. It is defined as follows. In (Input signal) ... Input signal to the bus agent Out (Output signal)
al)… output signal InOu from the bus agent
t (Bi-Directional Tri-Stat
e signal) A plurality of bus agents are driven by bidirectional signals. Only one agent drives at a time. The enable request signal of each agent that drives the signal is centrally managed by a default driver, and the default driver determines which agent drives. The default driver signal is driven when no agent issues an enable request or when a plurality of agents issue enable requests simultaneously. If the agent drives the signal low, it must drive high for one clock before and after. Signal assertion can be performed only after one or more clocks have passed since the drive was first started. Basically, the signal is released at the next negated clock.

[0110] Note that "" after each signal name is used. L "indicates that the signal is low active. The description of the signal substantially conforms to the description of the B bus signal. The description is divided into a system signal, an address and data signal, an interface control signal, and an arbitration signal. Do
The bus agent is a general term for a bus master and a bus slave connected to a bus.

(System Signal) gClk (G-Bus Clock)... Provides timing for all transactions on the G bus and is an input to all devices.

GRst L (G-Bus Reset)
... Resets all devices on the G bus. All internal registers are cleared and all output signals are negated.

(Address and Data Signals) gAddr [31: 7], InOut, (G-Bus
Address): Master> Slave ... Since all data transfer on the G bus is performed in units of 128 bytes (16 beats), gAddr [31] to gAddr
The address space of 4 Gbytes is supported by 25 bits of dr [7]. drive: gTs Master drives at the same time as L assert: The next clock after drive negate: gAack Clock whose L assertion has been confirmed.

G (Mastname) AddrOeR
eq (G-Bus AddressOutPut En
able Request): Master> Def
outputDriverLogic: An output signal to the default driver logic for realizing a bidirectional G bus. Request signal for the bus master to drive the address bus.

G (Mastername) AddrOe
L (G-Bus AddressOutPut En
ablet) DefaultDriveLogic> M
master… g (Mastername) Addr
A signal indicating that the default driver logic permits the bus master that has output OeReq to drive the address bus.

GData [63: 0], InOut,
(G-Bus Data): DataDriver> D
dataReceiver ... A 64-bit data bus.
The master drives when writing, and the slave drives when reading.

[Light] drive: gTs Master drives at the same time as L. Was
However, gSlvBsy Negate when L is asserted
Wait for drive and drive. assert: The next clock that has been driven. change: gAack L confirms the assertion of L
Lock, then every clock. negate: at the end of transfer or gTrStp L
GAack when the transfer stop request L's
Clock that asserted.

[Read] drive: gAack The slave drives at the same time as L. assert: the next clock after the drive if the slave is Ready, and Ready if not.
Wait until is asserted. change: gAack A clock that confirms L assertion, and thereafter every clock. For read, every clock from the asserted clock. negate: at the end of transfer. release: One clock after negation or gT
rStp A clock that has confirmed the transfer stop request by L.

G (DataDrivename) Da
taOeReq (G-Bus Data OutPut
Enable Request): DataDrive
er> DefaultDriverLogic A request signal for the data driver to drive the data bus.

G (DataDrivename) Da
taOe L (G-Bus Data OutPut
Enable) DefaultDriverLogi
c> DataDriver ... g (DataDrive
(ername) A signal indicating that the default driver logic permits the data driver that has output DataOeReq to drive the data bus.

(Interface control signal) gTs L (InOut G-Bus Transac
Tion Sart): Master> Slave ...
 Asserted low for one clock by master
And indicates the start of transfer (address phase). trout
Tar is gTs GAddr, gRdNotW with L
Drive r, gBstCnt, transfer type, data
Clarify quantity. Master here is clear in case of write
Guarantee that the transferred data volume can be output without weight.
There must be. In the case of a lead, a clear roll
We must guarantee that we will receive the amount of data sent without weight
Must. Slave cannot transfer data on the way
GBsStep L, the next 16 beats
Transfer may be canceled. However, 16 beats
There is no cancellation on the way. drive: gGnt Clock that confirmed assertion of L
Drive with assert: The next clock that has been driven. negate: negated after clock assertion
You.

G (Mastername) TsOeRe
q (G-Bus Transaction Start
OutPut EnableRequest): Ma
ster> DefaultDriverLogic ...
Bus master is gTs Request signal for driving L.

G (Mastername) TsOe L
(G-Bus Transaction Start
OutPut Enable): DefaultD
riverLogic> Master… g (Mas
terminator) The default driver clock is gTs for the bus master that has output TsOeReq. A signal indicating that L drive is permitted.

GAack L, InOut, (G-Bu
s Address Acknowledge): Sl
ave> Master ... for one clock by slave
Driven to Low. The relevant slave sends the transfer
Recognizes, confirms that the bus is free, and transfers data
Tell the master that you can start. Of the light
In this case, the slave sets the transfer data amount requested by the master
You have to guarantee that you get it without weight.
In the case of read, the requested transfer data amount is
You have to guarantee that you can get out without it. All
If data cannot be transferred on the way, gBs
tStp L cancels transmission of next 16 beats
Can be However, in the middle of 16 beats
You cannot cancel. drive: at the time of address decode bit, gTs L's
Driving starts with the clock that has been asserted.
However, gSlvBsy When L is asserted
Drive until it is negated. In addition,
If you have not been driven yet because Tabas is in use
If gTrStp Confirmed transfer stop request by L
Drive is started by the clock. assert: Drive if the slave is Ready
If the next clock is not Ready, if it is not Ready
Wait until is asserted. gTrStp By L
Response to the transfer stop
Asserted by the clock. negate: after driving
GTrStp If L is asserted, gTrS
tp Asserted at the clock that confirms L. Also,
It is negated after one clock assertion.

G (Slavename) AackOeR
eq (G-Bus AddressAcknowledd
getOutPut EnableRequest):
Slave> DefaultDriverLogic
… Slave is gAack Request to drive L
signal.

G (Slavename) AackOe
L (G-Bus AddressAcknowledg
e OutPut Enable): Default
DriverLogic> Slave ... g (Sla
Venue) Slave that outputs AackOeReq
The default driver logic is gAack L's
A signal indicating that the drive is allowed.

GSlvBsy L, InOut, (G-
Bus Slave Busy): Slave> Mas
ter: Indicates that the slave is driving and transferring data on the data bus. drive: When address decode hits, gTs Drive starts with the clock that confirms L assertion. However,
gSlvBsy When L is asserted, drive until it is negated. assert: the next clock after the drive if the slave is Ready, and Ready if not.
Wait until it asserts. negate: negate at the end of transfer. release: One clock after negation or gT
rStp A clock that has confirmed the transfer stop request by L.

G (Slavename) SlvBsyO
eReq (G-Bus SlaveBusy OutP
out Enable Request): Slave>
DefaultDriverLogic ... Slave is gSlvBsy Request signal for driving L g (Slavename) SlvBsyOe L (G-
Bus SlaveBusy OutPut Enab
le) DefaultDriverLogic> Sla
ve ... g (Slavename) SlvBsyOe
For the slave that outputs Req, the default driver logic is gSlvBsy A signal indicating that L drive is permitted.

GRdNotWr, InOut, (GB
us Read (High) / Write (Lo
w)): Master> Slave: Driven by the master, READ when High, WRITE when LOW
To represent. The driving period is the same as GA. drive: gTs Master drives at the same time as L. assert: The next clock that has been driven. negative: gAack Clock whose L assertion has been confirmed.

G (Mastername) RdNotW
rOeReq (G-Bus Read / Write O
outPut EnableRequests): Maste
r> DefaultDriverLogic ... A request signal for the bus master to drive gRdNotWr.

G (Mastername) RdNotW
rOe L (G-Bus Read / Write Ou
tPut Enable) Default Drive
rLogic> Master ... g (Mastern
ame) For the bus master that outputs RdNotWrOeReq, the default driver logic is gRdNot.
A signal indicating that drive of Wr is permitted.

GBstCnt [1: 0], InOut,
(G-Bus Burst Counter): Mas
ter> Slave... represents the number (1 to 4) of burst transfers that are driven by the master and performed continuously. Table 6 shows the correspondence between the signal value and the number of bytes to be burst-transferred. drive: gTs Master drives at the same time as L. assert: The next clock that has been driven. negative: gAack Clock whose L assertion has been confirmed.

[0133]

[Table 6]

G (Mastername) BstCnt
OeReq (G-Bus Burst Counter
OutPut EnableRequest): Ma
ster> DefaultDriverLogic ...
Request signal for the bus master to drive gBstCnt.

G (Mastername) BstCnt
Oe L (G-Bus BurstCounter O
outPut Enable): DefaultDri
verLogic> Master… g (Maste
rname) The default driver logic is gBstC for the bus master that has output BstCntOeReq.
Signal indicating that drive of nt is permitted.

GBstStp L, InOut, (G-
Bus Burst Stop): Slave> Mas
ter: It is driven by the slave and indicates that the next successive burst transfer cannot be accepted. Assert at the 15th beat of 1 burst (16 beats) transfer. If you do not stop, do not drive. drive: 14th beat. assert: 15th beat. negative: After assertion of one clock, g (Slavenname) BstStpOeReq (G
-Bus BurstStop OutPut Ena
ble Request): Slave> Defaul
tDriverLogic… slave is gBstS
tp Request signal for driving on L.

G (Slavename) BstStpO
e L (G-Bus BurstStop OutPu
t Enable) Default Driver
gic> Slave ... g (Slavename) B
For the slave that outputs stStOeReq, the default driver logic is gBstStp A signal indicating that L drive is permitted.

(Arbitration signal) g (Mast
ername) Req L, Out, (G-Bus R
request): Master> Arbiter ... mass
Is driven by the arbiter and requests the bus from the arbiter.
I do. GReq dedicated for each master device L
Have. assert: Master that needs data transfer is asserted negate: gGnt If receiving L, negate g (Mastername) Gnt L, In, (G-
Bus GNT): Arbiter> Master ...
 Driven by the arbiter, the next
Give the bus right. GGn dedicated for each master device
t Have L. From a high priority bus master
Give the bus right in order. Master of the same priority
On the other hand, the bus right is granted in the order of the bus request. assert: gGnt to other masters L is given
When not available, or given to other masters on next clock
gGnt Arbitration when negating L
Assert for the master selected by. negative: gAack L confirms the assertion of L
Lock gTrStp L, In, (G-Bus Trans
action Stop): Arbiter> Mast
er, Slave ... Driven by arbiter, g
Gnt Address phase already started by L
Abort the transaction. But already gAack
Transa that has started the data phase with L
Action cannot be stopped. Also, this signal is g
Aack L is masked by gAack
When L is asserted, even if it is asserted
Is also negated and output. assert: a traffic that has already started the address phase
Master from a higher priority than the transaction
When a request arrives. negative: gAack L confirms the assertion of L
Lock (G bus write cycle) The G bus write cycle is as follows
become that way. Master requests bus, gReq L assert. Arbiter allowed, gGnt L assert. gReq
L negate. gGnt After receiving L, the master receives gTs L, gAd
Dry dr, gRdNotWr, gBstCnt
Bu. In the case of a write operation, gSlvBsy L is asserted
If not, gData is also driven at the same time.
gSlvBsy If L is driven, gSlv
Bsy Drive after waiting for L to be free. Slave is gTs Add when L is asserted
Decode the address and hit it to transfer to yourself.
Recognize that At this time, gSlvBsy L is another
GSlvBs if not asserted by Reave
y L and gAack Start driving L. Also,
In the case of the mode, gData is also driven. gSlvBs
y If L is asserted by another slave,
Data bus is in use,
Wait until you start driving. gSlvBsy
L, gAack L, (gData) drive start
Later, when the slave is ready for data transfer,
Is asserted to start data transfer. gAack When L is asserted, the address
And the master is gAddr, gRdNotW
Negate r, gBstCnt. Also at that time
The master switches write data every clock, and gBs
Transfer is performed for the amount of data specified by tCnt. Master
And slaves each count their own clock
Must know the end of the data transfer.

If the slave cannot transfer the data transfer amount requested by the master during the transfer, bSt
By asserting Stp_L at the 15th beat, the transfer of the next 16 beats can be canceled.
You cannot cancel in the middle of a beat.

The master and slave are gBstStp
When _L is asserted, data transfer must be terminated at the next clock.

<Cache Validation Unit (CIU)> The cache invalidation unit (CIU) 2005 monitors a write transaction from the B bus to the memory.
Before writing to the memory is completed, the cache validation interface of the CPU shell is used to
The cache built in the U shell is invalidated.

The CPU shell uses the following three types of signals.・ Snoop ADDR [31: 5] (Cache In
validationAddress) DCINV (Dcache (data cache) In
Validation Strobe ICINV (Icache (Instruction Cache) Invalidation Strobe) The invalidation of the cache is performed at a maximum of three clocks. Since the writing from the B bus to the memory does not end in three clocks, the cache validation unit 20 is used.
05 is Stop_ output from the CPU shell 401.
The handshake of the end of invalidation is not performed using the L signal. However, in preparation for future changes, bS on the B bus
drive the noopWait for the same cycle as Stop_L.

In the current implementation, if a write from the B bus occurs, Icache is also invalidated for safety.
If the self-modifying code is prohibited by the OS and the instruction cache is intentionally invalidated when loading data that may be used as an instruction, the invalidation of Icache is not required. In this case, a slight performance improvement can be expected.

<Memory Map> FIGS. 23 and 24 show memory maps. FIG. 23 shows, in order from the left, a virtual memory map, a physical memory map, a memory map in the G bus address space, and a memory map in the B bus address space. FIG. 24 is a map showing 512 Mbytes indicated by hatching in FIG. 23 including registers and the like.

The memory model of the processor core is R300.
0 based. The physical address space of the processor core is 4 Gbytes by 32-bit addressing. The virtual space similarly performs 32-bit addressing. The maximum size of the user process is 2 GB. Address mapping differs between kernel mode and user mode. The figure shows a memory map when the MMU is not used.

(User Mode Virtual Addressing) In user mode virtual addressing, a 2 Gbyte user virtual address space (kuseg) is valid. The address of this user segment is 0x00000000
Starting at zero, all valid accesses have msb cleared to zero. In the user mode, referencing an address in which msb is set causes address error exception handling. The TLB maps all references to kuseg similarly in user mode and kernel mode.
It is also cacheable. Kuseg is usually used to hold user code and data.

(Kernel Mode Virtual Addressing) The kernel mode virtual address space has four address segments.・ Kuseg 2 GB from 0x00000000 of the virtual address. Caching and mapping per page and unit is possible. This segment overlaps with kernel memory access and user memory access. -Kseg0 512 Mbytes from 0x80000000 of the virtual address. Directly mapped to the first 512 Mbytes of physical memory. References are cached, but TLB is not used for address translation. kseg0
Is usually used for kernel executable code and kernel data. -Kseg1 512 Mbytes from 0xA00000000 of the virtual address. Directly mapped to the first 512 Mbytes of physical memory. References are not cached and TLB is not used for address translation. kseg1
Usually depends on the OS, I / O registers, ROM code,
Used for disk buffers. -Kseg2 1 GB from 0xC0000000 of the virtual address. Like the Kuseg, the virtual address is mapped to the physical address by the TLB. Caching is free. The OS normally uses kseg2 for data for each process that needs to be remapped by a stack or a context switch.

(Virtual address memory map (FIG. 23)
(A), FIG. 24 (a))) The virtual address space is 4 Gbytes, and all memories and I / O on the system can be accessed. kuseg has SYSTEM MEMO
RY (1 GB) exists.

The kseg0 has a built-in RAM (16 MB). This is implemented when it is desired to program an exception handling vector, and sets the exception vector base address to 0x80000000. This address is mapped to 0x00000000 in the physical address space.

The kseg1 has a ROM, I / O, and registers. The boot ROM (16 MB), the SBB internal register and the MC internal register (16 MB), and the IOBusI /
O1 (16 MB: Primitive B bus register such as G bus arbiter internal register, B bus arbiter internal register, PMU internal register), IOBus I / O2 (1
6MB), IOBusMEM (16MB), GbusM
EM (32MB), FONTROM (240MB), F
ONTROMorRAM (16 MB) is included.

The kseg2 has a PCI I / O (512M
B), PCI MEM (512 MB) exists.

Since kseg0 and kseg1 are both mapped to the first 512 Mbytes of the physical address space, kseg0, kseg1 and the first 5 bytes of kuseg are used.
All 12 Mbytes refer to the same physical address space.

(Physical address memory map (FIG. 23)
(B), FIG. 24 (b))) The physical address space is also 4 Gbytes like the virtual address space, and all memories and I / O on the system can be accessed.

PCI I / O, PCI MEM, SYS
The TEM MEMORY is the same as the virtual address memory map.

Since both kseg1 and kseg2 are mapped to the first 512 Mbytes of the physical address space, ROM, I / O, and Reg are 0x00000000.
Exists in the space from.

(G bus memory map (FIGS. 23 (c) and 24 (c))) The G bus address space has 4 Gbytes,
SYSTEM MEMORY, GBusMEM, FON
Only T is accessible.

(B bus memory map (FIGS. 23 (d), 24 (d))) The B bus address space has 4 Gbytes,
PCI I / O, PCI MEM, SYSTEMMEM
ORY, IOBusI / O2, IOBusMEM, FO
Only NT can access.

Since IOBus I / O1 is a primitive register, 0x1C000000 to 0x20,000 is used.
The space up to 000 is protected from PCI and cannot be accessed from PCI.

<Address Switch> Address Switch 2
Reference numeral 003 is for transmitting an address signal from the master bus to the slave bus via the SBB 402 in order to transfer data between the SC bus, the G bus, the B bus, and the MC bus. In the transfer via the SBB 402, the bus that can be the master is an SC bus, G
Buses and B buses, and buses that can be slaves are the B bus and MC bus. SC bus, G for MC bus
Either the bus or the B bus becomes the master, and only the SC bus becomes the master to send an address signal to the B bus.

The transfer between the SC bus and the B bus and the transfer between the G bus and the MC bus can be performed simultaneously.

FIG. 25 is a block diagram of the address switch 2003. The switch sequencer 2003a switches the switch 2003b to switch the slave between the B bus and the MC bus, and switches 2003c to switch the master between the SC bus, the G bus, and the B bus.
With this configuration, any one of the SC bus, the G bus, and the B bus becomes the master for the MC bus, and only the SC bus becomes the master for the B bus. Transfer between the bus and the MC bus can be performed simultaneously.

<Data Switch> The data switch is SC
When data is transferred between the bus, the G bus, the B bus, and the MC bus, the data flow is switched within the SBB. Data is sent from the master to the slave during writing, and from the slave to the master during reading.

FIG. 26 is a block diagram of the data switch 2004. In this configuration, the selectors A-1 to A-
3 and B-1 and B-2 are switched as shown in Table 7, so that any one of the SC bus, G bus and B bus is used as a master and any one of the B bus and MC bus is used as a slave to perform writing or reading. Can be controlled to do so.

[0164]

[Table 7]

<Arbitration> The switch sequencer 2003a in the SBB 402 performs arbitration between the following three types of connection requests from outside the SBB when switching each switch. 1. CPU 2. 2. G bus bus master B bus bus master This arbitration is determined by the current bus switch connection status and a preset priority, and as a result, the connection of the address switch and the data switch is switched.

<Timing Diagram> FIGS. 27 to 3
FIG. 2 shows a timing chart. FIG. 27 is a timing diagram of a write / read cycle from the G bus, FIG. 28 is a timing diagram of a burst stop cycle of the G bus, and FIGS.
FIG. 2 is a timing diagram of a G bus transaction stop cycle.

2.6. PCI Bus Interface FIG. 33 is a block diagram of the PCI bus interface 416.

[0168] The PCI bus interface 416
oEngine This is a block that interfaces between the B bus, which is an internal general-purpose IO bus, and the PCI bus, which is an IO bus external to the chip. By setting an input pin, it is possible to switch between a host bridge configuration in which a PCI bus configuration can be issued at the time of reset and a target configuration in which a PCI bus configuration is not issued.

The master DMA controller 3301 of the B bus interface receives DoEn from the PCI bus master via the PCI bus signal interface 3302.
When an access request is made to a resource inside the Gine, the access request is bridged inside the B bus as a B bus master.

Further, the master DMA controller 33
01 is D from the memory mapped on the PCI bus.
DMA transfer to the oEngine Memory can be performed. At this time, the B bus DMA
And the transfer destination address (bPciAddr [31:
0]) and the ID of the PCI master controller 3301
A signal (bPciID) is issued to the B bus and the arbitration sequencer at the same time as the bus request.

The master DMA controller 3301 receives the bus grant (bPciBGnt_L), and when the data transfer is completed by using the bus, the ID signal (bPc
Cancel assertion of iID).

The PCI bus is based on 33 MHz, 32 bits, and PCI 2.1.

2.7. G Bus Arbiter FIG. 34 is a block diagram of the G bus arbiter (GBA) 406.

The arbitration of the G bus is a central arbitration method, and a dedicated request signal (g (mastername) Req is sent to each bus master.
_L) and a grant signal (g (mastername) G
nt_L). In FIG. 34, mastername is M1 to M4. Bus arbiter 406 is G
It supports up to four bus masters on the bus and has the following features. The arbiter can be programmed by setting the register 3401a inside the arbiter. Register setting is performed from the B bus. There are a fair arbitration mode in which all bus masters have the same priority and the bus right is imparted fairly, and a priority arbitration mode in which the priority of one of the bus masters is raised and the bus is used preferentially. Which bus master is given priority is determined by the setting of the register 3401b. • It is possible to set the number of times that the priority bus master can use the bus continuously. -Supports a transaction stop cycle for stopping a transaction that has already started the address phase but has not started the data phase. -Programming of sequential processing in a plurality of bus masters can be performed (described later). The programmed order is stored in the register table 3401a. When the G bus master and the B bus master sequentially write to the same memory address, as a mechanism for maintaining the access order intended by the programmer, a specific master is controlled based on the master ID signal and the stop signal from the synchronization unit. On the other hand, it has a mechanism to suspend giving the bus use permission.

The programming of the register is performed by B
This is performed from the CPU 401 via the bus.

(Arbitration sequencer) Arbitration sequencer 3 which is the core of the G bus arbiter
In 402a and 402b, arbitration by five masters is performed between one priority master and the other four non-priority masters. Request signals and grant signals from the four bus masters are transmitted to a request dispatch circuit 3403.
And the grant dispatch circuit 3404 assigns four non-priority masters, thereby realizing a fair arbitration mode. In addition, by allocating one of the four bus masters to the priority master of the high-priority arbitration sequencer 3402a, it operates in the priority arbitration mode. These assignments are performed according to the settings of the registers 3401a and 3401b. As a result, the priority bus master can acquire the right to use the bus with a higher probability than other masters.

Further, in addition to adjusting the probability of acquiring a bus, the master assigned to the high-priority sequencer 3402a can use the bus continuously, and varies the number of times the master can be used continuously using a programmable register. Can do things. This means that the occupancy of the bus can be adjusted so that a particular master can use more of the bus.

(Fair Arbitration Mode) In this mode, all bus masters have the same priority,
Opportunities to be granted the bus are fair. When the bus is free, the bus master that has issued the request first can get the bus right. When a plurality of bus masters issue requests at the same time, bus rights are sequentially given according to a predetermined order (round robin method). For example, if all the bus masters from M1 to M4 issue requests with the same clock, M1
The bus right is granted in the order of → M2 → M3 → M4. When all bus masters have issued requests again at the end of the transaction of M4, M1 → M2
Bus rights are granted in the same order, such as → M3 → M4 → M1 → M2. If some bus masters are issuing requests, round wrapping from M4 to M1 is given, and a grant is given to the master with the largest number closest to the master that last used the bus.

Once the bus right has been transferred to another bus master, the bus right cannot be obtained again until after all other requesting bus masters have been given the bus right.

(Priority arbitration) In this mode, one bus master (a bus master registered in the register 3401b) becomes a priority bus master having a higher priority than the other bus masters, and the bus right has priority over the other bus masters. Given. All bus masters other than the priority bus master have the same priority.

When a plurality of bus masters have issued requests and the priority bus master makes successive requests, the priority bus master and other non-priority bus masters alternately obtain the bus right.

When the bus right is transferred from the non-priority bus master to another bus master, the bus right cannot be obtained again until after all other requesting bus masters have been given the bus right. .

(Transaction Stop Cycle) In the priority arbitration mode, when the priority bus master issues a request, even if another bus master has already started the address phase, if the data phase has not started, the transaction is stopped. And the priority bus master can get the bus right. However, if the priority bus master has the bus right immediately before that, the number of times that the continuous bus right can be obtained cannot be exceeded.

At the end of the transaction of the priority bus master, if the interrupted bus master has issued a request, the bus right is given priority.

(Switching of Priority Bus Master) To switch the priority bus master, the register 3401b may be rewritten. When the register for selecting the priority bus master is rewritten, the priority bus master is switched after the completion of the transaction being executed at that time. The state of the arbiter returns to the idle state, and the bus master that has issued the request at that time performs the request at the same time, and arbitration is performed again.

Care must be taken when switching the priority bus master. If the priority bus master is switched to a different bus master before the DMA of the bus master to be prioritized ends, the DM of the first priority bus master is changed.
A's priority drops. If it is not desired to lower the priority of the first priority bus master, it is necessary to switch the priority bus master after confirming that the DMA has been completed.

In software that needs to dynamically switch the priority bus master not only at the time of booting the system but also during the operation of the system, the switching of the priority bus master is performed so that a new DMA request is not generated on the G bus once. Of the bus master and the DMA controller, then set an appropriate value in a register in the G bus arbiter 406, and further check the status register in the G bus arbiter 406 to confirm that the priority of the bus master has been switched. After a new G
Access to the bus and activation of DMA should be performed.

The dynamic switching of the priority bus master may change or violate the real-time guarantee of the operating system and the setting of the priority of the task, and must be performed with due consideration.

(Order Processing) FIG. 35 is a diagram illustrating DoEngine
FIG. 4 is a block diagram related to DMA by a bus master on the G bus centering on the G bus 404 in the 400.

When it is necessary for a plurality of bus masters to sequentially perform processing, for example, after processing A on the data in the memory 3501 by the bus master 1, then perform processing B by the bus master 2, and after the processing, A series of processes, such as sending the data to the bus master 4, will be considered.

Software for performing this processing, that is, C
According to the program executed by the PU 401, the order in which the bus master uses the bus, the start condition for granting the bus right, and the end condition are set in the register table 3401a in the bus arbiter 406 via the B bus 405. In this example, bus master: start condition: end condition 1. Bus master 1: gM2BufEmpty: gM1BufReady 2. Bus master 2: gM1BufReady: gM1BufEmpty Bus master 4: gM2BufReady: gM2BufEmpty That is, G bus arbiter 4
06, upon receiving a signal set as a start condition from each bus master, gives the bus master the right to use the bus, and when receiving a signal set as an end condition, deprives the bus master of the right to use the bus.

The software assigns D to each bus master.
Set MA. Thereby, each master requests the G bus arbiter 404 (g (mas)
termname) Req_L). The G bus arbiter 404 gives a bus right to the bus master 1 in the order registered in the register table 3401a (gM1G
nt_L). The bus master 1 reads a certain unit of data from the memory 3501, performs the process A, and
Write data to internal buffer. The bus master 1 notifies the arbiter 40 that the processing of one unit has been completed and the buffer is ready by the gM1BufReady signal.
6 is notified.

The arbiter 406 receives the bus right from the bus master 1 and gives the bus master 2 to the bus master 2 in accordance with the conditions for the bus master to grant the bus right and the conditions for taking the bus right registered in the register table 3401a. The bus master 2 reads the data in the buffer of the bus master 1, performs the process B, and stores the data in the buffer inside the bus master 2. If the buffer of the bus master 1 becomes empty during this time, gM1BufEmpty is asserted and the arbiter 4
06 cancels giving the bus right to the bus master 2. The bus master 2 performs the process B, and notifies that the buffer is ready by the gM2BufReady signal.

The arbiter 406 receives this, and registers
In accordance with the contents of 401a, the bus right is given to the bus master 4 this time. The bus master 4 reads data from the buffer of the bus master 2. When the buffer of the bus master 2 becomes empty, the arbiter 4 is deactivated by gM2BufEmpty.
06, the arbiter 406 receives the notification, gives the bus right again to the bus master 1 according to the contents of the register 3401a, and starts processing the next data.

DM set in each bus master
When A is completed, each bus master notifies the processor by an interrupt. The software knows that a series of processing has been completed when all the bus masters have received the completion notification.

The operation described above is an operation in the complete sequential mode, and a bus master other than the bus master involved in the sequential processing cannot use the bus. Even during this sequential processing, a priority sequential mode is provided to enable a bus master unrelated to the sequential processing to use the bus. Switching between these modes is performed by programming a register inside the arbiter 406. In the priority sequential mode, a bus master performing sequential processing can use the bus preferentially, but a bus master not involved in the sequential processing is permitted to use the bus. Arbitration between a bus master that performs sequential processing and a bus master that is not involved is equivalent to the priority arbitration mode described above. As a matter of course, the bus masters who are not involved in the sequential process and whose turn is not turned because the conditions for granting the bus master are not satisfied are not given the bus master.

(Mechanism for Maintaining Access Order) When the signal stoppc is asserted, the scanner controller / printer controller, which is one of the G bus masters, is excluded from the target of arbitration, and even if the request is asserted, You are not entitled to use it. Arbitration is performed between masters excluding this master. A detailed description will be given in the section on the B bus arbiter.

<Timing Diagram> FIGS. 36 to 3
9, the timing of the G bus arbitration will be described. FIG. 36 shows that the number of times the bus is used continuously is
Fair arbitration mode when all bus masters 1 to 4 are set to 1 (fair mode)
This is an example. The second bus request (issued from timing 4) by the bus master 1 waits until all other bus masters issuing the bus request are processed one by one.

FIG. 37 shows an example of the fair arbitration mode in which the number of times the bus is continuously used is 2 for only the bus master 1 and the other bus masters are set to 1. The second bus request (issued from timing 4) issued by the bus master 1 is granted immediately after the first request, and the other bus masters are kept waiting until the processing is completed.

FIG. 38 shows an example of the priority arbitration mode when the number of times of continuous use of the bus is one each and bus master 1 is set as the priority bus master. Because the priority bus master and the non-priority bus master are alternately granted the right to use the bus, the bus master 1
The second bus request is granted after the bus master 2 uses the bus, and the bus request from the bus master 4 is granted after the bus master 1 uses the second bus. The second bus request from the bus master 2 is acknowledged after all other bus masters issuing the bus request, in FIG. 38, the bus masters 1 and 4 have finished using the bus.

FIG. 39 shows an example in which a bus request from the bus master 1 has been interrupted despite being permitted. In this case, bus master 1
Is completed, the bus request from the bus master 4 is acknowledged in preference to the bus request from the bus master 2.

2.8. B Bus Arbiter FIG. 40 is a block diagram of the B bus arbiter 407.

The B bus arbiter 407 is a DoEngine
Accepts a bus use request of B bus 405, which is an internal IO general bus, and after arbitration, grants use permission to the selected one master, and prohibits two or more masters from accessing the bus at the same time. I do.

The arbitration system has three levels of priorities, and a plurality of masters can be assigned to each priority in a programmable manner. Allocation is maximum, with 3 masters at the highest priority, 7 masters at the middle, and 3 masters at the lowest level.

When the G bus master and the B bus master sequentially write data to the same memory address, as a mechanism for maintaining the access order intended by the programmer, a master ID signal and a stop signal from the synchronization unit are used. Based on this, it has a mechanism to suspend giving a bus use permission to a specific master.

(Arbitration Sequencer) The B bus arbiter has three arbitration sequencers 400.
2,4003,4004. Each has a high priority, a medium priority, and a low priority, and 3, 7, and 3 bus master arbitration sequencers are built in each sequencer. Request signals from units which may become all bus masters on the B bus and grant signals thereto are distributed to these three sequencer units by a request selector and a grant selector. In this distribution, a unique combination can be selected from a plurality of combinations by a software programmable register 4005a in the BBus interface 4005.

For example, by connecting requests of up to seven masters to the middle-priority arbitration sequencer 4003, fair arbitration is realized among the seven masters. Also, by allocating some of the bus masters to the high-priority arbitration sequencer 4002, these masters are more
The right to use the bus can be acquired with a higher probability.
In addition, some requests are sent to the low-priority sequencer 40.
04, the usage rate of these buses can be kept low. Further, in addition to adjusting the probability of acquiring a bus, the master assigned to the high-priority sequencer 4002 can use the bus continuously, and the number of times the bus can be used continuously can be changed by the programmable register 4005a. it can. This means that the occupancy of the bus can be adjusted so that a particular master can use the bus more time.

(Fair Bus Arbitration Method) A method of realizing fair arbitration will be described using the middle-priority sequencer 4003 as an example. All bus masters connected to one sequencer have the same priority, and the opportunity to be granted the bus is fair. When the bus is free,
The bus master that has issued the request first can get the bus right (first come first serve).
When a plurality of bus masters issue requests at the same time, bus rights are sequentially given according to a predetermined order (round-robin at the time of issuing a simultaneous request). For example, if all bus masters from M1 to M7 issue requests with the same clock, M1 → M
The bus right is given in the order of 2 → M3 → M4 → M5 → M6 → M7. When all bus masters have issued requests again at the end of the transaction of M7, M1 → M2 → M3 → M4 → M5 → M6 → M7 → M1
→ The bus right is granted in the same order as in M2. If some bus masters are issuing requests, round wrapping is performed from M7 to M1, and a grant is given to the master having the largest number closest to the master that last used the bus.

(Priority Arbitration) The B bus interface has three arbitration sequencers of high priority, medium priority, and low priority. Arbitration with priorities is realized by selectively allocating a plurality of bus requests to high-priority and low-priority arbiters.

For example, by assigning one master with high priority and assigning the rest with medium priority, one bus master becomes a priority bus master having a higher priority than the other bus masters, and has priority over other bus masters. Bus right is granted. All bus masters assigned to the arbitration sequencer having the same priority have the same priority.

If a plurality of bus masters have issued requests and the priority bus master makes requests continuously, the priority bus master and the other bus masters alternately obtain the bus right. When M3 is the priority master and M1, M2, M3, and M4 keep issuing requests, M3 → M1 → M3 → M2 → M
The right to use the bus is given in the order of 3 → M4 → M3 → M1.

Further, the high-priority bus master can obtain a continuous bus right for a preset number of times in a programmable register in the arbiter. The maximum number of times a continuous bus can be used is four.

When the bus right is transferred from a bus master other than the priority bus master to another bus master, the bus master cannot obtain the bus right again until after all other requesting bus masters have been given the bus right. . When one bus master makes a request continuously, if there is no other requesting bus master, the bus mastership can be obtained continuously, but if another bus master makes a request, that bus master will The bus right can be continuously obtained a predetermined number of times. Once the bus right has been transferred to another bus master, the bus right can be obtained again only after all other requesting bus masters have been given the bus right.

The low-priority arbitration sequencer 40
04 can be assigned a maximum of three requests. The master assigned to the low-priority sequencer 4004 is not given the right to use the bus unless all master requests assigned to the medium-priority and high-priority sequencers are eliminated. The assignment of the bus master to this sequencer must be done with great care.

(Switching of priority bus master) To switch the priority bus master, the register in the arbiter may be rewritten. When the register for selecting the priority bus master is rewritten, the priority bus master is switched after the completion of the transaction being executed at that time.
The state of the arbiter returns to the idle state, and the bus master that has issued the request at that time performs the request at the same time, and arbitration is performed again.

Care must be taken in switching.
If the priority bus master is switched to a different bus master before the DMA of the bus master to be prioritized ends, the priority of the DMA of the first priority bus master decreases. If it is not desired to lower the priority of the first priority bus master, it is necessary to switch the priority bus master after confirming that the DMA has been completed.

In software that needs to dynamically switch the priority bus master not only at the time of booting the system but also during the operation of the system, the switching of the priority bus master is performed as follows.
Once the setting for all bus masters and DMA controllers is stopped so that a new DMA request does not occur on the B bus, an appropriate value is set in a register in the B bus arbiter 407, and a status register in the B bus arbiter is further set. Should be checked to confirm that the priority of the bus master has been switched, and then access to a new B bus and activation of DMA should be performed.

The dynamic switching of the priority bus master may change or violate the real-time guarantee of the operating system and the setting of the task priority.
This must be done with due consideration.

(Access Order Control Mechanism) The B bus arbiter 407 includes an access order control mechanism. The access sequence control mechanism includes a synchronization unit 4001 and a B bus arbiter 4.
07, a bus use right issuance suppression mechanism incorporated in the G bus arbiter 406. B bus arbiter 4
07 operates in the same manner as that of the G bus arbiter. That is, stop
When the Pci signal is input, a bus request is issued from the Pci bus master, and as a result of arbitration, even if the master can be given the right to use the bus, the right to use the bus is not issued. Give the master the right to use the bus. Specifically, when the stopPci signal is input, bPciReq is immediately This is done by masking L.

The bus request from the LAN controller 414 and the stop signal operate in exactly the same manner. FIG. 41 shows a block diagram of the synchronization unit 4001. In the synchronization unit, all the combinations between the plurality of DMA masters are included in the comparison unit 41.
In DoEngine where 01 to 4103 are connected,
The DMA master on Gbus has only a scanner controller / printer controller. On the B bus, DM
There are two units, an APCI unit and a LAN unit.
The B bus interface in the SBB is a bus master on the B bus, but does not directly access the memory, and thus does not output the ID and the transfer destination address to the synchronization unit 4001.

FIG. 42 shows one compare unit (ComparisonUnit 1) in the synchronization unit. Other compare units have the same configuration.

The DMA block attached to the PCI interface 416 or the scanner controller / printer controller sends the synchronization unit 4001
When the DMA write is programmed, a transfer destination address and a request signal unique to the DMA block are notified.

Each of the compare units stores an address together with the current time of a timer provided therein at the time when the request is output from each of the DMA blocks. Next, an address and a request relating to the DMA write are input from another DMA block. At this point, the compare unit compares both addresses. In the case of a match, the times stored in the respective registers are further compared, and the bus arbiter of the bus connected to the DMA block which has issued the DMA write request later in time is strengthened to use the bus for the master. Not give. This is a sto
The bus arbiter of each bus is notified by a signal p (ID).

Each bus arbiter does not assign a bus use right by arbitration to the master notified by the stop (ID) signal.

When the time has elapsed and the DMA write to the relevant memory address has been completed by the bus master that has made the access request first, the previous master withdraws the request to the synchronous unit.
The bus arbiter of the bus connected to the DMA block which issued the A write request is not issued a bus use right permission / prohibition signal to this DMA block. Then, the DMA write of the master to be written later is performed.

When both DMA writes are completed and both requests are withdrawn, the timer is reset. The count up of the timer is performed again when a request from one of the masters is output again.

2.9. Scanner Controller / Printer Controller FIG. 43 is a block diagram of the scanner controller / printer controller and its peripheral circuits. Scanner /
The printer controller controls the scanner and printer,
This is a block that interfaces with the G bus or the B bus. It is composed of the following three functional blocks. 1. Scanner controller The scanner controller is connected to the scanner by a video I / F, and performs operation control and data transfer control. G bus / B bus I / F unit 4
301A is connected by an IF-bus to perform data transfer and register read / write. Data transfer has a master function. 2. Printer controller The printer controller is connected to the printer via a video I / F, and performs operation control and data transfer control. G bus / B bus I / F unit 4
301B is connected by an I / F-bus to perform data transfer and register read / write. Data transfer has both master and slave functions. 3. G bus / B bus I / F unit A unit for connecting the scanner controller 4302 and the printer controller 4303 to the G bus or the B bus. Respectively connected to the scanner controller 4302 and the printer controller 4302 independently,
Connect to G bus and B bus. 4. CP bus A bus for directly connecting image data and a synchronization signal for horizontal and vertical synchronization between the scanner and the printer.

2.9.1. Scanner Controller FIG. 44 is a block diagram of the scanner controller 4302. The scanner controller 4302 has a video I / F
Is a block that connects to a scanner and interfaces with a G bus / B bus I / F unit (scc GBI) 4301A. The G bus / B bus I / F unit (scc GBI) 4301A is interfaced via the scc I / F-bus. It is roughly composed of the following blocks. 1. Scanner device I / F4401 An input / output port for inputting and outputting signals to and from the video I / F of the scanner. 2. Scanner video clock unit 4402 A unit that operates with the video clock of the scanner. 3. Scanner image data FIFO controller 4403 Controls a FIFO for transferring image data. 4. Scanner controller control register unit 4404 Register for controlling the entire scanner controller. 5. IRQ controller 4406 controls an interrupt signal generated inside the scanner controller (Scc). 6. Memory fill mode controller 4405 Controls the mode in which fixed data set in the register is transferred to the memory. Selectively switch to image data from the scanner. 7. FIFO (FIFO_SCC) 4407 This is a FIFO used when outputting a video data from a scanner and a device of an output destination may be asynchronous with the video data.

The type of image data input from the scanner is as follows. RGB 8-bit color multi-valued data 2.8-bit black-and-white multi-value data 3.1-bit black-and-white binary data

Next, the outline of each block constituting the scanner controller will be described.

[1. Outline of Scanner Device I / F] FIG. 45 is a block diagram of the scanner device I / F 4401. The scanner device I / F is an input / output port for inputting and outputting signals to and from the scanner video I / F 4501 of the scanner unit. Input video signal SVVideoR [7: 0], SVide from scanner video I / F
oG [7: 0] and SVVideoB [7: 0] signals are transmitted to the scanner controller control register 440.
4, it is possible to switch whether or not to invert the level according to the VDInvt signal from.

[2. Overview of Scanner Video Clock Unit] FIG.
02 shows a block diagram of FIG. The scanner video clock unit 4402 is a block that operates on the video clock from the scanner. It consists of the following blocks. 1. Scanner video data mask 4601 This block performs data masking on image data from the scanner. The masked data becomes the data of the value set in the register. 2. Scanner video synchronization control unit 4602 Video clock from scanner, VSYNC, HSYNC
This is a block for generating a timing signal for capturing image data and the like from the signal C. The number of lines and the number of lines of image data in the horizontal and vertical directions are managed. 3. Video data width converter This block packs the image data input from the scanner into 64-bit width data and converts the data.

(Overview of Scanner Video Data Mask) FIG. 47 is a block diagram of the scanner video data mask 4601. The scanner video data mask 4601 masks image data input from the scanner in pixel units. The masked image data becomes the value set by the register (RDMask [7: 0], GD
Mask [7: 0], BDMask [7: 0]).

(Outline of Scanner Video Synchronization Control Unit) FIG.
2 shows a block diagram of FIG. The scanner video synchronization control unit 4602 includes a vertical synchronization signal (SVSYNC), a horizontal synchronization signal (SHSYNC), and an image data synchronization clock (GTSV) of image data input from the scanner.
CLK), an enable signal (IVE) of the image data to be captured is generated. In addition, it manages the delay of image data in the main scanning direction, the number of captured pixels, the delay in the sub-scanning direction, and the number of captured lines. Further, the state signal (PEND) at the timing when the capture of the set amount of image data is completed.
P).

The line counter 4801 manages the delay in the sub-scanning direction and the number of fetched lines, and generates a vertical synchronizing signal (EH) of an image reading effective line. A pixel counter 4802 manages an image capture delay in the main scanning direction and the number of captured pixels. A page counter 4803 manages input image data in page units. When image data input for the set number of pages is completed, an end signal (AL
LPEND).

(Scanner Video Data Width Converter 46)
FIG. 49 shows a block diagram of the scanner video data width converter 4603. This is a unit for arranging image data input from the scanner in a 64-bit width. The arranged data is written to the FIFO as 64-bit data. The type of image data that can be input is R
There are three types of color image data of 8 bits each for GB, 8-bit monochrome image data of multi-valued, and binary 1-bit monochrome image data. Scanner controller control register 4
At 404, the mode is set. The mode is R
There is a mode in which GB color image data can be arranged in the memory in 24 bits, and a mode in which 1 byte is added and arranged in 32 bits. The three types of image data are input from the following signal lines. 1. RGB 8-bit color image data… R
[7: 0], G [7: 0], B [7: 0] Multi-valued 8-bit monochrome image data ... R [7:
0] 3.2 1-bit black-and-white image data... R7 64-bit data and memory arrangement are as follows.

[0237] 1. 8-bit color image data for each of RGB (24-bit storage mode) First pixel R8 bit → bit 63-56 First pixel G8 bit → bit 55-48 First pixel B8 bit → bit 47-40 Second pixel R8 bit → Bit 39-32 second pixel G8 bit → bit 31-24 second pixel B8 bit → bit 23-16 third pixel R8 bit → bit 15-8 third pixel G8 bit → bit 7-0 , As shown in FIG.

[0238] 2. RGB 8 bit color image data (32 bit storage mode) First pixel R8 bit → bit 63-56 First pixel G8 bit → bit 55-48 First pixel B8 bit → bit 47-40 Second pixel R8 bit → Bit 31-24 second pixel G8 bit → bit 23-16 second pixel B8 bit → bit 15-8 The arrangement on the memory is as shown in FIG.

[0239] 3. Multi-valued 8-bit monochrome image data First pixel 8 bits → bits 63-56 Second pixel 8 bits → bits 55-48 Third pixel 8 bits → bit 47-40 Fourth pixel 8 bits → bits 39-32 fifth Pixel 8 bits → bits 31-24 6th pixel 8 bits → bits 23-16 7th pixel 8 bits → bit 15-8 8th pixel 8 bits → bit 7-0 As shown in FIG. is there.

4.2 1-bit binary black and white image data 1st pixel 1 bit → bit 63 2nd pixel 1 bit → bit 62 3rd pixel 1 bit → bit 61 4th pixel 1 bit → bit 60 61st pixel 1 bit → bit 3 1 bit of the 62nd pixel → bit 2 1 bit of the 63rd pixel → bit 1 1 bit of the 64th pixel → bit 0 The arrangement on the memory is as shown in FIG.

Next, each packing unit will be described.

FIG. 54 shows a BW8 packing unit 49.
FIG. 11 is a timing chart when converting multi-valued 8-bit black and white image data into a 64-bit width in accordance with No. 01. The 8-bit black-and-white image data R [7: 0] from the scanner is captured when the signal VE goes high, and the signal L is output pixel by pixel.
The data is latched by a 64-bit latch in synchronization with P0 to LP7. When eight pixels are completed, the latched eight pixels of 64 bits are output as a signal BW8 [63: 0] in synchronization with the signal LP64.

FIG. 55 is a timing chart of image data input when converting binary black and white image data into a 64-bit width by shift register 4902. The binary black-and-white image data R7 (SVIDEOR0) from the scanner is supplied to a signal VE.
Becomes high level, is shifted by a shift register one bit at a time, and 64 bits are taken. The signal BW1 is synchronized with the signal SVLATCH64.
[63: 0] is output.

FIG. 56 shows an RGB packing unit 49.
FIG. 3 is a timing chart at the time of converting image data of 8 bits (24 bits in total) of RGB into a 64-bit width. FIG. 57 shows the RGB packing unit 490.
3 is a block diagram of FIG. In the figure, image data R [7: input from a scanner video data mask 4601:
0], G [7: 0], and B [7: 0] are input to the 24-bit data latches 5701A and 5701B. The data latches A and B latch 24-bit data that are respectively input in synchronization with latch signals LP0 and LPI that are obtained by dividing the clock CLK by half and that have opposite phases. The data latched by the data latches 5701A and 5701A is 48 → 3
The 2-bit data selector 5702 supplies the input signal RGBHT
[47: 0], and a 2-bit selection signal LP
In response to [3: 2], a 32-bit signal DATA [31:
0]. There are three ways of outputting according to the value of the selection signal. First, the input signal RGBH
In this method, T [47:16] is used as an output signal DATA [31: 0]. Second, the input signal RGBHT [1
5: 0] is output signal DATA [31:16], and input signal RGBHT [47:32] is output signal DATA [1].
5: 0]. Third, the input signal RG
In this method, BHT [31: 0] is used as an output signal DATA [31: 0].

The data latches 5701A and 5701A alternately latch 24-bit image data in synchronization with the latch signal, and sequentially switch the above three selection methods.
The output from the data selector 5702 is data obtained by combining 24-bit / pixel data into 32 bits.
However, after the data of the selector 5702 is selected by the third method, both data of the two pixels input to the data selector must be updated. Therefore, as shown in FIG. 56, the selection signal SELUL
[3: 2] is delayed by one clock.

As described above, the data selector 5702 uses 32
Once converted to the bit width, the data latch 57
40A and 40B alternately latch data latch 5704
At the timing when the content of B is updated, that is, at the timing when the latch signal SELUL1 becomes high level, it is output as data converted into a 64-bit width.

[3. Outline of Scanner Image Data Transfer FIFO Controller 4403] FIG. 58 is a block diagram of the scanner image data transfer FIFO controller 4403. This block includes a FIFO 5801 as a buffer for transferring image data input from the scanner via the G bus or the B bus, and the FIFO 581.
01. FI
FO has a capacity of 512 bytes (64 bits x 64)
FIFO. The data output from the FIFO is sent to the scanner FIFO write / read arbiter 5802 by the FIFO
It controls while monitoring the empty flag (EF) of 5801. Data input to the FIFO is performed by a request signal (WREQ) from the scanner video clock unit 4402.

[4. Outline of Scanner Controller Control Register 4404] FIG. 59 is a block diagram of the scanner controller control register 4404. This block has a register for controlling the inside of the scanner controller. The internal registers are as follows. 1. 1. Scanner controller power management control register 2. Scanner controller / control register Scanner controller interrupt factor status register 4. 4. Scanner / controller / interrupt factor mask register 5. Scanner sub-scanning mask line number setting register 6. Scanner main scanning mask pixel number setting register 7. Scanner sub-scanning line number setting register 8. Scanner sub-scan line number counter read register 9. Scanner sub-scanning pixel number setting register 10. Scanner main scanning pixel number counter readout register Scan page number setting register 12. 12. Scan page number counter read register Scanner device control register 14. Scanner device status register 15. Scanner video mask data register 16. Memory fill data register [5. Outline of IRQ Controller 4406] FIG.
A block diagram of the IRQ controller 4406 is shown. This block manages interrupt signals generated in the scanner controller. There are the following interrupt generation factors. 1. Complete input of image data for the set page (AL
LEND) 2. Complete input of image data for page (PageEn)
d) 3. The rising edge of the SPRDY signal from the scanner (fa
3. 1se → true) (INSPRDY) Falling of the SPRDY signal from the scanner (tr
4. ue → false) (INSPRDY) The rising edge of the SVSYNC signal from the scanner (f
5. true → true) (INSVSYNC) The falling edge of the SVSYNC signal from the scanner (t
6. true → false) (INSVSYNC) 7. Rise of EMPTY signal of image data FIFO (false → true) (EMPTY) 8. Fall (true → false) of EMPTY signal of image data FIFO (EMPTY) 9. Rise (false → true) of a FULL signal of image data FIFO (FULL) 10. Fall (true → false) of FULL signal of image data FIFO (FULL) Overwriting occurs in the image data FIFO (F
OW) Flag information (SCIRQ) corresponding to the above interrupt factor
[31:21]) to the scanner controller control register 4406. From the scanner controller control register 4406, a mask bit (SCIMask [31:21]) and a clear signal (SCICLRP [31:21]) for each interrupt cause are input. The logical sum of each interrupt factor is output to intScc.

[6. Memory fill mode controller 4
Outline of 405] FIG. 61 is a block diagram of the memory fill mode controller 4405. This block controls a mode in which fixed data set in the register is transferred to the memory via the GBI. This mode is set to Memf
This is performed by an ill signal. When the fixed data transfer mode is specified, the data output to the sccGBI is the data set in the register (MFData [3
1: 0]). A timing signal (sccWrite) for transferring data to the sccGBI is generated in this block.

(SccIF-Bus) The sccIF-bus is a local bus connecting the G bus / B bus I / F unit 4301A and the scanner controller 4302. The signals contained in this bus are as follows. The input / output of the signal is a signal output from the scanner controller to the G bus / B bus I / F unit (GBI) OUT, and a G bus / B bus I / F unit (GBI).
Is input to the scanner controller from IN. Since the IF-bus has the same definition for the scanner controller and the printer controller, signals for functions not supported by the scanner controller are also described. The basic clock uses Bclk of the B bus.・ SccRst0 L: IN By this signal, the FIFO inside the scanner controller
To the initial state. • sccDataOut [63: 0]: OUT This is a 64-bit data bus output from the scanner controller to the G bus / B bus I / F unit (GBI). Image data is transferred when the scanner controller performs a data transfer operation. • sccWrite: OUT G when the scanner controller performs data transfer operation.
This is a write signal to the bus / B bus I / F unit (GBI). G bus / B bus I / F unit is sccWr
At the rising edge of Bclk in which the item signal is asserted, sccDataOut [63: 0] is fetched. s
By continuing to assert the ccWrite signal, data can be written in units of one clock. -SccWriteEnable: G when the scanner controller performs data transfer operation.
This is a write signal to the bus / B bus I / F unit (GBI). It is output from the G bus / B bus I / F unit (GBI). At the rising edge of Bclk, sccWrit
If the eEnable signal is asserted, it indicates that writing is possible at the next rising edge of the clock. s
The assertion of the ccWrite signal is sccWriteE
This is performed after confirming the enable signal. SccRegAddr [31: 2]: A register address bus for accessing a register inside the scanner controller from the ING bus / B bus I / F unit (GBI). sccRegStart L
It becomes effective at the same time as assertion. If it is access to the scanner controller internal register, sccRegAck
It is effective until responding with the L signal. -SccRegbyteEn [3: 0]: Byte enable signal of sccRegDataIn [31: 0] output from the ING bus / B bus I / F unit (GBI). sccRegStart Valid at the same time as L assertion, sccRegAck It is effective until responding with the L signal. Only valid bytes indicated by this signal are written to the register. When reading from the internal register, this signal is ignored and all bytes are output. Each bit of this signal and sccRegDataIn
The correspondence with the byte of [31: 0] is as follows. ・ SccRegStart L: an access request signal for accessing a register inside the scanner controller from the ING bus / B bus I / F unit (GBI). “Low” indicates a register access request. sccRegAddr [31: 2] signal, s
Asserted with the ccRegRdNotWr signal,
Asserted for one Bclk clock. The scanner controller determines that sccRegAc for this access
k Unless L is returned, the next access is not asserted. • sccRegDataOut “31: 0”: OUT This is a 32-bit data bus for read access to the register inside the scanner controller from the G bus / B bus I / F unit (GBI).
It is valid when the L signal is asserted. • sccRegDataIn [31: 0]: This is a 32-bit data bus in the case where a register inside the scanner controller is write-accessed from the ING bus / B bus I / F unit (GBI). sccRegStar
t It becomes effective at the same time as the assertion of L. If it is an access to the internal register of the scanner controller, sccAck
It is effective until responding with the L signal. SccRegRdNotWr: a signal indicating the access direction (read or write) when accessing a register in the scanner controller from the ING bus / B bus I / F unit (GBI). "
When “High”, the contents of the register in the scanner controller are read out to sccRegDataOut [31: 0], and when “Low”, sccRegDataIn [31:
0] is written to the scanner controller internal register. sccRegStart It becomes effective at the same time as L assertion, and if it is an access to the scanner controller internal register, sccRegAck It is effective until responding with the L signal.・ SccRegAck L: OUT is a signal indicating that register access inside the scanner controller has been completed. G from scanner controller
Output to the bus / B bus I / F unit (GBI).
Asserted for one Bclk clock. sccRe
gReq The L signal is sensed from the next clock after the assertion.

The signal sccRst1 L, scc byte En [7: 0], sccRead, sccData
In [63: 0] is included in the IF bus,
Not used by the scanner controller.

FIGS. 62 and 63 are timing diagrams showing an example of the timing of the above-mentioned signals. FIG.
2 is timing when data is read from the scanner controller 4302 and DMA-transferred.
This is the timing for reading or writing to the internal register of the scanner controller 4302.

(Power Management) Inside the scanner controller, the scanner controller power management control register (0X1B00500)
The gate control of the video clock (SVCLK) according to the setting of 0) is performed, thereby performing power management. Power management unit (PMU) 4
09 output to the PM state signal (sccPmStat)
[1: 0]) is the G bus / B bus I / F unit 4
SccDmaPmState input from 301A
The state of [1: 0] and the state of the clock are determined together. SccPmState [1: 0] is as shown in FIG.

In FIG. 64, sccDmaPmSta
te [1: 0] is the G bus / B bus interface GBI of the scanner The power consumption state of scc is shown. GBI In the second, 4 of power consumption states 00 to 11
There are stages. This state signal sccDmaPmState
[1: 0] is output from GBI_scc to the scanner controller.

The power consumption of the scanner controller has two stages and is indicated by an internal signal SPStat.

The signal sccPmstate "1: 0" is
A state in which the two states of GBI_scc and the scanner controller are combined is shown. This signal is output to the power management unit of the system. That is, the power consumption state of the scanner controller is transmitted to the power management unit in four stages. The stage is the signal sc
It is indicated by the value of cPmstate [1: 0]. The value 00 is the lowest level, and the power consumption indicated by one increase increases.

(Scanner Controller Core Interface) FIG. 65 is a diagram summarizing signals input and output between the core portion including the above-described blocks in the scanner controller 4302 and an external bus or scanner. As described above, the scanner controller 4302 is connected to the system bus bridge 402 by the G bus, is connected to the IO device, the power management device, and the system bus bridge by the B bus, and is connected to the printer controller by the CP bus. They are connected by a bus, and are connected to the G bus / B bus I / F unit by an I / F bus.

2.9.2. Printer Controller FIG. 66 is a block diagram of the printer controller 4303. The printer controller is a block that is connected to a printer by a video I / F and interfaces with a G bus / B bus I / F unit. It is roughly composed of the following blocks. 1. Printer device I / F6601 Printer video I / F and optional controller I
/ F is an input / output port for inputting and outputting signals to / F. 2. Printer video clock unit 6602 This unit operates with the video clock of the printer. 3. Printer image data FIFO controller 6603 controls a FIFO for transferring image data. 4. Printer controller control register unit 6604 This is a register unit for controlling the entire printer controller. 5. IRQ controller 6605 controls an interrupt signal generated inside the printer controller (Prc). 6. Printer command / status control unit 6606 Controls command / status transmission and reception with the printer via the video I / F. 7. Optional controller control unit 66
07 This unit controls the printer option controller. 8. FIFO (FIFO PRC) 6608 This is a FIFO used when the printer may be asynchronous with the video data when outputting the video data to the printer.

The following five types of image data are output to the printer. 1. RGB 8-bit color multi-value data (dot sequential) 2. 8-bit black-and-white multi-value data 3. 1-bit black-and-white binary data 4. 4. CMYK 1-bit color data (surface-sequential) Next, an outline of each block constituting the printer controller will be described.

[1. Outline of Printer Device I / F] FIG. 67 is a block diagram of the printer device I / F 6601. This block is an input / output port for inputting and outputting signals from the printer video I / F and the optional controller I / F. P video R [7: 0], P video B
For each signal of [7: 0], it is possible to switch whether or not the level of the output signal is inverted by the VDInvt signal.

[2. Overview of Printer Video Clock Unit] FIG. 68 shows a printer video clock unit 660.
2 shows a block diagram of FIG. This block operates on the video clock from the printer and is composed of the following blocks. 1. Printer video data mask 6801 (DFF8E
NMask) A block that performs data masking on image data to be sent to the printer. The masked data becomes the data of the value set in the register. 2. Printer video synchronization control unit 6802
(Prc_sync unit) A block that generates a timing signal for outputting image data from a video clock, VSYNC, and HSYNC signals from a printer. The number of lines and the number of lines of image data in the horizontal and vertical directions are managed. 3. Printer video data width converter 6803 (pv
dwconv) Depending on the mode, image data transmitted from the IF bus in a 64-bit width is converted to RGB 24 bits,
A block that converts the data into 8-bit black and white and 1-bit black and white data. The mode is set by a register.

(Printer Video Data Mask) FIG. 69 shows a block diagram of the printer video data mask 6801. This block masks image data to be output to a printer in pixel units. The masked image data becomes the value set in the register (RDMas
k [7: 0], GDMask [7: 0], BDMask
[7: 0]).

(Printer Video Synchronization Control Unit) FIG. 70 is a block diagram of the printer video synchronization control unit 6802. This block is composed of a vertical synchronization signal (TOP), a horizontal synchronization signal (INPHSYNC), and an image data synchronization clock (GTVCLK) of image data to be output to a printer, an enable signal (VDOEN) of image data to be output, and a printer image data transfer FIFO. A signal (RREQ) for requesting data to the controller 6603 is generated.

In addition, the delay of image data in the main scanning direction, the number of captured pixels, the delay in the sub-scanning direction, and the number of captured lines are managed. The line counter 7001 outputs a state signal (PEN) at the timing when the output of the set amount of image data is completed.
DP). In addition, a delay in the sub-scanning direction and the number of output lines are managed to generate a vertical synchronization signal (EH) of an image output effective line. A pixel counter 7002 manages an image output delay in the main scanning direction and the number of output pixels. A page counter 7003 manages output image data in page units. When the image data output for the set number of pages is completed, an end signal (ALLPEND) is generated.

(Printer Video Data Width Converter) FIG. 71 shows a block diagram of the video data width converter 6803. This block is a GBI (G bus / B bus I /
This unit converts 64-bit data input from F) into image data format. The following three types of image data can be output. RGB 8-bit color image data, multi-valued 8-bit monochrome image data, and binary 1-bit monochrome image data. The 8-bit RGB color image data is stored in the memory in 24-bit units (24-bit mode), and the 1-byte data is added to 24 bits and stored in the memory in 32-bit units ( (32-bit mode). This mode is set in the printer controller control register 6604.
The three types of image data are output to the following signal lines. 1. RGB 8-bit color image data ... IR
[7: 0], IG [7: 0], IB [7: 0] Multi-valued 8-bit monochrome image data ... IR [7:
0] 3.2 binary 1-bit black and white image data... The manner in which IR7 64-bit data is arranged on the memory is as follows.

[0266] 1. RGB color image data of 8 bits each (24-bit mode) First pixel R8 bit → bit 63-56 First pixel G8 bit → bit 55-48 First pixel B8 bit → bit 47-40 Second pixel R8 bit → bit 39-32 Second pixel G8 bit → bit 31-24 Second pixel B8 bit → bit 23-16 Third pixel R8 bit → bit 15-8 Third pixel G8 bit → bit 7-0 In this case, The arrangement is as shown in FIG.

[0267] 2. RGB color image data of 8 bits each (32-bit mode) First pixel R8 bit → bit 63-56 First pixel G8 bit → bit 55-48 First pixel B8 bit → bit 47-40 Second pixel R8 bit → bit 31-24 Second pixel G8 bit → bit 23-16 Second pixel B8 bit → bit 15-8 In this case, the arrangement on the memory is as shown in FIG.

[0268] 3. Multi-valued 8-bit monochrome image data First pixel 8 bits → bit 63-56 Second pixel 8 bits → bit 55-48 Third pixel 8 bits → bit 47-40 Fourth pixel 8 bits → bit 39-32 fifth Pixel 8 bit → bit 31-24 6th pixel 8 bit → bit 23-16 7th pixel 8 bit → bit 15-8 8th pixel 8 bit → bit 7-0 In this case, the arrangement on the memory is shown in FIG. It is as shown in.

4.2 1-bit monochrome image data 1st pixel 1 bit → bit 63 2nd pixel 1 bit → bit 62 3rd pixel 1 bit → bit 61 4th pixel 1 bit → bit 60 60th pixel 1 bit → bit 4 1st pixel 1 bit → bit 3 62nd pixel 1 bit → bit 2 63rd pixel 1 bit → bit 1 64th pixel 1 bit → bit 0 In this case, the arrangement on the memory is shown in FIG. It becomes street.

Next, the blocks constituting the printer video data width converter will be described.

(RGBOut Unit 7101) FIG. 76
The block diagram of the RGBout unit 7101 is shown in FIG.
This block is a unit for converting 64-bit data packed in the 24-bit mode into 8-bit RGB color image data.

[3. Overview of Printer Image Data Transfer FIFO Controller] FIG.
A block diagram of the IFO controller 6603 is shown. This block converts the image data to be output to the printer into a GBI
(G bus / B bus I / F) to receive a FIFO as a buffer for transferring data and a circuit for controlling the FIFO. Capacity 512 bytes (64 bits x 6
4) FIFO7701 is provided. FIFO data input is performed by the printer FIFO write / read arbiter 7702.
Controls while monitoring the full flag (FF) of the FIFO7701. Data output from the FIFO is performed by a request signal (RREQ) from the printer video clock unit 6602.

[4. Printer Controller Control Register Unit] FIG. 78 is a block diagram of the printer controller control register 6604. This block has a register for controlling the inside of the printer controller. The internal registers are as follows. 1. 1. Printer power management control register 2. Printer controller control register 3. Printer controller interrupt factor status register 4. Printer controller interrupt factor mask register 5. Printer sub-scanning mask line number setting register 6. Printer main scan mask pixel number setting register 7. Printer sub-scanning line number setting register 8. Printer sub-scanning line number counter read register Printer main scanning pixel number setting register 10. 10. Printer main scan pixel number counter read register Print page number setting register 12. 12. Print page number counter read register Printer device control register 14. 14. Printer device status register Printer serial command register 16. Printer serial status register 17. Option, controller, TX, register 18． Option controller, RX, register 19． Printer video mask data register 20.4 Grayscale output level setting register 21.16 Grayscale output level setting register 1 22.16 Grayscale output level setting register 2 23.16 Grayscale output level setting register 3 24.16 Grayscale output level setting register 4 [5. IRQ controller] FIGS. 79 and 80 show the IRQ
A block diagram of a controller 6605 is shown. This block manages an interrupt signal generated in the printer controller. An interrupt is generated from the interrupt source. It has a mask function for each interrupt factor and can be cleared individually. The interrupt factors are as follows. 1. 1. End of image data transfer all pages (ALLPEnd) 2. One page of image data transfer ends (PageEnd) Serial status 1 byte reception completed (INPSB
SY) 4. 1-byte serial command transmission completed (EndCBS
Y) 5. PPRDY signal rise (hlse → true)
(INPPRDY) 6. PPRDY signal falling true → false)
(IMPPRDY) 7. RDY signal rising (false → true)
(INRDY) 8. RDY signal falling (true → false)
(INRDY) 9. PFED signal rise (false → true)
(INPFED) 10. Fall of PFED signal (true → falses)
e) (INPFED) SPCHG signal rising (false → true)
e) (INSPCHG) 12. SPCHG signal falling (true → falses)
e) (INSPCHG) 13. PDLV signal rise (false → tru
e) (INPDLV) 14. PDLV signal fall (true → falses)
e) (INPDLV) 15. TOPR signal rise (false → tru
e) (INTOPR) 16. Fall of TOPR signal (true → falses)
e) (INTOPR) CCRT signal rising (false → tru
e) (INCCRT) CCRT signal fall (true → falses)
e) (INCCRT) VSREQ signal rise (false → tru
e) (INPVSYNC) 20. VSREQ signal falling (true → falses)
e) (INPVSYNC) 21. 22. Completion of option controller TX transmission and RX reception 23. Rising edge of EMPTY signal of image data transfer FIFO 23. Fall of the EMPTY signal of the image data transfer FIFO 25. Rise of FULL signal of image data transfer FIFO 25. Fall of FULL signal of image data transfer FIFO Overread occurs in the image data transfer FIFO (EARDOut) Flag information (PCIRQ
[31: 6]) to the printer controller control register 6604. From the printer controller control register 6604, a mask bit (PCIMask [31: 6]) and a clear signal (PCICLRP [31: 6]) for each interrupt cause are input.
The logical sum of each interrupt factor is output to intPrc.

[6. Printer Command / Status Control Unit] FIG. 81 is a block diagram of the printer command / status control unit 6606. This block is for transmitting and receiving a serial command / status for controlling the printer.

As the serial command, an INPCBSY signal indicating a period during which the command is transmitted, an INPCCLK signal which is a synchronous clock of the serial command,
A serial command INPSRCMD signal is generated.

As the serial status, the INPSBSY signal indicating the period during which the status is transmitted and the serial status INPSRSTS signal are input, and
It outputs bit status PSRSTAT [7: 0]. As the synchronous clock for inputting the serial status, either the INPPCLK signal output from the printer or the PCCLK signal generated by this block can be selected. The selection is made by the PSRCLKMode signal.

[7. Option Controller Control Unit] FIG. 82 is a block diagram of the option controller control unit 6607. This block is a unit that outputs transmission data (TX) to the option controller. INSTROBE signal, INCKEN signal, CLK for TX transmission
(OPCLK) signal is generated. Also, reception data (RX) is received simultaneously with TX transmission.

(PrcIF-bus) prcIF-bus
Is the G bus / B bus I / F unit 4301B and
With a local bus connecting the
is there. The signals contained on this bus include:
You. In addition, the input and output of the signal from the printer controller
Signal output to G bus / B bus I / F unit (GBI)
Signal OUT, G bus / B bus I / F unit (GBI)
Signal input to printer controller from
You. The IF-bus connects the scanner controller and printer
Printer controller,
Signals for functions not supported by Laura are also described.
The basic clock uses Bclk of the B bus.・ PrcRst0 L: IN By this signal, the FIFO inside the printer controller
To the initial state.・ PrcDataIn [63: 0]: Printer from ING bus / B bus I / F unit (GBI)
A 64-bit data bus output to the controller.
You. When the printer controller operates data transfer
Image data is transferred. • prcRead: OUT When the printer controller performs data transfer operation, the G bus
Read signal from the bus / B bus I / F unit (GBI)
issue. G bus / B bus I / F unit (GBI) is pr
Start of Bclk where cRead signal is asserted
PrcDataIn [63: 0] is valid for the beam
And Keep asserting the prcRead signal
Thus, data can be read in units of one clock. • rcReadEnable: IN When the printer controller performs data transfer operation, G bus / B
Data read permission from bus I / F unit (GBI)
Signal. G bus / B bus I / F unit (GBI)
Output from At the rise of Bclk, prcRe
If the adEnable signal is asserted, the next
It indicates that reading is possible at the rise of the lock.
The assertion of the prcRead signal is based on the prcReadEn
This is performed after confirming the “able” signal. • prcRegAddr [31: 2]: Printer from ING bus / B bus I / F unit (GBI)
When accessing the register inside the controller,
Star address bus. prcRegStart L Asser
Enabled at the same time as the
PrcRegAck L Shin
It is valid until you respond with a number. • prcRegbyteEn [3: 0]: output from the ING bus / B bus I / F unit (GBI)
Byte rice of prcRegDataIn [31: 0]
Cable signal. prcRegStart Simultaneous with assert
Becomes effective, and prcRegAck Respond with L signal
Valid up to. Only valid bytes indicated by this signal
Write to the register. Read from internal register
At the time of output, this signal is ignored and all bytes are output. this
Each bit of the signal and prcRegDataIn [31:
[0] The correspondence with the cut bytes is as follows.・ PrcRegStart L: Printer from ING bus / B bus I / F unit (GBI)
When accessing registers inside the controller,
Access request signal. Register access request at "Low"
Show. prcRegAddr [31: 2] signal, prc
Asserted with RegRdNotWr signal, Bc
Asserted for lk1 clocks. Printer controller
Laura checks for a prcRegAck for this access
Unless it returns L, the next access will not be asserted.
No. -PrcRegDataOut [31: 0]: OU
TG bus / B bus I / F unit (GBI) to printer
For read access to the register inside the controller
32-bit data bus. prcRegAck L signal
Valid when asserted. • prcRegDataIn [31: 0]: Printer from ING bus / B bus I / F unit (GBI)
When writing to the register inside the controller
32-bit data bus. prcRegStart L
Valid at the same time as assertion,
PrcRegAck for access to the external register
It is effective until responding with the L signal. -PrcRegRdNotWr: Printer from ING bus / B bus I / F unit (GBI)
When accessing registers inside the controller,
Signal indicating the access direction (read or write). "Hig
h ”sets the contents of the printer controller internal register to pr
Read to cRegDataOut [31: 0],
Low "in prcRegDataIn [31: 0]
Is written to the internal register of the printer controller.
You. PrcRegStart Valid at the same time as L assert
Access to the printer controller internal registers.
PrcRegAck Until responding with L signal
Is effective in・ PrcRegAck L: OUT The register access inside the printer controller is completed.
Signal indicating that From printer controller to G bus /
Output to the B bus I / F unit (GBI). BCl
Asserted for k1 clocks. prcRegst
art The next clock after the L signal is asserted
Is performed.

The signal prcReq0 L, prc byte En [7: 0], prcWrite, prcDat
aOut [63: 0], prcReadEnable
Is unused in the printer controller.

FIGS. 83 and 84 are timing diagrams showing an example of the timing of the above-mentioned signals. FIG.
Reference numeral 3 denotes timing when data is DMA-transferred to the printer controller 4303, and FIG.

(Power Management) Inside the printer controller, the printer controller power management control register (0X1B000007)
The gate control of the video clock (VCLK) according to the setting of 0) is performed, thereby performing power management. Power management unit (PMU) 40
9 output to the PM state signal (prcPmStat)
[1: 0]) is the G bus / B bus I / F unit 4
PrcDmaPmState input from 301B
The state is determined by combining the [1: 0] state and the clock state. prcPmState [1: 0] is as shown in FIG.

In FIG. 85, prcDmaPmSta
te [1: 0] is the G bus / B bus interface GBI of the printer The power consumption state of prc is shown. GBI In prc, 4 of power consumption states 00 to 11
There are stages. This state signal prcDmaPmState
[1: 0] is GBI prc is output to the printer controller.

The power consumption state of the printer controller has two stages and is indicated by an internal signal PPStat.

The signal prcPmstate [1: 0] is
GBI A state in which the two states of the prc and the printer controller are combined is shown. This signal is output to the power management unit of the system. That is, the power consumption state of the printer controller is transmitted to the power management unit in four stages. The stage is the signal pr
It is indicated by the value of cPmstate [1: 0]. The value 00 is the lowest level, and the power consumption indicated by one increase increases.

2.9.3 G Bus / B Bus I / F Unit (GBI) FIG. 92 is a block diagram of the G bus / B bus I / F unit 4301. The G bus / B bus I / F unit is provided for each of the scanner and the printer, but since their configurations are the same, they will be described together here.

In FIG. 92, GBI4301 is GBI
and a BBus controller connected to the Bus and controlling the same, and a BBus controller connected to the Bbus and controlling the same. These units include a DMA controller 9205 for controlling a DMA address, a FIFO 9204 used for data transfer between the functional block and the GBus / BBus, and a register unit 9206 in which various set values are written. Of these, GBUS
The controller and the FIFO 9204 operate at a clock of 100 MHz according to the G bus, and the other blocks operate at 50 MHz according to the B bus.

The GBI 4301 is a functional block (SCC: scanner controller and PRC: printer controller) to be connected to both the G bus and the B bus.
It provides a selective connection between Bus and BBus and an interface of both buses. Between GBI and each functional block,
They are connected by IFBus 9201. In the function block,
There is no need to be aware of whether the data input / output destination is GBus or BBus. Also, since DMA is supported on the GBI side, there is no need to generate addresses on the functional block side.
The GBI is a unit in which functions required in common in each functional block are grouped into an independent unit.

IFBus 9201 supported by GBI
The functional blocks connected to receive or send continuous data. The IFBus does not include an address signal. In GBI, Channel1
0 (GBus / BBuS → IFBus0) and Chann
Two channels, e11 (GBus / BBus → IFBus1), are prepared, and a DMA controller is prepared for each of them. However, only the channel 0 is used (implemented) in the scanner controller and only the channel 1 is used in the printer controller.

The DMA controller 9205 has an I / O
(Fixed address) and memory can be set. In the case of a memory, a continuous physical address and a DMA of a chain table system (described later) can be set.

The GBI inputs and outputs data to and from the functional blocks via the FIFO. Therefore, when the GBI operates in the slave mode, the address of the GBI is G
Bus side is 0x18n0 0000-0x18n0
007F, BBus side is 0x19n0 0000-0
x19n0 Only 001F accesses the same location. Since the FIFO is used, it is difficult to cope with wrap-around during burst transfer. BB
For a burst transfer request involving wrap-around of us, a response is made as a single access. It does not respond to the transfer request with the wraparound of the GBus.

In the case of performing DMA transfer of image data between GBIs, control is performed by each DMA controller. At this time, it is not particularly determined which side becomes the master, but it is desirable that the data transfer timing be more strict. Therefore, in this embodiment, the GBI PRIS as master, GBISCC
Is used as a slave to perform DMA transfer.

The GBI (GBus / BBus interface) is: Fifo that exchanges data with functional blocks
Unit 2. 2. A GBus controller 9202 that is directly connected to the G bus and connects the G bus and the Fifo unit. 3. BBus controller 9203 directly connected to BBus and connecting BBus and Fifo unit 4. DMA controller 9205 that issues a DMA transfer request to each bus controller in master mode. A register unit 9206 holds the contents of the register and sends a signal to each block. The register unit also includes an interrupt control and a power control unit. Hereinafter, each part will be described.

<Fifo Unit> The Fi unit shown in FIG.
The fo unit is a portion serving as a buffer for transfer data between the GBus / BBus and the IF Bus. Fifo
The units are Fifo units 0 and Fi, which are independent of each other.
fo unit 1. Fifo Unit 0
Is the data input from IFBus and GBus or B
The FIFO unit 1 is used for data output to the bus, and the Fifo unit 1 is used for data input from the G bus or the B bus and data output to the IF bus.

The signal scGbiFifo0Clk or scGbiFifoClk is a gated clock,
Stopping the clock realizes the power saving mode. This clock is stopped by writing to the GBI FIFO register and automatically started when entering the master mode or the slave mode.

[Fifo unit 0] The Fifo unit 0 writes data from IFBus0 (IFBus specifications will be described later) to Fifo, and writes GBus / B
Send it to Bus. The signal ifDataOutB [63:
0], ifWriteB, ifWriteEnable
G is connected to IFBus.

The Fifo of this Fifo unit 0
0 inputs 64-bit data from IFBus,
64-bit data DataOut64 and B for GBus
This is a 64-bit × 17-stage Fifo that outputs 32-bit data DataOut32 for Bus.

The status signal output from the Fifo unit 0 includes the following signals.・ Fifo0EnableB1G: Fifo0Unit
Indicates that one word (32 bits) can be transferred from the to the BBus. The DMA controller is used in the master mode, and the BBus controller is used in the slave mode.・ Fifo0EnableB4G: Fifo0Unit
Indicates that four words can be transferred consecutively from Bbus to BBus. The DMA controller is used in the master mode, and the BBus controller is used in the slave mode.・ Fifo0EnableB8G: Fifo0Unit
Indicates that eight words can be continuously transferred from B to the bus. The DMA controller is used in the master mode, and the BBus controller is used in the slave mode.・ Fifo0EnableG4G: Fifo0Unit
Indicates that four words (one word is 64 bits) can be continuously transferred to the G bus. DMA in master mode
When the controller is in the slave mode, the GBus controller uses it.・ Fifo0EnableG16G: Fifo0Uni
Indicates that 16 words can be continuously transferred from t to GBus. The DMA controller is used in the master mode, and the GBus controller is used in the slave mode. -IfWriteEnable: Fifo0 is Full
Indicates no status. Connected to IFBus to inform function blocks that writing is possible.

[0298] The reading of 64-bit data of GBus from Fifo0 uses the signal Rd64 input to Fifo0, and the reading of 32-bit data of BBus uses the signal Rd32. By either read, the status signal and the data Out64 and DataOut32 output from Fifo0 are updated.

(B2G block) I / F bus and BBu
The clock of s is 50 MHz, and the clock of GBus is 100 MHz. For this reason, Fifo unit 0
The IFB block, not shown, included in the
write signal ifWriteFi synchronized with us clock
One clock of the read signal bReadFifoB synchronized with the foB or the BBUs clock is converted into a clock of the clock of the Fifo unit (twice the frequency of IFBus).

(ChkIllegal block) Fif
o0 is shared by GBus / BBus. In the master mode, the DMA controller uses GBus / BBu
Although exclusive use of s is controlled, in slave mode,
The DMA master must control exclusive use.
For this reason, ChkIll included in the Fifo unit O
In the egal block, when the Fifo0 is simultaneously accessed from the GBus and the BBus, the signal fifoEr is output.
Assert lorG. That is, when the read signal gReadFisoG from Gbus or the read signal bReadFisoB from BBus is simultaneously asserted, the signal fifoErrorG is asserted. This signal is latched in the register unit and generates an interrupt if not masked.

[Fifo unit 1] The Fifo unit 1 is a Fifo unit that stores data from the GBus / BBus.
Write to fo1 and send to IFBus1. ifDa
taIng [63: 0], ifByteEnG [7:
0], ifReadB, ifReadEnableG
Is connected to IFBus.

In the Fifo unit 1, a front buffer is provided before the Fifo 1 in order to cope with the backward DMA in the master mode. In the case of reverse DMA (input signal reverseMODE is enabled), buffer once in the front buffer, and then F
Send data to IFO. Other modes (signal r
When “everyMODE” is disabled, it functions as a normal FIFO.

(Front buffer) GBus or B
This is a 64 + 4 bit × 4 stage buffer with byte enable, which receives data from the bus and outputs it to Fifo1. In writing from BBus, data is written together with a byte enable signal. In writing from the G bus, all byte enables are made valid and data is written. Packing to 64 bits in writing from BBus is not performed.

A signal BufEmpty indicating that the front buffer is empty is provided as a status signal.

In the case of the backward DMA, the signal reverses
eMODE is enabled and the transfer mode is DMA
4 bus burst transfer of GBus by controller,
Alternatively, the transfer is limited to only the BBus single transfer. G
Bus 4-bit burst transfer data is stored once in the front buffer, and then transmitted in reverse order to Fifo 1 (in reverse order in 32-bit units).

In other modes, the signal "reve"
rsMODE is disabled and 4-stage FIF
Functions as O. Input signal dummyWriteFi
fo1B is latched once and sent to Fifo1 when the front buffer becomes empty.

(Fifo1) Fifo1 receives data from the front buffer and converts the input data to I
It is a 64 + 8 bit × 16-stage Fifo with byte enable output to the FBus. Data from the BBus is written with the byte enable signal. GB
Data from us is written with all byte enables enabled. In writing data from the B bus, packing to 64 bits is performed.

The following status signals are provided based on the internal state of Fifo1 and the BufEmpry signal of the front buffer.・ Fifo1EnableBIG: Fifo unit 1
Indicates that two words (32 bits) can be transferred from the BBus. This is enabled when Fifo1 has a space of one or more BBus words or the front buffer is empty.・ Fifo1EnableB4G: Fifo unit 1
Indicates that eight words can be continuously transferred from BBus. This is enabled when Fifo1 has a space of 4 words or more of BBus or the front buffer is empty.・ Fifo1EnableB8G: Fifo unit 1
Indicates that 12 words can be continuously transferred from BBus. If there is a free space of BBus 8 words or more in Fifo1, or there is a free space of BBus 4 words or more in Fifo1,
It is enabled when the front buffer is empty.・ Fifo1EnableG4G: Fifo unit 1
Indicates that four words (one word is 64 bits) can be continuously transferred from the GBus. This is enabled when Fifo1 has an empty space of 4 words or more of GBus or the front is empty. Fifo1EnableG16G: Indicates that 16 words can be continuously transferred from the GBus to the Fifo unit 1. If Fifo1 is empty or if Fifo1 has GBus
It is enabled when there is room for 12 words or more and the front buffer is empty. IfReadEnable: Indicates that Fifo1 is not empty. It is connected to IFBus and informs the function block that it can be read.

Signals Fifo1EnableB1G, Fi
fo1EnableB4G, Fifo1EnableB
8G is used by the DMA controller in the master mode and by the BBus controller in the slave mode.

Signal Fifo1EnableG4G, Fi
fo1EnableG16G has D in master mode.
When the MA controller is in the slave mode, the GBus controller uses it.

[0311] The Fifo unit 1 has a B2G block and a ChkIlle like the Fifo unit 0.
It has a gal block.

<GBus Controller> FIG.
It is a block diagram of us controller 9202. Gbu
The s-controller 9202 includes a GBus master controller for controlling the GBus when the GBI serves as a bus master, and a GBus controller for controlling when the GBI serves as a slave.
Slave controller and GB for controlling data
us data controller and a GBus interface buffer. With this configuration, GBI 4301
Can operate as a GBus master or slave.

[Gbus master operation] The Gbus controller controls the Gbus master as a Gbus master by the following procedure.

[0314] 1. Request from DMA Controller The DMA controller 9205 outputs the gMReq (N) signal to gMAddr at a stage where the transfer of the channel N is possible.
(N) [31: 5] signal, gMBst4Not16 N
1 with bClk (Bbus clock signal)
Assert only the clock to request DMA transfer.

GMAddr (N) [31: 5] signal, g
MBst4Not16 The N signal is a gMDone (N) signal, gMRtry by the GBus master controller.
It must not be changed until either the (N) signal or the gMBErr (N) signal is asserted.

[0316] 2. Transfer request to GBus arbiter The gMReq (N) signal is latched by the GBus master request interface (gLatchReq
(N) signal).

The gLatchReq signal of each channel is
Arbitrated by Gbus master request arbiter (not shown)
The G bus arbiter 406 sends a DMA request signal g
Req At the same time as asserting the L signal,
Send gIntReq (N) signal to address phase
You.

[0318] 3. Transfer permission from GBus arbiter DMA permission signal gGnt from GBus arbiter 406
When the L signal is asserted, the signal GGntSense is asserted from the GBus master address phase, and the DMA request signal gReq L is negated. At the same time, the gLatchReq (N) signal and gIntReq
(N) The signal is negated. The GBus master request interface monitors the signal gSlvBsy,
When the data bus becomes available, GMDataRq
(N) Assert the signal. This signal is sent to the GBus master generate end data and the GBus data controller. 4. GBus data transfer When the gAack signal of the slave is confirmed, data transfer starts. GBus signals other than EndData are G
It is generated in the Bus master address phase. EndD
“ata” is generated by GBus master generate end data. Fibus or Fifo from GBus
Data transfer from Gbus to GBus is performed by GMDataRq
The (N) signal is used by the GBus data controller. If the gRtry signal is detected before the gAack signal, the GBus data controller does not perform data transfer. 5. Gbus data transfer end (or retry) Gbus master generate end data is Gbus
The end of the data transfer is determined by the checkBErr signal.
Notify the Bus master request interface. The GBus master request interface receiving the signal clears the internally held request and asserts the gMDone signal if there is no bus error. If a bus error is detected, gMBErr
Assert the signal to notify the DMA controller 9205 that the transfer has been completed.

When the gRtry signal is detected, GB
The us master request interface clears the internally held request and asserts the gMRtry signal at the same time.

The DMA controller 49205 has a GBu
The signal received from the s controller 9202 is gMDone
If it is a signal, the transfer address and transfer length are updated. If the received signal is a gMRtry signal, the next action is taken without updating them. At the time of the gMBErr signal, the DMA controller 9202 stops the transfer, and if not masked, generates an interrupt.

[Gbus Slave Operation] The Gbus controller controls the Gbus slave as a Gbus slave by the following procedure. 1. Transfer request from master Gbus slave request interface, g
At the timing of TsReg signal assertion, gAddrR
Check the eg signal and the gRdNotWrReg signal (channel 0 or 1). GSEnab with access to GBI
If the le (N) signal (slave mode: set by a register) is asserted, it is determined from the gBst4Not16 signal, the ReadFifoEnable4 / 16 signal (channel 0) or the WriteFifoEnable4 / 16 signal (channel 1) whether transfer is possible. If possible, the gAack signal, otherwise the gRtry
Assert the signal. 2. Gbus data transfer If transfer is possible, the Gbus slave request interface confirms negation of the gSIvBsy signal, asserts the gAack signal, and
The GSlvStart signal is transmitted to the Gbus slave request slave busy. In addition, the GBus slave request interface starts data transfer by GS
By asserting the DataRq (N) signal, GBus
Tell the data controller. Data transfer from GBus to Fifo or from Fifo to GBus
This is performed by the Bus data controller. GBus slave request slave busy generates the gSlvBsy signal. 3. GBus data transfer end There is no signal indicating the transfer end. There is no assertion of the gBErr signal. However, gSEEnable (N)
If the signal is negated, there is no response to the master's access, and a bus error occurs due to timeout.

<BBus Controller> FIG.
FIG. 146 is a block diagram of a us controller 9203. BBu
The s controller 9203 includes a BBus master controller, a BBus data controller, a BBus slave controller, and a BBus interface buffer. With this configuration, the GBI 4301 can operate as a BBus master or slave.

[BBus Master Operation] Request from DMA Controller The DMA controller 9205 sends the bMReq (N) signal to bMAddr at the stage where the transfer of the channel N is possible.
(N) [31: 2] signal, bMBurst8n) signal,
bMBst4Not8 Together with the N signal, the BBus clock signal bClk asserts only one clock. At the stage where the chain table needs to be read in the chain DMA mode, the cMReq (N) signal is set to cMAd
Assert one clock with bClk together with the dr (N) [31: 2] signal. The reading of the chain table does not use the BBus burst transfer. In this way, the DMA transfer of BBus is requested from the DMA controller.

BMAddr (N) [31: 2] signal, b
MBurst (N) signal, bMBst4Not8 The N signal starts accessing the Fifo (bReadFi
fo, bWriteFifo is asserted).

The cMAddr (N) [31: 2] signal must not be changed until one of the cMDone (N) signal, cMrtry (N) signal, and cMBErr (N) signal is asserted.

[0326] 2. The transfer request to the BBus arbiter The BBusbMReq (N) signal and the cMReq (N) signal are latched by the BBus master request interface (the bLatchReq (N) signal and the cLa
tchReq (N) signal). Each request signal is arbitrated by a BBus master request arbiter, and bBReq is sent to the BBus arbiter 407. The L signal is asserted.

[0327] 3. Transfer permission from BBus arbiter bBGnt which is a permission signal from BBus arbiter L
When the signal is asserted, the BBus master request arbiter sends a BGnt (N) signal or C
Gnt (N) signal is sent and bBGnt The L signal is negated. The BBus master request interface uses the bLatchReq (N) signal or cLatc
The hReq (N) signal is negated, and the bTx signal and bSn
The waitWait signal is monitored, and when a transfer is possible, the BMDataRq (N) signal and the CMDDataRq
(N) Assert the signal. This signal is sent to the BBus master sequencer and the BBus data controller.

[0328] 4. BBus Data Transfer The BBus master sequencer generates all BBus signals other than the data to be driven by the BBus master. BMDataRq (N) signal or CMDData
Using the Rq (N) signal as a trigger, bStartOut
L (if in burst mode, bBurstOu
t L) is asserted, bRdy (bBurstAck in burst mode) is checked, and the end of transfer is detected. Movement of data from BBus to Fifo or from Fifo to BBus is performed by BMDataRq
The (N) signal is used by the BBus data controller.

When the bRetry signal is detected before (or simultaneously with) the bRdy signal, the BBus data controller does not perform data transfer.

[0330] 5. End of BBus data transfer (or
(Retry, bus error) The BBus data controller ends the data movement with the BMlastData signal of the BBus master sequencer. Further, the BBus master sequencer notifies the end of the BBus data transfer to the BBus request interface by a Done signal. In the case of a retry or a bus error, a Retry signal,
The error signal is transmitted. The BBus master request interface informs the DMA controller that the transfer has been completed by using [bc] MDone (N) (hereinafter, either b or C is represented by [bc]), and retrying or bus error. Are transmitted as a [bc] MRtry (N) signal and a [bc] MBErr signal, respectively.

The DMA controller outputs the signal bReadF
The transfer address, transfer length, and the like are updated by ifo and bWriteFifo, and the next action is caused by the bMDone (N) signal or the bMRtry (N) signal indicating the end of the DMA BBus transfer. The cMDone (N) signal indicating the end of reading the chain table updates the internal chain table, and if the signal is a cMRtry (N) signal, issues a transfer request again.

[Bc] In the case of the MBErr (N) signal,
The DMA controller stops the transfer and generates an interrupt if not mastered.

(Retry in Burst Mode) Signal bS
start L and signal bBurst At the same time, the slave asserts the signal bRetry. Without asserting L, the signal bRdy When responding with the simultaneous assertion of L and the signal bBurstAck-L, the slave is determined to be capable of burst transfer. During the burst transfer, the signal bRet
ry L is not checked. That is, the first bRdy
Only at the timing of L, the signal bRetry L is checked. Note that even during the burst transfer, the signal bEr
lor L is checked at each clock.

(Signal bError L, bRetry
L, bRdy L simultaneous coincidence) signal bEr
lor If L is asserted, the signal bRetry
Even if L is asserted, it is regarded as a bus error.
Signal bError L is negated and the signal bRetr
y When L is asserted, the signal bRdy Even if L is asserted, it is regarded as a retry.

(Signal byteEn in master mode) L
[3: 0]) Signal byteE in master mode
n L [3: 0] is always “0000” except for the last transfer of single access and burst access.

[BBus slave operation (other than register access)] Transfer request from master The BBus master sequencer sends the bAddr signal and bWr at the timing of the bStart-L signal assertion. Check the L signal (channel 0 or 1). In accessing the GBI, if the bSEEnable (N) signal (slave mode: set by a register) is asserted, bBur
stShortNotLong signal (bBurst L
Only when the signal is asserted) and ReadFifoEn
able 1/4/8 signal (channel 0) or WriteF
It is determined whether transfer is possible from the ifoEnable 1/4/8 signal (channel 1). If transfer is possible, bRdyO
Ut L signal (in the burst mode, bBurst
AckOut L signal), otherwise bRetryOut Assert the L signal.

Master burst mode (bBurst
In response to the request of (L signal is asserted), if the burst transfer cannot be performed but the single transfer is possible from the Fifo state, bRdyOut Assert only the L signal and perform single transfer. Further, when the master burst mode request generates a wraparound, single transfer is performed if possible because the GBI does not support wraparound (bBurstAckOut). L signal is not asserted).

[0338] 2. BBus data transfer If transfer is possible, BBus master sequencer is required
BRdyOut by the number of clocks Assert L signal
Keep doing. In the case of burst transfer, the first bRdyO
ut At the timing of the assertion of the L signal, bBurst
AckOut Assert L signal for 1 BBus clock
I do. In addition, the start of data transfer is indicated by BSDataRq.
The (N) signal indicates that data transfer has been completed by bMLastDat.
The signal a is transmitted to the BBus data controller. BB
us to Fifo or Fifo to BBus
Data movement is performed by the BBus data controller.

[0339] 3. BBus data transfer end There is no particular signal indicating transfer end. bErrorOut
There is no assertion of the L signal. However, bSEna
If the bIe (N) signal is negated, there is no response to the master's access, and a bus error due to timeout occurs.

[BBus Slave Operation (Register Access)] The GBI and registers in the functional blocks are accessed from the BBus. For register access,
It can be accessed at any time regardless of the GBI mode or state. bRetryOut LbErrorOut
It does not assert the L signal. A single transfer always responds to the master's burst mode request (bBurstAckOut) L signal is not asserted).

[0341] The register controller 9206 sets the reg
Start L, regAddr [31: 2], byt
eEnIn [3: 0], regWr L signal (BBus
Signal of the BBus clock).
If writing to a register, bDataIn [3
1: 0] signal, and the Ack signal (GBI
Then, regGbiAck-L, IFBus, re
gIfAck Assert L). Read from register
If the data is read, the data is transferred to the internal bus (in the GBI, re
gGbiDataOut [31: 0] on IFBus
Put on ReglfDataOut [31: 0])
The Ack signal (regGbiAck in GBI)
L, IFBus, regIfAck L) Asser
To

In the BBus slave generate ready,
BRdyOutL is created from the Ack signal.

(BBu other than GBI register access)
(cycle of s) In the GBI slave mode, the cycle of the single transfer is always 3 BBus clocks. The burst transfer performs the first bRdyOut at the same timing as the single transfer. Assert the L signal and then continue asserting for the required clock without negating.
If transfer (single and burst) is not possible, the first bRdyOut At the timing when L is asserted, bR
entryOut Assert L only.

(BBus slave generate ready)
Lock) BBus slave generate ready block
Is the Channel from the BBus slave sequencer
Rdy L signal and re from the GBI register unit
gGbiAck L signal and function block (IFBus)
RegIfAck from OR the L signal and use the clock
Hit.

<IFBus Interface> IFBu
s is a simple bus connecting GBI and functional blocks. The clock uses bClk (50 MHz).
The input signal here is a signal in the direction from the functional block to the GBI. There are no bidirectional signals. IFBu below
The signal of s will be described. A signal name ending with "_L" indicates that it is low active. This is the same for the part already described. In an actual implementation, “if” of the signal name is replaced with the name of the functional block.

・ IfRst0 L (channel 0), if
Rst1-L (channel 1) (output) This is an IFBus reset signal. With this signal, I
Return the state of the FBus to the initial state. Asserted by the GBI internal register. It must be asserted before the transfer between the GBI and the functional block.

• ifDataOutB [63: 0]
(Input: channel 0 only) This is a data signal from the functional block to the GBI. This signal is connected to the Fifo unit 0 (see FIG. 93).

IfWriteB (input: channel 0 only) This is a write signal from the functional block to the GBI. GBI
Is the ifCl signal for which the ifWrite signal is asserted.
At the rise of k, ifDataOut [63: 0] is written. By continuing to assert the ifWriteB signal, data can be written in units of one clock. This signal is connected to the Fifo unit 0 (see FIG. 93).

• ifWriteEnableG (output:
(Only channel 0) This is a write permission signal from the functional block to the GBI. i
at the rise of fClk, ifWriteEnable
If the G signal is asserted, it indicates that writing is possible at the next rising edge of the clock. ifWrite
The assertion of the B signal is performed after confirming the ifWriteEnableG signal. This signal is output from the Fifo unit 0.

IfDataInG [63: 0], if
ByteEnG [7: 0] (output: channel 1 only) Data and byte enable signal from GBI to functional block. This signal is connected to the Fifo unit 1. Table 8 shows the correspondence between each digit of the signal ifByteEnG [7: 0] and each byte unit of ifDataG [63: 0].

[0351]

[Table 8]

IfRead (input: channel 1 only) This is a read signal from the GBI to the functional block. GBI
Is the ifClk for which the ifRead signal is asserted
Rises, ifDataInG [63: 0] and i
Output fByteEnG [7: 0]. ifRead
By continuing to assert the signal, data can be read in units of one clock. This signal is connected to the Fifo unit 1.

IfReadEnableG (output: channel 1 only) This is a read permission signal from the GBI to the functional block. i
at the rising edge of fClk, ifReadEnableG
If the signal is asserted, it indicates that reading is possible at the next rising edge of the clock. The assertion of the ifRead signal is performed after confirming the ifReadEnableG signal. This signal is output from the Fifo unit 1.

・ IfRegStart L (common to channel) (output) BBus (7) bStart This is a signal obtained by tapping L with a clock. ifRegAddr [31: 2] signal, if
RegRdNotWr signal ifByteEn L [3:
0] signal is asserted for one clock. When writing to the internal register of the functional block, the signal ifRegDataIn [31: 0] is also valid. In the function block, ifRegStart When L is asserted, the address is checked. If access to the internal register of the functional block is performed, ifReg
Ack Responds with L signal. Otherwise, the next if
RegStart Wait for L assertion. This signal is
Output from the BBus controller.

IfRegAddr [31: 2] (common to channel) (output) This is an address signal obtained by hitting bAddr [31: 2] of the BBus with a clock. Signal ifRegStart It becomes effective at the same time as L assertion, and if it is an access to the internal register of the functional block, ifRegAck It is effective while responding with the L signal. This signal is output from the BBus controller.

• ifRegByteEn [3: 0] (common to channels) (output) byteEn of BBus This is a byte enable signal obtained by tapping L [3: 0] with a clock. Signal ifRegSt
art It becomes effective at the same time as L assertion, and if it is an access to the internal register of the functional block, ifRegAc
k It is effective while responding with the L signal. When writing to an internal register of a functional block, only valid bytes indicated by this signal are written. In the case of reading from the internal register of the functional block, this signal is ignored and all bytes are output. This signal is output from the BBus controller. Table 9 shows the signal ifRegB
Each digit of yteEn [3: 0] and signal ifRegData
The correspondence with each byte unit of InG [31: 0] is shown.

[0357]

[Table 9]

IfRegRdNotWr (common to channel) (output) bWr of BBus A signal obtained by tapping L with a clock, and indicates the direction of access to the internal register of the functional block. When high, the contents of the internal register of the functional block
output to eqDataOut [31: 0], low,
The data of ifReqDataIn [31: 0] is written to the internal register of the functional block. Signal ifRe
gStart It becomes effective at the same time as L assertion.
gAck It is effective while responding with the L signal. This signal is output from the BBus controller.

• ifRegAck L (common to channels)
(Input) This signal indicates that the function block has completed access to the internal register. Signal ifRegStart When L is asserted, the address is checked. If the internal register of the functional block is accessed, the register is read or written, and the signal is always asserted for one clock. If it is not an access to the internal register of the functional block, it must never be asserted. This signal is connected to the BBus controller.

• ifRegDataOut [31: 0]
(Common to channel) (Input) This is a data bus signal from which the contents of the internal register of the functional block are read. Signal ifRegAck Must be valid when the L signal is asserted. This signal is connected to the BBus controller.

• ifRegDataIn [31: 0]
(Common to channel) (Output) This is a bus signal indicating data to be written to the internal register of the functional block. Signal ifRegStart It becomes effective at the same time as L assertion, and if it is an access to the internal register of the functional block, ifRegAck It is effective while responding with the L signal. This signal is output from the BBus controller.

IfDmaPmState [1: 0]
(Common to channel) (output) A signal indicating the operating state of the GBI. This output is always valid. The function block generates a power management status signal to the power management unit based on this signal and the operation state of the function block itself. This signal is output from the register unit. The output value will be described later in the section on power management.

<DMA Controller> In the GBI, channels 0 and 1 have DMA controllers 9205 as shown in FIG. 96, respectively.

The DMA controller comprises a DMA main controller, a fetch chain table, a calculated pitch address, a generate address, and a lock for each part of the DMA request.

[0365] From register unit 9206, Table 10
The mode of DMA is transmitted by this signal.

[0366]

[Table 10]

Next, each part lock of the DMA controller will be described.

[DMA Main Controller] The DMA main controller controls the start and stop of the other four blocks. In the chain table type DMA, the fetch chain table, the generate address, the DMA
The blocks are started by shifting the clock by one clock in the order of the requests. In a pitch-added DMA, blocks are started up by shifting one clock at a time in the order of a calculated pitch address, a generate address and a DMA request. Otherwise, generate address and DMA
Activate the request with one clock delay.

The DMA main controller is a DMA main controller.
Is determined. When the fetch chain table is in an idle state (the chain table has been completely read or not activated) and the calculated pitch address is in an idle state (all lines have been completed or not activated), the Ne of the generated address is Ne.
assertion of xtAddReReq signal (length counter becomes zero) or bus error, stopDM
Upon detecting the assertion of the A signal (DMA forced termination by the register), the DMA main controller asserts the stopDMAReq signal to each block. When all the blocks are in the idle state, it is determined that the DMA is completed (endDMA is asserted).

[Fetch Chain Table] The fetch chain table is a block for fetching a table on the memory, and is not activated when the chain table is not used. A chain table pointer address counter for a memory address pointing to the chain table, a chain table entry counter indicating the number of remaining entries in the chain table, a next address register storing addresses and lengths fetched from the chain table, a next length register, and It comprises a fetch chain table controller for controlling these.

When activated by the DMA main controller, the contents of the register are loaded into the chain table pointer address and the chain table entry counter. A request for fetching the address chainAddress [31: 2] is made to the BBus controller by the chainReq signal. Ch from BBus controller
With the ainDone signal (normal end), the read contents are latched in the next address register, and the chain table pointer address counter is incremented. B
When a ChainRtry signal (retry) is returned from the Bus controller, the same request is issued again to the BBus controller.

After latching the next address register,
Address Chain Addr to BBus controller
Request fetch of esss [31: 2]. Chain
In response to the Done signal, the read content is latched in the next register, the chain table pointer address counter is incremented, and the chain table entry counter is decremented. At the same time, nextAd
Assert the drValid signal and notify the generated address block that the address and length have been read from the chain table.

If the data at the time of latching the next register is zero, the contents of the next address register are loaded into the chain table pointer address counter.

During the assertion of the nextAddrValid signal, the NextA
When the ddrReq signal is asserted, the generate address block determines that the address and length from the chain table have been received, and nextAddrVal
Negate the id signal.

Next, the chain table entry counter is checked. If it is not zero, the fetch of the chain table is continued again. If it is zero, the process returns to the idle state.

When the chain BErr signal (bus error) is received, it immediately returns to the idle state. When the stopDMAReq is received from the DMA main controller, if a request has been issued to the BBus controller, the end is waited for, and if not, the operation immediately returns to the idle state.

In the mode in which the chain table is not used, since it is not started, the idle state is maintained and next is maintained.
The AddrValid signal remains negated.

[Generate Address] The generate address block includes a transfer memory address counter for storing a transfer address for the memory, a transfer length counter for storing a transfer length to be transferred,
A transfer counter for storing the number of transferred bytes,
A generate address controller that controls these three counters, and a GBus /
Check for determining the mode requested for BBus
It has a GBusReq and a CheckBBusReq block (collectively referred to as CheckG / BBusReq).

(When a chain table is used) When activated by the DMA main controller, the transfer counter is cleared and ne
It waits for the xtValidAddrCT signal. next
When the ValidAddrCT signal is asserted, the address and length of the chain table are loaded into the transfer memory address counter and the transfer length counter, respectively.

CheckG / BB is determined by the contents of both counters.
usReq determines a transferable mode.

CheckG / BBusReq to DMA
The transfer mode of G / BBus is transmitted to the request block (when transfer is not possible, the g / b Valid signal is negated).
A transfer request is issued to each bus controller with priority.

In the transfer on the G bus, the transfer memory address counter and the transfer counter are incremented and the transfer counter is decremented at once according to the gMDone signal (the G bus transfer end signal) and the transfer mode at that time. In the transfer on the B bus, the transfer memory address counter is incremented and the transfer counter is decremented by an access signal of the FIFO.

When the transfer counter reaches zero, the next Va from the fetch chain table
If the lidAddrCT signal is negated, it waits for an assert, and loads the contents of the next chain table into the transfer memory address counter and the transfer counter, otherwise loads immediately. Then, the next transfer is started.

When the transfer counter has reached zero after the transfer of the last part of the chain table has been completed, the fetch chain table is in an idle state and n
The extValidAddrCT signal is negated. Since the DMA main controller detects the end of the DMA, the stop main DMA
Assert the Req signal. As a result, the generate address enters an idle state.

(When Using DMA with Pitch) DMA
When activated by the main controller, the transfer counter is cleared and the process waits for the next ValidAddrPA signal from the calculated pitch address. n
When the extValidAddrPA signal is asserted, the address and the length calculated from the start address and the pitch are loaded into the transfer memory address counter and the transfer length counter, respectively.

As in the case of using the chain table, the transfer memory address counter and the transfer counter are incremented, and the transfer counter is decremented.

When the transfer counter reaches zero, the next from the calculated pitch address
If the ValidAddrPA signal is negated,
Upon assertion, the contents of the next chain table are loaded into the transfer memory address counter and the transfer counter, otherwise immediately. Then, the next transfer is started.

When the transfer counter becomes zero after the transfer of the last line is completed, the calculated pitch address is in the idle state and nextVal
The idAddrPA signal is negated. Since the DMA main controller detects the end of the DMA, it asserts the StopDMAReq signal for the generate address. As a result, the generate address enters an idle state.

(In the case of I / ODMA) When activated by the DMA main controller, the transfer counter is cleared and the contents of the GBIDMA transfer length register storing the data length are loaded into the transfer counter. CheckGBusReq / CheckBBu
Each block of the sReq is a GBIDGMGBus I / O address register storing a DMA address of the I / O.
The contents of the GBIDDMAB Bus I / O address register are used.

Similarly to the above, the transfer counter is incremented and the transfer counter is decremented.

When the transfer counter becomes zero, the fetch chain table and the calculated pitch address are not activated, so that the next ValidAddr signal is negated in the idle state. Since the DMA main controller detects the end of the DMA, the stop main DMA
Assert the AReq signal. As a result, the generate address enters an idle state.

(Reverse mode) A reverse mode is supported except for paired I / ODMA. Chain table DM
One block of A and one line of DMA with pitch are accessed from the larger address to the smaller address. An instruction in the reverse direction for each block or line is made in the chain table DMA so that the chain table is reversed. In the case of a DMA with a pitch, the pitch value is set to a negative value (two's complement).

In the reverse mode, when loading a value into the transfer memory address counter, the last address is calculated and loaded using the transfer length. Decrement instead of incrementing the transfer memory address counter.

The CheckBBusReq block requests only a single transfer. CheckGBusReq
The block requests only 4-beat burst transfer. F
In the ifo unit, the data is sent to the functional block in reverse order in units of 32 bits (currently, only channel 1 is supported).

(Check of GBus Request) CheckG
In the BusReq block, a GBus request is checked. The signal gValid is always negated unless the signal useGBus is active.

[0396] Bits 6 and lower of the transfer memory address are all zero, and the transfer length is 128.
At this time, the signal gValid is asserted and g4Not1
6Req = '0', when bits 4 and below of the transfer memory address are all zero and the transfer length is 32 or more, the signal gValid is asserted, and g
4Not16Req = '1'. Otherwise, the signal gValid is negated.

(Check of BBus Request) CheckB
In the BusReq block, a BBus request is checked. The signal bValid is always negated unless the signal useBBus is active.

When bits 4 and below of the transfer memory address are all zero and the transfer length is 29 or more, the signal bValid is asserted, and bBurstR
When eq = “1” and b4Not8Req = “0”, and when bits 3 and below of the transfer memory address are all zero and the transfer index is 13 or more, bVa
lid is asserted, signal bBurstReq = '1',
b4Not8Req = '1'. Otherwise, b
Valid is asserted, and bBurstReq = '0'.

(DMA Request) When activated by the DMA main controller, a request for GBus / BBus from the generate address block is checked. When there are both G / BBus requests, G
Bus has priority. According to this request, a transfer request is issued to the Gbus controller or the BBus controller, and a response is waited. The response is g / bMDone, g / bMRtr
The signal is either y or g / b MBErr.

In the case of g / bMDone, the transfer is normally completed, and the GBus / B from the next generate address
Check the request for Bus.

In the case of g / bMRtry, a transfer request is issued again to the same bus controller.

In the case of g / bMBErr, it immediately returns to the idle state.

When the last transfer is completed, the DMA request block contains the GBu from the generate address.
s / BBus is in a request waiting state. Since the DMA main controller detects the end of DMA and issues stopDMAReq in response to the DMA request,
As a result, the DMA Request returns to the idle state.

Also, in the case of a bus error at the time of fetching the chain table or the forced termination of DMA by a register, the DM
A StopDMAReq is issued from the A main controller. When a transfer request is issued to the bus controller, the transfer is waited for to be completed. When the transfer request is not issued, the bus controller immediately returns to the idle state.

<Register Unit> In the internal register unit, there is a register unit corresponding to each channel. Each unit is the same except that the decoding address is different. The register unit has a register unit 0 and a register unit 1 as shown in FIG.

Each register unit has a register I / F,
The GBI, which consists of an action controller, an interrupt controller, and a power status block, supplies a set ground value to each block of the GBI. The interrupt controller controls interrupts, and the power status controls power-saving blocks. .

[Power Status] The units capable of the power saving mode in the GBI are the DMA controller and the FI
FO unit. The power saving mode is fifoInSl
This is realized by masking the clock of each block with the eep signal and the dmaInSleep signal. At the time of reset, both enter the power saving mode. The DMA controller starts automatically when it is started in the master mode.
Go to sleep by writing to the BIFIFO sleep register.

The power management status signal (pmState) output from the power status block
[1: 0]) is pmState [1: 0] 00 level 0 (stops both DMA and FIFO) 01 level 1 (operates only FIFO) 10 level 2 (operates both DMA and FIFO) 11 NotDefine in each channel.

In DoEngine, a scanner controller (Scc) and a printer controller (Pr)
Since GBI to which c) is connected has only one channel, the GBI is as described above. When the GBI includes two channels, the values of each channel are summed and degenerated into four stages as follows.

PmState [1: 0] 00 level0 (both channel FIFO and DMA are stopped) 01 level1 (one channel FIFO is operated only) 10 level2 (both channel FIFO is operated and both DMAs are stopped) 11 level3 ( The FIFOs of both channels operate, and one of the DMAs operates).

[0411] The power management status signal (p
mState [1: 0]) is sent to the functional block via IFBus. The function block generates a power management status signal to the power management unit based on this signal and the operation state of the function block itself.

<Operating Mode of GBI> The components constituting the GBI have been described above. Here, the operation of the GBI will be summarized. The operation modes of the GBI are roughly classified into the following.

[0413] 1. Slave mode 2. Master Mode The DMA mode in the master mode is as follows. B. Memory There is I / O (fixed address), and in memory DMA: a. Contiguous physical address b. Data is transferred to a memory at a discontinuous physical address (assuming that the transfer destination memory is divided into memory management pages). In addition, the memory DMA also supports a backward mode (only channel 1).

[0414] The DMA for the continuous physical address is a so-called two-dimensional DMA that specifies the start address, the length of one line, the pitch to the next line, and the number of lines. The one-dimensional case is realized by setting the number of rows to one.

[0415] In the DMA for discontinuous physics, the start address and length of each divided memory block are arranged in the memory, and the transfer destination address is calculated while referring to the address, and DMA is performed. This set of the start address and the length is called a chain table. FIG. 98 shows an example of the chain table. DMA for discontinuous physical addresses
Then, the number of pairs of the memory address and the address / length in which the chain table is arranged is specified. Of course, the chain table itself must be located at a contiguous address, but if the entire chain table cannot be located in a contiguous area, the address of the next chain table is used instead of the first address, and 0 is set for the length. By setting, you can connect chain tables.

[0416] In the reverse mode, the chain table DMA is used.
One block of the two-dimensional DMA is accessed from the larger address to the smaller address. Instructions in the reverse direction for each block or line can be made in the chain table DM.
In A, the chain table is made upside down. In the case of a DMA with a pitch, the pitch value is set to a negative value (two's complement).

<Interrupt Control> Next, interrupt control will be described. An interrupt from the DBI occurs under the following conditions.

[Master mode] 1. Normal end of DMA 2. Bus error detection during DMA transfer on GBus 3. Bus error detection during DMA transfer on BBus Detection of Bus Error During Chain Table Read in Chain DMA Mode In the case of forced termination by the GBI stop register, the transfer ends normally when the transfer requested by the DMA controller to the controller of each bus ends normally. If the requested transfer results in a bus error, the transfer ends abnormally due to the bus error.

[0419] In channel 0, the process ends when the functional block writes all data to the FIFO in the GBI (an interrupt is generated), but data remains in the FIFO. When GBI transfers data in the FIFO,
Since the transfer is completed, it is determined that the transfer is completed.

In channel 1, the GBI is the FI in the GBI.
Processing ends when all data has been written to the FO (an interrupt is generated), but data remains in the FIFO. Since the function block ends when the data of the FIFO is transferred, it is determined that the transfer is completed.

[Slave mode] 5. FIFO illegal access Data transfer between the functional blocks allocated to the GBI and the master is performed via the GBI FIFO.

In the case of using both GBus / BBus (in DoEngine, GBI is the only master that can use both GBus / BBus), in order to simultaneously access from both buses, which bus is first FIFO
There is no way to know what to access. Master is GBus
/ BBus must be exclusively requested to transfer (in the GBI master mode, a transfer request is exclusively requested). If both GBus / BBus are FIF
When O is accessed, it becomes FIFO illegal access.

If any of the above 1 to 5 occurs and the corresponding interrupt enable bit is set to "1", an interrupt is generated.

<Core Interface> FIG.
FIG. 2 shows a diagram of a core interface in which I and interfaces with BBus / GBus / functional blocks are summarized.
Since the GBI does not issue a bus error in the BBus slave operation, bError (Func) Out There is no L. In addition, GBI uses bInst
Because the NotData signal is not checked, (fun
c) bInstNotData There is no in, (fun
c) bInstNotData out is always "0"
Drive.

Since the GBI does not issue a bus error in the Gbus slave operation, (func) gErr L
There is no out.

In FIG. 99, Func (func) in the signal name of GBI indicates a function block to be connected.
That is, scc (scanner controller) or pr
Enter the name of c (printer controller).

In DoEngine, as a functional block, Scc (scc) of the scanner controller is used.
And Prc (prc) of the printer controller.
In either case, since the data flow is not bidirectional, the implementation is performed with unnecessary FIFOs, DMA controllers, and registers eliminated.

<Printer Controller Core Interface> FIG. 86 is a diagram summarizing signals input and output between the core portion including the above-described blocks in the printer controller 4303 and an external bus or scanner. As described above, the printer controller 4303 is connected to the system bus bridge 402 by the G bus, is connected to the IO device, the power management device, and the system bus bridge by the B bus, and is connected to the printer controller by the CP bus. They are connected by a bus, and are connected to the G bus / B bus I / F unit by an I / F bus.

2.10. Power Management Unit FIG. 87 is a block diagram of the power management unit 409.

The DoEngine is a large-scale ASIC with a built-in CPU. For this reason, if all the internal logics operate simultaneously, a large amount of heat is generated, and the chip itself may be destroyed. To prevent this,
The DoEngine performs power management for each block, that is, power management, and further monitors the power consumption of the entire chip.

The power management is performed individually by each block. Information on the power consumption of each block is collected in a power management unit (PMU) 409 as a power management level. The PMU 409 sums up the power consumption of each block and monitors the power consumption of each block of the DoEngine collectively so that the value does not exceed the limit power consumption.

<Operation> The operation of the power management block is as follows. -Each block has four power management levels. The PMU has the power consumption value at each level as a register. The values of the level configuration and the power consumption are held in the PM configuration register 5401. The PMU receives the power management level from each block as a 2-bit status signal (described later), and checks the power consumption of each block by checking the value set in the register 5401. The PMU adds the power consumption of each block by the adder 5403, and calculates the total power consumption of the DoEngine in real time. The calculated power consumption is compared with the power consumption limit value (PM limit) set in the configuration register 5401 by the comparator 5404. If the power consumption exceeds the limit, an interrupt signal is issued from the interrupt generator 5405. I do.・ This limit value can be set in two stages. In the first stage, a value is set with some margin from the true limit. If this value is exceeded, a normal interrupt signal is issued. In response, the software does not start a transfer that starts a new block. However, a new block can be started under the management of software within a range not reaching the limit value of the second stage. As the limit value in the second stage, a value that may cause destruction of the device is set. Should this value be exceeded, an NMI (interrupt for which an interrupt mask cannot be set) is issued to stop the system for safety. The interrupt signal is released by reading the status register 5402 of the PMU. The timer starts counting from the time when the status register 5402 is read. If the power consumption does not return until the timer expires, an interrupt signal is issued again. The setting of the timer value is set in the configuration register 5401 of the PMU.

<Power Management of Each Block> The power management control of each block may be freely configured for each block. The example of a structural example is shown.

(Configuration Example 1) In this example, since power management is performed by turning on / off a clock to internal logic, the power consumption level has only two levels. This level is sent to the power management unit 409 as a status signal. FIG. 88 shows a block diagram of the bus agent. The bus agent 5501 includes an internal logic 5502 for each unit and a decoder 55 for decoding an address.
03, a clock control unit 5504, and a clock gate 5505. -Decoder 5503 and clock control unit 5504
Is always running and monitors bus activity and gates clocks to internal logic as power management controls.

<Clock Control> The bus agent detects bus activity and automatically turns on / off the clock.・ Sleep, Wake U
There are three states, p and Wait. Sleep is a state where the bus agent has no activity and the clock gate clock is stopped. -Even in the sleep state, the decoder unit 5503 and the clock control unit 5504 are operating, monitor the bus, and wait for a request. When the decoder 5503 detects its own address, it opens the clock gate 5505, operates the clock of the internal logic, and responds to the bus request. State is Wake
Move to Up. Further, this state is notified to the power management unit 409. When the data transfer is completed, the state shifts to the Wait state and waits for the next request. At this time, the clock remains running. If requested, return to the Wake Up state,
Perform a transfer. The timer counts while waiting for a request, and if the counter times out without a request, the process proceeds to the Sleep state and stops the clock. This state is also notified to the power management unit 409.

As described above, the power consumption is managed so as not to exceed the predetermined value.

<Copy Operation> With the configuration described above, the image data read from the scanner can be directly transferred to the printer, and the operation of forming an image by the printer can be performed as a copy operation. In the scanner / printer system using the Do Engine of the present embodiment, the following three types of copying methods are selected according to the system configuration.

(Method 1) In the first method, the vertical / horizontal timing of image input by the scanner matches the horizontal / vertical timing of image output by the printer, and the transfer speed of video data also matches. This is a method in a combination system.

The vertical synchronization signal (VSYNC) is output from the printer and input to the printer controller (PRC). This VSYNC signal is input from the printer controller (PRC) to the scanner controller (SCC) via the CP bus. Then, it is output from the scanner controller (SCC) to the scanner. As a result, the printer and the scanner are vertically synchronized. As for the horizontal synchronization, similarly to the vertical synchronization signal VSYNC, the horizontal synchronization signal (HSYNC) is output from the printer and input to the scanner via the printer controller, the CP-bus, and the scanner controller. Thus, horizontal synchronization between the scanner and the printer is achieved. As described above, the scanner and the printer operate in synchronization with each other in the vertical and horizontal directions. The video data is output from the scanner together with a video clock for synchronization. The output video clock and video data are sent to the scanner controller (SCC).
To the printer controller (PRC) via the CP bus. Then, the data is output from the printer controller (PRC) to the printer. The printer receives video data in synchronization with a video clock and outputs an image.

This copy operation is performed by the structure shown in FIG. In this copy operation, the copy operation is performed without using the G bus and the B bus.

During the copying operation, the image data is directly transferred from the scanner to the printer via the CP bus. At the same time, the scanner controller (SCC) sends the image data from the G bus to the DM bus.
It is possible to write to SDRAM by A transfer. The image data written to the SDRAM simultaneously with the copy operation can be stored as image data if necessary. Further, by outputting the image data on the SDRAM to the printer, it is possible to output the image data read by the scanner to a plurality of units without operating the scanner.

(Method 2) In the second method, the horizontal timing of image input by the scanner and the horizontal timing of image output by the printer match, and the vertical timing does not match the transfer speed of video data. This is a method in a combination system.

The copying operation in this case will be described with reference to FIG.
You. When the scanner starts reading the image, the vertical sync signal
(VSYNC), horizontal sync signal (HSYNC), video
Three timing signals called clocks
Input to the roller (SCC). Sync to video clock
Video data to the scanner controller (SCC)
Is entered. Scanner synchronized with the above timing signal
The controller (SCC) sends video data to the internal FIFO
O (FIFO SCC). FIFO To SCC
As soon as image data starts to enter, FIFO SCC or
G / B bus I / F unit 430 of the scanner
1A (GBI FIFO of SCC) GBI
SCC) starts data transfer. From the scanner
Image data is FIFO FIFO via SCC
GBI Transferred to SCC. FIFO GBI S
When data starts to enter the CC, the printer's G bus / B bus
Switch I / F unit 4301B (GBI PRC)
G bus / B bus I / F unit 43 of the scanner
01A (GBI DMA transfer with SCC) as slave
Is started. At this time, if the G bus is vacant
We use that, but if it is not vacant, it is B bus
Is also good.

[0444] By this DMA transfer, the FIFO SCC
Image data is GBI FIFO in the PRC (FIFO
GBI PRC). FIFO GBI
The PRC image data is sequentially stored in a printer controller (P
RC) FIFO (FIFO PRC). F
IFO When image data starts to enter the PRC, the printer
The controller (PRC) sends a vertical synchronizing signal (V
SYNC). From the printer, VSYNC
Depending on the timing, the horizontal synchronization signal (HSYNC) and video
Start outputting the clock. Printer controller
(PRC) is used for horizontal synchronization with the horizontal synchronization signal HSYNC.
Synchronizes the video data with the video clock
O Output from PRC. The video data to a printer
Outputs an image.

In the case of this copy operation, the image data is
FIFO for FIFO controller (FIFO)
SCC), FIFO of G bus / B bus I / F unit
(FIFO GBI SCC), G bus / B bus I / F
Unit FIFO (FIFO GBI PRC), Puri
Of the controller (FIFO PRC),
The images are transferred in the order of the linters, and the image copying operation is performed.
The horizontal synchronization interval is the same for the scanner and the printer.
Therefore, the difference in the transfer speed of image data is moderated by each FIFO.
Be hit.

(Method 3) The third method is a method in a combination system in which the vertical synchronization timing, the horizontal synchronization timing, and the video data transfer speed of the scanner and the printer are all different from each other.

The copying operation in this case will be described with reference to FIG. When the scanner starts reading an image, the scanner starts a vertical synchronization signal (VSYNC) and a horizontal synchronization signal (HS).
YNC) and the video clock to the scanner controller (S
CC). Image data is output in synchronization with these timing signals. Scanner controller (SC
C) captures image data in synchronization with the timing signal. The captured image data is GBI The data is transferred to the memory controller (MC) 403 by DMA transfer by the SCC. The MC 403 writes the DMA-transferred image data to the SDRAM. When the amount of image data written to the SDRAM reaches an amount that can buffer the difference in image data transfer speed between the scanner and the printer, the transfer of image data to the printer is started. The determination of the image data amount is based on the data transfer time from the scanner,
Judgment by address written to AM, GBI SC
There are various methods, such as the determination of the amount of DMA transfer in C.

The image data transfer to the printer is performed by the printer controller (PRC). The printer controller (PRC) is GBI The image data written in the SDRAM is sequentially input to the internal FIFO by the PRC DMA transfer. At the same time, a vertical synchronization signal (VSYNC) is output to the printer. Thereafter, a horizontal synchronization signal (HSYNC) and a video clock are input from the printer. In synchronization with the HSYNC and the video clock, the printer controller (PRC) outputs image data from the internal FIFO to the printer. According to the flow of the image data, a copy operation for outputting the image data read by the scanner from the printer is performed. The flow of image data in this case is as follows: a scanner, a scanner controller,
G bus / B bus I / F unit (GBI S
CC), memory controller (MC), SDRAM, memory controller (MC), printer G bus / B bus I / F unit (GBI PRC), a printer controller (RRC), and a printer. As described above, the image data is temporarily stored in the memory, and is used as a buffer memory between the scanner and the printer to transfer the image data from the scanner to the printer and perform copying.

The present system has the above three types of copy operation functions. (System 1), (System 2), and (System 3) in this order, the number of internal blocks that operate during the copy operation increases. As internal block usage increases, overall system performance can be a factor in reducing efficiency. In this system, the most efficient copy operation method can be selected for the entire system according to the connected device (printer / scanner).

As a method of selecting a copy method, for example, there is the following method. The user inputs the specified copy method via a UART or the like, and performs a copy operation in the specified method. Necessary parameters such as the data transfer speed of the printer and the scanner and the horizontal / vertical synchronization frequencies are input from the UART or the like.
01 selects one and causes a copy operation to be performed in that manner. The printer controller reads necessary parameters such as the data transfer speed and the horizontal / vertical synchronization frequency of the printer, and the scanner controller reads the necessary parameters such as the data transfer speed and the horizontal / vertical synchronization frequency from the scanner, and the CPU 401 compares and determines them. To determine the type of copy operation.

The copy method determined or selected by the above-mentioned methods is notified from the CPU to the printer controller and the scanner controller, and the printer controller and the scanner controller perform copying by the method.

Next, a procedure for determining a copy method by the above method will be described.

FIG. 100 is a flowchart of a procedure by the CPU 401 for selecting a copy method to be used in the system from three types of copy methods. This operation is started from step S1 when the power of the system is turned on.

In step S2, the type of the printer is determined. The CPU 401 is the printer controller 43
An ID indicating the type is acquired from the printer via a command / status line included in the printer video I / F via the printer 03. The command / status line is a serial communication line that allows the printer controller and the printer to exchange commands / status on a one-to-one basis.

[0455] In step S3, the CPU similarly controls the scanner video I / O via the scanner controller 4302.
An ID indicating the type is acquired from the scanner through the command / status line included in F.

In step S4, a copy path suitable for the combination of the scanner and the printer, which is determined in steps S2 and S3, is determined. The determination of the copy path suitable for the combination of the scanner and the printer is prepared in the form of a table in advance in a memory such as a flash ROM that can be referred to by the CPU. There are the following combinations of scanners and printers suitable for each copy path. (Method 1) A combination in which the horizontal and vertical timings of the scanner and the printer are synchronized and the transfer rate of video data is also synchronized. (Method 2) The speed of the horizontal synchronization timing of the scanner and the printer is the same, and the vertical timing and the video are synchronized. Combination of data transfer speed not synchronized (Method 3) Vertical synchronization timing of scanner and printer,
The combination CPU having different horizontal synchronization timings and different video data transfer speeds selects an appropriate copy method from the above three methods by referring to a prepared table.

[0457] In step S5, a mode setting corresponding to the copy method selected in step S4 is made to the scanner controller 4302. This mode setting is
PU performs via BBus.

FIG. 101 shows the scanner controller 430.
FIG. 2 is a diagram showing a circuit for switching a data bus inside the device; The data bus selector is included in the scanner device I / F 4401 in FIG. Further, a scanner video clock unit and the like which are not necessary for explaining the switching of the data bus are omitted.

In register 1, the mode of the data bus is set. The CPU sets a mode corresponding to the copy method selected in step S4 of FIG. Select control signal 4 is a signal for selecting a data path according to the mode set in mode setting register 1. The scanner video bus 2 is a bus for video data from the scanner. The bus 5 uses video data from the scanner as a FIFO. This is a bus for transferring to the SCC6. The CP video bus 7 is a bus used when performing the (method 1) copy operation. The data path is selected so that video data from the scan video bus is output to the CP video bus 7 in the case of (method 1). In the case of (method 2) and (method 3), video data is output to the bus 5 and the FIFO 5 Transferred to SCC4407.

In FIG. 100, the flow shifts to step S6. In step S6, the GBI The scc operation mode is set. This mode setting is performed based on the copy method selected by the CPU in step S4. In (method 1), G
BI Scc is designated as non-operational. In (method 2), D
Master transfer is designated for MA transfer, and GBI is prc is set. In (method 3), the master designation of the DMA transfer is made, and the SDR is
AM is set.

Next, in step S7, the GBI The operation mode of prc is set. This mode setting is performed based on the copy method selected by the CPU in step S4. (Method 1) uses GBI For prc, non-operation is designated.
In (method 2), slave designation for DMA transfer is performed.
In (method 3), the master designation of the DMA transfer is performed,
The SDRAM is set as the read source of the DMA transfer.

Next, in step S8, the mode of the printer controller is set. This mode setting is performed by the CPU based on the copy method selected in step S4.

FIG. 102 shows the printer controller 430
FIG. 3 is a diagram showing a data bus switching circuit in the internal circuit 3; The data bus mode is set in the register 11. C
The PU sets the mode corresponding to the copy method selected in step S4 of FIG. The select control signal 14 is a signal for selecting a data bus according to the mode set in the mode setting register 11. Bus 15 is FIFO This is a bus for data output from the PRC 16. Bus 12 is a video data bus to the printer. The CP video bus 17 is used when performing the (method 1) copy operation. In the case of (method 1), the video data to the printer selects and outputs the data on the CP video bus. In the case of (method 2) or (method 3), data from the bus 15 is output to the printer video bus 12.

[0464] In step S9, the flow of the copy method selection at the time of turning on the power supply ends. As described above, the CP
U can determine the copy method according to the type of scanner and printer.

The above procedure is for determining the type of copy operation based on the vertical synchronization timing and horizontal synchronization timing of the scanner and the printer, and the transfer rate of video data. However, this does not apply to cases where That is, before step 2 in FIG. 100, it is determined whether or not to process the image data. If the image data is to be processed, method 3 is selected regardless of the specifications of the scanner and the printer.
In the settings in 5 to S8, each block is set so that the data path is the method 3. By doing so, when the image data is processed, the read image data is temporarily stored in the memory, so that necessary processing can be performed on the image data there.

[0466] In the method 2 or 3, a bus is used. At this time, whether to use the G bus or the B bus is determined according to the usage status of each bus. That is, if both the G bus and the B bus are in the idle state, the G bus having a wide bus width is used. If any are in use, use the unused one.

As described above, in DoEngine, the scanner is the scanner controller 4302
And GBI It is connected to buses (G bus and B bus) via SCC4301A. Scanner controller 4
302 and GBI SCC4301A is FI
They are connected so as to transfer image data to each other via the FO. Thus, since each has a FIFO, the GBI has a 64-bit width and an operation clock of 1
Despite being connected to a very high-speed G bus of 00 MHz, image data read from a relatively low-speed scanner can be efficiently transferred. this is,
The same applies to the printer controller.

Further, by selecting a data path at the time of copying in accordance with the coincidence or non-coincidence of the respective synchronization signals of the scanner and the printer, the data can be transmitted as quickly as possible regardless of the specifications of the scanner and the printer. Copying can be performed using data transfer.

That is, by connecting the scanner and the printer to the DoEngine bus using the above-mentioned scanner controller and printer controller and their respective GBIs, the DoE from the specifications of the scanner and the printer can be obtained.
This has made it possible to further increase the independence of ngine. [Other Configuration Examples] The operation procedure of the cache shown in FIGS. 9 and 10 may be as shown in FIGS.

In FIG. 103, when data transfer is started from the MC bus, m is first indicated by the MC bus.
It is determined by TType [60: 0] whether the transfer is performed with the cache on or off. Here, when the transfer is a burst transfer, the determination is made based on whether the burst transfer data amount is larger or smaller than the data amount of one line of the cache. One line of the cache is 256 bits = 4
It is a burst amount.

In FIG. 103, the memory controller checks mTType [3: 0] at the start of transfer, and
If the burst length indicated by TType is 1/2/4, the operation is performed with the cache turned on, and 6/8/16/2 × 16/3 ×
In the case of 16/4 × 16, it operates with the cache off. The operation after the cache is turned on or off is shown in FIGS.
Is the same as

As shown in FIGS. 105 and 106, the cache can be switched on / off depending on the device. In FIG. 105, the memory controller identifies the transfer request device by checking mTType [6: 4] at the start of transfer, and determines whether the transfer request of the device operates with the cache on or off. For this purpose, it is determined whether to operate with the cache on or off with reference to a preset value of the configuration register. The operation after the cache is turned on or off is the same as in FIGS. The setting of the configuration register may be determined (cannot be changed) by hardware or may be rewritable by software.

(Embodiment) <Division of Job> First, an embodiment of the present invention will be described.
This will be described with reference to FIGS. In this embodiment,
In order to process various jobs input to the digital MFP in page units, acquisition and release of devices are performed in parallel to process information.

FIG. 107 is a block diagram of an information processing system according to the present invention. In FIG. 107, 101a, 102a, 1
A host computer 03a generates various jobs and transmits the jobs to peripheral devices. A digital multifunction peripheral 104a executes various jobs such as a print job, a scan job, a fax job, and a copy job.
The first and second host computers 101a and 102a and the digital multifunction peripheral 104a are each connected to a LAN (local area network) 105a,
The digital multifunction peripheral 104a can be used.

Also, the third host computer 103a
Is a digital multifunction peripheral 104 via an interface 106a such as a parallel (or serial) instead of a LAN.
a, and the digital multifunction peripheral 104a can be used.

FIG. 108 is a block diagram showing a basic configuration of the information processing system shown in FIG. 107. In FIG. 108, reference numeral 201a denotes a CPU (Central Processing Unit), which controls the entire system and performs arithmetic processing and the like. I do. An engine interface (engine I / F) 207a exchanges commands and the like for actually controlling the engine.

Reference numeral 208a denotes a network interface (network I / F).
The device is connected to the network via 08a.

209a is an external interface (external I
/ F), it is connected to a host computer via an interface such as parallel (or serial). 21
Reference numeral 0 denotes a system bus, which serves as a data path between the above-described components.

A CPU 201a, an engine interface (engine I / F) 207a, a network interface (network I / F) 208a, and an external interface (external I / F) 209a are DoEngine.
201 (FIG. 2).

Reference numeral 202a denotes a ROM (Read Only Memory), which is a storage area for a system startup program, a program for controlling a printer engine, character data, character code information, and the like. A RAM (random access memory) 203a is a storage area having no expiration date, in which font data additionally registered by downloading is stored, and programs and data are loaded and executed for various processes.

Reference numeral 204a denotes an external storage device such as a hard disk, which spools a print job (print job) received by the printing device (printer), stores programs and various information files, and is used as a work area. Is done.

Reference numeral 205a denotes a display unit such as a liquid crystal display, which is a setting state of the printing apparatus, a current processing state inside the printing apparatus,
Displays error status, etc.

An operation unit 206a is used to change or reset the settings of the printing apparatus.

FIG. 109 is a diagram showing the internal software structure of the host computer and the digital multifunction peripheral 104a. In FIG. 109, reference numeral 301 denotes the host computer (FIG.
07 corresponding to 101a to 103a). 302
Denotes controller software, in which the protocol interpreter 303, the job controller 304, and the device 30
It is divided into five.

The protocol interpreting unit 303 interprets a command (protocol) transmitted from the host computer 301 via the LAN 105 in FIG. 1 or the external I / F 209 in FIG. This is the part that requests execution. Also, the job control unit 304
Is a part for actually processing the job requested by the protocol interpreting unit 303. Further, the device unit 305 is used when the job control unit 304 executes a job.

FIG. 110 shows the controller software 3
FIG. 2 is a block diagram for explaining an outline of the second embodiment. In the figure, reference numeral 303 denotes a protocol interpreting unit, 304 denotes a job control unit, and 305 denotes a device unit. Job control unit 304
Has a job generation unit 401a, a job processing unit 402a, a document processing unit 403a, a page processing unit 404a, a band processing unit 405a, and a device allocation unit 406a.

The device section 305 includes a first device 407a, a second device 408a, and a third device 40a.
9a.

The host computers 101a to 101a to
A series of operation requests sent from the network interface 103a are transmitted as a command (protocol) in the form of a network I / F 208.
a and the external I / F 209a. The sent command is interpreted by the protocol interpreting unit 303 and then sent to the job control unit 401a. At this point, the command is converted into a form that the job control unit 304 can understand.

[0489] The job generation unit 401a generates a job 410a. Various jobs such as a copy job, a print job, a scan job, and a fax job can be considered as the job 410a.

For example, in the case of a print job, it also includes the setting information such as the name of the document to be printed, the number of copies to be printed, the designation of the output tray, and the print data itself (PDL data). The job 410a is sent to the job processing unit 402a,
Processing is performed. Here, settings (such as collectively printing and stapling a plurality of documents) and processing relating to the entire job 410a are performed.

Further, the job processing section 402a divides the job 410a into input documents 411a, which are smaller units of work, except for the settings and processing relating to the entire job 410a.
The input document 411a is sent to the document processing unit 40
The document is converted into an output document 414a by 3a.

That is, for example, considering a scan job in which a bundle of documents is read by a scanner and converted into a plurality of image data, an input document 411a describes settings and operation procedures related to the bundle of documents. An output document 414a describes settings and operation procedures for a plurality of image data. The document processing unit 403a has a role of converting a bundle of paper into a plurality of image data.

[0493] The document processing unit 403a performs only processing in units of documents, and generates an input page 412a that is a smaller unit of work. This is the same as the case where the job processing unit 402a concentrates on processing on a job basis and generates a document for more detailed work. The setting and operation in the document unit specifically relate to page order such as page rearrangement, double-sided printing designation, display addition, OHP insertion, and the like.

The input page 412a is converted into an output page 415a by the page processing section 404a. For example, in the case of the above-described scan job, the input page 4
Settings and procedures such as reading resolution and reading direction (landscape / portrait) are written in 12a, and the storage location of image data (address and data name of the RAM 203a and the external storage device 204a) is written in the output page 415a. Settings and procedures are written.

With the above processing, it becomes possible to handle the job configuration by decomposing it in page units.

In an expensive system, if a page memory for one page can be provided, the job may be finally detailed in page units. However, in reality, when the cost of the memory is a problem or when the print engine is at a low speed such as an ink jet printer, a system having only a few lines of memory (band memory) may be considered. In such a case, the page is divided into bands, which are smaller units. That is the input band 413a, the band processing unit 40
5a, the role of the output band 416a. These operations are similar to those of the page.

[0497] Job processing unit 402a, document processing unit 403a, page processing unit 404a, and band processing unit 4
05a uses a device when proceeding with the process. If a plurality of processing units work simultaneously, device contention occurs, and the device arbitration unit 406a mediates the conflict. First to third devices 407a to 407
09a is a device assigned to the processing unit by the device assignment unit 406a.

Examples of the device include a page memory, a band memory, a document feeder, a marking engine, and a scanner.

(Processing of Composite Job) FIG. 110 shows a process of decomposing a single job into pages and allocating devices. Next, processing of a combined job will be described with reference to FIG.

The “composite job” is, for example, a scan job and a print job if the job is a copy job, and a data reception job and a print job of the received data if the job is a FAX reception job. And divided into Devices are allocated to the divided jobs on a page basis and are processed. Hereinafter, the processing content will be described. Note that the basic configuration of the information processing system is the same as in FIGS. 107 to 109 described in the above-described division of a single job, and therefore, these drawings will be used as necessary.

FIG. 111 is a diagram showing details of the software structure of peripheral devices in the information processing system for processing a composite job. In the figure, reference numeral 303 denotes a protocol interpreting unit, 304 denotes a job control unit, and 305 denotes a device unit.

[0502] The copy job is divided into two jobs (scan job and print job) in the job control unit 304 and processed. A series of operation requests sent from the host computers 101a to 103a in FIG. 107 are sent in the form of commands (protocols) via the network I / F 208a and the external I / F 209a in FIG.

[0503] The sent command is interpreted by the protocol interpreting unit 303 and then sent to the job control unit 304. At this point, the command is converted into a form that the job control unit 304 can understand. Job generation unit 401
a generates the job 410a of FIG. In the present embodiment, a copy job is generated.

[0504] The generated copy job 513 is shown in FIG.
The scan job 514 and the print job 521 are sent to the first composite job processing unit 501. The scan job 514 and the print job 521 are sent to the scan job processing unit 502 and the print job processing unit 506, respectively, at the same time as the generation. Of course, the printing operation cannot be started unless the scanning operation starts and data to be output to the printer 512 is completed (or ready). Therefore, the processing units (502, 503, 504, 50
5) and a processing unit (506, 507, 50) related to printing
8, 509), the process proceeds while synchronizing via an intermediate document 518, an intermediate page 519, and an intermediate band 520 which mean intermediate data. In the copy job, the scanner 51 is used as a device to be used.
0, page memory 511, and printer 512.

FIG. 115 is a block diagram showing an example of job division. If the command sent from the host computer 301 is a copy job, the job control unit 30
The processing of No. 4 further divides the copy job into a print job and a scan job, and a device (eg, printer, scanner, memory, etc.) for processing the divided job
Are assigned, and the processing proceeds.

As described above, by dividing a job into pages and allocating and releasing devices for executing respective processes in combination with the above-described DoEngine, efficient control of the multifunction peripheral is achieved. The possibilities are described below.

The flow of data when a copy operation is performed using the DoEngine block in FIG. 4 will be described.
In this case, a scanner and a printer are assigned as processing devices (514 and 521 in FIG. 5).
In the case of the scan job (514), image data from the scanner is controlled by the scanner controller 4302 and written into the memory 403 via the GBUs 404 and the system bus bridge 402. In the case of a print job, the data written in the memory 403 is sent to the printer controller 4303 via the system bus bridge 402 and BBus 405, and is subjected to print processing. Dua
By adopting the l-Bus configuration, the occupation of the Bus is eliminated, and the CPU and the memory can be accessed in parallel. The output can be performed in parallel with the data input and the output in parallel.

That is, the copy job 513 in the processing of FIG.
Scan job 514 and print job 52 obtained by dividing
1 can be processed in parallel.

[0509] The allocation and release of devices when performing input / output processing in page units using DoEngine will be described below.

FIG. 113 shows a scanner (printer) as an example of a processing system device and a conventional case where processing is performed serially on a job basis (FIG. 113 (a)).
FIG. 113 is a timing chart showing device allocation and release when processing is performed in parallel in page units (FIG. 113B).

In the case of FIG. 113A, the device of job 1 is allocated to the scanner at time T1 and released at time T2. Subsequently, the printer is assigned at time T3 and released at time T4. Scanner processing required for the subsequent job 2 is assigned at time T5.
The time zone from T2 to T4 in the processing of job 1 is the idle time of the scanner, and is the dead time for job 2.
After releasing the scanner (time T6), the printer of job 2
It is allocated at time T7 and released at time T8.

[0512] Here, "dead time" refers to a time during which a device as a resource is in a processable state but cannot start processing due to a process of information to be input.

[0513] On the other hand, in the case of FIG. 113 (b), the device for job 1 is allocated to the scanner at time T1 and released at time T2. Before the scanner is released (time T2), the process is parallelized by DoEngine.
Printer assignment is performed (time T1a). The assignment of the scanner to the job 2 becomes possible after the time T2. For example, when there is a scanner assignment request at T1c, the time from T1c to T2 is the standby time until scanner assignment.

Similarly, the printer can be allocated before the scanner is released (time T1d), allocated after time T1b, and released at time T1f. When the printer allocation request is received at time T1e, T1e is changed to T1b.
The time period up to is a waiting time until the printer is assigned. In the above description, copy jobs are described as examples.
The same applies to the case of processing copy and facsimile, copy and PDL print, and the like. The throughput of jobs 1 and 2 is reduced to T8-T1f when comparing (a) and (b).

[0515] Here, the "waiting time" refers to the time during which data to be processed is already prepared and the device is waiting for release, and enables parallel processing of input / output data.
This is different from the related art in that the in-process data is eliminated. The arbitration by DoEngine, which reflects conditions such as the priority of a job, is controlled by DoEngine, so that the “standby time” can be optimized (minimized).

[0516] The job unit includes FAX transmission / reception, PDL printing, copying, and the like. The device allocating unit 406a allocates the first to third devices 407a to 409a.
Devices include, for example, page memory and band memory,
Document feeders, marking engines and scanners are also included.

FIG. 114 shows copy jobs 513a and 51
FIG. 3B is a block diagram in a case where 3b is generated. Even when various base jobs are generated, as described above, the same applies in that page division is performed and devices are allocated and released in parallel.

[0518] The system bus bridge 402 and Dual
According to the DoEngine architecture using -Bus (GBus404, BBus405), it is possible to eliminate data processing conflicts, and a memory conventionally held locally in an interface or the like becomes unnecessary. Information can be shared by the centrally managed memory 403.

(Improvement of real-time property) FIG.
In the configuration shown in FIG. 08, the processing unit that requires real-time performance and the processing unit with low real-time performance use a common CPU. However, by using DoEngine as a satellite and using CPUs properly, real-time performance It can be further improved.

[0520] Instead of the configuration in Fig. 107, a configuration as shown in Fig. 115 (a) may be used. In FIG. 115 (a), P
C115-1 and C115-2 are host computers, and 115-3 is a satellite PC equipped with DOEngine. Since DOEngine has a PCI bus interface, it can be used with computer systems having PCI bus slots. The scanner 115-4 and the printer 115-5 have a PCI satellite configuration connected to the PC 115-3 via a PCI slot. FIG. 115 (b) is a diagram (115-6, 115-) in which a host computer and a satellite PC are connected in parallel.
7) is a diagram connected to a next-generation multifunction peripheral (MFP) via a PCI bus.

(Satellite DoEngine) FIG. 116
Is the DOEn in the satellite PC shown in FIG.
FIG. 4 is a block diagram relating to connection of a Gine. In the figure, the DOEngine 116-1 includes a CPU 401, and preferentially processes a job having a high real-time property.

Reference numeral 116-2 denotes a ROM (read only memory), which is a storage area for a system startup program, a program for controlling the printer engine, character data, character code information, and the like.

Reference numeral 116-3 denotes a RAM (random access memory) which is a storage area with no expiration date, in which font data additionally registered by download is stored, and programs and data are loaded and executed for various processes. .

[0524] Reference numeral 116-4 denotes an external storage device such as a hard disk, which spools a print job (print job) received by the printing device (printer), stores programs and various information files, and stores a work area. Used as

[0525] Reference numeral 116-5 denotes a display unit such as a liquid crystal display, which displays a setting state of the printing apparatus, a current processing state in the printing apparatus, an error state, and the like.

An operation unit 116-6 is used for changing or resetting the settings of the printing apparatus.

[0527] Reference numeral 116-7 denotes an engine interface (engine I / F) for exchanging commands and the like for actually controlling the engine.

Reference numeral 116-8 denotes a network interface (network I / F).
The device is connected to the network via 208a.

An external interface (external I / F) 116-9 is connected to a host computer via an interface such as parallel (or serial). 2
Reference numeral 10 denotes a system bus, which serves as a data path between the above-described components.

FIG. 117 is a diagram showing the configuration of software corresponding to FIG. In the figure, a part having a low real-time property and a part having a high real-time property are divided and processed. The entire processing is not performed by a single CPU, but is processed by a host computer. The overall processing is not performed by a single CPU, but the processing is selectively used by the host computer and the satellite computer, whereby the load on the CPU can be reduced and the processing capacity of the entire system can be improved.

For example, the protocol interpreter 11 shown in FIG.
The processing of 7-3 requires a PC
117-2 (for example, PCs 115-1, 11 in FIG. 115)
The command processed and interpreted by the CPU of 5-2) is a PC
The data is sent to the satellite computer 117-6 (PC115-3 in FIG. 115) via the I bus, and is transmitted to the DoEngine.
Is processed in real time by the CPU. The transmitted command is job-controlled by the satellite computer (11).
7-4), device allocation and release are performed (117-).
5).

[0532]

As described above, the conflict between the input and output of image information is eliminated by the system bus bridge and the DoEngine architecture using Dual-Bus.
Data used by each device for processing image information can be shared by a centrally managed memory.

[0533]

[Brief description of the drawings]

FIG. 1 is a diagram of a configuration example of an apparatus or a system using DoEngine.

FIG. 2 is a diagram of a configuration example of an apparatus or a system using DoEngine.

FIG. 3 is a diagram of a configuration example of an apparatus or system using DoEngine.

FIG. 4 is a block diagram of DoEngine.

FIG. 5

FIG. 6 is a block diagram of an interrupt controller 410.

FIG. 7 is a block diagram of a memory controller 403.

FIG. 8 is a detailed block diagram mainly showing a cache controller 706;

FIG. 9 is a flowchart showing a cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 10 is a flowchart showing a cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 11 is a diagram showing a configuration of a ROM / RAM controller 707.

FIG. 12 is a timing chart showing the timing of burst reading from the CPU.

FIG. 13 is a timing chart showing the timing of burst writing from the CPU.

FIG. 14 is a timing chart showing the timing of burst reading from a G bus device.

FIG. 15 is a timing chart showing the timing of burst write from a G bus device.

FIG. 16 is a timing chart showing the timing of a single read when a hit occurs in a memory front cache.

FIG. 17 is a timing chart showing the timing of a single read when no hit occurs in the memory front cache.

FIG. 18 is a timing chart showing the timing of a single write when a hit occurs in a memory front cache.

FIG. 19 is a timing chart showing the timing of a single write when no hit occurs in the memory front cache.

20 is a block diagram of a system bus bridge (SBB) 402. FIG.

FIG. 21 is a block diagram of a B bus interface.

FIG. 22 is a block diagram of a G bus interface 2006.

FIG. 23 is a diagram of a virtual memory map, a physical memory map, a memory map in a G bus address space, and a memory map in a B bus address space.

FIG. 24 shows a hatched portion 5 in FIG. 23 including a register and the like;
FIG. 4 is a diagram of a map showing 12 megabytes.

FIG. 25 is a block diagram of an address switch 2003.

FIG. 26 is a block diagram of a data switch 2004.

FIG. 27 is a timing chart of a write / read cycle from the G bus.

FIG. 28 is a timing chart of a burst stop cycle of the G bus.

FIG. 29 is a timing chart of a G bus transaction stop cycle.

FIG. 30 is a timing chart of a G bus transaction stop cycle.

FIG. 31 is a timing chart of a G bus transaction stop cycle.

FIG. 32 is a timing chart of a G bus transaction stop cycle.

FIG. 33 is a block diagram of a PCI bus interface 416.

FIG. 34 is a block diagram of a G bus arbiter (GBA) 406.

FIG. 35 shows a G bus 4 in DoEngine 400.
DMA by bus master on G bus centered on 04
FIG.

FIG. 36 is a diagram illustrating an example of a fair arbitration mode (fair mode) when the number of times of continuous use of the bus is set to 1 for all of the bus masters 1 to 4;

FIG. 37 is a diagram illustrating an example of the fair arbitration mode when the number of times of continuous bus use is 2 for only the bus master 1 and the other bus masters are set to 1;

FIG. 38 is a diagram illustrating an example of a priority arbitration mode when the number of times of continuous use of the bus is one and the bus master 1 is set as a priority bus master.

FIG. 39 is a diagram showing an example in which a bus request from the bus master 1 is interrupted even though the bus request from the bus master 4 is permitted.

40 is a block diagram of a B bus arbiter 407. FIG.

FIG. 41 is a block diagram of a synchronization unit 4001.

FIG. 42 is a diagram of one compare unit in the synchronization unit.

FIG. 43 is a block diagram of a scanner / printer controller.

FIG. 44 is a block diagram of a scanner controller 4302.

FIG. 45 is a block diagram of a scanner device I / F4401.

FIG. 46 is a block diagram of a scanner video clock unit 4402.

FIG. 47 is a block diagram of a scanner video data mask 4601.

FIG. 48 is a block diagram of a scanner video data mask 4602.

FIG. 49: Scanner video data width converter 4603
It is a block diagram of.

FIG. 50 shows color image data (24 bits) for each of 8 bits of RGB.
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 51 shows color image data (32 bits) for each of 8 bits of RGB.
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 52 is a diagram showing an arrangement of 8-bit monochrome image data on a memory.

FIG. 53 is a diagram showing the arrangement of binary black and white image data on a memory.

FIG. 54: Using a BW8 packing unit 4901
FIG. 9 is a timing chart when converting multi-valued 8-bit monochrome image data to a 64-bit width.

FIG. 55 is a timing chart of image data input when binary black-and-white image data is converted into a 64-bit width by the shift register 4902.

FIG. 56 shows an RGB packing unit 4903.
RGB image data of 8 bits (24 bits in total) is 64
It is a timing chart at the time of converting into a bit width.

FIG. 57 is a block diagram of an RGB packing unit 4903.

FIG. 58 is a block diagram of a scanner image data transfer FIFO controller 4403.

FIG. 59 is a block diagram of a scanner controller control register 4404.

60 is a block diagram of the IRQ controller 4406. FIG.

FIG. 61 is a block diagram of a memory fill mode controller 4405.

FIG. 62 is a timing chart when data is read from the scanner controller 4302 and DMA-transferred.

FIG. 63 is a timing chart for reading or writing to an internal register of the scanner controller 4302.

FIG. 64 is a diagram illustrating a relationship between a value of a signal sccDmaPmState and a state of a clock and a value of a signal sccPmState.

FIG. 65 is a diagram summarizing signals input and output between a core portion including each block and an external bus or scanner in the scanner controller 4302.

FIG. 66 is a block diagram of a printer controller 4303.

FIG. 67 is a block diagram of a printer device I / F6601.

FIG. 68 is a block diagram of a printer video clock unit 6602.

FIG. 69 is a block diagram of a printer video data mask 6801.

FIG. 70: Printer video synchronization control unit 6
802 is a block diagram.

FIG. 71 is a block diagram of a video data width converter 6803.

FIG. 72 shows color image data (24 bits) for each of 8 bits of RGB.
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 73 shows color image data of 32 bits each of RGB (32 bits).
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 74 is a diagram showing the arrangement of 8-bit monochrome image data on a memory.

FIG. 75 is a diagram showing the arrangement of binary monochrome image data on a memory.

FIG. 76 is a block diagram of an RGBOut unit 7101.

FIG. 77 is a block diagram of a printer image data transfer FIFO controller 6603.

FIG. 78 is a block diagram of a printer controller control register 6604.

FIG. 79 is a block diagram of an IRQ controller 6605.

FIG. 80 is a block diagram of an IRQ controller 6605.

FIG. 81 is a block diagram of a printer command / status control unit 6606.

FIG. 82 is a block diagram of an option controller control unit 6607.

FIG. 83: Data is sent to the printer controller 4303 by D.
It is a timing chart at the time of MA transfer.

FIG. 84 is a timing chart for reading or writing to an internal register of the printer controller 4303.

FIG. 85 is a diagram illustrating a relationship between a value of a signal pscDmaPmState and a clock state and a value of a signal prcPmState.

FIG. 86 is a diagram summarizing signals input and output between a core portion including each block and an external bus or scanner in the printer controller 4303.

FIG. 87 is a block diagram of a power management unit 409.

FIG. 88 is a block diagram of a bus agent.

FIG. 89 is a diagram illustrating blocks used in an image copying method in which image data is directly transferred from a scanner controller to a printer controller and copied.

FIG. 90 is a diagram illustrating blocks used in an image copy method in which image data is transferred from a scanner controller to a printer controller via a FIFO and copied.

FIG. 91 is a diagram showing blocks used in an image copy method in which image data is transferred from a scanner controller to a printer controller via a memory and copied.

FIG. 92 is a block diagram of GBI.

FIG. 93 is a block diagram of a FIFO unit.

FIG. 94 is a block diagram of a GBus controller.

FIG. 95 is a block diagram of a BBus controller.

FIG. 96 is a block diagram of a DMA controller.

FIG. 97 is a block diagram of a register unit.

FIG. 98 is a diagram illustrating a configuration example of a chain table.

FIG. 99 is a diagram showing a GBI core interface.

FIG. 100 is a flowchart of a procedure for selecting a copy method.

FIG. 101 is a diagram showing a data bus switching circuit inside a scanner controller 4302.

FIG. 102 is a diagram illustrating a data bus switching circuit inside a printer controller 4303.

FIG. 103 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 104 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 105 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 106 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 107 is a configuration diagram of an information processing system according to an embodiment of the present invention.

FIG. 108 is a block diagram showing a basic configuration of a peripheral device in the information processing system according to the embodiment of the present invention.

FIG. 109 is a diagram showing an outline of a software structure of a peripheral device in the information processing system according to the embodiment of the present invention.

FIG. 110 is a diagram showing details of a software structure of a peripheral device in the information processing system according to the first embodiment of the present invention.

FIG. 111 is a diagram illustrating details of a software structure of a peripheral device in the information processing system according to the second embodiment of the present invention.

FIG. 112 is a timing chart in the case where jobs are conventionally processed as one unit.

FIG. 113 is a diagram for describing processing for allocating and releasing devices.

FIG. 114 is a diagram for describing processing when a plurality of jobs are generated.

FIG. 115 is a diagram illustrating a configuration example of a system when DoEngine is used as a satellite.

FIG. 116 shows a system software process performed by two CPUs.
It is a figure explaining the case where processing is carried out separately.

FIG. 117 is a diagram illustrating an outline of a software structure when processing is divided by a plurality of CPUs.

[Explanation of symbols]

401 CPU 402 Bus bridge 403 Memory 404 G bus 405 B bus 406 G bus arbiter 407 B bus arbiter 4301A G bus / B bus interface (scanner) 4301B G bus / B bus interface (printer) 4302 Scanner controller 4303 Printer controller

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 16, 1999 (1999.4.1
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Information processing system for multifunction devices

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system for processing information regarding a complex device such as a printer, a facsimile (FAX), and a copying machine.

[0002]

2. Description of the Related Art Conventionally, an image processing apparatus called a composite apparatus such as a copier or facsimile combining an image input apparatus such as a scanner and an image output apparatus such as a printer, or a computer system having the same as a single unit has been put to practical use. Have been. In such a device, in order to realize a composite function such as an image input function, an image output function, and a copy function, if the image input device and the image output device cannot operate synchronously, the image input The copy function has been realized by outputting the image data once taken into the memory from the device to the image output device. When the image input device and the image output device can operate in synchronization, a copy function is realized by providing a path for directly transferring an image signal from the image input device to the image output device.

Conventional digital multifunction peripherals have been developed in the form of additional functions of conventional machines, such as those in which a fax function is added to a copying machine and those in which a printer function is added to a fax machine. Only the composite operation and the parallel operation in job units could be performed. In conventional digital multifunction devices, when it is not possible to secure a sufficient bus to transmit and receive various data to be
The configuration is such that a local memory is distributed in an interface unit such as a printer.

FIG. 112 is a timing chart for explaining job processing when control is performed on a job basis.
Print job 1 and print job 2 are jobs to be processed by the multifunction peripheral. Consider a case where these jobs acquire a certain resource (for example, page memory).
At time T1, the print job 1 previously input acquires the resource. At the timing of T2, the subsequent print job 2 acquires the resource, but the print job 1 occupies the resource (locks) and cannot acquire the resource.
The resource acquisition request is queued. And T3
When the print job 1 releases the resources at the timing of (1), the print job 2 acquires the resources and performs the processing in accordance with the resource acquisition request of the queued print job 2. In other words, during the time from T1 to T3, the print job 1 exclusively uses resources, so that the processes of the print job 1 and the print job 2 become serial.

[0005]

However, in the conventional digital multi-function peripheral, a series of jobs are processed in a job-by-job order and executed. Therefore, when a plurality of jobs are input to the digital multi-function peripheral. The next job is in a standby state until the processing of the preceding job is completed, and the throughput of the job is reduced.

[0006] In some cases, a locally secured memory stores redundant information for each device, and thus requires a redundant memory area larger than a necessary area.

Further, when a single CPU is used for processing having a difference in necessity of real-time processing, processing that requires real-time processing is sacrificed by processing that does not require real-time processing. Had been lowered.

[0008]

The system according to the present invention is for solving any of the above-mentioned problems, and is characterized mainly by the following constitution.

That is, the information processing system of the multifunction device includes an interface for inputting an image signal from the image signal input means, a first bus connecting the interface to a system bus bridge, and the input bus via the system bus bridge. A memory for storing the stored image signal, an interface for outputting the image signal from the image signal output unit, and a second bus connecting the stored image signal to the interface for outputting the image signal via the system bus bridge. It is characterized by having.

[0010] The information processing system of the multifunction peripheral includes an interpreting means for interpreting a procedure transmitted from the information processing apparatus, a job generating means for generating a job based on the interpretation of the procedure, and a Dividing means for dividing into constituent elements, device managing means for managing allocation and release of devices for processing the divided elements, means for writing processing results of the allocated devices to a memory, Means for outputting data written in the memory to another device.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a description will be given of "DoEngine" which is a single-chip scanning and printing engine including a processor core, a processor peripheral controller, a memory controller, a scanner / printer controller, a PCI interface and the like.

1. DoEngine Overview DoEngine is an R40 from MIPS Technology.
It is a single-chip scanning and printing engine with a built-in processor core, processor peripheral controller, memory controller, scanner / printer controller, PCI interface, etc. It is implemented using high-speed parallel operation and the building block method.

In a processor shell (general term for processor peripheral circuits including a processor core), a maximum of 32 Kbytes of cache memory of 16 Kbytes each of instructions and data, an FPU (floating point arithmetic unit), an MMU (memory management unit), It is possible to incorporate a user-definable coprocessor or the like.

Since it has a PCI bus interface, it can be used with a computer system having a PCI bus slot. In addition to the PCI satellite configuration, a PCI bus configuration can be issued in a PCI host bus bridge configuration. By combining with a low-cost PCI peripheral device, a main engine of a multifunction peripheral (multifunction peripheral) can be issued. It is also possible to use as. Furthermore, it is possible to combine with a rendering engine and a compression / decompression engine having a PCI bus interface.

An IO for connecting a general-purpose IO core inside the chip
It has two independent buses, a bus (B bus) and a graphic bus (G bus: Graphics Bus) optimized for image data transfer, and connects these buses with a memory and a processor via a crossbar switch. As a result, high-speed data transfer with high parallelism, which is essential for simultaneous operation in a multifunction system, is realized.

The memory has a synchronous DRAM (SDRAM) having the highest cost performance for accessing a continuous data string represented by image data.
In order to minimize the performance degradation of random access in small data units that cannot enjoy the advantages of SDRAM burst access high-speed data transfer, an 8-Kbyte 2-way set associative memory front cache is provided in the memory controller. . The memory front cache, even in a system configuration that employs a crossbar switch, in which bus snooping for all memory writes is difficult, without a complicated mechanism,
This is a system that can achieve high performance by a cache memory. In addition, it has a data interface (Video Interface) with a printer and a scanner capable of real-time data transfer (device control), and further supports hardware synchronization between devices and performs image processing to separate the scanner and printer. Also in the mold configuration, a high-quality and high-speed copy operation can be realized.

Note that DoEngine has a core of 3.3.
Operates at V and IO is 5V tolerant.

FIGS. 1, 2 and 3 show DoEngine
1 shows an example of the configuration of an apparatus or a system that uses the same.
FIG. 1 shows a personal computer 10 of a separated configuration type.
A local board 101 equipped with DoEngine is attached to 2 via a PCI interface provided therein. The local board 101 includes, in addition to DoEngine, a memory connected to DoEngine via a memory bus, which will be described later, and a color processing circuit (chip). The high-speed scanner 103 and the color / monochrome printer 104 are connected to the personal computer 102 via the local board 101. With this configuration, under the control of the personal computer, the local board 101 can process the image information input from the scanner 103 and output the image information from the printer 104.

FIGS. 2 and 3 show an example in which the scanner 203 and the printer 202 are integrated. FIG. 2 shows a configuration similar to a normal copying machine, and FIG. 3A shows a configuration of a facsimile machine and the like. ing. FIG. 3B shows a computer that controls FIG. 3A.

FIGS. 1 and 2 show DoP by an external CPU connected via a PCI interface.
FIG. 3 shows an example in which the engine is used in a slave mode in which the engine is controlled.
This is an example in which U is a main component and is used in a master mode for controlling a device connected via a PCI interface.

Table 1 shows the specifications of DoEngine. External interfaces include PCI, memory bus, video, general purpose input / output, IEEE1284, RS23
2C, 100baseT / 10baseT, LCD panel and key, but may further have USB. As a built-in block, a primary cache, a memory controller with a cache, a copy engine, an IO bus arbiter (B bus arbiter), a graphic bus arbiter (G bus arbiter), and the like are provided in addition to the CPU core. The DMA controller has five channels, and has a graphic bus (G bus) and an IO bus (B bus).
In both cases, arbitration is performed in a first-come-first-served manner with priority.

[0022]

[Table 1]

2. Configuration and operation of DoEngine In this chapter, in addition to the general description of DoEngine, a block diagram for each functional block, an overview, details, a core interface, a timing diagram, and the like are described.

2.1. DoEngine Chip Configuration FIG. 4 shows a block diagram of DoEngine. D
oEngine 400 is a next-generation multifunction peripheral (system) (MFP: Multi Function Peripheral or MFS: Multi
Function System) was designed and developed as the main controller.

As a CPU (processor core) 401,
Adopt MIPSR4000 core from MIPS Technology. In the processor core 401, instructions and data cache memory of 8 Kbytes each, M
MU and the like are implemented. The processor core 401 has 64
It is connected to a system bus bridge (SBB) 402 via a bit processor bus (SC bus). S
A BB 402 is a 4 × 4 64-bit crossbar switch, and is connected to a memory controller 403 for controlling an SDRAM or a ROM having a cache memory in addition to the processor core 401 by a dedicated local bus (MC bus). G bus 40 which is a graphic bus
4. Connected to the B bus 405, which is an IO bus,
Connected to two buses. System bus bridge 402
Is designed to ensure simultaneous parallel connection between these four modules as much as possible.

The G bus 404 is a G bus arbiter (GBA).
Coordinated control is performed by a control unit 406, which is connected to a scanner controller 4302 or a printer controller 4303 for connecting to a scanner or a printer. The B bus 405 is cooperatively controlled by a B bus arbiter (BBA) 407, and includes a scanner / printer controller, a power management unit (PMU) 409, an interrupt controller (IC) 410, and a serial interface controller (UART) using a UART. SIC) 411, U
SB controller 412, parallel interface controller (PIC) 41 using IEEE1284
3. LAN controller using Ethernet (LAN
C) 414, LCD panel, keys, general-purpose input / output controller (PC) 415, PCI bus interface (P
CIC) 416.

2.2. Processor shell A processor shell is an MMU in addition to a processor core.
(Memory Management Unit), an instruction cache, a data cache, a write-back buffer, and a block including a multiplication unit.

(Cache Memory) As shown in FIG. 5, the cache memory controller is invalid.
d) manages three state caches: valid and clean (Valid Clean: the cache has not been updated), and valid and dirty (Valid Dirty: the cache has been updated). The cache is controlled according to this state.

2.3. Interrupt Controller FIG. 6 shows a block diagram of the interrupt controller 410.

The interrupt controller 410 is connected to the B bus 405 via the B bus interface 605, integrates each functional block in the DoEngine chip and an interrupt from outside the chip, and has six levels of CPUs supported by the CPU core 401. Redistribute to external interrupts and non-maskable interrupts (NMI). Each functional block includes a power management unit 409,
Serial interface controller 411, USB
Controller 412, parallel interface controller 413, Ethernet controller 414, general-purpose IO controller 415, PCI interface controller 416, scanner controller 4302, printer controller 4303, and the like.

At this time, a mask register (Int Mask Logic 0-5) 60 capable of software configuration is used.
According to 2, it is possible to mask an interrupt for each factor. For the external interrupt input, the edge sensing / level sensing can be selected for each signal line by the selective edge detection circuit 601. A cause register (Detect and set Cause Reg 0-5) 603 indicates which interrupt is asserted for each level, and can perform a clear operation for each level by performing a write operation.

The interrupt signal of each level is output as a logical sum by the logical sum circuit 604 so as to output an interrupt signal if there is at least one interrupt for each level. The level assignment between a plurality of factors in each level is performed by software.

2.4. Memory Controller FIG. 7 is a block diagram of the memory controller 403. The memory controller 403 is connected via an MC bus interface 701 to an MC bus, which is a local bus dedicated to the memory controller, and supports a maximum of 1 gigabyte synchronous DRAM (SDRAM) and a 32 megabyte flash ROM or ROM.
64 (16 × 4) burst transfer is realized to take advantage of the high speed at the time of burst transfer, which is a feature of SDRAM. In consideration of single transfer of continuous addresses from the CPU and the B bus, an SRAM (memory front cache) 702 is built in the memory controller, and transfer efficiency is reduced by avoiding direct single transfer to the SDRAM as much as possible. Improve. The data bus width between the memory controller and the SDRAM is a total of 72 bits including the signals ramData and ramPar (of which the signal ramPar of 8 bits is parity), and the data buses fntromData and pr between the flash ROM.
The width of gromData is 32 bits.

2.4.2. Configuration and Operation The components of the memory controller are configured as described below.

(MC bus interface (701))
MC bus is SBB 402-memory controller 403
It is a dedicated bus between them and is used as a basic bus inside the SBB.

While the burst transfer of the dedicated bus PBus connecting the CPU 401 and the bus bridge 402 specifies only four bursts, the MC bus adds a transfer of up to 16 bursts × 4. For this purpose, mTType [6: 0] is newly defined as a signal indicating the burst length. (Definition of MC bus signal) Each signal of the MC bus is defined as follows. • mClk (output) ··· MC bus clock · mAddr [31: 0] (output) ··· MC bus address This is a 32-bit address bus and is held from the time when mTs_L is asserted until mBRdy_L is asserted. • mDataOut [63: 0] (output) ··· MC bus data output This is a 64-bit output data bus, and is valid only when mDataOe_L is asserted. • mDataOe_L (output) ... MC bus data output enable Indicates that mDataOut [63: 0] is valid. It also indicates that the transfer is a Write. • mDataIn [63: 0] (input) ··· MC bus data input This is a 64-bit input data bus, sampled at the rising edge of mClk where mBRdy_L is asserted. • mTs_L (output)… MC bus transaction start strobe Indicates that transfer has started. Asserted only during the first clock of the transfer. If the transfer is completed in one clock and the next transfer is started immediately, mTs_L will remain asserted. • mTType [6: 0] (output) ... MC bus transaction type Indicates the type of transfer on the MC bus. It is held during the single transfer and during the first transfer (beat) during the burst transfer. The upper 3 bits represent the source (master) and the lower bits represent the single / burst length. The types are as follows.

MTType [6: 4] Signal source --------------- -------------------- CPU CPU 010 B bus 100 G bus -------------- −−− mTType [3: 0] Single / burst length −−−−−−−−−−−−−−−−−− 1xxx Single (1-8 bytes) 0001 2 burst 0010 4 burst 0011 6 burst 0100 8 burst 0101 16 bursts 0110 2 × 16 bursts 0111 3 × 16 bursts 0000 4 × 16 bursts • mBE_L [7: 0] (output) ... MC bus transaction byte enable Indicates the valid byte lane on the 64-bit data bus during single transfer. At the time of burst transfer, it is effective only at the time of Write, and is ignored at the time of Read. • mBRdy_L (input)… MC bus ready Indicates that the current transfer (beat) has been completed.・ MTPW_L (output)… next transaction
In-page write (in-page write) Indicates that the next transfer is a write of the same page (same Row address), and up to four writes can be continued. The page size is set in the configuration register in advance. • mBPWA_L (input)… Write enable in-page write of bus Indicates whether the MC bus slave (memory controller) allows write-in-page transactions, mBWA_L (input)
Sampled at the same clock as Rdy_L. At this time mBP
If WA_L is deasserted, mTPW_L is meaningless. • mBRty_L (input) ... Bus retry Assert when the MC bus slave (memory controller) terminates access without executing it, and indicates that retry must be performed after idle for at least one cycle. (If mBRdy_L and mBRty_L are asserted at the same time, mBRty_L has priority.)-MBerr_L (input) ... Bus error This signal is asserted when a parity error or other bus error occurs.

The above-mentioned distinction between input and output is a definition from the viewpoint of the SBB. (MC bus transaction) The following transactions are supported as transactions on the MC bus. Basic transaction (1,2,3,4,8 bytes Read /
Write) According to the mBE_L [7: 0] signal, a single transaction of 1, 2, 3, 4, or 8 bytes is supported. Burst Transactions (from CPU) Supports transactions up to 4-doubleword burst. Supports up to four 16-doubleword burst transactions from the G bus. In-page write (in-page write) transaction Regarding the write in the same page indicated by mTPW_L,
Supports continuous Write access. Bus retry If memory access is not possible due to restrictions in the memory controller, the mBRty_L signal is asserted to notify bus retry.

(SDRAM Controller (705)) The memory controller 403 has the following configuration.
The DRAM is controlled as follows.

(DRAM Configuration) A DRAM has a 16/64 megabit S of x4, x8, and x16 bit type.
The DRAM can be controlled by eight banks using a 64-bit data bus.

[0041]

[Table 2]

(DRAM address bit configuration) DRAM
For the assignment of the address bits of
MA [13: 0] is used for a RAM, and MA [11: 0] is used for a 16-bit SDRAM.

[0043]

[Table 3]

(SDRAM Programmable Configuration (Mode Register)) The SDRAM has an internal mode register, and sets the following items using a mode register setting command. Burst Length The burst length can be set to one of 1, 2, 4, 8 and full page, but the burst length of 4 is optimal because the burst transfer length from the CPU is 4. Transfer of 16 bursts or more from the G bus is realized by continuously issuing a Read / Write command (without auto precharge). Wrap Type Set the increment order of addresses during burst transfer. Either “sequential” or “interleave” can be set. CAS Latency The CAS latency can be set to one of 1, 2, and 3, and is determined by the grade of SDRAM to be used and the operation clock.

(SDRAM command) The following commands are supported for the SDRAM. Details of each command are described in the SDRAM data book.・ Mode register setting command ・ Active command ・ Precharge command ・ Write command ・ Read command ・ CBR (Auto) refresh command ・ Self refresh start command ・ Burst stop command ・ NOP command (SDRAM refresh) SDRAM is 2048 cycles / 32ms (4096 / 64 ms), a CBR refresh command is issued every 16,625 ns. The memory controller has a configurable refresh counter and automatically sets the CBR
Issue a refresh command. During the transfer of 16-burst xn from the G bus, no refresh request is accepted. So the refresh counter is 16-burst x
4 You must set a value that has a margin for the transfer time. It also supports self refresh. When this command is issued, power down mode (ramclke_L
= Low), self-refresh is continued.

(SDRAM Initialization) After the power-on reset, the memory controller performs the following initialization on the SDRAM. That is, all banks are precharged using a precharge command after a pause period of 100 μs after power-on. Set the mode register of the SDRAM. Refresh is performed eight times using an auto-refresh command.

(Flash ROM controller (70
4)) The flash ROM controller 704 uses romAdd
r [23: 2] address signal and four chip select (romCs_
L [3: 0]) signals are supported. Address signals romAddr2 to r
omAddr9 is multiplexed with parity signals ramPar0 to ramPar7, and address signals romAddr10 to romAddr23 are
It is multiplexed with AM addresses ramAddr0 to ramAddr13.

(SRAM control (memory front cache)) SDRA used as main memory
M is very fast in burst transfer, but cannot exhibit high speed in single transfer. Therefore, a memory front cache is implemented in the memory controller to increase the speed of single transfer. The memory front cache includes a cache controller 706 and an SRAM.
702. MTType defined for MC bus
Since the transfer master and transfer length can be known from the [6: 0] signal, the cache can be turned on / off for each master or for each transfer length. The cache method is as follows. Hereinafter, unless otherwise specified, the term “cache” or “cache memory” refers not to a cache built in a processor core but to a memory front cache built in a memory controller. -2-way set associative-8k byte data RAM-128 x 21 x 2 tag RAM-LRU (Least Recently Used) algorithm-Write through-No Write Allocate Next, a detailed block diagram centering on the cache controller 706 is shown in FIG. Show.

(Cache Operation) Here, the cache operation when a memory read / write transfer is requested from the MC bus will be described with reference to the block diagram of FIG. 8 and the flowcharts of FIGS. 9 and 10.

When data transfer is started from the MC bus,
At the beginning of the transfer, whether or not the transfer is performed with the cache on or off is determined by mTType [6: 0] indicated on the MC bus. In this description, it is determined that the transfer is ON if the transfer is a single transfer and OFF if the transfer is a burst transfer (step S901). That is, if mTType (3) is "1" h, it indicates a single transfer, indicating cache-on, and if "0" h, indicates burst transfer, and indicates cache-off transfer.

In the case of single transfer (cache on),
When an address lmaddr [31: 0] is given, lmaddr [11: 5] is used as an index for b1_tag_ram801 and b2_tag_ram80.
2, b1_data_ram 702-a, b2_data_ram 702-b,
lru 803, from each block, valid bits "v" and b corresponding to the input index
1_tag_addr, valid bit "v" and b2_tag_addr, b1_o
ut_data, b2_out_data, and lru_in are output (step S902).

The b1_tag_addr and b2_tag_addr output from the b1_tag_ram 801 and b2_tag_ram 802 are respectively b1_com
address lmaddr with parater804, b2_comparater805
[31:12], and the result, that is, whether or not a hit is notified to the cache controller 706 by the b1_hit_miss_L and b2_hit_miss_L signals, and is determined (step S903).

If it is a hit here, it is determined whether it is read or write (step S904). A hit is an address lm in either b1_tag_addr or b2_tag_addr.
This is the case where there is a match with addr [31:12]. In the case of a hit and a lead, it is as follows. That is, b1
Is a hit and the requested transfer was a read, b1_out_data and b2_out_data already read
Select b1_out_data from among the 8 indicated by lmaddr [4: 3]
Byte data is output to the MC bus (step S90)
5). At the same time, lru corresponding to the index is set to “0”
(= b1 hit) and the transfer ends. If b2 is a hit and the requested transfer is a read, then b1_out_data and b2_out_data
b2_out_data is selected, and 8-byte data indicated by lmaddr [4: 3] is output to the MC bus (step S905).
At the same time, lru corresponding to the index is set to “1” h (= b2
Hit) and the transfer ends.

On the other hand, in the case of hit and write, the operation is as follows. That is, if b1 is a hit and the requested transfer is a write, it is indicated by an index
Of the 8-byte data indicated by lmaddr [4: 3] of b1_data_ram 702-a, only the valid byte lane indicated by mBE_L [7: 0] is rewritten, and lru corresponding to the index is set to “0” h (= b1 hit). Also SDR
The AM is similarly rewritten and the transfer is completed (step S9).
06). If b2 is a hit and the requested transfer is a write, b2_data_ram7 indicated by the index
Of the 8-byte data indicated by lmaddr [4: 3] of 02-b, only the valid byte lane indicated by mBE_L [7: 0] is rewritten, and at the same time, lru corresponding to the index is set to “1”.
Rewrite to h (= b2 hit). Similarly, the SDRAM is rewritten and the transfer is completed (step S906).

On the other hand, when both b1 and b2 are mistakes,
It is determined whether it is a read or a write (step S1001).
If the requested transfer was a read, its lmaddr [3
1: 3] is read from the SDRAM (step S1003) and output to the MC bus (step S1004). At the same time, lru corresponding to the index is read, and if it is “0” h, b2_da
Write data from SDRAM to ta_ram and lru also "1" h
Rewrite to If lru is "1" h, b1_data_r
The data from the SDRAM is written to am, and the rewriting of lru to "0" h is completed (step S1005). If both b1 and b2 are misses and the requested transfer is a write, the transfer is completed only by writing to the SDRAM (step S1002).

In the case of burst transfer (cache off) in step S901, both read and write
Performed only for AM (steps S907-S90)
9), rewriting of cache data and tags is not performed.

(ROM / RAM interface (70
7)) The configuration of the ROM / RAM controller 707 is shown in FIG.
It is shown in FIG. Blocks 1101 to 1104 multiplex the data signal, address signal, and parity signal of the SDRAM with the data signal and address signal of the flash ROM.

2.4.3. Timing Diagram FIGS. 12 to 1 show timings of processing of reading and writing data by the memory controller 403 described above.
9 will be described.

FIG. 12 shows the timing of burst reading from the CPU. The burst length is 4, and the CAS latency is 3. This corresponds to the processing in step S909 in FIG.

FIG. 13 shows the timing of burst write from the CPU. The burst length is 4, and the CAS latency is 3. This corresponds to the processing in step S908 in FIG.

FIG. 14 shows the timing of burst reading from the G bus device. G bus burst length is 1
6, the burst length of the SDRAM is 4, and the CAS latency is 3. This corresponds to the processing in step S909 in FIG.

FIG. 15 shows the timing of burst write from the G bus device. G bus burst length is 1
6, the burst length of the SDRAM is 4, and the CAS latency is 3. This corresponds to the processing in step S908 in FIG.

FIG. 16 shows the timing of single reading when a hit occurs in the memory front cache.
As the data mDataIn [63: 0] to be read, b1_data_ram 702-a or b2_data
b1 / b2_out_data read from the _ram 702-b is output. The burst length of the SDRAM is 4 and the CAS latency is 3. This corresponds to the processing in step S905 in FIG.

FIG. 17 shows the timing of a single read when no hit occurs in the memory front cache. As data mDataIn [63: 0] to be read, S
Data ramData [63: 0] read from the DRAM is output. This data is stored as b1 / b2_in_data in the cache memory b1_data_ram 702-a or b2_in_data.
It is also written to data_ram 702-b. The burst length of the SDRAM is 4 and the CAS latency is 3. This corresponds to the processing in steps S1004 and S1005 in FIG.

FIG. 18 shows the timing of a single write when a hit occurs in the memory front cache.
The data mDataOut [63: 0] to be written is the cache memory b1_data_ram 702-a or b2_data_ram7
02-b as well as SDRAM. The burst length of the SDRAM is 4 and the CAS latency is 3. This corresponds to the processing in step S906 in FIG.

FIG. 19 shows the timing of a single write when no hit occurs in the memory front cache. The data mDataOut [63: 0] to be written is the cache memory b1_data_ram 702-a or b2_data
The data is not written to the _ram 702-b, but is written only to the SDRAM. SDRAM burst length is 4, CA
The S latency is 3. Step S1002 in FIG.
Corresponds to the processing in.

Here, when data transfer is started from the MC bus, if the transfer is a single transfer, it is turned on by mTType [6: 0] indicated on the MC bus at the beginning of the transfer, and burst transfer is performed. If the burst length is smaller than one line of the cache, the cache is turned on; if not, the cache is turned off; otherwise, the cache is turned off. You may do so.

Also, by including in the MC bus a signal indicating the identifier of the bus master that has requested data transfer to the memory, the memory controller determines the identifier and controls cache on / cache off according to the identifier. You can do it. In this case, it is also possible to prepare a rewritable table in which the identifier is associated with the cache ON / OFF, and switch the cache ON / OFF with reference to the rewritable table. This table can be made rewritable by the CPU 401 or the like by assigning a specific address, for example.

2.5. System bus bridge (SBB)
FIG. 20 is a block diagram of a system bus bridge (SBB) 402.

The SBB 402 includes a B bus (input / output bus),
A multi-channel bi-directional bus bridge that provides interconnection between a G bus (graphic bus), SC bus (processor local bus) and MC bus using a crossbar switch. With the crossbar switch, two systems can be simultaneously connected, and high-speed data transfer with high parallelism can be realized.

The SBB 402 includes a B bus interface 2906 for connecting to the B bus 405 and a G bus 40
G bus interface 2006 to connect to
And a CPU interface slave port 2002 for connecting to the processor core 401, a memory interface master port for connecting to the memory controller 403, an address switch 2003 for connecting an address bus, and a data switch 2004 for connecting a data bus. including. Further, a cache invalidation unit 2005 for invalidating the cache memory of the processor core is provided.

The B bus interface 2009 has B
A write buffer for speeding up DMA writing from the bus device and a read prefetch queue for improving the efficiency of reading from the B bus device are implemented. Coherency management for data temporarily existing in these queues is performed by hardware. Note that a device connected to the B bus is called a device.

The processor core supports dynamic bus sizing for a 32-bit bus.
The BB 402 does not support this. In the future, even if a processor that does not support bus sizing is used, S
This is for minimizing the modification required for the BB.

2.5.1. Configuration and operation of SBB and each bus (B bus interface) FIG. 21 is a block diagram of the B bus interface.

The B bus interface 2009 is a bidirectional bridge circuit between the B bus and the MC bus. The B bus is a DoEngine internal general-purpose bus.

In the B bus interface 2009,
Master control block 2011, slave control block 2010, data interface 20
12, DMAC 2013, and 5 blocks of the B bus buffer. In FIG. 21, the DMAC 2013 is functionally divided into three sequencers and register blocks. Of these three sequencers, the DMA memory access sequencer sends a B bus slave control block 2010
The reg sequencer is built in the B bus master control block 2011. DMA as a register block
The register is built in the B bus data interface 2012 unit.

Further, the B bus interface 2009
At the time of writing to the memory from the bus side and when transfer from the device to the memory by DMA occurs, invalidation of both data and instruction caches in the CPU shell is controlled via the cache invalidation interface.

Although a write-back buffer for CPU write is not mounted on the B bus interface, a write buffer for external master write on the B bus is mounted.
As a result, continuous writing from an external master, which is not a burst transfer, is speeded up. The flushing of the write buffer is performed when the connection to the memory by the B bus arbiter 407 is permitted. The write buffer bypass for the B bus master read is not performed.

The read prefetch queue of the external master is executed. Thus, the speed of reading the continuous data stream from the external master is increased. To invalidate the read buffer: When a new read of the B bus does not hit the buffer. 2. When writing to the memory from the CPU is performed. 3. When data is written from the G bus to the memory. 4. When data is written from the B bus to the memory. Done in

The B bus interface 2009 incorporates a DMA controller 2013 between each device on the B bus 405 and the memory. System bus bridge 40
2 has a built-in DMA controller so that access requests can be issued to both bridges simultaneously, resulting in efficient DMA
Transfer can be realized. The B bus interface 2009 does not request the use of dynamic bus sizing in response to an access request from the processor 401. It also does not support bus sizing from the memory controller 403 when a memory access request is made from the B bus master. That is, the memory controller should not expect bus sizing.

(B Bus) The B bus is a general-purpose IO bus in DoEngine and has the following specifications. -Address / data separation type 32-bit bus.・ Any wait cycle can be inserted. The shortest is no wait. -Support for burst transactions.・ The maximum transfer speed is 200Mbyte / Se when the clock is 50MHz.
c. -Support for bus error and bus retry. -Support for multiple bus masters.

(B Bus Signal Definition) The definition of the bus signal will be described below. For each signal, it is described in the manner of "Signal name (English name): input source> output destination (, 3States) ... Explanation of signal". Note that the three-state item is described only for three-state signals.

BAddr [31: 2] (IOBus Address Bus): Mast
er> Slabe, 3State ... IOBus address bus.

BData [31: 0] (IOBus Data Bus): DataDr
iver> DataReceiver, 3State… IOBus data bus.

B (Datadrivername) DataOeReq (IOBus Data
Output Enable Request): Datadriver> DefaultDrive
rLogic… To realize the bidirectional IO bus described later,
Output signal to the default driver control logic. This is a request signal for a device having Datadrivername to drive data on the bus. For devices that are allowed to output data, b (Datadrivername) DataOe_L
Is output. Datadriver example: Pci, Sbb, Jpeg, Spu.

B (Datadrivername) DataOe_L (IOBus Data
Output Enable): dfaultDriverLogic> Datadriver
… B (Datadrivername) DataOe_ if the default driver logic allows driving the data to the data bus for the device that output b (Datadrivername) DataOeReq
Returns an L signal to the device.

BError_L (IOBus Bus Error): Slave> Ma
ster 3State ... Indicates that the IO bus transaction ended with an error.

B (Mastername) BGnt_L (IOBus Grant): Ar
biter> Master ... Indicates that this master has obtained the right to use the bus by bus arbitration. Mastername example: Pci, Sbb, Jpeg, Spu.

BlnstNotData (IOBus Instruction / Data O
utput Indicator): Master> Slave, 3State ... Drives high when the B bus master performs instruction fetch for the B bus slave. Drive low for data transactions.

B (Mastername) CntlOeReq (IOBus Master C
ontrol Output Enable Request): Master> DefaultDri
verLogic… B bus master is bStart_L, bTx_L, bWr_
Assert for IOBus Output Control Logic when you want to drive L, vInstNotData and bAddr [31: 2] on a three-state bus. The IOBus Output Control Logic returns a b (Mastername) CntlOe_L signal from each master to the master that permits driving based on bMCntlOeReq.

B (Mastername) CntlOe_L (IOBus Master Co
ntrol Output Enable): DefaultDriverLogic> Master
When the default driver logic permits driving for the master that has output b (Mastername) CntlOeReq, a b (Mastername) CntlOe_L signal is returned to the master.

BRdy_L (IOBus Ready): Slave> Master,
3State... The B bus slave asserts this signal to indicate that the current B bus data transaction will end the current clock cycle last. The B bus master knows from this signal that the current transaction will end in this clock cycle. b (Mastername) BReq_L (IOBus Bus Request): Master>
Arbiter... Indicates that the B bus master issues a bus use right request to the B bus arbiter.

BRetry_L (IOBus Bus Retry): Slave> Ma
ster 3State: The B bus slave requests the master to execute the bus transaction again.

B (Slavename) RdyOeReq (IOBus Slave Read
y Output Enable Request): Slave> DefaultDriverLog
ic… B bus slave is bRdy_L, bWBurstReq_L, bBur
If you want to drive stAck_L on a 3-state bus,
Assert for OBus Output Control Logic. IOB
us DefaultDriverLogic uses b (Slavenam
e) For slaves that allow driving based on RdyOeReq, b
(Slavename) Return RdyOe_L signal.

B (Slavename) RdyOe_L (IOBus Slave Ready
Output Enable): DefaultDriverLogic> Slave… b
(Slavename) If the default driver logic allows driving for the master that outputs RdyOeReq b (Slaven
ame) Return the RdyOe_L signal to its master.

BSnoopWait (IOBus Snoop Wait): SBB> N
extMaster... Indicates that the B bus interface is executing snooping of the cache to other devices connected to the B bus. Devices connected to the B bus cannot issue new transactions while this signal is asserted.

BStart_L (IOBus Transaction START): M
aster> Slave 3State... A signal indicating that the B bus master starts the B bus transaction, and the B bus slave can know the start of the B bus transaction by monitoring this signal.

BTx_L (IOBus Transaction Indicator Inp
ut): Master> Slave 3State... The B bus master asserts to the B bus slave to indicate that a B bus transaction is currently being executed.

BWBurstGnt_L (IOBus Burst Write Gran
t): Master> Slave, 3State… B bus master is B
Drives to indicate that a burst write is to be performed in response to a bus burst write request.

BWBurstReq_L (IOBus Burst Write Reques
t): Slave> Master, 3Stete ... B bus slave is B
Assert when requesting a bus master for berth and write.

BWr_L (IOBus Write Transaction Indicat
er): Master> Slave, 3State ... B bus master is B
Assert to the bus slave to indicate that the current transaction is a write.

BByteEn [3: 0] (IOBus Byte Enables): Da
taDriver> DataReceiver, 3State… Agent that drives data on B bus, bD corresponding to each bit
Drive high to indicate that the byte lane on ata [31: 0] is valid. Table 4 shows the correspondence between each line of this signal and the byte lane of bData.

[0103]

[Table 4]

BBurst_L (IOBus Extended Burst Reques
t): Master> Slave, 3Sate ... Indicates that the B bus master wants to perform an extended burst. Assert and negate timings are the same as bTx_L.

BBurstAck_L (IOBus Extended Burst Ackn
owledge): Slave> Maste, 3State ... Indicates that the B bus slave can perform an extended burst. Assert and negate timings are the same as bRdy_L.

BBurstShortNotLong_L (IOBus Burst Leng
th): Master> Slave, 3State: Indicates the burst length when the B bus master performs an extended burst. Assert and negate timings are the same as bTx_L, and the correspondence between the signal value and the burst length is as shown in Table 5.

[0107]

[Table 5]

The B bus signal is as described above. DoEn
The B bus (and G bus), which is a bus inside the Gine, has 10 or more functional blocks to be connected.
It is difficult to connect all the blocks with a separate bus. DoEngine employs an on-chip bidirectional bus.

(G Bus Interface) FIG. 22 is a block diagram of the G bus interface 2006. The outline is as follows.

(Overview of G Bus) The G bus is a bus defined to execute high-speed data transfer between image data processing units in the MFP one-chip controller DoEngine. 4G with 64-bit data bus
Supports byte (128 byte boundary) address space. Basically, transfer is performed with 16 beats (128 bytes = 64 bits × 16) as one long burst, and up to 4 long bursts (512 bytes = 16 beats × 4) can be continuously performed. (Transfer of 16 beats or less such as single beat is not supported.) (G bus signal definition) First, a symbol used for signal definition is determined. Immediately after the signal name, the direction of the signal is described as necessary. It is defined as follows. In (Input signal) ... Input signal to the bus agent Out (Output signal) ... Output signal from the bus agent InOut (Bi-Directional Tri-State signal) ... This is a bidirectional signal and is driven by a plurality of bus agents.
Only one agent drives at a time. The enable request signal of each agent that drives the signal is centrally managed by a default driver, and the default driver determines which agent drives. The default driver signal is driven when no agent issues an enable request or when a plurality of agents issue enable requests simultaneously. If the agent drives the signal low, it must drive high for one clock before and after. Signal assertion starts from the first drive.
This can only be done after the clock has elapsed. Basically, the signal is released at the next negated clock.

"_L" after each signal name indicates that the signal is low active. The description of the signal substantially conforms to the description of the B bus signal. The description is divided into system signals, address and data signals, interface control signals, and arbitration signals. The bus agent is a general term for a bus master and a bus slave connected to the bus.

(System Signal) gClk (G-Bus Clock)... Provides timing for all transactions on the G bus and is an input to all devices.

GRst_L (G-Bus Reset)... Resets all devices on the G bus. All internal registers are cleared and all output signals are negated.

(Address and data signals) gAddr [31: 7], InOut, (G-Bus Address): Master> Sla
ve ... All data transfer on the G bus is 128 bytes (16
Since the processing is performed in units of (beat), 25 bits of gAddr [31] to gAddr [7] support an address space of 4 Gbytes. drive: gTs_L and the master drive at the same time. assert: next clock after driving negate: gAack_L is the clock that confirmed assertion.

G (Mastename) AddrOeReq (G-Bus Address O
utPut Enable Request): Master> DefaultDriverLogic
... Output signal to default driver logic to realize bidirectional G bus. Request signal for the bus master to drive the address bus.

G (Mastername) AddrOe_L (G-Bus Address O
utPut Enablet): DefaultDriveLogic> Master… g
(Mastername) For the bus master that output AddrOeReq,
Signal indicating that the default driver logic allows the address bus to be driven.

GData [63: 0], InOut, (G-Bus Data): D
ataDriver> DataReceiver… A 64-bit data bus. The master drives when writing, and the slave drives when reading.

[Write] drive: The master drives at the same time as gTs_L. Where gSlvB
When sy_L is asserted, drive until it is negated. assert: The next clock after driving. change: The clock that confirmed the assertion of gAack_L, and then every clock thereafter. negate: A clock that confirms the assertion of gAack_L at the end of transfer or when a transfer stop request by gTrStp_L is confirmed.

[Read] drive: The slave drives at the same time as gAack_L. assert: If the slave is Ready, it is asserted at the next clock after driving, and if it is not Ready, it waits until it becomes Ready. change: The clock that confirmed the assertion of gAack_L, and then every clock thereafter. For read, every clock from the asserted clock. negate: At the end of transfer. release: One clock after negation or a clock that confirms a transfer stop request by gTrStp_L.

G (DataDrivername) DataOeReq (G-Bus Data
OutPut Enable Request) ： DataDriver ＞ DefaultDrive
rLogic… Request signal for the data driver to drive the data bus.

G (DataDrivername) DataOe_L (G-Bus Data
OutPut Enablet): DefaultDriverLogic> DataDriver
… G (DataDrivername) This signal indicates that the default driver logic allows the data driver that outputs DataOeReq to drive the data bus.

(Interface control signal) gTs_L (InOut G-Bus Transaction Sart): Master> Sla
ve: Asserted low for one clock by the master, indicating the start of transfer (address phase). The master drives gAddr, gRdNotWr, and gBstCnt together with gTs_L, and clarifies the type of transfer and the amount of data. The master must ensure that the transfer data amount specified here can be issued without weight in the case of a write. In the case of a read, it must be guaranteed that the specified transfer data amount is received without any wait. GBsStep_L if the slave cannot transfer data in the middle
As a result, the transfer of the next 16 beats may be canceled. However, there is no cancellation in the middle of 16 beats. drive: Drives with the clock that confirms the assertion of gGnt_L. assert: The next clock after driving. negate: Negate after one clock assertion.

G (Mastername) TsOeReq (G-Bus Transactio
n Start OutPut Enable Request): Master> DefaultDr
iverLogic… Request signal for the bus master to drive gTs_L.

G (Mastername) TsOe_L (G-Bus Transaction
Start OutPut Enablet): DefaultDriverLogic> Maste
r ... A signal indicating that the default driver clock permits driving of gTs_L to the bus master that has output g (Mastername) TsOeReq.

GAack_L, InOut, (G-Bus Address Acknow
ledge): Slave> Master ... Driven low for one clock by the slave. The relevant slave recognizes the transfer, confirms that the bus is free, and informs the master that data transfer can be started. In the case of a write, the slave must ensure that it receives the transfer data amount requested by the master without waiting. In the case of a read, it must be ensured that the requested transfer data amount can be output without waiting. If data cannot be transferred in the middle, gBst
The transfer of the next 16 beats can be canceled by Stp_L. However, it cannot be canceled in the middle of 16 beats. drive: At the time of an address decode bit, driving is started with a clock that confirms assertion of gTs_L. Where gS
When lvBsy_L is asserted, wait until it is negated and drive. If the drive has not been driven yet because the data bus is in use, the drive is started with the clock that has confirmed the transfer stop request by gTrStp_L. assert: If the slave is Ready, it is asserted at the next clock after driving, and if it is not Ready, it waits until it becomes Ready. In response to a transfer stop by gTrStp_L, it is asserted at the next clock after driving. negate: When gTrStp_L is asserted after driving, it is asserted at the clock that confirms gTrStp_L. It is negated after one clock assertion.

G (Slavename) AackOeReq (G-Bus Address A
cknowledge OutPut Enable Request): Slave> Default
DriverLogic… Request signal for the slave to drive gAack_L.

G (Slavename) AackOe_L (G-Bus Address Ac
knowledge OutPut Enablet): DefaultDriverLogic> Sl
ave ... A signal indicating that the default driver logic permits gAack_L to be driven for slaves that output g (Slavename) AackOeReq.

GSlvBsy_L, InOut, (G-Bus Slave Bus
y): Slave> Master ... Indicates that the slave is driving and data is being transferred on the data bus. drive: When the address decode hits, drive starts with the clock that confirms assertion of gTs_L. Where gSlvBsy_L
When is asserted, wait until negated and drive. assert: If the slave is Ready, the next clock after driving. If not, wait until it becomes Ready and assert. negate: Negate at the end of transfer. release: One clock after negation or a clock that confirms a transfer stop request by gTrStp_L.

G (Slavename) SlvBsyOeReq (G-Bus Slave B
usy OutPut Enable Request): Slave> DefaultDriverL
ogic… Request signal for the slave to drive gSlvBsy_L g (Slavename) SlvBsyOe_L (G-Bus Slave Busy OutPut En
able): DefaultDriverLogic> Slave… g (Slavenam
e) A signal indicating that the default driver logic permits the slave that outputs SlvBsyOeReq to drive gSlvBsy_L.

GRdNotWr, InOut, (G-Bus Read (High) / Wr
ite (Low)): Master> Slave ... Driven by the master, High indicates READ, LOW indicates WRITE. The driving period is the same as GA. derive: Master drives at the same time as gTs_L. assert: Next clock driven. negate: Clock that confirmed assertion of gAack_L.

G (Mastername) RdNotWrOeReq (G-Bus Read /
Write OutPut Enable Reques): Master> DefaultDrive
rLogic… Request signal for the bus master to drive gRdNotWr.

G (Mastername) RdNotWrOe_L (G-Bus Read / W
rite OutPut Enablet): DefaultDriverLogic> Master
... A signal indicating that the default driver logic permits gRdNotWr to drive the bus master that output g (Mastername) RdNotWrOeReq.

GBstCnt [1: 0], InOut, (G-Bus Burst Cou
nter): Master> Slave ... Indicates the number (1 to 4) of burst transfers that are driven by the master and performed continuously. Table 6 shows the correspondence between the signal value and the number of bytes to be burst-transferred. derive: Master drives at the same time as gTs_L. assert: Next clock driven. negate: Clock that confirmed assertion of gAack_L.

[0134]

[Table 6]

G (Mastername) BstCntOeReq (G-Bus Burst
Counter OutPut Enable Request): Master> DefaultDr
iverLogic… Request signal for the bus master to drive gBstCnt.

G (Mastername) BstCntOe_L (G-Bus Burst C
ounter OutPut Enablet): DefaultDriverLogic> Maste
r ... A signal indicating that the default driver logic permits gBstCnt drive for the bus master that output g (Mastername) BstCntOeReq.

GBstStp_L, InOut, (G-Bus Burst Sto
p): Slave> Master: Indicates that the slave is driven by the slave and cannot accept the next successive burst transfer. Assert at the 15th beat of 1 burst (16 beats) transfer. If you do not stop, do not drive. drive: 14th beat. assert: 15th beat. negate: After clock assertion, g (Slavename) BstStpOeReq (G-Bus Burst Stop OutPut E
nable Request): Slave> DefaultDriverLogic…
Request signal for the slave to drive on gBstStp_L.

G (Slavename) BstStpOe_L (G-Bus Burst St
op OutPut Enablet): DefaultDriverlogic> Slave…
This signal indicates that the default driver logic permits gBstStp_L to be driven for slaves that output g (Slavename) BstStpOeReq.

(Arbitration signal) g (Mastername) Req_L, Out, (G-Bus Request): Master
> Arbiter: Driven by the master, requesting a bus from the arbiter. Each master device has its own gReq_L. assert: Master that needs data transfer is asserted negate: Negative if gGnt_L is received g (Mastername) Gnt_L, In, (G-Bus GNT): Arbiter> Ma
ster: Driven by the arbiter, grants the next bus right in response to a bus request. Each master device has a dedicated gGnt_L. Bus rights are given in order from the bus master with the highest priority. Bus rights are given to masters of the same priority in the order in which bus requests are made. assert: Assert for the master selected by arbitration when gGnt_L is not given to another master or when gGnt_L given to another master is negated at the next clock. negate: Clock that confirmed assertion of gAack_L gTrStp_L, In, (G-Bus Transaction Stop): Arbiter
> Master, Slave… driven by arbiter, gGnt
Abort the transaction whose address phase has already been started by _L. However, transactions that have already started the data phase with gAack_L cannot be aborted. This signal is masked by gAack_L, and when gAack_L is asserted, it is negated and output even if asserted. assert: When a bus request comes from a master with a higher priority than the transaction that has already started the address phase. negate: Clock that confirms assertion of gAack_L (G bus write cycle) The G bus write cycle is as follows. Master requests bus, gReq_L asserted. Arbiter allowed, gGnt_L asserted. gReq_L negate. Upon receiving gGnt_L, the master receives gTs_L, gAddr, gRdNotWr, gBs
Drive tCnt. In the case of a write operation, gData is also driven at the same time unless gSlvBsy_L is asserted. If gSlvBsy_L is driven, wait for gSlvBsy_L to become free before driving. The slave decodes the address when gTs_L is asserted, and recognizes that the transfer is for itself if hit. At this time, if gSlvBsy_L is not asserted by another slave, driving of gSlvBsy_L and gAack_L is started. In the case of read, gData is also driven. If gSlvBsy_L is asserted by another slave, the data bus is in use,
Wait until it is negated and start driving. gSlvBsy_
After the drive of L, gAack_L, (gData) starts, if the slave is ready for data transfer, it asserts each signal and starts data transfer. The address phase ends when gAack_L is asserted, and the master negates gAddr, gRdNotWr, and gBstCnt. Also, from that point on, the master switches the write data every clock, and transfers the data by the data amount specified by gBstCnt. The master and the slave must each count the clock on their own and know that the data transfer has ended.

If the slave cannot transfer the data transfer amount requested by the master during the transfer, bStStp
By asserting _L at the 15th beat, the transfer of the next 16 beats can be canceled, however, it cannot be canceled in the middle of the 16 beats.

When gBstStp_L is asserted, the master and the slave must end the data transfer at the next clock.

(Cache Validation Unit (CIU)) The cache validation unit (hereinafter, CIU) 2005 monitors a write transaction from the B bus to the memory, and when this occurs, before writing to the memory is completed. In addition, using the cache validation interface of the CPU shell, the CPU
Invalidate the cache built into the shell.

The CPU shell uses the following three types of signals.・ SnoopADDR [31: 5] (Cache Invalidation Address) ・ DCINV (Dcache (data cache) Invalidation St
robe) ・ ICINV (Icache (Instruction Cache) Inv
alidation Strobe) The invalidation of the cache is performed in a maximum of three clocks. Since the writing from the B bus to the memory does not end in three clocks, the cache invalidation unit 20
No. 05 does not perform invalidation end handshake using the Stop_L signal output from the CPU shell 401. However, in preparation for future changes, bSnoopWait on B bus
Is driven for the same cycle as Stop_L.

In the current implementation, when writing from the B bus occurs, Icache is also invalidated for safety. If the self-modifying code is prohibited by the OS, it is used as an instruction. If you intentionally invalidate the instruction cache when loading data that might be affected, you don't need Icache invalidation. In this case, a slight performance improvement can be expected.

(Memory Map) FIGS. 23 and 24 show memory maps. FIG. 23 shows, in order from the left, a virtual memory map, a physical memory map, a memory map in the G bus address space, and a memory map in the B bus address space. FIG. 24 is a map showing 512 Mbytes indicated by hatching in FIG. 23 including registers and the like.

The memory model of the processor core is based on R3000. The physical address space of the processor core is 4 Gbytes by 32-bit addressing. The virtual space similarly performs 32-bit addressing. The maximum size of the user process is 2 GB. Address mapping differs between kernel mode and user mode. The figure shows a memory map when the MMU is not used.

(User Mode Virtual Addressing) In user mode virtual addressing, a 2 Gbyte user virtual address space (kuseg) is valid. The address of this user segment starts at 0x00000000 and all valid accesses have msb cleared to zero.
In the user mode, referencing the address where msb is set causes address error exception handling. TLB kuseg
Map all references to in user mode and kernel mode as well. It is also cacheable.
kuseg is usually used to hold user code and data.

(Kernel Mode Virtual Addressing) The virtual address space in the kernel mode has four address segments.・ Kuseg 2 GB from virtual address 0x00000000.
Caching and mapping per page and unit is possible.
This segment overlaps with kernel memory access and user memory access. -Kseg0 512 Mbytes from the virtual address 0x80000000. Directly mapped to the first 512 Mbytes of physical memory. References are cached, but TLB is not used for address translation. kseg0 is usually used for kernel executable code and kernel data. -Kseg1 512 Mbytes from the virtual address 0xA0000000. Directly mapped to the first 512 Mbytes of physical memory. References are not cached and TLB is not used for address translation. kseg1 is usually I / O
Used for registers, ROM code, and disk buffers. -Kseg2 1 GB from virtual address 0xC0000000. k
Similar to useg, a virtual address is mapped to a physical address by TLB. Caching is free. OS is usually kseg
Use 2 for per-process data that needs to be remapped by stack or context switch.

(Virtual address memory map (FIG. 23)
(A), FIG. 24 (a))) The virtual address space is 4 Gbytes, and all memories and I / O on the system can be accessed. There is SYSTEM MEMORY (1GB) in kuseg.

Kseg0 has a built-in RAM (16 MB).
This is implemented if you want to program the exception handling vector, and set the exception vector base address to 0x80.
Set to 000000. This address is
Maps to 0x00000000.

There are ROM, I / O, and registers in kseg1. Boot ROM (16 MB), SBB internal registers and MC
Internal register (16MB), IOBusI / O1 (16MB: Primitive B bus register such as G bus arbiter internal register, B bus arbiter internal register, PMU internal register, etc.), IOBusI
/ O2 (16MB), IOBusMEM (16MB), Gbus MEM (32MB), FONT ROM (2
40MB), FONT ROM or RAM (16MB).

For kseg2, PCI I / O (512MB), PCI MEM (512MB)
Exists.

Since both kseg0 and kseg1 are mapped to the first 512 Mbytes of the physical address space, kseg0, kseg1
The first 512 Mbytes of eg1 and kuseg all refer to the same physical address space.

(Physical address memory map (FIG. 23)
(B), FIG. 24 (b))) The physical address space is also 4 Gbytes like the virtual address space, and all memories and I / O on the system can be accessed.

The PCI I / O, PCI MEM, and SYSTEM MEMORY are the same as the virtual address memory map.

Since kseg1 and kseg2 are both mapped to the first 512 Mbytes of the physical address space, the ROM, I / O,
Reg exists in the space from 0x00000000.

(G bus memory map (FIGS. 23 (c), 24 (c))) The G bus address space is 4 Gbytes,
Only SYSTEM MEMORY, GBus MEM, and FONT are accessible.

(B bus memory map (FIGS. 23 (d), 24 (d))) The B bus address space has 4 Gbytes,
PCI I / O, PCI MEM, SYSTEM MEMORY, IOBusI / O2, IOBus MEM,
Only FONT is accessible.

Since IOBus I / O1 is a primitive register, the space from 0x1C000000 to 0x20000000 is protected from PCI and cannot be accessed from PCI.

(Address Switch) Address Switch 2
Reference numeral 003 is for transmitting an address signal from the master bus to the slave bus via the SBB 402 in order to transfer data between the SC bus, the G bus, the B bus, and the MC bus. In the transfer via the SBB 402, the buses that can be the master are the SC bus, the G bus, and the B bus, and the buses that can be the slaves are the B bus, M bus.
C bus. SC bus, G bus, B for MC bus
Either of the buses serves as a master, and only the SC bus serves as a master to send an address signal to the B bus.

The transfer between the SC bus and the B bus and the transfer between the G bus and the MC bus can be performed simultaneously.

FIG. 25 is a block diagram of the address switch 2003. The switch sequencer 2003a switches the switch 2003b to switch the slave between the B bus and the MC bus, and switches 2003c to switch the master between the SC bus, the G bus, and the B bus.
With this configuration, the SC bus, G bus,
One of the B buses becomes the master, and the B bus is SC
Only the bus becomes the master, and the transfer between the SC bus and the B bus and the transfer between the G bus and the MC bus can be performed simultaneously.

(Data Switch) The data switch is SC
When data is transferred between the bus, the G bus, the B bus, and the MC bus, the flow of data is switched within the SBB. Data is sent from the master to the slave during writing, and from the slave to the master during reading.

FIG. 26 is a block diagram of the data switch 2004. In this configuration, the selectors A-1 to A-
3 and B-1 and B-2 are switched as shown in Table 7, so that any one of the SC bus, G bus and B bus is used as a master and any one of the B bus and MC bus is used as a slave to perform writing or reading. Can be controlled to do so.

[0165]

[Table 7]

(Arbitration) The switch sequencer 2003a in the SBB 402 performs arbitration between the following three types of connection requests from outside the SBB when switching each switch. 1. CPU 2. 2. G bus bus master B bus bus master This arbitration is determined by the current bus switch connection status and a preset priority, and as a result, the connection of the address switch and the data switch is switched.

(Timing Diagram) FIGS. 27 to 3
FIG. 2 shows a timing chart. FIG. 27 is a timing diagram of a write / read cycle from the G bus, FIG. 28 is a timing diagram of a burst stop cycle of the G bus, and FIGS.
FIG. 2 is a timing diagram of a G bus transaction stop cycle.

2.6. PCI Bus Interface FIG. 33 is a block diagram of the PCI bus interface 416.

The PCI bus interface 416 is
It is a block that interfaces between the B bus, which is an internal general-purpose IO bus, and the PCI bus, which is an external IO bus on the chip. Depending on the input pin setting, PCI at reset
It is possible to switch between a host bridge configuration that can issue a bus configuration and a target configuration that does not issue a PCI bus configuration.

The master DMA controller 3301 of the B bus interface receives DoEngine from the PCI bus master via the PCI bus signal interface 3302.
When an access request is made to a resource inside e, the access request is bridged into the B bus as a B bus master.

Further, the master DMA controller 330
1 is the DoE from the memory mapped on the PCI bus.
DMA transfer to NgineMemory can be performed. At this time, the transfer destination address (bPciAddr [31: 0]) and the PCI master controller 33 are used in order to operate in accordance with the order of access of the B bus DMA and the G bus DMA intended by the programmer.
An ID signal (bPciID) of 01 is issued to the B bus and the arbitration sequencer simultaneously with the bus request.

The master DMA controller 3301 receives the bus grant (bPciBGnt_L), and cancels the assertion of the ID signal (bPciID) when the data transfer is completed using the bus.

The PCI bus is a 33 MHz, 32-bit, PCI
2.1 compliant.

2.7. G Bus Arbiter FIG. 34 is a block diagram of the G bus arbiter (GBA) 406.

The arbitration of the G bus is a central arbitration method, and a dedicated request signal (g (mastername) Req_L) and a grant signal are provided to each bus master.
(g (mastername) Gnt_L). FIG. 34 shows that the mastername is
M1 to M4. The bus arbiter 406 supports up to four bus masters on the G bus and has the following features. The arbiter can be programmed by setting the register 3401a inside the arbiter. Register setting is performed from the B bus. There are a fair arbitration mode in which all bus masters have the same priority and the bus right is imparted fairly, and a priority arbitration mode in which the priority of one of the bus masters is raised and the bus is used preferentially. Which bus master is given priority is determined by the setting of the register 3401b. • It is possible to set the number of times that the priority bus master can use the bus continuously. -Supports a transaction stop cycle for stopping a transaction that has already started the address phase but has not started the data phase. -Programming of sequential processing in a plurality of bus masters can be performed (described later). The programmed order is stored in the register table 3401a. -When the G bus master and the B bus master sequentially write to the same memory address, as a mechanism for maintaining the access order intended by the programmer, a specific master is determined based on the master ID signal and stop signal from the synchronization unit. On the other hand, it has a mechanism to suspend giving the bus use permission.

The programming of the register is performed by B
This is performed from the CPU 401 via the bus.

(Arbitration sequencer) Arbitration sequencer 3 which is the core of G bus arbiter
In 402a and 402b, arbitration by five masters is performed between one priority master and the other four non-priority masters. Request signals and grant signals from the four bus masters are transmitted to a request dispatch circuit 3403.
And the grant dispatch circuit 3404 assigns four non-priority masters, thereby realizing a fair arbitration mode. In addition, by allocating one of the four bus masters to the priority master of the high-priority arbitration sequencer 3402a, it operates in the priority arbitration mode. These assignments are performed according to the settings of the registers 3401a and 3401b. As a result, the priority bus master can acquire the right to use the bus with a higher probability than other masters.

Further, in addition to adjusting the probability of acquiring a bus, the master assigned to the high-priority sequencer 3402a can use the bus continuously, and varies the number of times the bus can be used continuously using a programmable register. Can do things. This means that the occupancy of the bus can be adjusted so that a particular master can use more of the bus.

(Fair Arbitration Mode) In this mode, all bus masters have the same priority,
Opportunities to be granted the bus are fair. When the bus is free, the bus master that has issued the request first can get the bus right. When a plurality of bus masters issue requests at the same time, bus rights are sequentially given according to a predetermined order (round robin method). For example, if all the bus masters from M1 to M4 issue requests with the same clock, M1
The bus right is granted in the order of → M2 → M3 → M4. When all bus masters have issued requests again at the end of the transaction of M4, M1 → M2
Bus rights are granted in the same order, such as → M3 → M4 → M1 → M2. If some bus masters are issuing requests, round wrapping from M4 to M1 is given, and a grant is given to the master with the largest number closest to the master that last used the bus.

Once the bus right has been transferred to another bus master, the bus right cannot be obtained again until after all other requesting bus masters have been given the bus right.

(Priority arbitration) In this mode, one bus master (the bus master registered in the register 3401b) becomes a priority bus master having a higher priority than the other bus masters, and the bus right has priority over the other bus masters. Given. All bus masters other than the priority bus master have the same priority.

When a plurality of bus masters have issued requests and the priority bus master makes successive requests, the priority bus master and the other non-priority bus masters alternately obtain the bus right.

When the bus right is transferred from the non-priority bus master to another bus master, the bus right cannot be obtained again until after all other requesting bus masters have been granted the bus right. .

(Transaction Stop Cycle) In the priority arbitration mode, when a priority bus master issues a request, even if another bus master has already started an address phase, if the data phase has not yet started, the transaction is stopped. And the priority bus master can get the bus right. However, if the priority bus master has the bus right immediately before that, the number of times that the continuous bus right can be obtained cannot be exceeded.

At the end of the transaction of the priority bus master, if the suspended bus master has issued a request, the bus right is given priority.

(Switching of priority bus master) To switch the priority bus master, the register 3401b may be rewritten. When the register for selecting the priority bus master is rewritten, the priority bus master is switched after the completion of the transaction being executed at that time. The state of the arbiter returns to the idle state, and the bus master that has issued the request at that time performs the request at the same time, and arbitration is performed again.

Care must be taken when switching the priority bus master. If the priority bus master is switched to a different bus master before the DMA of the priority bus master ends, the priority of the DMA of the first priority bus master decreases. If you do not want to lower the priority of the first priority bus master, it is necessary to switch the priority bus master after confirming that DMA has ended.

In software that needs to dynamically switch the priority bus master not only at the time of system boot but also during the operation of the system, the switching of the priority bus master is performed so that a new DMA request is not generated on the G bus once. Of the G bus arbiter 406 is stopped, and then an appropriate value is set in a register in the G bus arbiter 406.
After checking the status register in 06 and confirming that the priority of the bus master has been switched, access to a new G bus and activation of DMA should be performed.

The dynamic switching of the priority bus master may change or violate the real-time guarantee of the operating system and the setting of the task priority, and must be performed with due consideration.

(Order Processing) FIG. 35 is a diagram showing DoEngine
FIG. 4 is a block diagram relating to DMA by a bus master on the G bus, centering on the G bus 404 in 400

When it is necessary for a plurality of bus masters to sequentially perform processing, for example, after processing A on the data in the memory 3501 by the bus master 1, then perform processing B by the bus master 2, and after the processing, A series of processes, such as sending the data to the bus master 4, will be considered.

Software for performing this processing, that is, C
According to the program executed by the PU 401, the order in which the bus master uses the bus, the start condition for granting the bus right, and the end condition are set in the register table 3401a in the bus arbiter 406 via the B bus 405. In this example, And so on. That is, G bus arbiter 4
06, upon receiving a signal set as a start condition from each bus master, gives the bus master the right to use the bus, and when receiving a signal set as an end condition, deprives the bus master of the right to use the bus.

[0193] The software sends DM to each bus master.
Set A. Thereby, each master is G
Request to bus arbiter 404 (g (mastername)
Req_L). The G bus arbiter 404 gives a bus right to the bus master 1 according to the order registered in the register table 3401a (gM1Gnt_L). The bus master 1 reads a certain unit of data from the memory 3501, performs process A, and writes data to a buffer inside the bus master 1. The bus master 1 notifies the arbiter 406 by the gM1BufReady signal that the processing of one unit is completed and the buffer is ready.

The arbiter 406 receives the bus right from the bus master 1 and gives the bus master 2 to the bus master 2 in accordance with the conditions for granting the bus right and the conditions for taking the bus right registered in the register table 3401a. The bus master 2 reads the data in the buffer of the bus master 1, performs the process B, and stores the data in the buffer inside the bus master 2. If the buffer of the bus master 1 becomes empty during this time, gM1BufEmpty is asserted, and the arbiter 406 stops giving the bus right to the bus master 2. The bus master 2 performs processing B, and when the buffer is ready, gM
Notify by 2BufReady signal.

The arbiter 406 receives it, and registers
In accordance with the contents of 401a, the bus right is given to the bus master 4 this time. The bus master 4 reads data from the buffer of the bus master 2. When the buffer of the bus master 2 becomes empty, the arbiter 406 is notified by gM2BufEmpty, and the arbiter 406 receives the notification and registers 3401a.
The bus right is again given to the bus master 1 according to the contents of the above, and the processing of the next data is started.

DMA set in each bus master
Is completed, each bus master notifies the processor by an interrupt. The software knows that a series of processing has been completed when all the bus masters have received the completion notification.

The operation described above is an operation in the complete sequential mode, and a bus master other than the bus master involved in the sequential processing cannot use the bus. Even during this sequential processing, a priority sequential mode is provided to enable a bus master unrelated to the sequential processing to use the bus. Switching between these modes is performed by programming a register inside the arbiter 406. In the priority sequential mode, a bus master performing sequential processing can use the bus preferentially, but a bus master not involved in the sequential processing is permitted to use the bus. Arbitration between a bus master that performs sequential processing and a bus master that is not involved is equivalent to the priority arbitration mode described above. As a matter of course, the bus masters who are not involved in the sequential process and whose turn is not turned because the conditions for granting the bus master are not satisfied are not given the bus master.

(Mechanism for Maintaining Access Order) When the signal stopSpc is asserted, the scanner controller / printer controller which is one of the G bus masters is excluded from the arbitration target, and even if the request is asserted, You are not entitled to use it. Arbitration is performed between masters excluding this master. A detailed description will be given in the section on the B bus arbiter.

(Timing Diagram) FIGS. 36 to 3
9, the timing of the G bus arbitration will be described. FIG. 36 shows that the number of times the bus is used continuously is
Fair arbitration mode when all bus masters 1 to 4 are set to 1 (fair mode)
This is an example. The second bus request (issued from timing 4) by the bus master 1 waits until all other bus masters issuing the bus request are processed one by one.

FIG. 37 shows an example of the fair arbitration mode when the number of times of continuous bus use is 2 only for bus master 1 and the other bus masters are set to 1. The second bus request (issued from timing 4) issued by the bus master 1 is granted immediately after the first request, and the other bus masters are kept waiting until the processing is completed.

FIG. 38 shows an example of the priority arbitration mode when the number of times of continuous use of the bus is 1 and the bus master 1 is set as the priority bus master. Because the priority bus master and the non-priority bus master are alternately granted the right to use the bus, the bus master 1
The second bus request is granted after the bus master 2 uses the bus, and the bus request from the bus master 4 is granted after the bus master 1 uses the second bus. The second bus request from the bus master 2 is acknowledged after all other bus masters issuing the bus request, in FIG. 38, the bus masters 1 and 4 have finished using the bus.

FIG. 39 shows an example in which the bus request from the bus master 4 is interrupted by the bus request from the bus master 1 even though the bus request is permitted. In this case, bus master 1
Is completed, the bus request from the bus master 4 is acknowledged in preference to the bus request from the bus master 2.

2.8. B Bus Arbiter FIG. 40 is a block diagram of the B bus arbiter 407.

The B bus arbiter 407 is a DoEngine
Accepts a bus use request of B bus 405, which is an internal IO general bus, and after arbitration, grants use permission to the selected one master, and prohibits two or more masters from accessing the bus at the same time. I do.

The arbitration system has three levels of priorities, and a plurality of masters can be assigned to each priority in a programmable manner. Allocation is maximum, with 3 masters at the highest priority, 7 masters at the middle, and 3 masters at the lowest level.

When the G bus master and the B bus master sequentially write data to the same memory address, as a mechanism for maintaining the access order intended by the programmer, a master ID signal and a stop signal from the synchronization unit are used. Based on this, it has a mechanism to suspend giving a bus use permission to a specific master.

(Arbitration Sequencer) The B bus arbiter has three arbitration sequencers 400.
2,4003,4004. Each has a high priority, a medium priority, and a low priority, and 3, 7, and 3 bus master arbitration sequencers are built in each sequencer. Request signals from units which may become all bus masters on the B bus and grant signals thereto are distributed to these three sequencer units by a request selector and a grant selector. In this distribution, a unique combination can be selected from a plurality of combinations by a software programmable register 4005a in the BBus interface 4005.

For example, by connecting requests of up to seven masters to the middle-priority arbitration sequencer 4003, fair arbitration is realized among the seven masters. Also, by allocating some of the bus masters to the high-priority arbitration sequencer 4002, these masters are more
The right to use the bus can be acquired with a higher probability.
In addition, some requests are sent to the low-priority sequencer 40.
04, the usage rate of these buses can be kept low. Further, in addition to adjusting the probability of acquiring a bus, the master assigned to the high-priority sequencer 4002 can use the bus continuously, and the number of times the bus can be used continuously can be changed by the programmable register 4005a. it can. This means that the occupancy of the bus can be adjusted so that a particular master can use the bus more time.

(Fair Bus Arbitration Method) A method of realizing fair arbitration will be described using the middle priority sequencer 4003 as an example. All bus masters connected to one sequencer have the same priority, and the opportunity to be granted the bus is fair. When the bus is free,
The bus master that has issued the request first can get the bus right (first come first serve).
When a plurality of bus masters issue requests at the same time, bus rights are sequentially given according to a predetermined order (round-robin at the time of issuing a simultaneous request). For example, if all bus masters from M1 to M7 issue requests with the same clock, M1 → M
The bus right is given in the order of 2 → M3 → M4 → M5 → M6 → M7. When all bus masters have issued requests again at the end of the transaction of M7, M1 → M2 → M3 → M4 → M5 → M6 → M7 → M1
→ The bus right is granted in the same order as in M2. If some bus masters are issuing requests, round wrapping is performed from M7 to M1, and a grant is given to the master having the largest number closest to the master that last used the bus.

(Priority Arbitration) The B bus interface has three arbitration sequencers of high priority, medium priority, and low priority. Arbitration with priorities is realized by selectively allocating a plurality of bus requests to high-priority and low-priority arbiters.

For example, by allocating one master with high priority and allocating the rest with medium priority, one bus master becomes a priority bus master having a higher priority than other bus masters, and has priority over other bus masters. Bus right is granted. All bus masters assigned to the arbitration sequencer having the same priority have the same priority.

When a plurality of bus masters have issued requests and the priority bus master makes requests continuously, the priority bus master and the other bus masters alternately obtain the bus right. When M3 is the priority master and M1, M2, M3, and M4 keep issuing requests, M3 → M1 → M3 → M2 → M
The right to use the bus is given in the order of 3 → M4 → M3 → M1.

Further, the high-priority bus master can obtain a continuous bus right for a preset number of times in a programmable register in the arbiter. The maximum number of times a continuous bus can be used is four.

When the bus right is transferred from a bus master other than the priority bus master to another bus master, the bus master cannot obtain the bus right again after giving the bus right to all other requesting bus masters. . When one bus master makes a request continuously, if there is no other requesting bus master, the bus mastership can be obtained continuously, but if another bus master makes a request, that bus master will The bus right can be continuously obtained a predetermined number of times. Once the bus right has been transferred to another bus master, the bus right can be obtained again only after all other requesting bus masters have been given the bus right.

The low-priority arbitration sequencer 40
04 can be assigned a maximum of three requests. The master assigned to the low-priority sequencer 4004 is not given the right to use the bus unless all master requests assigned to the medium-priority and high-priority sequencers are eliminated. The assignment of the bus master to this sequencer must be done with great care.

(Switching of priority bus master) To switch the priority bus master, the register in the arbiter may be rewritten. When the register for selecting the priority bus master is rewritten, the priority bus master is switched after the completion of the transaction being executed at that time.
The state of the arbiter returns to the idle state, and the bus master that has issued the request at that time performs the request at the same time, and arbitration is performed again.

Care must be taken in switching.
Before the DMA of the bus master to be prioritized ends,
If the priority bus master is switched to a different bus master, the priority of the DMA of the first priority bus master decreases. If you do not want to lower the priority of the first priority bus master, it is necessary to switch the priority bus master after confirming that DMA has ended.

In software that needs to dynamically switch the priority bus master not only at the time of booting the system but also during the operation of the system, the switching of the priority bus master is performed as follows.
Once the settings for all bus masters and DMA controllers are stopped so that no new DMA request is generated on the B bus, appropriate values are set in the registers in the B bus arbiter 407, and the status register in the B bus arbiter is set. Should be checked to confirm that the priority of the bus master has been switched, and then access to a new B bus and activation of DMA should be performed.

Dynamic switching of the priority bus master may change or violate the real-time guarantee of the operating system and the setting of the task priority.
This must be done with due consideration.

(Access Order Control Mechanism) The B bus arbiter 407 includes an access order control mechanism. The access sequence control mechanism includes a synchronization unit 4001 and a B bus arbiter 4.
07, a bus use right issuance suppression mechanism incorporated in the G bus arbiter 406. B bus arbiter 4
07 operates in the same manner as that of the G bus arbiter. That is, stopPci
When a signal is input, a bus request is issued from the Pci bus master, and as a result of arbitration, even if it is possible to give this master the right to use the bus,
The right to use the bus is not issued, and the right to use the bus is given to another master. Specifically, when the stopPci signal is input, this is immediately performed by masking bPciReq_L.

The bus request from the LAN controller 414 and the stop signal operate in exactly the same manner. FIG. 41 shows a block diagram of the synchronization unit 4001. In the synchronization unit, all the combinations between the plurality of DMA masters are compared with the comparison unit 4101.
To 4103 are connected, and in DoEngine, Gbu
The DMA master on s exists only in the scanner controller / printer controller. On the B bus, there are two units, a DMAPCI unit and a LAN unit. The B bus interface in the SBB is a bus master on the B bus, but does not directly access the memory.
1 does not output the ID and the transfer destination address.

FIG. 42 shows one comparison unit (Comparation Unit 1) in the synchronization unit. Other compare units have the same configuration.

The DMA attached to the PCI interface 416
When the DMA write is programmed from the block or the scanner controller / printer controller to the synchronization unit 4001, a transfer destination address and a request signal unique to the DMA block are notified.

Each compare unit stores an address together with the current time by a timer having an internal address when a request is output from each DMA block.
When the address and the request for the DMA write are input from the A block, the compare unit compares the two addresses. If a match occurs, the time stored in each register is compared, and the bus arbiter of the bus connected to the DMA block that issued the DMA write request later in time is strengthened to use the bus for this master. Not give. This is notified to the bus arbiter of each bus by a signal called stop (ID).

Each bus arbiter does not assign a bus use right by arbitration to the master notified by the stop (ID) signal.

When the time elapses and the DMA write to the relevant memory address is completed by the bus master that has made the access request first, the previous master withdraws the request to the synchronous unit. The bus arbiter of the bus connected to the DMA block that has issued the request is issued a bus use right permission / prohibition signal to this DMA block. And DMA later
The DMA write of the master to be written is performed.

When both DMA writes are completed and both requests are withdrawn, the timer is reset.
The count up of the timer is performed again when a request from one of the masters is output again.

2.9. Scanner Controller / Printer Controller FIG. 43 is a block diagram of the scanner controller / printer controller and its peripheral circuits. Scanner /
The printer controller controls the scanner and printer,
This is a block that interfaces with the G bus or the B bus. It is composed of the following three functional blocks. 1. Scanner controller Connected to the scanner via video I / F, and controls operation and data transfer. G bus / B bus I / F unit 430
1A is connected via an IF-bus, and data transfer and register read / write are performed. Data transfer has a master function. 2. Printer controller Connected to a printer via a video I / F and controls operation and data transfer. G bus / B bus I / F unit 430
1B is connected by an I / F-bus, and data transfer and register read / write are performed. Data transfer has both master and slave functions. 3. G bus / B bus I / F unit A unit for connecting the scanner controller 4302 and the printer controller 4303 to the G bus or the B bus. Respectively connected to the scanner controller 4302 and the printer controller 4302 independently,
Connect to G bus and B bus. 4. CP bus A bus for directly connecting image data and a synchronization signal for horizontal and vertical synchronization between the scanner and the printer.

2.9.1. Scanner Controller FIG. 44 is a block diagram of the scanner controller 4302. The scanner controller 4302 is a block that is connected to a scanner by a video I / F and interfaces with a G bus / B bus I / F unit (scc GBI) 4301A. G bus / B bus I / F unit (scc GBI) 43
01A is interfaced via the sccI / F-bus. It is roughly composed of the following blocks. 1. Scanner device I / F4401 Input / output port for inputting and outputting signals to and from the video I / F of the scanner. 2. Scanner video clock unit 4402 A unit that operates with the video clock of the scanner. 3. Scanner image data FIFO controller 4403 Controls a FIFO for transferring image data. 4. Scanner controller control register unit 4404 Register for controlling the entire scanner controller. 5. IRQ controller 4406 controls an interrupt signal generated inside the scanner controller (Scc). 6. Memory fill mode controller 4405 Controls the mode in which fixed data set in the register is transferred to the memory. Selectively switch to image data from the scanner. 7. FIFO (FIFO_SCC) 4407 This is a FIFO used when outputting a video data from the scanner and the output destination device may be asynchronous with the video data.

Note that the types of image data input from the scanner are as follows. RGB 8-bit color multi-valued data 2.8-bit black-and-white multi-valued data 3.1-bit black-and-white binary data are included.

Next, the outline of each block constituting the scanner controller will be described.

[1. Overview of Scanner Device I / F] Figure 4
FIG. 5 shows a block diagram of the scanner device I / F 4401. The scanner device I / F is an input / output port for inputting and outputting signals to and from the scanner video I / F 4501 of the scanner unit. The input video signals SVideoR [7: 0], SVideoG [7: 0] and SVideoB [7: 0] from the scanner video I / F are transferred to the scanner controller control register 44.
It is possible to switch whether or not the level is inverted in accordance with the VDInvt signal from the terminal 04.

[2. Overview of Scanner Video Clock Unit] FIG.
02 shows a block diagram of FIG. The scanner video clock unit 4402 is a block that operates on the video clock from the scanner. It consists of the following blocks. 1. Scanner video data mask 4601 This block performs data masking on image data from the scanner. The masked data becomes the data of the value set in the register. 2. Scanner video synchronization control unit 4602 This block generates a timing signal for capturing image data from a video clock, VSYNC, and HSYNC signals from the scanner. The number of lines and the number of lines of image data in the horizontal and vertical directions are managed. 3. Video data width converter This block packs the image data input from the scanner into 64-bit width data and converts the data.

(Outline of Scanner Video Data Mask) FIG. 47 is a block diagram of the scanner video data mask 4601. The scanner video data mask 4601 masks image data input from the scanner in pixel units. The masked image data has the value set by the register (RDMask [7: 0], GDMask [7: 0], BD
Mask [7: 0]).

(Outline of Scanner Video Synchronization Control Unit) FIG.
2 shows a block diagram of FIG. The scanner video synchronization control unit 4602 includes a vertical synchronization signal (SVSYNC) and a horizontal synchronization signal (SHSYN) for image data input from the scanner.
C), an enable signal (IVE) for the image data to be captured is generated by the image data synchronous clock (GTSVCLK).
In addition, it manages the delay of image data in the main scanning direction, the number of captured pixels, the delay in the sub-scanning direction, and the number of captured lines. Further, a state signal (PENDP) is generated at the timing when the capture of the set amount of image data is completed.

The line counter 4801 manages the delay in the sub-scanning direction and the number of fetched lines, and generates a vertical synchronizing signal (EH) of an image reading effective line. A pixel counter 4802 manages an image capture delay in the main scanning direction and the number of captured pixels. A page counter 4803 manages input image data in page units. When image data input for the set number of pages is completed, an end signal (ALLP
END).

(Scanner Video Data Width Converter 4
Outline of 603) FIG. 49 is a block diagram of the scanner video data width converter 4603. This is a unit for arranging image data input from the scanner in a 64-bit width. The arranged data is written to the FIFO as 64-bit data. The type of image data that can be input is RGB
There are three types: 8-bit color image data, multi-valued 8-bit monochrome image data, and binary 1-bit monochrome image data. Scanner controller control register 440
At 4, the mode is set. The mode includes a mode in which RGB color image data can be arranged in the memory in 24 bits and a mode in which 1 byte is added and arranged in 32 bits. The three types of image data are input from the following signal lines. 1. RGB 8-bit color image data… R [7: 0], G
[7: 0], B [7: 0] 2. Multi-valued 8-bit black-and-white image data... R [7: 0] 3.2 Binary 1-bit black-and-white image data... R7 The arrangement of 64-bit data and the arrangement on the memory are as follows.

[0238] 1. RGB 8-bit color image data (24-bit storage mode) First pixel R 8 bits → bits 63-56 First pixel G 8 bits → bits 55-48 First pixel B 8 bits → bits 47-40 Second pixel R 8 bits → Bit 39-32 second pixel G8 bit → bit 31-24 second pixel B8 bit → bit 23-16 third pixel R8 bit → bit 15-8 third pixel G8 bit → bit 7-0 , As shown in FIG.

[0239] 2. RGB 8-bit color image data (32-bit storage mode) First pixel R 8 bits → bits 63-56 First pixel G 8 bits → bits 55-48 First pixel B 8 bits → bits 47-40 Second pixel R 8 bits → Bit 31-24 8th bit of second pixel G → bit 23-16 8th bit of second pixel B → bit 15-8 The arrangement on the memory is as shown in FIG.

[0240] 3. Multi-valued 8-bit monochrome image data First pixel 8 bits → bits 63-56 Second pixel 8 bits → bits 55-48 Third pixel 8 bits → bit 47-40 Fourth pixel 8 bits → bits 39-32 fifth Pixel 8 bits → bits 31-24 6th pixel 8 bits → bits 23-16 7th pixel 8 bits → bit 15-8 8th pixel 8 bits → bit 7-0 As shown in FIG. is there.

4.2 1-bit monochrome image data 1st pixel 1 bit → bit 63 2nd pixel 1 bit → bit 62 3rd pixel 1 bit → bit 61 4th pixel 1 bit → bit 60: 61st pixel 1 Bit → bit 3 1st bit of the 62nd pixel → bit 2 1 bit of the 63rd pixel → bit 1 1 bit of the 64th pixel → bit 0 The arrangement on the memory is as shown in FIG.

Next, each packing unit will be described.

FIG. 54 shows a BW8 packing unit 49.
FIG. 11 is a timing chart when converting multi-valued 8-bit black and white image data into a 64-bit width in accordance with No. 01. The 8-bit black-and-white image data R [7: 0] from the scanner is captured when the signal VE goes high, and the signal LP0 is output pixel by pixel.
Latched to a 64-bit latch in synchronization with .about.LP7.
When eight pixels are aligned, 64 bits of the latched eight pixels are output as a signal BW8 [63: 0] in synchronization with the signal LP64.

FIG. 55 is a timing chart of image data input when converting binary black and white image data into a 64-bit width by shift register 4902. It is assumed that the binary black-and-white image data R7 (SVIDEOR0) from the scanner is captured when the signal VE goes high, shifted by one bit by a shift register, and captured by 64 bits. signal
The signal is output as a signal BW1 [63: 0] in synchronization with SVLATCH64.

FIG. 56 shows an RGB packing unit 49.
FIG. 3 is a timing chart at the time of converting image data of 8 bits (24 bits in total) of RGB into a 64-bit width. FIG. 57 shows an RGB packing unit 4903.
It is a block diagram of. In the figure, image data R [7: 0], G input from scanner video data mask 4601
[7: 0] and B [7: 0] are 24-bit data latches 5701
A and B are input. Data latches A and B are clocked
Latch signals L of opposite phases obtained by dividing CLK by 1/2
The 24-bit data respectively input in synchronization with P0 and LP1 are latched. The data latched in the data latches 5701A and 5701A is
02 is input as an input signal RGBHT [47: 0] and is a 32-bit signal DATA [31: 0] according to a 2-bit selection signal LP [3: 2].
Is output as There are three ways of outputting according to the value of the selection signal. First is the input signal RGBHT [47:16]
Is an output signal DATA [31: 0]. The second is
In this method, the input signal RGBHT [15: 0] is used as the output signal DATA [31:16], and the input signal RGBHT [47:32] is used as the output signal DATA [15: 0]. The third is to convert the input signal RGBHT [31: 0] to the output signal DATA
[31: 0].

The data latches 5701A and 5701 alternately latch 24-bit image data in synchronization with a latch signal, and sequentially switch the above three selection methods.
The output from the data selector 5702 is data obtained by combining 24-bit / pixel data into 32 bits.
However, after the data of the selector 5702 is selected by the third method, both data of the two pixels input to the data selector must be updated. Therefore, as shown in FIG. 56, the selection signals SELUL [3: 2]
Is delayed by one clock.

As described above, the data selector 5702 uses 32
Once converted to the bit width, the data latch 57
40A and 40B alternately latch data latch 5704
The timing at which the content of B is updated, ie, the latch signal
At the timing when SELUL1 becomes high level, it is output as data converted into a 64-bit width.

[3. Overview of Scanner Image Data Transfer FIFO Controller 4403] FIG. 58 is a block diagram of the scanner image data transfer FIFO controller 4403. This block converts the image data input from the scanner into G
It comprises a FIFO 5801 as a buffer for transferring data via the bus or the B bus, and a circuit for controlling the FIFO 5801. FIFO has a capacity of 5
It has a 12-byte (64 bits x 64) FIFO. FIFO
Data output of scanner FIFO write / read arbiter 5
802 controls while monitoring the empty flag (EF) of the FIFO 5801. Data input to the FIFO is performed by a request signal (WREQ) from the scanner video clock unit 4402.

[4. Outline of Scanner Controller Control Register 4404] FIG. 59 is a block diagram of the scanner controller control register 4404. This block has a register for controlling the inside of the scanner controller. The internal registers are as follows. 1. 1. Scanner controller power management control register 2. Scanner controller / control register Scanner controller interrupt factor status register 4. 4. Scanner / controller / interrupt factor mask register 5. Scanner sub-scanning mask line number setting register 6. Scanner main scanning mask pixel number setting register 7. Scanner sub-scanning line number setting register 8. Scanner sub-scan line number counter read register 9. Scanner sub-scanning pixel number setting register 10. Scanner main scanning pixel number counter readout register Scan page number setting register 12. 12. Scan page number counter read register Scanner device control register 14. Scanner device status register 15. Scanner video mask data register 16. Memory fill data register [5. Outline of IRQ Controller 4406] FIG.
A block diagram of the controller 4406 is shown. This block manages interrupt signals generated in the scanner controller. There are the following interrupt generation factors. 1. Finish inputting image data for the set page (ALLE
2. ND) 2. End input of image data for page (PageEnd). Rise of SPRDY signal from scanner (false → tr
ue) (INSPRDY) Fall of SPRDY signal from scanner (true → fal
se) (INSPRDY) SVSYNC signal rising from scanner (false → t
rue) (INSVSYNC) Falling of SVSYNC signal from scanner (true → fa
lse) (INSVSYNC) Rise of the EMPTY signal of the image data FIFO (false →
true) (EMPTY) Falling of the EMPTY signal of the image data FIFO (true → f
alse) (EMPTY) Rise of FULL signal of image data FIFO (false → t
rue) (FULL) Falling of FULL signal of image data FIFO (true →
false) (FULL) Overwrite occurs in the image data FIFO (FOW). Flag information (SCIRQ [31: 2
1]) the scanner controller control register 44
06 is output. From the scanner controller control register 4406, a mask bit (SCIMask [31:21]) and a clear signal (SCICLRP [31: 2]) for each interrupt cause
1]) is input. IntScc is the logical sum of each interrupt factor
Output to

[6. Memory fill mode controller 4
Outline of 405] FIG. 61 is a block diagram of the memory fill mode controller 4405. This block controls a mode in which fixed data set in the register is transferred to the memory via the GBI. This mode is set by the Memfill signal. When the fixed data transfer mode is specified, the data (MFData [31: 0]) set in the register is selected as the data output to the sccGBI. In addition, a timing signal (sccWrit
e) is generated within this block.

(SccIF-Bus) The sccIF-bus is a local bus connecting the G bus / B bus I / F unit 4301A and the scanner controller 4302. The signals contained in this bus are as follows. The input / output of the signal is a signal output from the scanner controller to the G bus / B bus I / F unit (GBI) as OUT,
A signal input from the G bus / B bus I / F unit (GBI) to the scanner controller is indicated by IN. Since the IF-bus has the same specifications for the scanner controller and the printer controller, signals for functions not supported by the scanner controller are also described. The basic clock uses Bclk of the B bus.・ SccRst0_L: IN This signal returns the FIFO inside the scanner controller to the initial state.・ SccDataOut [63: 0]: OUT G bus / B bus I / F unit from scanner controller
(GBI) is a 64-bit data bus. Image data is transferred when the scanner controller performs a data transfer operation.・ SccWrite: OUT G when the scanner controller performs data transfer operation.
This is a write signal to the bus / B bus I / F unit (GBI).
The G bus / B bus I / F unit captures sccDataOut [63: 0] at the rising edge of Bclk where the sccWrite signal is asserted. By continuing to assert the sccWrite signal, 1
Data can be written in clock units.・ SccWriteEnable: G when the scanner controller is in data transfer operation
This is a write signal to the bus / B bus I / F unit (GBI).
Output from the G bus / B bus I / F unit (GBI). Bclk
If the sccWriteEnable signal is asserted at the rising edge of, this indicates that writing is possible at the rising edge of the next clock. Assertion of sccWrite signal is sccWriteEn
Check the able signal. -SccRegAddr [31: 2]: Register address bus for accessing registers inside the scanner controller from the ING bus / B bus I / F unit (GBI). It becomes valid at the same time as sccRegStart_L is asserted, and is valid until the response is made with the sccRegAck_L signal when accessing the scanner controller internal register. -SccRegbyteEn [3: 0]: sccReg output from ING bus / B bus I / F unit (GBI)
This is a byte enable signal of DataIn [31: 0]. sccRegSt
It is valid at the same time as art_L assertion and is valid until responding with the sccRegAck_L signal. Only valid bytes indicated by this signal are written to the register. When reading from the internal register, this signal is ignored and all bytes are output. The correspondence between each bit of this signal and the byte of sccRegDataIn [31: 0] is as follows. SccRegStart_L: An access request signal for accessing a register inside the scanner controller from the ING bus / B bus I / F unit (GBI). “Low” indicates a register access request. s
It is asserted together with the ccRegAddr [31: 2] signal and the sccRegRdNotWr signal, and is asserted for one Bclk clock. The scanner controller determines that sccRegAck_
The next access will not be asserted unless L is returned. • sccRegDataOut [31: 0]: OUT This is a 32-bit data bus for read access to the registers inside the scanner controller from the G bus / B bus I / F unit (GBI). Valid when the sccRegAck_L signal is asserted. • sccRegDataIn [31: 0]: A 32-bit data bus for write access to registers inside the scanner controller from the ING bus / B bus I / F unit (GBI). It is valid at the same time as sccRegStart_L is asserted, and is valid until the response to the sccAck_L signal is made for accessing the scanner controller internal register. SccRegRdNotWr: This signal indicates the access direction (read or write) when accessing a register inside the scanner controller from the ING bus / B bus I / F unit (GBI). “High” indicates that the contents of the scanner controller internal registers are sccRegData
Out [31: 0] is read out and sccRegDataIn [31: 0] at “Low”
Is written into the internal register of the scanner controller. It becomes valid at the same time as sccRegStart_L is asserted, and is valid until the response is made with the sccRegAck_L signal when accessing the scanner controller internal register. • sccRegAck_L: OUT This signal indicates that register access inside the scanner controller has been completed. G from scanner controller
Output to the bus / B bus I / F unit (GBI). Asserted for one Bclk clock. The sccRegReq_L signal is sensed from the next clock after the assertion.

Note that the signal sccRst1_L, scc byte En [7: 0],
Although sccRead and sccDataIn [63: 0] are included in the IF bus, they are not used in the scanner controller.

FIGS. 62 and 63 are timing diagrams showing an example of the timing of the above-mentioned signals. FIG.
Reference numeral 2 denotes timing when data is read from the scanner controller 4302 and DMA-transferred. FIG. 63 shows timing when reading or writing is performed on the internal register of the scanner controller 4302.

(Power Management) In the scanner controller, the gate control of the video clock (SVCLK) according to the setting of the scanner controller power management control register (0X1B005000) is performed, thereby performing power management. The value of the PM state signal (sccPmStat [1: 0]) output to the power management unit (PMU) 409 depends on the G bus / B bus I /
SccDmaPmState [1: input from F unit 4301A]
0] and the state of the clock. sc
cPmState [1: 0] is as shown in FIG.

In FIG. 64, sccDmaPmState [1: 0] is
The power consumption state of the G bus / B bus interface GBI_scc of the scanner is shown. GBI_sec has four stages of power consumption states 00 to 11. This state signal sccDmaPmState
[1: 0] is output from GBI_scc to the scanner controller.

The power consumption of the scanner controller has two stages, which are indicated by an internal signal SPStat.

The signal sccPmstate [1: 0] indicates a state in which the two states of GBI_scc and the scanner controller are combined. This signal is output to the power management unit of the system. That is, the power consumption state of the scanner controller is transmitted to the power management unit in four stages. The stage is indicated by the value of the signal sccPmstate [1: 0]. The value 00 is the lowest level, and the power consumption indicated by one increase increases.

(Scanner Controller Core Interface) FIG. 65 is a diagram summarizing signals input and output between the core portion including the above-described blocks in the scanner controller 4302 and an external bus or scanner. As described above, the scanner controller 4302 is connected to the system bus bridge 402 by the G bus, is connected to the IO device, the power management device, and the system bus bridge by the B bus, and is connected to the printer controller by the CP bus. They are connected by a bus, and connected to a G bus / B bus I / F unit by an I / F bus.

2.9.2. Printer Controller FIG. 66 is a block diagram of the printer controller 4303. The printer controller is a block that is connected to a printer by a video I / F and interfaces with a G bus / B bus I / F unit. It is roughly composed of the following blocks. 1. Printer device I / F6601 An input / output port for inputting / outputting signals to / from a printer video I / F and an optional controller I / F. 2. Printer video clock unit 6602 This unit operates with the video clock of the printer. 3. Printer image data FIFO controller 6603 controls a FIFO for transferring image data. 4. Printer controller control register unit 6604 This is a register unit for controlling the entire printer controller. 5. The IRQ controller 6605 controls an interrupt signal generated inside the printer controller (Prc). 6. Printer command / status control unit 6606 Controls command / status transmission and reception with the printer via the video I / F. 7. Optional controller control unit 66
07 This unit controls the printer option controller. 8. FIFO (FIFO_PRC) 6608 This FIFO is used when there is a possibility that the printer is asynchronous with the video data when outputting the video data to the printer.

There are the following five types of image data to be output to the printer. 1. RGB 8-bit color multi-value data (dot sequential) 2.8-bit black-and-white multi-value data 3.1-bit black-and-white binary data 4. CMYK 1-bit color data (screen-sequential) Next, an outline of each block constituting the printer controller will be described.

[1. Overview of Printer Device I / F] FIG.
FIG. 7 shows a block diagram of the printer device I / F6601. This block is an input / output port for inputting and outputting signals from the printer video I / F and the optional controller I / F. Each signal of P video R [7: 0] and P video B [7: 0] is VD
It is possible to switch whether or not the level of the output signal is inverted by the Invt signal.

[2. Overview of Printer Video Clock Unit] FIG. 68 shows a printer video clock unit 660.
2 shows a block diagram of FIG. This block operates on the video clock from the printer and is composed of the following blocks. 1. Printer video data mask 6801 (DFF8ENMask)
A block that performs data masking on image data to the printer. The masked data becomes the data of the value set in the register. 2. Printer video synchronization control unit 6802
(Prc_sync unit) Video clock from printer, VS
A block for generating a timing signal for outputting image data from a YNC or HSYNC signal. Horizontal direction of image data,
Manages the number of data and lines in the vertical direction. 3. Printer Video Data Width Converter 6803 (pvdw
conv) A block for converting image data transmitted from the IF bus at a 64-bit width into RGB 24-bit, black-and-white 8-bit, and black-and-white 1-bit data depending on the mode. The mode is set by a register.

(Printer Video Data Mask) FIG. 69 is a block diagram of the printer video data mask 6801. This block masks image data to be output to a printer in pixel units. The masked image data becomes the value set in the register (RDMask [7:
0], GDMask [7: 0], BDMask [7: 0]).

(Printer Video Synchronization Control Unit) FIG. 70 is a block diagram of the printer video synchronization control unit 6802. This block includes a vertical synchronization signal (TOP), a horizontal synchronization signal (INPHSYNC), and an image data synchronization clock (GTVC) for the image data to be output to the printer.
LK) to output image data enable signal (VD
OEN), Printer image data transfer FIFO controller 66
03, a signal (RREQ) for requesting data is generated.

In addition, the delay of image data in the main scanning direction, the number of captured pixels, the delay in the sub-scanning direction, and the number of captured lines are managed. The line counter 7001 outputs the state signal (PEND) at the timing when the output of the set amount of image data is completed.
P). Also, the delay in the sub-scanning direction and the number of output lines are managed, and the vertical synchronizing signal (E
H). A pixel counter 7002 manages an image output delay in the main scanning direction and the number of output pixels. A page counter 7003 manages output image data in page units. When image data output for the set number of pages is completed, an end signal (ALLPEND) is generated.

(Printer Video Data Width Converter)
FIG. 71 shows a block diagram of the video data width converter 6803. This block is a unit for converting 64-bit data input from the GBI (G bus / B bus I / F) into a format of image data. The following three types of image data can be output. RGB 8-bit color image data,
Multi-valued 8-bit monochrome image data and binary 1-bit monochrome image data. When the color image data of 8 bits each of RGB is stored in the memory in units of 24 bits (24 bits)
Two mode outputs are supported, one in which a 1-bit data is added to 24 bits and stored in a memory in 32-bit units (32-bit mode). This mode is set in the printer controller control register 6604. The three types of image data are output to the following signal lines. 1. RGB 8-bit color image data… IR [7: 0],
IG [7: 0], IB [7: 0] Multi-valued 8-bit monochrome image data ... IR [7: 0] 3.2 1-bit monochrome image data ... IR7 The arrangement of 64-bit data on the memory is as follows.

[0267] 1. RGB 8 bit color image data (24 bit mode) 1st pixel R8bit → bit63-56 1st pixel G8bit → bit55-48 1st pixel B8bit → bit47-40 2nd pixel R8bit → bit 39-32 Second pixel G8 bit → bit 31-24 Second pixel B8 bit → bit 23-16 Third pixel R8 bit → bit 15-8 Third pixel G8 bit → bit 7-0 In this case, The arrangement is as shown in FIG.

[0268] 2. 8-bit RGB color image data (32-bit mode) First pixel R 8 bits → bits 63-56 First pixel G 8 bits → bits 55-48 First pixel B 8 bits → bits 47-40 Second pixel R 8 bits → bits 31-24 Second pixel G8 bit → bit 23-16 Second pixel B8 bit → bit 15-8 In this case, the arrangement on the memory is as shown in FIG.

[0269] 3. Multi-valued 8-bit monochrome image data First pixel 8 bits → bit 63-56 Second pixel 8 bits → bit 55-48 Third pixel 8 bits → bit 47-40 Fourth pixel 8 bits → bit 39-32 fifth Pixel 8 bit → bit 31-24 6th pixel 8 bit → bit 23-16 7th pixel 8 bit → bit 15-8 8th pixel 8 bit → bit 7-0 In this case, the arrangement on the memory is shown in FIG. It is as shown in.

4.2 1-bit monochrome image data 1st pixel 1 bit → bit 63 2nd pixel 1 bit → bit 62 3rd pixel 1 bit → bit 61 4th pixel 1 bit → bit 60: 60th pixel 1 Bit → bit 4 1st pixel 1 bit → bit 3 62nd pixel 1 bit → bit 2 63rd pixel 1 bit → bit 1 64th pixel 1 bit → bit 0 In this case, the arrangement on the memory is shown in FIG. As expected.

Next, the blocks constituting the printer video data width converter will be described.

(RGB Out Unit 7101) FIG. 76
The block diagram of the RGBout unit 7101 is shown in FIG. This block is a unit for converting 64-bit data packed in the 24-bit mode into 8-bit RGB color image data.

[3. Overview of Printer Image Data Transfer FIFO Controller] FIG. 77 is a block diagram of a printer image data transfer FIFO controller 6603. This block is a FIFO as a buffer for transferring image data to be output to the printer via GBI (G bus / B bus I / F).
And get a circuit that controls that FIFO. Capacity 51
A 2-byte (64 bits × 64) FIFO 7701 is provided. Data input to the FIFO is controlled while the printer FIFO write / read arbiter 7702 monitors the full flag (FF) of the FIFO 7701. The data output of the FIFO is performed by a request signal (RREQ) from the printer video clock unit 6602.

[4. Printer Controller Control Register Unit] FIG. 78 is a block diagram of the printer controller control register 6604. This block has a register for controlling the inside of the printer controller. The internal registers are as follows. 1. 1. Printer power management control register 2. Printer controller control register 3. Printer controller interrupt factor status register 4. Printer controller interrupt factor mask register 5. Printer sub-scanning mask line number setting register 6. Printer main scan mask pixel number setting register 7. Printer sub-scanning line number setting register 8. Printer sub-scanning line number counter read register Printer main scanning pixel number setting register 10. 10. Printer main scan pixel number counter read register Print page number setting register 12. 12. Print page number counter read register Printer device control register 14. 14. Printer device status register Printer serial command register 16. Printer serial status register 17. Option, controller, TX, register 18． Option controller, RX, register 19． Printer video mask data register 20.4 Grayscale output level setting register 21.16 Grayscale output level setting register 1 22.16 Grayscale output level setting register 2 23.16 Grayscale output level setting register 3 24.16 Grayscale output level setting register 4 [5. IRQ controller] FIGS. 79 and 80 show the IRQ
A block diagram of a controller 6605 is shown. This block manages an interrupt signal generated in the printer controller. An interrupt is generated from the interrupt source. It has a mask function for each interrupt factor and can be cleared individually. The interrupt factors are as follows. 1. 1. End of image data transfer all pages (ALLPEnd) 2. One page of image data transfer (PageEnd) 3. Serial status 1 byte reception completed (INPSBSY) 4. One byte transmission of serial command completed (EndCBSY) 5. PPRDY signal rise (false → true) (INPPRDY) 6. PPRDY signal falling true → false) (INPPRDY) 7. RDY signal rising (false → true) (INRDY) 8. RDY signal falling (true → false) (INRDY) 9. PFED signal rise (false → true) (INPFED) 10. Fall of PFED signal (true → false) (INPFED) SPCHG signal rising (false → true) (INSPCH
G) 12. SPCHG signal falling (true → false) (INSPCH
G) 13. 13. PDLV signal rising (false → true) (INPDLV) 14. PDLV signal falling (true → false) (INPDLV) TOPR signal rise (false → true) (INTOPR) 17. Fall of TOPR signal (true → false) (INTOPR) 17. CCRT signal rising (false → true) (INCCRT) 18. Fall of CCRT signal (true → false) (INCCRT) VSREQ signal rising (false → true) (INPVSYN
C) 20. VSREQ signal falling (true → false) (INPVSYN
C) 21. Option controller TX transmission & RX reception completed 22. 23. Rise of EMPTY signal of image data transfer FIFO 23. Fall of the EMPTY signal of the image data transfer FIFO 25. Rise of FULL signal of image data transfer FIFO Fall of FULL signal of image data transfer FIFO 26. Overread occurred in the image data transfer FIFO (EE
RDOut) Flag information (PCIRQ [31:
6]) to the printer controller control register 66
04. From the printer controller control register 6604, a mask bit (PCIMask [31: 6]) and a clear signal (PCICLRP [31:
6]). The logical sum of each interrupt factor is output to intPrc.

[6. Printer Command / Status Control Unit] FIG. 81 is a block diagram of the printer command / status control unit 6606. This block is for transmitting and receiving a serial command / status for controlling the printer.

As the serial command, an INPCBSY signal indicating a period during which the command is transmitted, an INPCCLK signal which is a synchronous clock of the serial command, and a serial command INPSRCMD signal are generated.

As the serial status, an INPSBSY signal indicating a period during which the status is transmitted and a serial status INPSRSTS signal are input, and an 8-bit status PSRSTAT [7: 0] is output. The synchronous clock for inputting the serial status is IN output from the printer.
Either the PPCLK signal or the PCCLK signal generated by this block can be selected. The selection is made by the PSRCLKMode signal.

[7. Option Controller Control Unit] FIG. 82 is a block diagram of the option controller control unit 6607. This block is a unit that outputs transmission data (TX) to the option controller. IN for TX transmission
Generate the STROBE signal, INCKEN signal, and CLK (OPCLK) signal.
Also, the reception data (RX) is received simultaneously with the TX transmission.

(PrcIF-Bus) The prcIF-bus is a local bus that connects the G bus / B bus I / F unit 4301B and the printer controller 4303. The signals contained in this bus are as follows. The input / output of the signal is a signal output from the printer controller to the G bus / B bus I / F unit (GBI) as OUT,
A signal input from the G bus / B bus I / F unit (GBI) to the printer controller is indicated by IN. Since the IF-bus has the same specifications for the scanner controller and printer controller, signals for functions not supported by the printer controller are also described. Basic clock is Bc of B bus
Use lk. • prcRst0_L: IN This signal returns the FIFO inside the printer controller to the initial state. PrcDataIn [63: 0]: 64-bit data bus output from the ING bus / B bus I / F unit (GBI) to the printer controller. Image data is transferred when the printer controller performs a data transfer operation. • prcRead: OUT Read signal from the G bus / B bus I / F unit (GBI) when the printer controller performs data transfer operation. The G bus / B bus I / F unit (GBI) responds to the rising edge of Bclk for which the prcRead signal is asserted by prcDataIn [63:
0] is valid. By continuously asserting the prcRead signal, data can be read in units of one clock.・ PrcReadEnable: G bus / B when IN printer controller is in data transfer operation
A signal indicating that data read from the bus I / F unit (GBI) is enabled. Output from the G bus / B bus I / F unit (GBI).
If the prcReadEnable signal is asserted at the rising edge of Bclk, it indicates that reading is possible at the rising edge of the next clock. The assertion of the prcRead signal is prcRead
Check the Enable signal and execute. • prcRegAddr [31: 2]: Register address bus for accessing registers inside the printer controller from the ING bus / B bus I / F unit (GBI). It becomes effective at the same time as prcRegStart_L is asserted, and is effective until the response to the prcRegAck_L signal is made for access to the scanner controller internal register. • prcRegbyteEn [3: 0]: prcReg output from ING bus / B bus I / F unit (GBI)
DataIn [31: 0] byte enable signal. prcRegStart_L
It is valid at the same time as assertion, and is valid until responding with the prcRegAck_L signal. Only valid bytes indicated by this signal are written to the register. When reading from the internal register, this signal is ignored and all bytes are output.
The correspondence between each bit of this signal and the byte of prcRegDataIn [31: 0] is as follows. • prcRegStart_L: An access request signal for accessing a register inside the printer controller from the ING bus / B bus I / F unit (GBI). “Low” indicates a register access request. prcRe
It is asserted together with the gAddr [31: 2] signal and the prcRegRdNotWr signal, and is asserted for one Bclk clock. The printer controller determines that this access
, The next access is not asserted. • prcRegDataOut [31: 0]: OUT A 32-bit data bus for read access to registers in the printer controller from the G bus / B bus I / F unit (GBI). Valid when the prcRegAck_L signal is asserted. • prcRegDataIn [31: 0]: A 32-bit data bus for write access to registers inside the printer controller from the ING bus / B bus I / F unit (GBI). It becomes effective at the same time as prcRegStart_L is asserted, and is valid until the response to the prcRegAck_L signal is made for access to the printer controller internal register. PrcRegRdNotWr: A signal indicating the access direction (read or write) when accessing a register in the printer controller from the ING bus / B bus I / F unit (GBI). When “High”, the content of the printer controller internal register is prcRegDataOut [3
1: 0], and the content of prcRegDataIn [31: 0] is written to the printer controller internal register at “Low”. It becomes effective at the same time as PrcRegStart_L assertion.
It is valid until responding with the prcRegAck_L signal. • prcRegAck_L: OUT This signal indicates that register access inside the printer controller has been completed. From printer controller to G bus /
Output to the B bus I / F unit (GBI). Asserted for one BClk clock. It is sensed from the next clock after the prcRegstart_L signal is asserted.

Note that the signal prcReq0_L, prc byte En [7: 0],
prcWrite, prcDataOut [63: 0], and prcReadEnable are not used in the printer controller.

FIGS. 83 and 84 are timing diagrams showing an example of the timing of the above-mentioned signals. FIG.
Reference numeral 3 denotes a timing when data is DMA-transferred to the printer controller 4303, and FIG. 63 shows a timing at which reading or writing is performed on an internal register of the printer controller 4303.

(Power Management) In the printer controller, the gate control of the video clock (VCLK) according to the setting of the printer controller power management control register (0X1B007000) is performed, thereby performing power management. The value of the PM state signal (prcPmStat [1: 0]) output to the power management unit (PMU) 409 is based on the G bus / B bus I / F.
PrcDmaPmState [1: 0] input from unit 4301B
And the state of the clock. prcP
mState [1: 0] is as shown in FIG.

In FIG. 85, prcDmaPmState [1: 0] is
The power consumption state of the G bus / B bus interface GBI_prc of the printer is shown. GBI_prc has four stages of power consumption states 00 to 11. This state signal prcDmaPmState
[1: 0] is output from GBI_prc to the printer controller.

The power consumption of the printer controller has two stages, which are indicated by an internal signal PPStat.

A signal prcPmstate [1: 0] indicates a state in which the two states of GBI_prc and the printer controller are combined. This signal is output to the power management unit of the system. That is, the power consumption state of the printer controller is transmitted to the power management unit in four stages. The stage is indicated by the value of the signal prcPmstate [1: 0]. The value 00 is the lowest level, and the power consumption indicated by one increase increases.

2.9.3 G Bus / B Bus I / F Unit (GBI) FIG. 92 is a block diagram of the G bus / B bus I / F unit 4301. The G bus / B bus I / F unit is prepared for each of the scanner and the printer, but since the configurations are the same, they will be described together here.

In FIG. 92, GBI4301 is GBI
and a BBus controller connected to the Bus and controlling the same, and a BBus controller connected to the Bbus and controlling the same. These units include a DMA controller 9205 for controlling a DMA address, a FIFO 9204 used for data transfer between the functional block and the GBus / BBus, and a register unit 9206 in which various set values are written. Of these, GBUS
The controller and the FIFO 9204 operate at a clock of 100 MHz according to the G bus, and the other blocks operate at 50 MHz according to the B bus.

The GBI 4301 is a functional block (SCC: scanner controller and PRC: printer controller) to be connected to both the G bus and the B bus.
It provides a selective connection between Bus and BBus and an interface of both buses. Between GBI and each functional block,
They are connected by IFBus 9201. In the function block,
There is no need to be aware of whether the data input / output destination is GBus or BBus. Also, since DMA is supported on the GBI side, there is no need to generate addresses on the functional block side.
The GBI is a unit in which functions required in common in each functional block are grouped into an independent unit.

IFBus 9201 supported by GBI
The functional blocks connected to receive or send continuous data. The IFBus does not include an address signal. In GBI, Channel
0 (GBus / BBus → IFBus0) and Chann
Two channels, e11 (GBus / BBus → IFBus1), are prepared, and a DMA controller is prepared for each of them. However, only the channel 0 is used (implemented) in the scanner controller and only the channel 1 is used in the printer controller.

The DMA controller 9205 has an I / O
(Fixed address) and memory can be set. In the case of a memory, a continuous physical address and a DMA of a chain table system (described later) can be set.

The GBI inputs / outputs data to / from functional blocks via FIFO. Therefore, when the GBI operates in the slave mode, the address of the GBI is G
Bus side is 0x18n0_0000 to 0x18n0_
007F, BBus side is 0x19n0_0000-0
The same location is accessed only by x19n0_001F. Since the FIFO is used, it is difficult to cope with wrap-around during burst transfer. BB
For a burst transfer request involving wrap-around of us, a response is made as a single access. It does not respond to the transfer request with the wraparound of the GBus.

When DMA transfer of image data is performed between GBIs, control is performed by the respective DMA controllers. At this time, it is not particularly determined which side becomes the master, but it is desirable that the data transfer timing be more strict. For this reason, in this embodiment, DMA transfer is performed with GBI_PRC being the master and GBI_SCC being the slave.

The GBI (GBus / BBus interface) is: Fifo that exchanges data with functional blocks
Unit 2. 2. A GBus controller 9202 that is directly connected to the G bus and connects the G bus and the Fifo unit. 3. BBus controller 9203 directly connected to BBus and connecting BBus and Fifo unit 4. DMA controller 9205 that issues a DMA transfer request to each bus controller in master mode. A register unit 9206 holds the contents of the register and sends a signal to each block. The register unit also includes an interrupt control and a power control unit. Hereinafter, each part will be described.

(Fifo Unit) The Fi unit shown in FIG.
The fo unit is a portion serving as a buffer for transfer data between the GBus / BBus and the IF Bus. Fifo
The units are Fifo units 0 and Fi, which are independent of each other.
fo unit 1. Fifo Unit 0
Is the data input from IFBus and GBus or B
The FIFO unit 1 is used for data output to the bus, and the Fifo unit 1 is used for data input from the G bus or the B bus and data output to the IF bus.

Signal scGbiFifo0Clk or scGbiFifo1Clk
Is a gated clock, which realizes a power saving mode by stopping the clock. This clock is GBI FIF
It stops by writing the O register and starts automatically when entering the master mode or the slave mode.

[Fifo unit 0] The Fifo unit 0 writes data from IFBus0 (IFBus specifications will be described later) to Fifo, and writes GBus / B
Send it to Bus. The signals ifDataOutB [63: 0], ifWriteB,
ifWriteEnableG is connected to IFBus.

The Fifo unit 0 has a Fifo
0 inputs 64-bit data from IFBus,
64-bit data DataOut64 and B for GBus
This is a 64-bit × 17-stage Fifo that outputs 32-bit data DataOut32 for Bus.

The status signal output from the Fifo unit 0 includes the following signals.・ Fifo0EnableB1G: Fifo0Unit
Indicates that one word (32 bits) can be transferred from the to the BBus. The DMA controller is used in the master mode, and the BBus controller is used in the slave mode.・ Fifo0EnableB4G: Fifo0Unit
Indicates that four words can be transferred consecutively from Bbus to BBus. The DMA controller is used in the master mode, and the BBus controller is used in the slave mode.・ Fifo0EnableB8G: Fifo0Unit
Indicates that eight words can be continuously transferred from B to the bus. The DMA controller is used in the master mode, and the BBus controller is used in the slave mode.・ Fifo0EnableG4G: Fifo0Unit
Indicates that four words (one word is 64 bits) can be continuously transferred to the G bus. DMA in master mode
When the controller is in the slave mode, the GBus controller uses it.・ Fifo0EnableG16G: Fifo0Uni
Indicates that 16 words can be continuously transferred from t to GBus. The DMA controller is used in the master mode, and the GBus controller is used in the slave mode. -IfWriteEnable: Fifo0 is Full
Indicates no status. Connected to IFBus to inform function blocks that writing is possible.

Also, the reading of 64-bit data of GBus from Fifo0 uses the signal Rd64 input to Fifo0, and the reading of 32-bit data of BBus uses the signal Rd32. By either read, the status signal and the data Out64 and DataOut32 output from Fifo0 are updated.

(B2G block) I / F bus and BBu
The clock of s is 50 MHz, and the clock of GBus is 100 MHz. For this reason, Fifo unit 0
The IFB block, not shown, included in the
write signal ifWriteFi synchronized with us clock
One clock of the read signal bReadFifoB synchronized with the foB or the BBUs clock is converted into a clock of the clock of the Fifo unit (twice the frequency of IFBus).

(ChkIllegal block) Fif
o0 is shared by GBus / BBus. In the master mode, the DMA controller uses GBus / BBu
Although exclusive use of s is controlled, in slave mode,
The DMA master must control exclusive use.
Therefore, ChkIll included in Fifo unit 0
In the egal block, when the Fifo0 is simultaneously accessed from the GBus and the BBus, the signal fifoEr is output.
Assert lorG. That is, when the read signal gReadFisoG from Gbus or the read signal bReadFisoB from BBus is simultaneously asserted, the signal fifoErrorG is asserted. This signal is latched in the register unit and generates an interrupt if not masked.

[Fifo unit 1] The Fifo unit 1 is a Fifo unit containing data from the GBus / BBus.
Write to fo1 and send to IFBus1. ifDa
taIng [63: 0], ifByteEnG [7:
0], ifReadB, ifReadEnableG
Is connected to IFBus.

[0303] In the Fifo unit 1, a front buffer is provided before the Fifo1 in order to cope with the backward DMA in the master mode. In the case of reverse DMA (input signal reverseMODE is enabled), buffer once in the front buffer, and then F
Send data to IFO. Other modes (signal r
When “everyMODE” is disabled, it functions as a normal FIFO.

(Front buffer) GBus or B
This is a 64 + 4 bit × 4 stage buffer with byte enable, which receives data from the bus and outputs it to Fifo1. In writing from BBus, data is written together with a byte enable signal. In writing from the G bus, all byte enables are made valid and data is written. Packing to 64 bits in writing from BBus is not performed.

As a status signal, a signal BufEmpty indicating that the front buffer is empty is provided.

At the time of reverse DMA, the signal reverses
eMODE is enabled and the transfer mode is DMA
4 bus burst transfer of GBus by controller,
Alternatively, the transfer is limited to only the BBus single transfer. G
Bus 4-bit burst transfer data is stored once in the front buffer, and then transmitted in reverse order to Fifo 1 (in reverse order in 32-bit units).

In other modes, the signal “reve”
rsMODE is disabled and 4-stage FIF
Functions as O. Input signal dummyWriteFi
fo1B is latched once and sent to Fifo1 when the front buffer becomes empty.

(Fifo1) Fifo1 receives data from the front buffer and converts the input data to I
It is a 64 + 8 bit × 16-stage Fifo with byte enable output to the FBus. Data from the BBus is written with the byte enable signal. GB
Data from us is written with all byte enables enabled. In writing data from the B bus, packing to 64 bits is performed.

The following status signals are provided based on the internal state of Fifo1 and the BufEmpry signal of the front buffer.・ Fifo1EnableB1G: Fifo unit 1
Indicates that two words (32 bits) can be transferred from the BBus. This is enabled when Fifo1 has a space of one or more BBus words or the front buffer is empty.・ Fifo1EnableB4G: Fifo unit 1
Indicates that eight words can be continuously transferred from BBus. This is enabled when Fifo1 has a space of 4 words or more of BBus or the front buffer is empty.・ Fifo1EnableB8G: Fifo unit 1
Indicates that 12 words can be continuously transferred from BBus. If there is a free space of BBus 8 words or more in Fifo1, or there is a free space of BBus 4 words or more in Fifo1,
It is enabled when the front buffer is empty.・ Fifo1EnableG4G: Fifo unit 1
Indicates that four words (one word is 64 bits) can be continuously transferred from the GBus. This is enabled when Fifo1 has an empty space of 4 words or more of GBus or the front is empty. Fifo1EnableG16G: Indicates that 16 words can be continuously transferred from the GBus to the Fifo unit 1. If Fifo1 is empty or if Fifo1 has GBus
It is enabled when there is room for 12 words or more and the front buffer is empty. IfReadEnable: Indicates that Fifo1 is not empty. It is connected to IFBus and informs the function block that it can be read.

Signals Fifo1EnableB1G, Fi
fo1EnableB4G, Fifo1EnableB
8G is used by the DMA controller in the master mode and by the BBus controller in the slave mode.

Signals Fifo1EnableG4G, Fi
fo1EnableG16G has D in master mode.
When the MA controller is in the slave mode, the GBus controller uses it.

Also, the Fifo unit 1 has a B2G block and a ChkIlle like the Fifo unit 0.
It has a gal block.

(GBus Controller) FIG.
It is a block diagram of us controller 9202. Gbu
The s-controller 9202 includes a GBus master controller for controlling the GBus when the GBI serves as a bus master, and a GBus controller for controlling when the GBI serves as a slave.
Slave controller and GB for controlling data
us data controller and a GBus interface buffer. With this configuration, GBI 4301
Can operate as a GBus master or slave.

[GBus Master Operation] The GBus controller controls the GBus master as a GBus master in the following procedure.

[0315] 1. Request from DMA Controller The DMA controller 9205 outputs the gMReq (N) signal to gMAddr at a stage where the transfer of the channel N is possible.
(N) [31: 5] signal, gMBst4Not16_N
1 with bClk (Bbus clock signal)
Assert only the clock to request DMA transfer.

GMAddr (N) [31: 5] signal, g
The MBst4Not16_N signal is a gMDone (N) signal, gMRtry by the GBus master controller.
It must not be changed until either the (N) signal or the gMBErr (N) signal is asserted.

[0317] 2. Transfer request to GBus arbiter The gMReq (N) signal is latched by the GBus master request interface (gLatchReq
(N) signal).

The gLatchReq signal of each channel is
Arbitrated by a GBus master request arbiter (not shown), a DMA request signal g is sent to the GBus arbiter 406.
At the same time as asserting the Req_L signal, a gIntReq (N) signal is sent to the GBus master address phase.

[0319] 3. Transfer permission from GBus arbiter DMA permission signal gGnt from GBus arbiter 406
When the _L signal is asserted, the signal GGntSense is asserted from the GBus master address phase, and the DMA request signal gReq_L is negated. At the same time, the gLatchReq (N) signal and gIntReq
(N) The signal is negated. The GBus master request interface monitors the signal gSlvBsy,
When the data bus becomes available, GMDataRq
(N) Assert the signal. This signal is sent to the GBus master generate end data and the GBus data controller.

[0320] 4. GBus data transfer When the gAack signal of the slave is confirmed, data transfer starts. GBus signals other than EndData are G
It is generated in the Bus master address phase. EndD
“ata” is generated by GBus master generate end data. Fibus or Fifo from GBus
Data transfer from Gbus to GBus is performed by GMDataRq
The (N) signal is used by the GBus data controller. If the gRtry signal is detected before the gAack signal, the GBus data controller does not perform data transfer.

[0321] 5. Gbus data transfer end (or retry) Gbus master generate end data is Gbus
The end of the data transfer is determined by the checkBErr signal.
Notify the Bus master request interface. The GBus master request interface receiving the signal clears the internally held request and asserts the gMDone signal if there is no bus error. If a bus error is detected, gMBErr
Assert the signal to notify the DMA controller 9205 that the transfer has been completed.

When the gRtry signal is detected, GB
The us master request interface clears the internally held request and asserts the gMRtry signal at the same time.

The DMA controller 49205 has a GBu
The signal received from the s controller 9202 is gMDone
If it is a signal, the transfer address and transfer length are updated. If the received signal is a gMRtry signal, the next action is taken without updating them. At the time of the gMBErr signal, the DMA controller 9202 stops the transfer, and if not masked, generates an interrupt.

[Gbus Slave Operation] The GBus controller controls the Gbus slave by the Gbus slave controller in the following procedure. 1. Transfer request from master Gbus slave request interface, g
At the timing of TsReg signal assertion, gAddrR
Check the eg signal and the gRdNotWrReg signal (channel 0 or 1). GSEnab with access to GBI
If the le (N) signal (slave mode: set by a register) is asserted, it is determined from the gBst4Not16 signal, the ReadFifoEnable4 / 16 signal (channel 0) or the WriteFifoEnable4 / 16 signal (channel 1) whether transfer is possible. If possible, the gAack signal, otherwise the gRtry
Assert the signal. 2. Gbus data transfer If transfer is possible, the Gbus slave request interface confirms that the gSlvBsy signal is negated, asserts the gAack signal, and sets the timing to
The GSlvStart signal is transmitted to the Gbus slave request slave busy. In addition, the GBus slave request interface starts data transfer by GS
By asserting the DataRq (N) signal, GBus
Tell the data controller. Data transfer from GBus to Fifo or from Fifo to GBus
This is performed by the Bus data controller. GBus slave request slave busy generates the gSlvBsy signal. 3. GBus data transfer end There is no signal indicating the transfer end. There is no assertion of the gBErr signal. However, gSEEnable (N)
If the signal is negated, there is no response to the master's access, and a bus error occurs due to timeout.

(BBus controller) FIG.
FIG. 146 is a block diagram of a us controller 9203. BBu
The s controller 9203 includes a BBus master controller, a BBus data controller, a BBus slave controller, and a BBus interface buffer. With this configuration, the GBI 4301 can operate as a BBus master or slave.

[BBus Master Operation] Request from DMA Controller The DMA controller 9205 sends the bMReq (N) signal to bMAddr at the stage where the transfer of the channel N is possible.
(N) [31: 2] signal, bMBurst8n) signal,
The BBus clock signal bClk is asserted for one clock together with the bMBst4Not8_N signal. At the stage where the chain table needs to be read in the chain DMA mode, the cMReq (N) signal is set to cMAd
Assert one clock with bClk together with the dr (N) [31: 2] signal. The reading of the chain table does not use the BBus burst transfer. In this way, the DMA transfer of BBus is requested from the DMA controller.

The bMAddr (N) [31: 2] signal, b
The MBurst (N) signal and the bMBst4Not8_N signal start accessing the Fifo (bReadFi).
fo, bWriteFifo is asserted).

The cMAddr (N) [31: 2] signal must not be changed until one of the cMDone (N) signal, the cMrtry (N) signal, and the cMBErr (N) signal is asserted.

[0329] 2. The transfer request to the BBus arbiter The BBusbMReq (N) signal and the cMReq (N) signal are latched by the BBus master request interface (the bLatchReq (N) signal and the cLa
tchReq (N) signal). Each request signal is arbitrated by the BBus master request arbiter, and the bBReq_L signal is asserted to the BBus arbiter 407.

[0330] 3. Transfer permission from BBus arbiter bBGnt_L which is a permission signal from BBus arbiter
When the signal is asserted, the BBus master request arbiter sends a BGnt (N) signal or C to the corresponding requesting BBus master request interface.
Gnt (N) signal is sent, and bBGnt_L signal is negated. The BBus master request interface uses the bLatchReq (N) signal or cLatc
The hReq (N) signal is negated, and the bTx signal and bSn
The waitWait signal is monitored, and when a transfer is possible, the BMDataRq (N) signal and the CMDDataRq
(N) Assert the signal. This signal is sent to the BBus master sequencer and the BBus data controller.

[0331] 4. BBus Data Transfer The BBus master sequencer generates all BBus signals other than the data to be driven by the BBus master. BMDataRq (N) signal or CMDData
Using the Rq (N) signal as a trigger, bStartOut_
L (if in burst mode, bBurstOu
t_L), checks bRdy (or bBurstAck in burst mode), and detects the end of transfer. Movement of data from BBus to Fifo or from Fifo to BBus is performed by BMDataRq
The (N) signal is used by the BBus data controller.

When the bRetry signal is detected before (or simultaneously with) the bRdy signal, the BBus data controller does not perform data transfer.

[0333] 5. End of BBus data transfer (or
(Retry, bus error) The BBus data controller ends the data movement with the BMlastData signal of the BBus master sequencer. Further, the BBus master sequencer notifies the end of the BBus data transfer to the BBus request interface by a Done signal. In the case of a retry or a bus error, a Retry signal,
The error signal is transmitted. The BBus master request interface indicates that the transfer has been completed to the DMA controller by using [bc] MDone (N) (hereinafter, either b or c is represented by [bc]). Are transmitted as a [bc] MRtry (N) signal and a [bc] MBErr signal, respectively.

The DMA controller outputs the signal bReadF
The transfer address, transfer length, and the like are updated by ifo and bWriteFifo, and the next action is caused by the bMDone (N) signal or the bMRtry (N) signal indicating the end of the DMA BBus transfer. The cMDone (N) signal indicating the end of reading the chain table updates the internal chain table, and if the signal is a cMRtry (N) signal, issues a transfer request again.

[Bc] In the case of the MBErr (N) signal,
The DMA controller stops the transfer and generates an interrupt if it is not masked.

(Retry in Burst Mode) Signal bS
If the slave responds with the simultaneous assertion of the signal bBurst_L and the signal bRdy_L and the signal bBurstAck_L without asserting the signal bRetry_L, the slave is determined to be capable of burst transfer. During the burst transfer, the signal bRet
ry_L is not checked. That is, the first bRdy
Only at the timing of _L, the signal bRetry_L is checked. Note that even during the burst transfer, the signal bEr
lor_L is checked at each clock.

(Signals bError_L, bRetry_L
L, bRdy_L simultaneous assertion) signal bEr
When lor_L is asserted, the signal bRetry_
Even if L is asserted, it is regarded as a bus error.
The signal bError_L is negated and the signal bRetr
When y_L is asserted, it is regarded as a retry even if the signal bRdy_L is asserted.

(Signal byteEn_L in master mode)
[3: 0]) Signal byteE in master mode
n_L [3: 0] is always “0000” except for the last transfer of single access and burst access.

[BBus slave operation (other than register access)] Transfer request from master The BBus master sequencer checks the bAddr signal and the bWr_L signal (channel 0 or 1) at the timing of the bStart_L signal assertion. In accessing the GBI, if the bSEEnable (N) signal (slave mode: set by a register) is asserted, bBur
stShortNotLong signal (bBurst_L
Only when the signal is asserted) and ReadFifoEn
able 1/4/8 signal (channel 0) or WriteF
It is determined whether transfer is possible from the ifoEnable 1/4/8 signal (channel 1). If transfer is possible, bRdyO
ut_L signal (in the burst mode, bBurst
Assert the AckOut_L signal); otherwise, assert the bRetryOut_L signal.

The master burst mode (bBurst_
In response to the request (assert L signal), if burst transfer is not possible but single transfer is possible from the Fifo state, only the bRdyOut_L signal is asserted to perform single transfer. When the master burst mode request generates a wraparound, single transfer is performed if possible because the GBI does not support wraparound (the bBurstAckOut_L signal is not asserted).

[0341] 2. BBus Data Transfer If transfer is possible, the BBus master sequencer keeps asserting the bRdyOut_L signal for the required clock. In the case of burst transfer, the first bRdyO
At the timing of the assertion of the out_L signal, bBurst
Assert the AckOut_L signal for 1 BBus clock. In addition, the start of data transfer is indicated by BSDataRq.
The (N) signal indicates that data transfer has been completed by bMLastDat
The signal a is transmitted to the BBus data controller. BB
The movement of data from us to Fifo or from Fifo to BBus is performed by the BBus data controller.

[0342] 3. BBus data transfer end There is no particular signal indicating transfer end. bErrorOut_
There is no assertion of the L signal. However, bSEna
If the ble (N) signal is negated, there is no response to the master's access, and a bus error due to timeout occurs.

[BBus Slave Operation (Register Access)] The GBI and registers in the functional blocks are accessed from the BBus. For register access,
It can be accessed at any time regardless of the GBI mode or state. bRetryOut_L, bErrorOut
It does not assert the _L signal. A single transfer always responds to the master's burst mode request (does not assert the bBurstAckOut_L signal).

[0344] The register controller 9206 stores the reg
Start_L, regAddr [31: 2], byt
eEnIn [3: 0], regWr_L signal (BBus
Signal that was hit with the BBus clock)
If writing to a register, bDataIn [3
1: 0] signal, and the Ack signal (GBI
Then, in regGbiAck_L, IFbus, re
gIfAck_L) is asserted. In the case of reading from a register, data is transferred to an internal bus (in the GBI, re
gGbiDataOut [31: 0], in IFBus, regIfDataOut [31: 0], and the Ack signal (regGbiAck_ in GBI).
L, IFBus asserts (regIfAck_L).

In the BBus slave generate ready,
Create bRdyOut_L from the Ack signal.

(BBu other than GBI register access)
(cycle of s) In the GBI slave mode, the cycle of the single transfer is always 3 BBus clocks. In the burst transfer, the first bRdyOut_L signal is asserted at the same timing as the single transfer, and thereafter, the assertion continues for the necessary clock without being negated.
When transfer (single and burst) cannot be performed, bRdyOut_L is asserted at the first timing, bRdyOut_L is asserted.
Assert only entryOut_L.

(BBus Slave Generate Ready Block) The BBus slave generate ready block is a Channel from the BBus slave sequencer.
The Rdy_L signal and re from the GBI register unit
gGbiAck_L signal and functional block (IFBus)
OR the regIfAck_L signal from, and hit with the clock.

(IFBus Interface) IFBu
s is a simple bus connecting GBI and functional blocks. The clock uses bClk (50 MHz).
The input signal here is a signal in the direction from the functional block to the GBI. There are no bidirectional signals. IFBu below
The signal of s will be described. A signal name ending with "_L" indicates that it is low active. This is the same for the part already described. In an actual implementation, “if” of the signal name is replaced with the name of the functional block.

• ifRst0_L (channel 0), if
Rst1_L (channel 1) (output) This is an IFBus reset signal. With this signal, I
Return the state of the FBus to the initial state. Asserted by the GBI internal register. It must be asserted before the transfer between the GBI and the functional block.

IfDataOutB [63: 0] (input: channel 0 only) This is a data signal from the functional block to the GBI. This signal is connected to the Fifo unit 0 (see FIG. 93).

IfWriteB (input: channel 0 only) This is a write signal from the functional block to the GBI. GBI
Is the ifCl signal for which the ifWrite signal is asserted.
At the rise of k, ifDataOut [63: 0] is written. By continuing to assert the ifWriteB signal, data can be written in units of one clock. This signal is connected to the Fifo unit 0 (see FIG. 93).

• ifWriteEnableG (output:
(Only channel 0) This is a write permission signal from the functional block to the GBI. i
at the rise of fClk, ifWriteEnable
If the G signal is asserted, it indicates that writing is possible at the next rising edge of the clock. ifWrite
The assertion of the B signal is performed after confirming the ifWriteEnableG signal. This signal is output from the Fifo unit 0.

• ifDataInG [63: 0], if
ByteEnG [7: 0] (output: channel 1 only) Data and byte enable signal from GBI to functional block. This signal is connected to the Fifo unit 1. Table 8 shows the correspondence between each digit of the signal ifByteEnG [7: 0] and each byte unit of ifDataInG [63: 0].

[0354]

[Table 8]

• ifRead (input: channel 1 only) This is a read signal from GBI to the functional block. GBI
Is the ifClk for which the ifRead signal is asserted
Rises, ifDataInG [63: 0] and i
Output fByteEnG [7: 0]. ifRead
By continuing to assert the signal, data can be read in units of one clock. This signal is connected to the Fifo unit 1.

IfReadEnableG (output: channel 1 only) This is a read permission signal from the GBI to the function block. i
at the rising edge of fClk, ifReadEnableG
If the signal is asserted, it indicates that reading is possible at the next rising edge of the clock. The assertion of the ifRead signal is performed after confirming the ifReadEnableG signal. This signal is output from the Fifo unit 1.

IfRegStart_L (common to channel) (output) This signal is a signal obtained by hitting bStart_L of the BBus with a clock. ifRegAddr [31: 2] signal, ifRe
gRdNotWr signal ifByteEn_L [3: 0]
It is asserted for one clock with the signal. In the case of writing to the internal register of the functional block, the signal if
RegDataIn [31: 0] is also valid.
In the functional block, the address is checked when ifRegStart_L is asserted. If access to an internal register of the functional block is performed, ifRegAc_L is accessed.
Responds with k_L signal. Otherwise, the next ifRe
Wait for gStart_L to be asserted. This signal is BB
output from the us controller.

IfRegAddr [31: 2] (common to channel) (output) This is an address signal obtained by hitting bAddr [31: 2] of BBus with a clock. The signal becomes valid at the same time as the assertion of the signal ifRegStart_L, and is effective during the response to the ifRegAck_L signal when accessing the internal register of the functional block. This signal is output from the BBus controller.

IfRegByteEn [3: 0] (common to channel) (output) This is a byte enable signal obtained by hitting byteEn_L [3: 0] of the BBus with a clock. Signal ifRegSt
It becomes effective at the same time as the assertion of the "art_L" signal.
It is effective while responding with the k_L signal. When writing to an internal register of a functional block, only valid bytes indicated by this signal are written. In the case of reading from the internal register of the functional block, this signal is ignored and all bytes are output. This signal is output from the BBus controller. Table 9 shows the signal ifRegB
Each digit of yteEn [3: 0] and signal ifRegData
The correspondence with each byte unit of InG [31: 0] is shown.

[0360]

[Table 9]

IfRegRdNotWr (common to channel) (output) This signal is a signal obtained by tapping bWr_L of the BBus with a clock, and indicates the direction of access to the internal register of the functional block. When high, the contents of the internal register of the functional block
output to eqDataOut [31: 0], low,
The data of ifReqDataIn [31: 0] is written to the internal register of the functional block. Signal ifRe
It becomes valid at the same time as the gStart_L assertion.
It is valid while responding with the gAck_L signal. This signal is output from the BBus controller.

IfRegAck_L (common to channels)
(Input) This signal indicates that the function block has completed access to the internal register. When the signal ifRegStart_L is asserted, the address is checked, and if the internal register of the functional block is accessed, the register is read or written, and the signal is always asserted for one clock. If it is not an access to the internal register of the functional block, it must never be asserted. This signal is connected to the BBus controller.

• ifRegDataOut [31: 0]
(Common to channel) (Input) This is a data bus signal from which the contents of the internal register of the functional block are read. Must be valid when the signal ifRegAck_L is asserted. This signal is connected to the BBus controller.

IfRegDataIn [31: 0]
(Common to channel) (Output) This is a bus signal indicating data to be written to the internal register of the functional block. The signal becomes valid at the same time as the assertion of the signal ifRegStart_L, and is effective during the response to the ifRegAck_L signal when accessing the internal register of the functional block. This signal is output from the BBus controller.

IfDmaPmState [1: 0]
(Common to channel) (output) A signal indicating the operating state of the GBI. This output is always valid. The function block generates a power management status signal to the power management unit based on this signal and the operation state of the function block itself. This signal is output from the register unit. The output value will be described later in the section on power management.

(DMA Controller) In the GBI, DMA controllers 9205 as shown in FIG. 96 exist for channels 0 and 1, respectively.

The DMA controller comprises a DMA main controller, a fetch chain table, a calculated pitch address, a generate address, and a lock for each part of the DMA request.

From the register unit 9206, Table 10
The mode of DMA is transmitted by this signal.

[0369]

[Table 10]

Next, each part lock of the DMA controller will be described.

[DMA Main Controller] The DMA main controller controls the start and stop of the other four blocks. In the chain table type DMA, the fetch chain table, the generate address, the DMA
The blocks are started by shifting the clock by one clock in the order of the requests. In a pitch-added DMA, blocks are started up by shifting one clock at a time in the order of a calculated pitch address, a generate address and a DMA request. Otherwise, generate address and DMA
Activate the request with one clock delay.

The DMA main controller is a DMA main controller.
Is determined. When the fetch chain table is in an idle state (the chain table has been completely read or not activated) and the calculated pitch address is in an idle state (all lines have been completed or not activated), the Ne of the generated address is Ne.
assertion of xtAddReReq signal (length counter becomes zero) or bus error, stopDM
Upon detecting the assertion of the A signal (DMA forced termination by the register), the DMA main controller asserts the stopDMAReq signal to each block. When all the blocks are in the idle state, it is determined that the DMA is completed (endDMA is asserted).

[Fetch Chain Table] The fetch chain table is a block for fetching a table on the memory, and is not activated when the chain table is not used. A chain table pointer address counter for a memory address pointing to the chain table, a chain table entry counter indicating the number of remaining entries in the chain table, a next address register storing addresses and lengths fetched from the chain table, a next length register, and It comprises a fetch chain table controller for controlling these.

When activated by the DMA main controller, the contents of the register are loaded into the chain table pointer address and the chain table entry counter. A request for fetching the address chainAddress [31: 2] is made to the BBus controller by the chainReq signal. Ch from BBus controller
With the ainDone signal (normal end), the read contents are latched in the next address register, and the chain table pointer address counter is incremented. B
When a ChainRtry signal (retry) is returned from the Bus controller, the same request is issued again to the BBus controller.

After latching the next address register,
Address Chain Addr to BBus controller
Request fetch of esss [31: 2]. Chain
In response to the Done signal, the read content is latched in the next register, the chain table pointer address counter is incremented, and the chain table entry counter is decremented. At the same time, nextAd
Assert the drValid signal and notify the generated address block that the address and length have been read from the chain table.

If the data at the time of latching the next register is zero, the contents of the next address register are loaded into the chain table pointer address counter.

During the assertion of the nextAddrValid signal, the NextA
When the ddrReq signal is asserted, the generate address block determines that the address and length from the chain table have been received, and nextAddrVal
Negate the id signal.

Next, the chain table entry counter is checked. If it is not zero, the fetch of the chain table is continued again. If it is zero, the process returns to the idle state.

When the chain BErr signal (bus error) is received, it immediately returns to the idle state. When the stopDMAReq is received from the DMA main controller, if a request has been issued to the BBus controller, the end is waited for, and if not, the operation immediately returns to the idle state.

In the mode in which the chain table is not used, since it is not started, the idle state is maintained and next
The AddrValid signal remains negated.

[Generate Address] The generate address block includes a transfer memory address counter for storing a transfer address for the memory, a transfer length counter for storing a transfer length to be transferred,
A transfer counter for storing the number of transferred bytes,
A generate address controller that controls these three counters, and a GBus /
Check for determining the mode requested for BBus
It has a GBusReq and a CheckBBusReq block (collectively referred to as CheckG / BBusReq).

(When a chain table is used) When activated by the DMA main controller, the transfer counter is cleared and ne
It waits for the xtValidAddrCT signal. next
When the ValidAddrCT signal is asserted, the address and length of the chain table are loaded into the transfer memory address counter and the transfer length counter, respectively.

CheckG / BB is determined by the contents of both counters.
usReq determines a transferable mode.

CheckG / BBusReq to DMA
The transfer mode of G / BBus is transmitted to the request block (when transfer is not possible, the g / b Valid signal is negated).
A transfer request is issued to each bus controller with priority.

In the transfer by the G bus, the transfer memory address counter and the transfer counter are incremented and the transfer counter is decremented at a time by the gMDone signal (the G bus transfer end signal) and the transfer mode at that time. In the transfer on the B bus, the transfer memory address counter is incremented and the transfer counter is decremented by an access signal of the FIFO.

When the transfer counter becomes zero, the next Va from the fetch chain table is read.
If the lidAddrCT signal is negated, it waits for an assert, and loads the contents of the next chain table into the transfer memory address counter and the transfer counter, otherwise loads immediately. Then, the next transfer is started.

When the transfer counter has reached zero after the transfer of the last part of the chain table has been completed, the fetch chain table is in an idle state and n
The extValidAddrCT signal is negated. Since the DMA main controller detects the end of the DMA, the stop main DMA
Assert the Req signal. As a result, the generate address enters an idle state.

(When Using DMA with Pitch) DMA
When activated by the main controller, the transfer counter is cleared and the process waits for the next ValidAddrPA signal from the calculated pitch address. n
When the extValidAddrPA signal is asserted, the address and the length calculated from the start address and the pitch are loaded into the transfer memory address counter and the transfer length counter, respectively.

As in the case of using the chain table, the transfer memory address counter and the transfer counter are incremented, and the transfer counter is decremented.

When the transfer counter reaches zero, the next from the calculated pitch address
If the ValidAddrPA signal is negated,
Upon assertion, the contents of the next chain table are loaded into the transfer memory address counter and the transfer counter, otherwise immediately. Then, the next transfer is started.

When the transfer counter becomes zero after the transfer of the last line is completed, the calculated pitch address is in the idle state and nextVal
The idAddrPA signal is negated. Since the DMA main controller detects the end of the DMA, it asserts the stopDMAReq signal for the generate address. As a result, the generate address enters an idle state.

(In the case of I / ODMA) When activated by the DMA main controller, the transfer counter is cleared, and the contents of the GBIDMA transfer length register storing the data length are loaded into the transfer counter. CheckGBusReq / CheckBBu
Each block of the sReq is a GBIDGMGBus I / O address register storing a DMA address of the I / O.
The contents of the GBIDDMAB Bus I / O address register are used.

Similarly to the above, the transfer counter is incremented and the transfer counter is decremented.

When the transfer counter becomes zero, the fetch chain table and the calculated pitch address have not been activated, so that the next ValidAddr signal is negated in the idle state. Since the DMA main controller detects the end of the DMA, the stop main DMA
Assert the AReq signal. As a result, the generate address enters an idle state.

(Reverse Mode) The reverse mode is supported except for the paired I / ODMA. Chain table DM
One block of A and one line of DMA with pitch are accessed from the larger address to the smaller address. An instruction in the reverse direction for each block or line is made in the chain table DMA so that the chain table is reversed. In the case of a DMA with a pitch, the pitch value is set to a negative value (two's complement).

In the reverse mode, when loading a value into the transfer memory address counter, the last address is calculated and loaded using the transfer length. Decrement instead of incrementing the transfer memory address counter.

The CheckBBusReq block requests only a single transfer. CheckGBusReq
The block requests only 4-beat burst transfer. F
In the ifo unit, the data is sent to the functional block in reverse order in units of 32 bits (currently, only channel 1 is supported).

(Check of GBus Request) CheckG
In the BusReq block, a GBus request is checked. The signal gValid is always negated unless the signal useGBus is active.

[0399] Bits 6 and lower of the transfer memory address are all zero, and the transfer length is 128.
At this time, the signal gValid is asserted and g4Not1
6Req = '0', when bits 4 and below of the transfer memory address are all zero and the transfer length is 32 or more, the signal gValid is asserted, and g
4Not16Req = '1'. Otherwise, the signal gValid is negated.

(Check of BBus Request) CheckB
In the BusReq block, a BBus request is checked. The signal bValid is always negated unless the signal useBBus is active.

When bits 4 and below of the transfer memory address are all zero and the transfer length is 29 or more, the signal bValid is asserted and bBurstR
When eq = “1” and b4Not8Req = “0”, and when bits 3 and below of the transfer memory address are all zero and the transfer index is 13 or more, bVa
lid is asserted, signal bBurstReq = '1',
b4Not8Req = '1'. Otherwise, b
Valid is asserted, and bBurstReq = '0'.

(DMA Request) When activated by the DMA main controller, a request for a GBus / BBus from the generate address block is checked. When there are both G / BBus requests, G
Bus has priority. According to this request, a transfer request is issued to the Gbus controller or the BBus controller, and a response is waited. The response is g / bMDone, g / bMRtr
The signal is either y or g / b MBErr.

In the case of g / bMDone, transfer is normally completed, and GBus / B from the next generate address
Check the request for Bus.

In the case of g / bMRtry, a transfer request is issued again to the same bus controller.

In the case of g / bMBErr, the operation immediately returns to the idle state.

When the last transfer is completed, the DMA request block contains the GBu from the generate address.
s / BBus is in a request waiting state. Since the DMA main controller detects the end of DMA and issues stopDMAReq in response to the DMA request,
As a result, the DMA Request returns to the idle state.

[0407] Also, in the case of a bus error at the time of fetching a chain table or a forced termination of DMA by a register, the DM
A StopDMAReq is issued from the A main controller. When a transfer request is issued to the bus controller, the transfer is waited for to be completed. When the transfer request is not issued, the bus controller immediately returns to the idle state.

(Register Unit) In the internal register unit, there is a register unit corresponding to each channel. Each unit is the same except that the decoding address is different. The register unit has a register unit 0 and a register unit 1 as shown in FIG.

Each register unit has a register I / F,
The GBI, which consists of an action controller, an interrupt controller, and a power status block, supplies a set ground value to each block of the GBI. The interrupt controller controls interrupts, and the power status controls power-saving blocks. .

[Power Status] The units capable of the power saving mode in the GBI are the DMA controller and the FI
FO unit. The power saving mode is fifoInSl
This is realized by masking the clock of each block with the eep signal and the dmaInSleep signal. At the time of reset, both enter the power saving mode. The DMA controller starts automatically when it is started in the master mode.
Go to sleep by writing to the BIFIFO sleep register.

The power management status signal (pmState) output from the power status block
[1: 0]) is pmState [1: 0] 00 level0 (stops both DMA and FIFO) 01 level1 (operates only FIFO) 10 level2 (operates both DMA and FIFO) 11 NotDefine in each channel.

In DoEngine, a scanner controller (Scc) and a printer controller (Pr)
Since GBI to which c) is connected has only one channel, the GBI is as described above. When the GBI includes two channels, the values of each channel are summed and degenerated into four stages as follows.

PmState [1: 0] 00 level0 (both channel FIFO and DMA are stopped) 01 level1 (only one channel FIFO is operated) 10 level2 (both channel FIFO is operated and DMA is both stopped) 11 level3 ( The FIFOs of both channels operate, and one of the DMAs operates).

The power management status signal (p
mState [1: 0]) is sent to the functional block via IFBus. The function block generates a power management status signal to the power management unit based on this signal and the operation state of the function block itself.

(GBI Operation Mode) The components constituting the GBI have been described above. Here, the operation of the GBI will be summarized. The operation modes of the GBI are roughly classified into the following.

[0416] 1. Slave mode 2. Master Mode The DMA mode in the master mode is as follows. B. Memory There is I / O (fixed address), and in memory DMA: a. Contiguous physical address b. Data is transferred to a memory at a discontinuous physical address (assuming that the transfer destination memory is divided into memory management pages). In addition, the memory DMA also supports a backward mode (only channel 1).

[0417] The DMA for the continuous physical address is a so-called two-dimensional DMA that specifies the start address, the length of one line, the pitch to the next line, and the number of lines. The one-dimensional case is realized by setting the number of rows to one.

[0418] In the DMA for discontinuous physics, the start address and length of each divided memory block are arranged in the memory, and the transfer destination address is calculated while referring to the address, and DMA is performed. This set of the start address and the length is called a chain table. FIG. 98 shows an example of the chain table. DMA for discontinuous physical addresses
Then, the number of pairs of the memory address and the address / length in which the chain table is arranged is specified. Of course, the chain table itself must be located at a contiguous address, but if the entire chain table cannot be located in a contiguous area, the address of the next chain table is used instead of the first address, and 0 is set for the length. By setting, you can connect chain tables.

[0419] In the reverse mode, the chain table DMA is used.
One block of the two-dimensional DMA is accessed from the larger address to the smaller address. Instructions in the reverse direction for each block or line can be made in the chain table DM.
In A, the chain table is made upside down. In the case of a DMA with a pitch, the pitch value is set to a negative value (two's complement).

(Interrupt Control) Next, interrupt control will be described. An interrupt from the DBI occurs under the following conditions.

[Master mode] 1. Normal end of DMA 2. Bus error detection during DMA transfer on GBus 3. Bus error detection during DMA transfer on BBus Detection of Bus Error During Chain Table Read in Chain DMA Mode In the case of forced termination by the GBI stop register, the transfer ends normally when the transfer requested by the DMA controller to the controller of each bus ends normally. If the requested transfer results in a bus error, the transfer ends abnormally due to the bus error.

[0422] In channel 0, the processing ends when the functional block writes all data to the FIFO in the GBI (an interrupt is generated), but data remains in the FIFO. When GBI transfers data in the FIFO,
Since the transfer is completed, it is determined that the transfer is completed.

[0423] In channel 1, the GBI is the FI in the GBI.
Processing ends when all data has been written to the FO (an interrupt is generated), but data remains in the FIFO. Since the function block ends when the data of the FIFO is transferred, it is determined that the transfer is completed.

[Slave mode] 5. FIFO illegal access Data transfer between the functional blocks allocated to the GBI and the master is performed via the GBI FIFO.

In the case of using both GBus / BBus (in DoEngine, GBI is the only master that can use both GBus / BBus), in order to access both buses simultaneously, which bus is first FIFO
There is no way to know what to access. Master is GBus
/ BBus must be exclusively requested to transfer (in the GBI master mode, a transfer request is exclusively requested). If both GBus / BBus are FIF
When O is accessed, it becomes FIFO illegal access.

If any one of the above 1 to 5 occurs and the corresponding interrupt enable bit is set to "1", an interrupt is generated.

(Core Interface) FIG.
FIG. 2 shows a diagram of a core interface in which I and interfaces with BBus / GBus / functional blocks are summarized.
Since the GBI does not issue a bus error in the BBus slave operation, there is no bError (Func) Out_L. In addition, GBI uses bInst
Because the NotData signal is not checked, (fun
c) no bInstNotData_in, (fun
c) bInstNotData_out is always “0”
Drive.

Since the GBI does not issue a bus error in the Gbus slave operation, (func) gErr_L
There is no _out.

In FIG. 99, Func (func) in the signal name of GBI indicates a functional block to be connected.
That is, scc (scanner controller) or pr
Enter the name of c (printer controller).

In DoEngine, as a functional block, Scc (scc) of the scanner controller is used.
And Prc (prc) of the printer controller.
In either case, since the data flow is not bidirectional, the implementation is performed with unnecessary FIFOs, DMA controllers, and registers eliminated.

(Printer Controller Core Interface) FIG. 86 is a diagram summarizing signals input and output between the core portion including the above-described blocks in the printer controller 4303 and an external bus or scanner. As described above, the printer controller 4303 is connected to the system bus bridge 402 by the G bus, is connected to the IO device, the power management device, and the system bus bridge by the B bus, and is connected to the printer controller by the CP bus. They are connected by a bus, and connected to a G bus / B bus I / F unit by an I / F bus.

2.10. Power Management Unit FIG. 87 is a block diagram of the power management unit 409.

[0433] DoEngine is a large-scale ASIC with a built-in CPU. For this reason, if all the internal logics operate simultaneously, a large amount of heat is generated, and the chip itself may be destroyed. To prevent this,
The DoEngine performs power management for each block, that is, power management, and further monitors the power consumption of the entire chip.

The power management is performed individually by each block. Information on the power consumption of each block is collected in a power management unit (PMU) 409 as a power management level. The PMU 409 sums up the power consumption of each block and monitors the power consumption of each block of the DoEngine collectively so that the value does not exceed the limit power consumption.

(Operation) The operation of the power management block is as follows. -Each block has four power management levels. The PMU has the power consumption value at each level as a register. The values of the level configuration and the power consumption are held in the PM configuration register 5401. The PMU receives the power management level from each block as a 2-bit status signal (described later),
The power consumption of each block is known by checking the value set in the register 5401. The PMU adds the power consumption of each block by the adder 5403, and calculates the total power consumption of the DoEngine in real time. The calculated power consumption is compared with the power consumption limit value (PM limit) set in the configuration register 5401 by the comparator 5404. If the power consumption exceeds the limit, an interrupt signal is issued from the interrupt generator 5405. I do.・ This limit value can be set in two stages. In the first stage, a value is set with some margin from the true limit. If this value is exceeded, a normal interrupt signal is issued. In response, the software does not start a transfer that starts a new block. However, a new block can be started under the management of software within a range not reaching the limit value of the second stage. As the limit value in the second stage, a value that may cause destruction of the device is set. Should this value be exceeded, an NMI (interrupt for which an interrupt mask cannot be set) is issued to stop the system for safety. The interrupt signal is released by reading the status register 5402 of the PMU. The timer starts counting from the time when the status register 5402 is read. If the power consumption does not return until the timer expires, an interrupt signal is issued again. The setting of the timer value is set in the configuration register 5401 of the PMU.

(Power Management of Each Block) The power management control of each block may be freely configured for each block. The example of a structural example is shown.

(Configuration Example 1) In this example, the power management is performed by turning on / off the clock to the internal logic, so that the power consumption level has only two levels. This level is sent to the power management unit 409 as a status signal. FIG. 88 shows a block diagram of the bus agent. The bus agent 5501 includes an internal logic 5502 for each unit and a decoder 55 for decoding an address.
03, a clock control unit 5504, and a clock gate 5505. -Decoder 5503 and clock control unit 5504
Is always running and monitors bus activity and gates clocks to internal logic as power management controls.

(Clock Control) The bus agent detects bus activity and automatically turns on / off the clock. The bus agent has three states: Sleep, Wake Up, and Wait. -Sleep is a state where the bus agent has no activity and the clock gate clock is stopped. -Even in the sleep state, the decoder unit 5503 and the clock control unit 5504 are operating, monitor the bus, and wait for a request. When the decoder 5503 detects its own address, it opens the clock gate 5505, operates the clock of the internal logic, and responds to the bus request. State is Wake Up
Move to Also, this state is changed to the power management unit 409.
Notify. When the data transfer is completed, the state shifts to the Wait state and waits for the next request. At this time, the clock remains running.
If there is a request, it returns to the Wake Up state and performs transfer. The timer counts while waiting for a request, and when the counter has timed out without a request, shifts to a sleep state and stops the clock. This state is also notified to the power management unit 409.

As described above, the power consumption is managed so as not to exceed the predetermined value.

(Copy Operation) With the above-described configuration, the image data read from the scanner can be directly transferred to the printer, and a copy operation can be performed to form an image with the printer. In the scanner / printer system using the Do Engine of the present embodiment, the following three types of copying methods are selected according to the system configuration.

(Method 1) In the first method, the vertical / horizontal timing of image input by the scanner and the horizontal / vertical timing of image output by the printer match, and the transfer speed of video data also matches. This is a method in a combination system.

[0442] The vertical synchronization signal (VSYNC) is output from the printer and input to the printer controller (PRC).
This VSYNC signal is transmitted from the printer controller (PRC) to the CP
Input to the scanner controller (SCC) via the bus. Then, it is output from the scanner controller (SCC) to the scanner. As a result, the printer and the scanner are vertically synchronized. As for the horizontal synchronization, similarly to the vertical synchronization signal VSYNC, a horizontal synchronization signal (HSYNC) is output from the printer and input to the scanner via the printer controller, the CP-bus, and the scanner controller. Thus, horizontal synchronization between the scanner and the printer is achieved.
As described above, the scanner and the printer operate in synchronization with each other in the vertical and horizontal directions. The video data is output from the scanner together with a video clock for synchronization. The output video clock and video data are input to a scanner controller (SCC) and input to a printer controller (PRC) via a CP bus. The data is output from the printer controller (PRC) to the printer. The printer receives video data in synchronization with a video clock and outputs an image.

This copy operation is performed by the structure shown in FIG. In this copy operation, the copy operation is performed without using the G bus and the B bus.

During the copying operation, the image data is directly transferred from the scanner to the printer via the CP bus. At the same time, the image data can be written to the SDRAM by the G bus DMA transfer from the scanner controller (SCC). The image data written to the SDRAM at the same time as the copy operation can be stored as image data if necessary. Further, by outputting the image data on the SDRAM to the printer, it becomes possible to output the image data read by the scanner to a plurality of units without operating the scanner.

(Method 2) In the second method, the horizontal timing of image input by the scanner and the horizontal timing of image output by the printer match, and the vertical timing does not match the transfer speed of video data. This is a method in a combination system.

The copy operation in this case will be described with reference to FIG. When the scanner starts reading an image, three timing signals, a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), and a video clock, are transmitted to the scanner controller (SC).
Entered in C). Video data is also input to the scanner controller (SCC) in synchronization with the video clock. Scanner controller (SCC) synchronized with the above timing signal
Captures video data into an internal FIFO (FIFO_SCC). As soon as image data starts to enter FIFO_SCC,
_SCC, scanner G bus / B bus I / F unit 43
Data transfer to the FIFO (FIFO_GBI_SCC) of 01A (GBI_SCC) is started. The image data from the scanner is
The data is sequentially transferred to FIFO_GBI_SCC via FO_SCC. FIFO_G
When data starts to enter BI_SCC, the printer's G bus / B
The bus I / F unit 4301B (GBI_PRC) is the master,
G bus / B bus I / F unit 4301A (GBI
_SCC) as a slave starts DMA transfer. At this time, if the G bus is available, use that bus,
If it is not vacant, it may be a B bus.

By this DMA transfer, the image data of FIFO_SCC is transferred to a FIFO (FIFO_GBI_PRC) in GBI_PRC. The image data of the FIFO_GBI_PRC is sequentially transferred to the FIFO (FIFO_PRC) of the printer controller (PRC). FIF
When image data starts to enter O_PRC, the printer controller (PRC) inputs a vertical synchronization signal (VSYNC) to the printer. The printer starts outputting a horizontal synchronization signal (HSYNC) and a video clock at the timing of VSYNC. The printer controller (PRC) performs horizontal synchronization with the horizontal synchronization signal HSYNC, and outputs video data from the FIFO_PRC in synchronization with the video clock. The printer outputs the video data as an image.

In the case of this copy operation, the image data is stored in the FIFO (FIFO_SC
C), G bus / B bus I / F unit FIFO (FIFO_GBI
_SCC), FIFO of the G bus / B bus I / F unit (FIFO_G
BI_PRC), Printer controller FIFO (FIFO_PR)
C), the image is transferred in the order of the printer, and the image copy operation is performed. Since the horizontal synchronization interval is the same between the scanner and the printer, differences in the transfer speed of image data are buffered by each FIFO.

(Method 3) The third method is a method in a combination system in which the vertical synchronization timing, the horizontal synchronization timing, and the video data transfer speed of the scanner and the printer are all different.

The copying operation in this case will be described with reference to FIG. When the scanner starts reading an image, the scanner sends a vertical sync signal (VSYNC), a horizontal sync signal (HSYNC),
Outputs the video clock to the scanner controller (SCC). Image data is output in synchronization with these timing signals. The scanner controller (SCC) captures image data in synchronization with the timing signal. The captured image data is transferred to the memory controller (MC) 403 by DMA transfer using GBI_SCC. The MC 403 writes the DMA-transferred image data to the SDRAM. When the amount of image data written in the SDRAM reaches an amount that can buffer the difference in image data transfer speed between the scanner and the printer, the transfer of image data to the printer is started. The determination of the image data amount is based on the data transfer time from the scanner,
There are various methods such as a determination based on an address written to a RAM and a determination of a DMA transfer amount in GBI_SCC.

The image data transfer to the printer is performed by the printer controller (PRC). The printer controller (PRC) sequentially inputs the image data written in the SDRAM to the internal FIFO by DMA transfer of GBI_PRC. At the same time, a vertical synchronization signal (VSYNC) is output to the printer. afterwards,
A horizontal synchronization signal (HSYNC) and a video clock are input from the printer. In synchronization with the HSYNC and the video clock, the printer controller (PRC) outputs image data from the internal FIFO to the printer. According to the flow of the image data, a copy operation for outputting the image data read by the scanner from the printer is performed. The flow of image data in this case is as follows: scanner, scanner controller,
Scanner G bus / B bus I / F unit (GBI_SCC), memory controller (MC), SDRAM, memory controller (M
C), Printer G bus / B bus I / F unit (GBI_PR
C), the printer controller (RRC), and the printer.
As described above, the image data is temporarily stored in the memory, and is used as a buffer memory between the scanner and the printer to transfer the image data from the scanner to the printer and perform copying.

The present system has the above three types of copy operation functions. (System 1), (System 2), and (System 3) in this order, the number of internal blocks that operate during the copy operation increases. As internal block usage increases, overall system performance can be a factor in reducing efficiency. In this system, the most efficient copy operation method can be selected for the entire system according to the connected device (printer / scanner).

As a method of selecting a copy method, for example, there is the following method. The user inputs the specified copy method via a UART or the like, and performs a copy operation in the specified method. Necessary parameters such as the data transfer speed of the printer and the scanner and the horizontal / vertical synchronization frequencies are input from the UART or the like.
01 selects one and causes a copy operation to be performed in that manner. The printer controller reads necessary parameters such as the data transfer speed and the horizontal / vertical synchronization frequency of the printer, and the scanner controller reads the necessary parameters such as the data transfer speed and the horizontal / vertical synchronization frequency from the scanner, and the CPU 401 compares and determines them. To determine the type of copy operation.

The copy method determined or selected by the above method is notified from the CPU to the printer controller and the scanner controller, and the printer controller and the scanner controller perform copying in that method.

Next, a procedure for determining a copy method by the above method will be described.

FIG. 100 is a flowchart of a procedure by the CPU 401 for selecting a copy method to be used in the system from the three copy methods. This operation is started from step S1 when the power of the system is turned on.

In step S2, the type of the printer is determined. The CPU 401 is the printer controller 43
An ID indicating the type is acquired from the printer via a command / status line included in the printer video I / F via the printer 03. The command / status line is a serial communication line that allows the printer controller and the printer to exchange commands / status on a one-to-one basis.

In step S 3, the CPU similarly controls the scanner video I / O via the scanner controller 4302.
An ID indicating the type is acquired from the scanner through the command / status line included in F.

In step S4, a copy path suitable for the combination of the scanner and the printer, determined in steps S2 and S3, is determined. The determination of the copy path suitable for the combination of the scanner and the printer is prepared in the form of a table in advance in a memory such as a flash ROM that can be referred to by the CPU. There are the following combinations of scanners and printers suitable for each copy path. (Method 1) A combination in which the horizontal and vertical timings of the scanner and the printer are synchronized and the transfer rate of video data is also synchronized. (Method 2) The speed of the horizontal synchronization timing of the scanner and the printer is the same, and the vertical timing and the video are synchronized. Combination of data transfer speed not synchronized (Method 3) Vertical synchronization timing of scanner and printer,
The combination CPU having different horizontal synchronization timings and different video data transfer speeds selects an appropriate copy method from the above three methods by referring to a prepared table.

[0460] In step S5, a mode setting corresponding to the copy method selected in step S4 is made to the scanner controller 4302. This mode setting is
PU performs via BBus.

FIG. 101 shows the scanner controller 430.
FIG. 2 is a diagram showing a circuit for switching a data bus inside the device; The data bus selector is included in the scanner device I / F 4401 in FIG. Further, a scanner video clock unit and the like which are not necessary for explaining the switching of the data bus are omitted.

In register 1, the mode of the data bus is set. The CPU sets a mode corresponding to the copy method selected in step S4 of FIG. The select control signal 4 is a signal for selecting a data path according to the mode set in the mode setting register 1. The scanner video bus 2 is a bus for video data from the scanner. The bus 5 is a bus that transfers video data from the scanner to the FIFO_SCC 6. C
The P video bus 7 is a bus used when performing the (method 1) copy operation. The data path is selected so that video data from the scan video bus is output to the CP video bus 7 in the case of (method 1). In the case of (method 2) or (method 3), video data is output to the bus 5 and transferred to the FIFO_SCC 4407.

In FIG. 100, the flow shifts to step S6. In step S6, the operation mode of GBI_scc is set. This mode setting is performed based on the copy method selected by the CPU in step S4. In (method 1), GBI_scc
Is designated as non-operational. In (method 2), the master of DMA transfer is designated, and GBI_prc is set as the DMA transfer destination. In (method 3), the master designation of the DMA transfer is performed, and the SDRAM is set as the DMA transfer destination.

Next, in step S7, the operation mode of GBI_prc is set. This mode is set by the CPU in step S
This is performed based on the copy method selected in step 4. In (method 1), non-operation is specified for GBI_prc. In (method 2), slave designation for DMA transfer is performed. In (method 3), the master designation of the DMA transfer is specified, and the SDRAM is set as the read source of the DMA transfer.

Next, in step S8, the mode of the printer controller is set. This mode setting is performed by the CPU based on the copy method selected in step S4.

FIG. 102 is a block diagram showing the printer controller 430.
FIG. 3 is a diagram showing a data bus switching circuit in the internal circuit 3; The data bus mode is set in the register 11. C
The PU sets the mode corresponding to the copy method selected in step S4 of FIG. The select control signal 14 is a signal for selecting a data bus according to the mode set in the mode setting register 11. The bus 15 is a bus for data output from the FIFO_PRC 16. Bus 12 is a video data bus to the printer. The CP video bus 17 is used when performing the (method 1) copy operation. In the case of (method 1), the video data to the printer selects and outputs the data on the CP video bus. In the case of (method 2) or (method 3), data from the bus 15 is transferred to the printer video bus 12
Is output to

[0467] In step S9, the flow of the copy method selection at the time of turning on the power supply ends. As described above, the CP
U can determine the copy method according to the type of scanner and printer.

The above procedure is for determining the type of copy operation based on the vertical synchronization timing and horizontal synchronization timing of the scanner and the printer, and the video data transfer rate. However, this does not apply to cases where That is, before step 2 in FIG. 100, it is determined whether or not to process the image data. If the image data is to be processed, method 3 is selected regardless of the specifications of the scanner and the printer.
In the settings in 5 to S8, each block is set so that the data path is the method 3. By doing so, when the image data is processed, the read image data is temporarily stored in the memory, so that necessary processing can be performed on the image data there.

[0469] In the method 2 or 3, a bus is used. At this time, whether to use the G bus or the B bus is determined according to the usage status of each bus. That is, if both the G bus and the B bus are in the idle state, the G bus having a wide bus width is used. If any are in use, use the unused one.

As described above, in DoEngine, the scanner is the scanner controller 4302
And a bus (G bus and B bus) via the GBI_SCC 4301A. Scanner controller 4
302 and GBI_SCC4301A are FI
They are connected so as to transfer image data to each other via the FO. Thus, since each has a FIFO, the GBI has a 64-bit width and an operation clock of 1
Despite being connected to a very high-speed G bus of 00 MHz, image data read from a relatively low-speed scanner can be efficiently transferred. this is,
The same applies to the printer controller.

Further, by selecting a data path at the time of copying in accordance with the coincidence or non-coincidence of the respective synchronization signals of the scanner and the printer, the data can be transmitted as quickly as possible regardless of the specifications of the scanner and the printer. Copying can be performed using data transfer.

That is, by connecting the scanner and the printer to the DoEngine bus using the above-mentioned scanner controller and printer controller and their respective GBIs, the DoE from the specifications of the scanner and the printer can be obtained.
This has made it possible to further increase the independence of ngine.

[Other Configuration Examples] The operation procedure of the cache shown in FIGS. 9 and 10 may be as shown in FIGS. 103 and 104.

In FIG. 103, when data transfer is started from the MC bus, m is first indicated by the MC bus.
It is determined by TType [60: 0] whether the transfer is performed with the cache on or off. Here, when the transfer is a burst transfer, the determination is made based on whether the burst transfer data amount is larger or smaller than the data amount of one line of the cache. One line of the cache is 256 bits = 4
It is a burst amount.

In FIG. 103, the memory controller checks mTType [3: 0] at the start of transfer, and
If the burst length indicated by TType is 1/2/4, the operation is performed with the cache turned on, and 6/8/16/2 × 16/3 ×
In the case of 16/4 × 16, it operates with the cache off. The operation after the cache is turned on or off is shown in FIGS.
Is the same as

Also, as shown in FIGS. 105 and 106, the cache can be switched on / off depending on the device. In FIG. 105, the memory controller identifies the transfer request device by checking mTType [6: 4] at the start of transfer, and determines whether the transfer request of the device operates with the cache on or off. For this purpose, it is determined whether to operate with the cache on or off with reference to a preset value of the configuration register. The operation after the cache is turned on or off is the same as in FIGS. The setting of the configuration register may be determined (cannot be changed) by hardware or may be rewritable by software.

(Embodiment) (Job division) First, an embodiment of the present invention will be described.
This will be described with reference to FIGS. In this embodiment,
In order to process various jobs input to the digital MFP in page units, acquisition and release of devices are performed in parallel to process information.

FIG. 107 is a block diagram of an information processing system according to the present invention. In FIG. 107, 101a, 102a, 1
A host computer 03a generates various jobs and transmits the jobs to peripheral devices. A digital multifunction peripheral 104a executes various jobs such as a print job, a scan job, a fax job, and a copy job.
The first and second host computers 101a and 102a and the digital multifunction peripheral 104a are each connected to a LAN (local area network) 105a,
The digital multifunction peripheral 104a can be used.

Also, the third host computer 103a
Is a digital multifunction peripheral 104 via an interface 106a such as a parallel (or serial) instead of a LAN.
a, and the digital multifunction peripheral 104a can be used.

FIG. 108 is a block diagram showing a basic configuration of the information processing system shown in FIG. 107. In FIG. 108, reference numeral 201a denotes a CPU (Central Processing Unit) which controls the entire system and executes arithmetic processing and the like. I do. An engine interface (engine I / F) 207a exchanges commands and the like for actually controlling the engine.

Reference numeral 208a denotes a network interface (network I / F).
The device is connected to the network via 08a.

209a is an external interface (external I
/ F), it is connected to a host computer via an interface such as parallel (or serial). 21
Reference numeral 0 denotes a system bus, which serves as a data path between the above-described components.

A CPU 201a, an engine interface (engine I / F) 207a, a network interface (network I / F) 208a, and an external interface (external I / F) 209a are DoEngine.
201 (FIG. 2).

Reference numeral 202a denotes a ROM (read only memory), which is a storage area for a system startup program, a program for controlling the printer engine, character data, character code information, and the like. A RAM (random access memory) 203a is a storage area having no expiration date, in which font data additionally registered by downloading is stored, and programs and data are loaded and executed for various processes.

Reference numeral 204a denotes an external storage device such as a hard disk, which spools a print job (print job) received by the printing device (printer), stores programs and various information files, and uses it as a work area. Is done.

[0486] Reference numeral 205a denotes a display unit such as a liquid crystal display, which indicates the setting state of the printing apparatus, the current processing state inside the printing apparatus,
Displays error status, etc.

An operation unit 206a is used to change or reset the settings of the printing device.

FIG. 109 is a diagram showing the internal software structure of the host computer and the digital multifunction peripheral 104a. In FIG. 109, reference numeral 301 denotes the host computer (FIG. 1).
07 corresponding to 101a to 103a). 302
Denotes controller software, in which the protocol interpreter 303, the job controller 304, and the device 30
It is divided into five.

The protocol interpreting unit 303 interprets a command (protocol) transmitted from the host computer 301 via the LAN 105 in FIG. 1 or the external I / F 209 in FIG. This is the part that requests execution. Also, the job control unit 304
Is a part for actually processing the job requested by the protocol interpreting unit 303. Further, the device unit 305 is used when the job control unit 304 executes a job.

FIG. 110 shows the controller software 3
FIG. 2 is a block diagram for explaining an outline of the second embodiment. In the figure, reference numeral 303 denotes a protocol interpreting unit, 304 denotes a job control unit, and 305 denotes a device unit. Job control unit 304
Has a job generation unit 401a, a job processing unit 402a, a document processing unit 403a, a page processing unit 404a, a band processing unit 405a, and a device allocation unit 406a.

The device section 305 includes a first device 407a, a second device 408a, and a third device 40a.
9a.

The host computers 101a to 101a to
A series of operation requests sent from the network interface 103a are transmitted as a command (protocol) in the form of a network I / F 208.
a and the external I / F 209a. The sent command is interpreted by the protocol interpreting unit 303 and then sent to the job control unit 401a. At this point, the command is converted into a form that the job control unit 304 can understand.

[0493] The job generation unit 401a generates a job 410a. Various jobs such as a copy job, a print job, a scan job, and a fax job can be considered as the job 410a.

For example, in the case of a print job, it also includes setting information such as the name of a document to be printed, the number of copies, designation of an output tray as an output destination, and print data itself (PDL data). The job 410a is sent to the job processing unit 402a,
Processing is performed. Here, settings (such as collectively printing and stapling a plurality of documents) and processing relating to the entire job 410a are performed.

Further, the job processing unit 402a divides the job 410a into input documents 411a, which are smaller units of work, except for the settings and processing relating to the entire job 410a.
The input document 411a is sent to the document processing unit 40
The document is converted into an output document 414a by 3a.

That is, for example, considering a scan job in which a bundle of originals is read by a scanner and converted into a plurality of image data, the input document 411a describes the settings and operation procedures related to the bundle of originals. An output document 414a describes settings and operation procedures for a plurality of image data. The document processing unit 403a has a role of converting a bundle of paper into a plurality of image data.

[0497] The document processing unit 403a performs only processing in units of documents, and generates an input page 412a that is a smaller unit of work. This is the same as the case where the job processing unit 402a concentrates on processing on a job basis and generates a document for more detailed work. The setting and operation in the document unit specifically relate to page order such as page rearrangement, double-sided printing designation, display addition, OHP insertion, and the like.

The input page 412a is converted into an output page 415a by the page processing section 404a. For example, in the case of the above-described scan job, the input page 4
Settings and procedures such as reading resolution and reading direction (landscape / portrait) are written in 12a, and the storage location of image data (address and data name of the RAM 203a and the external storage device 204a) is written in the output page 415a. Settings and procedures are written.

[0499] Through the above processing, the job configuration can be decomposed into pages and handled.

In an expensive system, if a page memory for one page can be provided, the job may be finally detailed in page units. However, in reality, when the cost of the memory is a problem or when the print engine is at a low speed such as an ink jet printer, a system having only a few lines of memory (band memory) may be considered. In such a case, the page is divided into bands, which are smaller units. That is the input band 413a, the band processing unit 40
5a, the role of the output band 416a. These operations are similar to those of the page.

[0501] Job processing unit 402a, document processing unit 403a, page processing unit 404a, and band processing unit 4
05a uses a device when proceeding with the process. If a plurality of processing units work simultaneously, device contention occurs, and the device arbitration unit 406a mediates the conflict. First to third devices 407a to 407
09a is a device assigned to the processing unit by the device assignment unit 406a.

[0502] Examples of the device include a page memory, a band memory, a document feeder, a marking engine, and a scanner.

(Processing of Composite Job) FIG. 110 shows processing of decomposing a single job into pages and allocating devices. Next, processing of a combined job will be described with reference to FIG.

[0504] The "combined job" is, for example, if the job is a copy job, it is divided into a scan job and a print job, and if it is a FAX reception job, the data reception job and the received data print job And divided into Devices are allocated to the divided jobs on a page basis and are processed. Hereinafter, the processing content will be described. Note that the basic configuration of the information processing system is the same as in FIGS. 107 to 109 described in the above-described division of a single job, and therefore, these drawings will be used as necessary.

FIG. 111 is a diagram showing details of the software structure of peripheral devices in the information processing system for processing a composite job. In the figure, reference numeral 303 denotes a protocol interpreting unit, 304 denotes a job control unit, and 305 denotes a device unit.

The copy job is divided into two jobs (scan job and print job) in the job control unit 304 and processed. A series of operation requests sent from the host computers 101a to 103a in FIG. 107 are sent in the form of commands (protocols) via the network I / F 208a and the external I / F 209a in FIG.

[0507] The transmitted command is interpreted by the protocol interpreting unit 303 and then sent to the job control unit 304. At this point, the command is converted into a form that the job control unit 304 can understand. Job generation unit 401
a generates the job 410a of FIG. In the present embodiment, a copy job is generated.

[0508] The generated copy job 513 corresponds to the copy job 513 shown in FIG.
The scan job 514 and the print job 521 are sent to the first composite job processing unit 501. The scan job 514 and the print job 521 are sent to the scan job processing unit 502 and the print job processing unit 506, respectively, at the same time as the generation. Of course, the printing operation cannot be started unless the scanning operation starts and data to be output to the printer 512 is completed (or ready). Therefore, the processing units (502, 503, 504, 50
5) and a processing unit (506, 507, 50) related to printing
8, 509), the process proceeds while synchronizing via an intermediate document 518, an intermediate page 519, and an intermediate band 520 which mean intermediate data. In the copy job, the scanner 51 is used as a device to be used.
0, page memory 511, and printer 512.

FIG. 115 is a block diagram showing an example of job division. If the command sent from the host computer 301 is a copy job, the job control unit 30
The processing of No. 4 further divides the copy job into a print job and a scan job, and a device (eg, printer, scanner, memory, etc.) for processing the divided job
Are assigned, and the processing proceeds.

As described above, by dividing a job into pages and allocating and releasing devices for executing each processing in combination with the above-described DoEngine, efficient control of the multifunction peripheral is achieved. The possibilities are described below.

[0511] The data flow when a copy operation is performed using the DoEngine block in Fig. 4 will be described.
In this case, a scanner and a printer are assigned as processing devices (514 and 521 in FIG. 5).
In the case of the scan job (514), image data from the scanner is controlled by the scanner controller 4302 and written into the memory 403 via the GBUs 404 and the system bus bridge 402. In the case of a print job, the data written in the memory 403 is sent to the printer controller 4303 via the system bus bridge 402 and BBus 405, and is subjected to print processing. Dua
By adopting the l-Bus configuration, the occupation of the Bus is eliminated, and the CPU and the memory can be accessed in parallel. The output can be performed in parallel with the data input and the output in parallel.

That is, the copy job 513 in the processing of FIG.
Scan job 514 and print job 52 obtained by dividing
1 can be processed in parallel.

[0513] The allocation and release of devices when performing input / output processing in page units using DoEngine will be described below.

[0514] Fig. 113 shows a conventional case in which a scanner and a printer are serially processed on a job basis using a processing system as an example of a processing system (Fig. 113 (a)).
FIG. 113 is a timing chart showing device allocation and release when processing is performed in parallel in page units (FIG. 113B).

In the case of FIG. 113 (a), the device of job 1 is allocated to the scanner at time T1 and released at time T2. Subsequently, the printer is assigned at time T3 and released at time T4. Scanner processing required for the subsequent job 2 is assigned at time T5.
The time zone from T2 to T4 in the processing of job 1 is the idle time of the scanner, and is the dead time for job 2.
After releasing the scanner (time T6), the printer of job 2
It is allocated at time T7 and released at time T8.

[0516] Here, "dead time" refers to a time during which a device as a resource is in a processable state but cannot start processing due to a process of information to be input.

[0517] On the other hand, in the case of FIG. 113 (b), the device for job 1 is allocated to the scanner at time T1 and released at time T2. Before the scanner is released (time T2), the process is parallelized by DoEngine.
Printer assignment is performed (time T1a). The assignment of the scanner to the job 2 becomes possible after the time T2. For example, when there is a scanner assignment request at T1c, the time from T1c to T2 is the standby time until scanner assignment.

Similarly, the printer can be allocated before the scanner is released (time T1d), allocated after time T1b, and released at time T1f. When the printer allocation request is received at time T1e, T1e is changed to T1b.
The time period up to is a waiting time until the printer is assigned. In the above description, copy jobs are described as examples.
The same applies to the case of processing copy and facsimile, copy and PDL print, and the like. The throughput of jobs 1 and 2 is reduced to T8-T1f when comparing (a) and (b).

[0519] Here, the "standby time" refers to the time during which data to be processed is already prepared and the device is waiting to be released, enabling parallel processing of input / output data.
This is different from the related art in that the in-process data is eliminated. The arbitration by DoEngine, which reflects conditions such as the priority of a job, is controlled by DoEngine, so that the “standby time” can be optimized (minimized).

[0520] Job units include FAX transmission / reception, PDL printing, copying, and the like. The device allocating unit 406a allocates first to third devices 407a to 409a.
Devices include, for example, page memory and band memory,
Document feeders, marking engines and scanners are also included.

FIG. 114 shows copy jobs 513a and 51
FIG. 3B is a block diagram in a case where 3b is generated. Even when various base jobs are generated, as described above, the same applies in that page division is performed and devices are allocated and released in parallel.

The system bus bridge 402 and Dual
According to the DoEngine architecture using -Bus (GBus404, BBus405), it is possible to eliminate data processing conflicts, and a memory conventionally held locally in an interface or the like becomes unnecessary. Information can be shared by the centrally managed memory 403.

(Improvement of real-time property) FIG.
In the configuration shown in FIG. 08, the processing unit that requires real-time performance and the processing unit with low real-time performance use a common CPU. However, by using DoEngine as a satellite and using CPUs properly, real-time performance It can be further improved.

[0524] Instead of the configuration in Fig. 107, a configuration as shown in Fig. 115 (a) may be used. In FIG. 115 (a), P
C115-1 and C115-2 are host computers, and 115-3 is a satellite PC equipped with DOEngine. Since DOEngine has a PCI bus interface, it can be used with computer systems having PCI bus slots. The scanner 115-4 and the printer 115-5 have a PCI satellite configuration connected to the PC 115-3 via a PCI slot. FIG. 115 (b) is a diagram (115-6, 115-) in which a host computer and a satellite PC are connected in parallel.
7) is a diagram connected to a next-generation multifunction peripheral (MFP) via a PCI bus.

(Satellite DoEngine) FIG. 116
Is the DOEn in the satellite PC shown in FIG.
FIG. 4 is a block diagram relating to connection of a Gine. In the figure, the DOEngine 116-1 includes a CPU 401, and preferentially processes a job having a high real-time property.

Reference numeral 116-2 denotes a ROM (Read Only Memory), which is a storage area for a system startup program, a program for controlling the printer engine, character data, character code information, and the like.

Reference numeral 116-3 denotes a RAM (random access memory), which is a storage area with no expiration date, in which font data additionally registered by download is stored, and programs and data are loaded and executed for various processes. .

Reference numeral 116-4 denotes an external storage device such as a hard disk, which spools a print job (print job) received by the printing device (printer), stores programs and various information files, and stores a work area. Used as

Reference numeral 116-5 denotes a display unit such as a liquid crystal display, which displays a setting state of the printing apparatus, a current processing state in the printing apparatus, an error state, and the like.

An operation unit 116-6 is used to change or reset the settings of the printing apparatus.

[0531] Reference numeral 116-7 denotes an engine interface (engine I / F) for exchanging commands and the like for actually controlling the engine.

Reference numeral 116-8 denotes a network interface (network I / F).
The device is connected to the network via 208a.

An external interface (external I / F) 116-9 is connected to a host computer via an interface such as parallel (or serial). 2
Reference numeral 10 denotes a system bus, which serves as a data path between the above-described components.

FIG. 117 is a diagram showing a software configuration corresponding to FIG. 109. In the figure, a part having a low real-time property and a part having a high real-time property are divided and processed. The overall processing is not performed by a single CPU, but the processing is selectively used by the host computer and the satellite computer, whereby the load on the CPU can be reduced and the processing capacity of the entire system can be improved.

For example, the protocol interpreter 11 shown in FIG.
The processing of 7-3 requires a PC
117-2 (for example, PCs 115-1, 11 in FIG. 115)
The command processed and interpreted by the CPU of 5-2) is a PC
The data is sent to the satellite computer 117-6 (PC115-3 in FIG. 115) via the I bus, and is transmitted to the DoEngine.
Is processed in real time by the CPU. The transmitted command is job-controlled by the satellite computer (11).
7-4), device allocation and release are performed (117-).
5).

[0536]

As described above, the conflict between the input and output of image information is eliminated by the system bus bridge and the DoEngine architecture using Dual-Bus.
Data used by each device for processing image information can be shared by a centrally managed memory.

[Brief description of the drawings]

FIG. 1 is a diagram of a configuration example of an apparatus or a system using DoEngine.

FIG. 2 is a diagram of a configuration example of an apparatus or a system using DoEngine.

FIG. 3 is a diagram of a configuration example of an apparatus or system using DoEngine.

FIG. 4 is a block diagram of DoEngine.

FIG. 5 is a diagram showing three states of a cache memory controller.

FIG. 6 is a block diagram of an interrupt controller 410.

FIG. 7 is a block diagram of a memory controller 403.

FIG. 8 is a detailed block diagram mainly showing a cache controller 706;

FIG. 9 is a flowchart showing a cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 10 is a flowchart showing a cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 11 is a diagram showing a configuration of a ROM / RAM controller 707.

FIG. 12 is a timing chart showing the timing of burst reading from the CPU.

FIG. 13 is a timing chart showing the timing of burst writing from the CPU.

FIG. 14 is a timing chart showing the timing of burst reading from a G bus device.

FIG. 15 is a timing chart showing the timing of burst write from a G bus device.

FIG. 16 is a timing chart showing the timing of a single read when a hit occurs in a memory front cache.

FIG. 17 is a timing chart showing the timing of a single read when no hit occurs in the memory front cache.

FIG. 18 is a timing chart showing the timing of a single write when a hit occurs in a memory front cache.

FIG. 19 is a timing chart showing the timing of a single write when no hit occurs in the memory front cache.

20 is a block diagram of a system bus bridge (SBB) 402. FIG.

FIG. 21 is a block diagram of a B bus interface.

FIG. 22 is a block diagram of a G bus interface 2006.

FIG. 23 is a diagram of a virtual memory map, a physical memory map, a memory map in a G bus address space, and a memory map in a B bus address space.

FIG. 24 shows a hatched portion 5 in FIG. 23 including a register and the like;
FIG. 4 is a diagram of a map showing 12 megabytes.

FIG. 25 is a block diagram of an address switch 2003.

FIG. 26 is a block diagram of a data switch 2004.

FIG. 27 is a timing chart of a write / read cycle from the G bus.

FIG. 28 is a timing chart of a burst stop cycle of the G bus.

FIG. 29 is a timing chart of a G bus transaction stop cycle.

FIG. 30 is a timing chart of a G bus transaction stop cycle.

FIG. 31 is a timing chart of a G bus transaction stop cycle.

FIG. 32 is a timing chart of a G bus transaction stop cycle.

FIG. 33 is a block diagram of a PCI bus interface 416.

FIG. 34 is a block diagram of a G bus arbiter (GBA) 406.

FIG. 35 shows a G bus 4 in DoEngine 400.
FIG. 4 is a block diagram related to a DMA by a bus master on a G bus centering on 04.

FIG. 36 is a diagram illustrating an example of a fair arbitration mode (fair mode) when the number of times of continuous use of the bus is set to 1 for all of the bus masters 1 to 4;

FIG. 37 is a diagram illustrating an example of the fair arbitration mode when the number of times of continuous bus use is 2 for only the bus master 1 and the other bus masters are set to 1;

FIG. 38 is a diagram illustrating an example of a priority arbitration mode when the number of times of continuous use of the bus is one and the bus master 1 is set as a priority bus master.

FIG. 39 is a diagram showing an example in which a bus request from the bus master 1 is interrupted even though the bus request from the bus master 4 is permitted.

40 is a block diagram of a B bus arbiter 407. FIG.

FIG. 41 is a block diagram of a synchronization unit 4001.

FIG. 42 is a diagram of one compare unit in the synchronization unit.

FIG. 43 is a block diagram of a scanner / printer controller.

FIG. 44 is a block diagram of a scanner controller 4302.

FIG. 45 is a block diagram of a scanner device I / F 4401.

FIG. 46 is a block diagram of a scanner video clock unit 4402.

FIG. 47 is a block diagram of a scanner video data mask 4601.

FIG. 48 is a block diagram of a scanner video data mask 4602.

FIG. 49: Scanner video data width converter 4603
It is a block diagram of.

FIG. 50 shows color image data (24 bits) for each of 8 bits of RGB.
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 51 shows color image data (32 bits) for each of 8 bits of RGB.
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 52 is a diagram showing an arrangement of 8-bit monochrome image data on a memory.

FIG. 53 is a diagram showing the arrangement of binary black and white image data on a memory.

FIG. 54: Using a BW8 packing unit 4901
FIG. 9 is a timing chart when converting multi-valued 8-bit monochrome image data to a 64-bit width.

FIG. 55 is a timing chart of image data input when binary black-and-white image data is converted into a 64-bit width by the shift register 4902.

FIG. 56 shows an RGB packing unit 4903.
RGB image data of 8 bits (24 bits in total) is 64
It is a timing chart at the time of converting into a bit width.

FIG. 57 is a block diagram of an RGB packing unit 4903.

FIG. 58: Scanner image data transfer FIFO controller 4
It is a block diagram of 403.

FIG. 59 is a block diagram of a scanner controller control register 4404.

FIG. 60 is a block diagram of an IRQ controller 4406.

FIG. 61 is a block diagram of a memory fill mode controller 4405.

FIG. 62 is a timing chart when data is read from the scanner controller 4302 and DMA-transferred.

FIG. 63 is a timing chart for reading or writing to an internal register of the scanner controller 4302.

FIG. 64 is a diagram illustrating a relationship between a value of a signal sccDmaPmState, a state of a clock, and a value of a signal sccPmState.

FIG. 65 is a diagram summarizing signals input and output between a core portion including each block and an external bus or scanner in the scanner controller 4302.

FIG. 66 is a block diagram of a printer controller 4303.

FIG. 67 is a block diagram of a printer device I / F6601.

FIG. 68 is a block diagram of a printer video clock unit 6602.

FIG. 69 is a block diagram of a printer video data mask 6801.

FIG. 70: Printer video synchronization control unit 6
802 is a block diagram.

FIG. 71 is a block diagram of a video data width converter 6803.

FIG. 72 shows color image data (24 bits) for each of 8 bits of RGB.
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 73 shows color image data of 32 bits each of RGB (32 bits).
FIG. 9 is a diagram showing the arrangement on a memory in a bit storage mode).

FIG. 74 is a diagram showing the arrangement of 8-bit monochrome image data on a memory.

FIG. 75 is a diagram showing the arrangement of binary monochrome image data on a memory.

FIG. 76 is a block diagram of an RGBout unit 7101.

FIG. 77: Printer image data transfer FIFO controller 6
603 is a block diagram of FIG.

FIG. 78 is a block diagram of a printer controller control register 6604.

FIG. 79 is a block diagram of an IRQ controller 6605.

FIG. 80 is a block diagram of an IRQ controller 6605.

FIG. 81 is a block diagram of a printer command / status control unit 6606.

FIG. 82 is a block diagram of an option controller control unit 6607.

FIG. 83 shows data DM sent to the printer controller 4303.
FIG. 6 is a timing chart when performing A transfer.

FIG. 84 is a timing chart for reading or writing to an internal register of the printer controller 4303.

[Fig. 85] Fig. 85 is a diagram illustrating the relationship between the value of the signal pscDmaPmState, the state of the clock, and the value of the signal prcPmState.

FIG. 86 is a diagram summarizing signals input and output between a core portion including each block and an external bus or scanner in the printer controller 4303.

FIG. 87 is a block diagram of a power management unit 409.

FIG. 88 is a block diagram of a bus agent.

FIG. 89 is a diagram illustrating blocks used in an image copying method in which image data is directly transferred from a scanner controller to a printer controller and copied.

FIG. 90 is a diagram illustrating blocks used in an image copy method in which image data is transferred from a scanner controller to a printer controller via a FIFO and copied.

FIG. 91 is a diagram showing blocks used in an image copy method in which image data is transferred from a scanner controller to a printer controller via a memory and copied.

FIG. 92 is a block diagram of GBI.

FIG. 93 is a block diagram of a FIFO unit.

FIG. 94 is a block diagram of a GBus controller.

FIG. 95 is a block diagram of a BBus controller.

FIG. 96 is a block diagram of a DMA controller.

FIG. 97 is a block diagram of a register unit.

FIG. 98 is a diagram illustrating a configuration example of a chain table.

FIG. 99 is a diagram showing a GBI core interface.

FIG. 100 is a flowchart of a procedure for selecting a copy method.

FIG. 101 is a diagram showing a data bus switching circuit inside a scanner controller 4302.

FIG. 102 is a diagram illustrating a data bus switching circuit inside a printer controller 4303.

FIG. 103 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 104 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 105 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 106 is a flowchart showing another example of the cache operation when a memory read / write transfer is requested from the MC bus.

FIG. 107 is a configuration diagram of an information processing system according to an embodiment of the present invention.

FIG. 108 is a block diagram showing a basic configuration of a peripheral device in the information processing system according to the embodiment of the present invention.

FIG. 109 is a diagram showing an outline of a software structure of a peripheral device in the information processing system according to the embodiment of the present invention.

FIG. 110 is a diagram showing details of a software structure of a peripheral device in the information processing system according to the first embodiment of the present invention.

FIG. 111 is a diagram illustrating details of a software structure of a peripheral device in the information processing system according to the second embodiment of the present invention.

FIG. 112 is a timing chart in the case where jobs are conventionally processed as one unit.

FIG. 113 is a diagram for describing processing for allocating and releasing devices.

FIG. 114 is a diagram for describing processing when a plurality of jobs are generated.

FIG. 115 is a diagram illustrating a configuration example of a system when DoEngine is used as a satellite.

FIG. 116 shows a system software process performed by two CPUs.
It is a figure explaining the case where processing is carried out separately.

FIG. 117 is a diagram illustrating an outline of a software structure when processing is divided by a plurality of CPUs.

[Description of Signs] 401 CPU 402 Bus bridge 403 Memory 404 G bus 405 B bus 406 G bus arbiter 407 B bus arbiter 4301A G bus / B bus interface (scanner) 4301B G bus / B bus interface (printer) 4302 Scanner controller 4303 Printer controller

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 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhisa Ishizawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Satoshi Nagata 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inside (72) Inventor Ken Onodera 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term in Canon Inc. (reference) 2C087 AA03 AA09 BB10 BC05 BC07 5B061 FF01 GG02 GG06 PP05 RR03 5C062 AA13 AB38 AB42 AC48 AE15 BA04 9A001 BB03 BB04 HH23 JJ35 KK42

Claims (4)

[Claims] An interface for inputting an image signal from an image signal input unit; a first bus connecting the interface to a system bus bridge; and a memory for storing the input image signal via the system bus bridge. An interface that outputs an image signal from an image signal output unit; and a second bus that connects the stored image signal to an interface that outputs the image signal via the system bus bridge. Information processing system for composite equipment. 2. The information processing system according to claim 1, wherein the memory centrally manages the image signal. 3. An interpreting means for interpreting a procedure transmitted from the information processing apparatus; a job generating means for generating a job based on the interpretation of the procedure; Device management means for managing allocation and release of devices for processing the divided elements; means for writing processing results of the allocated devices to memory; and data written to the memory. And means for outputting to another device. An information processing system for a multifunction device, comprising: 4. A means for writing a processing result of a device to said memory and a means for outputting data written to said memory to another device, transmitting and receiving data in parallel to eliminate competition. The information processing system for a multifunction device according to claim 3, wherein: