JP2000208910A - Printed circuit board with bump - Google Patents

Printed circuit board with bump

Info

Publication number
JP2000208910A
JP2000208910A JP11002969A JP296999A JP2000208910A JP 2000208910 A JP2000208910 A JP 2000208910A JP 11002969 A JP11002969 A JP 11002969A JP 296999 A JP296999 A JP 296999A JP 2000208910 A JP2000208910 A JP 2000208910A
Authority
JP
Japan
Prior art keywords
bumps
wiring board
printed wiring
bump
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11002969A
Other languages
Japanese (ja)
Inventor
Ryoji Sugiura
良治 杉浦
Masayuki Sakurai
正幸 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc filed Critical Hitachi AIC Inc
Priority to JP11002969A priority Critical patent/JP2000208910A/en
Publication of JP2000208910A publication Critical patent/JP2000208910A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

PROBLEM TO BE SOLVED: To form a bump of a low cost with good production efficiently and to improve productivity of overall component mounting by previously forming the bump on an electrode pad for connecting a bare chip component of a printed circuit board by a plating method. SOLUTION: Electrode pads 2 or the like for connecting an upper surface outer layer conductor 3, a lower surface outer layer conductor 5 and bumps are formed. Bumps 9 of a protrusion shape, a columnar shape, a trapezoidal shape, a hemispherical shape or the like are formed on an electrode pad part 2 higher than the surface of the printed circuit board by a plating method as the board with the bumps. Thus, it is not necessary to form the bump at a conventional bare chip component side and to supply the component to a set maker as a flip-chip component, and the bare chip component can be connected directly to the board with the bump.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品のベアチ
ップ(裸チップ)を接続するバンプ付きプリント配線基
板に関する。
The present invention relates to a printed wiring board with bumps for connecting bare chips (bare chips) of electronic components.

【0002】[0002]

【従来の技術】図3に示す従来のプリント配線基板にベ
アチップ部品を実装する方法を説明する断面図に基づい
て説明する。図3(a)で示すように、半導体チップ部
品、抵抗、コンデンサあるいはモジュール部品などのベ
アチップ部品10の下部表面に外部接続用のパット部が
設けられ、この部分の所定の位置にバンプ9を形成し、
フリップチップ部品20としている。次に図3(b)で
示すように、従来のプリント配線基板30にはプリント
配線基板の上部表面外層導体3、下部表面外層導体5、
貫通導通穴6、内層導体4、およびベアチップ部品10
に形成されているバンプ9を接続するための電極パット
部2などが設けられる。その次に図3(c)で示すよう
に、図3(a)のベアチップ部品10の下部表面にバン
プ9が形成してあるフリップチップ部品20を、図3
(b)で示す従来のプリント配線基板30の電極パット
部2に接着ペ−ストや接着フィルムなどによりプリント
配線基板に接続してベアチップ部品10を従来のプリン
ト配線基板30の電極パット部2に接続し部品実装して
いる。
2. Description of the Related Art A conventional method for mounting a bare chip component on a printed wiring board shown in FIG. As shown in FIG. 3A, a pad portion for external connection is provided on a lower surface of a bare chip component 10 such as a semiconductor chip component, a resistor, a capacitor or a module component, and a bump 9 is formed at a predetermined position in this portion. And
The flip chip component 20 is used. Next, as shown in FIG. 3B, the conventional printed wiring board 30 includes an upper surface outer layer conductor 3, a lower surface outer layer conductor 5,
Through conduction hole 6, inner conductor 4, and bare chip component 10
Are provided with electrode pads 2 for connecting the bumps 9 formed on the substrate. Next, as shown in FIG. 3C, the flip chip component 20 having the bump 9 formed on the lower surface of the bare chip component 10 of FIG.
The bare chip component 10 is connected to the electrode pad 2 of the conventional printed wiring board 30 by bonding to the electrode pad 2 of the conventional printed wiring board 30 shown in FIG. Components are mounted.

【0003】つまりベアチップ部品10側にバンプ9を
形成し、従来のプリント配線基板30の平坦な電極パッ
ト部2に接続する方法はフリップチップ(FC)法と呼
ばれている。フリップチップ部品20は高密度化、小型
化によりベアチップを接続するための電極パッド数の増
加、電極パッド端子間いわゆる端子ピッチ間隔が狭くな
るためバンプも小さくなり、かつベアチップ部品10に
バンプ9を接続する時やフリップチップ部品20の完成
後の運搬、梱包、納入時の取り扱いが困難となってベア
チップ部品10にバンプ9を形成したフリップチップ部
品20の生産性や品質上の安定性が悪く供給が思うよう
に進んでいないのが実態である。
That is, a method of forming the bumps 9 on the bare chip component 10 side and connecting the bumps 9 to the flat electrode pads 2 of the conventional printed wiring board 30 is called a flip chip (FC) method. The flip chip component 20 has a higher density and a smaller size, the number of electrode pads for connecting bare chips has increased, and the so-called terminal pitch interval between electrode pad terminals has become smaller, so that the bumps have become smaller, and the bump 9 has been connected to the bare chip component 10. And the transportation, packing, and delivery of the flip chip component 20 after completion is difficult, and the productivity and quality stability of the flip chip component 20 in which the bumps 9 are formed on the bare chip component 10 are poor due to poor supply. The reality is that things are not going as expected.

【0004】[0004]

【発明が解決しようとする課題】従来のベアチップ部品
10側にバンプ9を形成し、フリップチップ部品20と
してからプリント配線基板に接続する実装方法では、フ
リップチップ部品20の生産性が悪く、かつ前記に示し
たように各種の取り扱いが問題となっている。本発明で
はプリント配線基板のベアチップ部品10を接続するた
めの電極パッド部2に、あらかじめ凸形状などのバンプ
9をメッキ方法により形成してバンプ付きプリント配線
基板とするものである。つまり、バンプ9をプリント配
線基板側の電極パッド部2に、あらかじめ形成すること
により、ベアチップ部品10側にバンプ9を形成しフリ
ップチップ部品20とせずにベアチップ部品10を直接
バンプ付きプリント配線基板に接続する実装方法であ
る。前記のベアチップ部品10は従来と同一ものを使用
出来ることから十分な供給対応ができ、プリント配線基
板のメッキ方法によるバンプの形成も生産効率良く低価
格で出来るため全体の部品実装の生産性を大幅に向上で
きる。
In the conventional mounting method in which the bumps 9 are formed on the bare chip component 10 side and the flip chip component 20 is connected to a printed wiring board, the productivity of the flip chip component 20 is low, and As described above, various types of handling are problematic. In the present invention, a bump 9 having a convex shape or the like is previously formed on an electrode pad portion 2 for connecting a bare chip component 10 of a printed wiring board by a plating method, thereby forming a printed wiring board with bumps. That is, by forming the bumps 9 in advance on the electrode pads 2 on the printed wiring board side, the bumps 9 are formed on the bare chip parts 10 side, and the bare chip parts 10 are directly formed on the printed wiring board with bumps instead of the flip chip parts 20. This is an implementation method to connect. The bare chip component 10 can be used in the same manner as the conventional one, so that it can be supplied sufficiently, and the bump formation by the plating method of the printed wiring board can be performed with high production efficiency and at a low price. Can be improved.

【0005】[0005]

【課題を解決するための手段】本発明ではプリント配線
基板のベアチップ部品を接続するための電極パッド部
に、あらかじめ凸形状、円柱形状、台形形状、半球面形
状などのバンプをメッキ方法により形成してあるバンプ
付きプリント配線基板にベアチップ部品を接続して部品
実装をするものである。
According to the present invention, bumps having a convex shape, a cylindrical shape, a trapezoidal shape, a hemispherical shape, etc. are previously formed on an electrode pad portion for connecting bare chip components of a printed wiring board by a plating method. A bare chip component is connected to a printed wiring board with bumps for component mounting.

【0006】また、プリント配線基板のベアチップ部品
を接続するための電極パッド部の凹形状などに陥没して
いる箇所に、凸形状となるようにバンプをプリント配線
基板の表面より高く形成し、バンプ付きプリント配線基
板とすることもできる。なお、電極パッド部の凹形状な
どに陥没している箇所に形成するバンプはメッキ方法に
よるバンプの形成に限定するものではなく、はんだや導
電性ペーストを半硬化状態で凸形状となるようにバンプ
を形成してもよい。
Further, a bump is formed higher than the surface of the printed wiring board so as to have a convex shape at a place where the electrode pad portion for connecting bare chip parts of the printed wiring board is depressed into a concave shape. Printed wiring board with a cable. The bumps to be formed in the concave portions of the electrode pad portions are not limited to the bumps formed by the plating method, and the bumps are formed so that the solder or the conductive paste becomes a convex shape in a semi-cured state. May be formed.

【0007】メッキ方法により形成するバンプの材質
は、銅、ニッケル、金、鉛、スズ、はんだ、銀、ロジウ
ム、およびこれらの金属の多層構造からなるもので良
い。また、バンプをメッキ方法により形成する場合、メ
ッキレジストとして所定の厚さの感光性の皮膜をプリン
ト配線基板の全面または一部に形成し、フォト法やレー
ザー加工によりベアチップ部品を接続する電極パッド部
の所定の位置に微少径の大きさで感光性の皮膜を除去
し、メッキレジスト膜とするものである。
[0007] The material of the bump formed by the plating method may be copper, nickel, gold, lead, tin, solder, silver, rhodium, or a multilayer structure of these metals. When bumps are formed by a plating method, a photosensitive film having a predetermined thickness is formed as a plating resist on the entire surface or a part of the printed wiring board, and an electrode pad portion for connecting bare chip components by a photo method or laser processing. The photosensitive film having a small diameter is removed at a predetermined position to form a plating resist film.

【0008】[0008]

【発明の実施の形態】本発明の実施の形態について、図
2に示す本発明の製造工程を説明するための断面図に基
づいて説明する。プリント配線基板1は内層導体を形成
してある多層配線基板、あるいは両面配線基板、片面配
線基板などのいずれでもよいが図2においては両面配線
基板で説明する。図2(a)で示すように、両面銅張り
積層板に部品を取り付ける部品穴や層間を接続するため
の貫通穴、および非貫通穴を穴あけ加工する。それから
無電解メッキや電解メッキをして、めっきスールホール
やバイヤホールなどの貫通導通穴6、および非貫通導通
穴などを形成する。また、サブトラクティブ法やアデテ
ィブ法でプリント配線基板1の上部表面外層導体3、下
部表面外層導体5、およびバンプを接続するための電極
パット部2などを形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to a cross-sectional view for explaining a manufacturing process of the present invention shown in FIG. The printed wiring board 1 may be any of a multi-layered wiring board having an inner conductor formed thereon, a double-sided wiring board, a single-sided wiring board, and the like. As shown in FIG. 2A, a component hole for attaching a component to the double-sided copper-clad laminate, a through hole for connecting layers, and a non-through hole are formed. Then, electroless plating or electrolytic plating is performed to form through conduction holes 6 such as plated through holes and via holes, and non-through conduction holes. In addition, the upper surface outer layer conductor 3, the lower surface outer layer conductor 5, and the electrode pad portion 2 for connecting the bumps are formed by the subtractive method or the additive method.

【0009】次に図2(b)で示すように、メッキレジ
ストとして所定の厚さのアルカリ剥離タイプの感光性の
塗膜、またはポジ型フォトフィルムをプリント配線基板
の全面または一部に形成する。その後、紫外線照射後ア
ルカリ現像により微少径の大きさの穴を形成するフォト
法や炭酸ガスレーザーによりベアチップ部品を接続する
電極パッド部の表面に達する微少径の大きさの穴を感光
性の塗膜、またはポジ型フォトフィルムの所定の位置に
感光性の皮膜、またはフォトフィルムを除去し、バンプ
を接続するための電極パット部2の銅箔表面を露出させ
るメッキレジスト膜7とする。このバンプを接続するた
めの電極パット部2のメッキレジスト膜7はプリント配
線基板の上部表面外層導体3、下部表面外層導体5、お
よび貫通導通穴6、非貫通導通穴の部分はバンプを形成
するためのメッキが析出しないように皮膜を形成するこ
とがよい。
Next, as shown in FIG. 2B, a predetermined thickness of an alkali peeling type photosensitive coating film or a positive type photo film is formed on the entire surface or a part of the printed wiring board as a plating resist. . After that, irradiate ultraviolet rays and then develop a small-diameter hole by alkali development using a photo method or a carbon dioxide laser to form a fine-diameter hole reaching the surface of the electrode pad that connects the bare chip components with a photosensitive coating. Alternatively, the photosensitive film or the photo film is removed at a predetermined position of the positive type photo film to form a plating resist film 7 exposing the copper foil surface of the electrode pad portion 2 for connecting the bump. The plating resist film 7 of the electrode pad portion 2 for connecting the bumps forms the upper surface outer layer conductor 3, the lower surface outer layer conductor 5, the through conduction hole 6, and the non-through conduction hole of the printed wiring board. It is preferable to form a film so that plating for the purpose does not precipitate.

【0010】その次に図2(c)で示すように、バンプ
を形成するためのメッキとして無電解銅メッキを20μ
m〜30μm 、無電解ニッケルメッキを10μm、無
電解金メッキを更に0.5μm施してベアチップ部品を
接続するための電極パッド部2に凸形状、円柱形状、台
形形状、半球面形状などのバンプ9をメッキ方法により
プリント配線基板の表面より30μm〜50μm高く形
成してバンプ付きプリント配線基板とする。バンプを形
成するためのメッキ後、アルカリ水溶液でメッキレジス
ト膜7を剥離して図2(c)で示すようなバンプの径が
30μm〜40μmの微少径の大きさのバンプ9をプリ
ント配線基板1の電極パット部2の銅箔表面に形成しバ
ンプ付きプリント配線基板とする。なお、図2(c)に
示すバンプを形成するメッキ工程において、無電解銅メ
ッキを施してからメッキレジスト膜7を剥離し、その後
無電解ニッケルメッキ、無電解金メッキをすることによ
りプリント配線基板1の表面の防錆処理を省略すること
もできる。または、メッキレジスト膜7を剥離せずに永
久皮膜とすることも可能である。
Next, as shown in FIG. 2C, electroless copper plating is applied to form a bump of 20 μm.
m to 30 μm, electroless nickel plating 10 μm, electroless gold plating further 0.5 μm, and bumps 9 having a convex shape, a cylindrical shape, a trapezoidal shape, a hemispherical shape, etc. are formed on the electrode pad portion 2 for connecting bare chip components. The printed wiring board is formed to have a height of 30 μm to 50 μm higher than the surface of the printed wiring board by a plating method. After plating for forming the bumps, the plating resist film 7 is peeled off with an alkaline aqueous solution, and the bumps 9 having a small diameter of 30 μm to 40 μm as shown in FIG. To form a printed wiring board with bumps formed on the surface of the copper foil of the electrode pad portion 2. In the plating step of forming the bumps shown in FIG. 2C, the plating resist film 7 is peeled off after electroless copper plating, and then electroless nickel plating and electroless gold plating are performed to form the printed wiring board 1. The surface rust prevention treatment can be omitted. Alternatively, it is also possible to form a permanent film without removing the plating resist film 7.

【0011】図1には本発明のバンプ付きプリント配線
基板として多層配線板の断面図を示してある。プリント
配線基板1の上部表面外層導体3、内層導体4、下部表
面外層導体5、貫通導通穴6、ソルダーレジスト膜8,
およびベアチップ部品を搭載するための微少径の大きさ
のバンプ9が電極パット部2に設けられている。ソルダ
ーレジスト膜8は図2(a)のプリント配線基板1の上
部表面外層導体3、下部表面外層導体5、および電極パ
ット部2などを形成した後で所定の位置にソルダーレジ
スト膜8を形成してからメッキレジスト膜7を形成して
もよく、また図2(c)の電極パット部2の銅箔表面に
バンプ9を形成してからメッキレジスト膜7を形成して
もよい。
FIG. 1 is a sectional view of a multilayer wiring board as a printed wiring board with bumps according to the present invention. Upper surface outer layer conductor 3, inner layer conductor 4, lower surface outer layer conductor 5, through conduction hole 6, solder resist film 8, printed wiring board 1,
In addition, a bump 9 having a small diameter for mounting a bare chip component is provided on the electrode pad portion 2. The solder resist film 8 is formed at a predetermined position after forming the upper surface outer layer conductor 3, the lower surface outer layer conductor 5, the electrode pad portion 2, etc. of the printed wiring board 1 of FIG. After that, the plating resist film 7 may be formed, or the plating resist film 7 may be formed after the bumps 9 are formed on the copper foil surface of the electrode pad portion 2 in FIG.

【0012】なお、プリント配線基板のベアチップ部品
を接続するための電極パッド部に形成するバンプはメッ
キ方法によるバンプの形成に限定するものではない。例
えば、プリント配線基板のベアチップ部品を接続するた
めの電極パッド部の表面を凹形状などに陥没しメッキを
析出させた箇所に、はんだボールを接着したり、導電性
ペーストを塗布して半硬化状態として凸形状となるよう
にバンプをプリント配線基板の表面より30μm〜50
μm高く形成することによりバンプ付きプリント配線基
板とすることも出来るものである。
The bumps formed on the electrode pads for connecting bare chip components of the printed wiring board are not limited to the bumps formed by the plating method. For example, the surface of the electrode pad part for connecting bare chip parts of the printed wiring board is depressed into a concave shape and the like, and solder plating is applied to the place where plating is deposited, or a conductive paste is applied and semi-cured state 30 μm to 50 μm from the surface of the printed wiring board so as to have a convex shape.
A printed wiring board with bumps can be formed by forming the wiring board with a height of μm.

【0013】[0013]

【発明の効果】本発明のバンプ付きプリント配線基板は
ベアチップ部品を接続するためのバンプをプリント配線
基板側の電極パッド部に、あらかじめメッキ方法により
形成することにより、従来のベアチップ部品側にバンプ
を形成してフリップチップ部品としてセットメーカーへ
部品供給する必要がなくなり、ベアチップ部品を直接バ
ンプ付きプリント配線基板に接続することの出来る実装
方法である。従ってベアチップ部品は従来と同一ものを
使用出来ることから十分な供給ができ、プリント配線基
板のメッキ方法によるバンプの形成も生産効率良く低価
格で出来るため全体の部品実装の生産性を約40〜60
%と大幅に向上できる。
According to the printed wiring board with bumps of the present invention, bumps for connecting bare chip components are formed on the electrode pads of the printed wiring board in advance by a plating method so that bumps are formed on the conventional bare chip components. This is a mounting method that eliminates the need to form and supply a component to a set maker as a flip chip component, and allows a bare chip component to be directly connected to a printed wiring board with bumps. Accordingly, since the same bare chip components can be used as before, they can be supplied sufficiently, and the bumps can be formed by the plating method of the printed wiring board with good production efficiency and at a low price.
%.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のバンプ付きプリント配線基板の断面
図。
FIG. 1 is a sectional view of a printed wiring board with bumps according to the present invention.

【図2】本発明の製造工程を説明するための断面図。FIG. 2 is a sectional view for explaining a manufacturing process of the present invention.

【図3】従来のプリント配線基板にベアチップ部品を実
装する方法を説明する断面図。
FIG. 3 is a cross-sectional view illustrating a conventional method for mounting a bare chip component on a printed wiring board.

【符号の説明】[Explanation of symbols]

1…プリント配線基板 2…電極パッド部 3…上部表面
外層導体 4…内層導体 5…下部表面外層導体 6…貫通導通穴 7…メッキレジスト膜 8…ソルダーレジスト膜 9…バ
ンプ 10…ベアチップ部品 20…フリップチップ部品 30…従来のプリント配線基板。
DESCRIPTION OF SYMBOLS 1 ... Printed wiring board 2 ... Electrode pad part 3 ... Upper surface outer layer conductor 4 ... Inner layer conductor 5 ... Lower surface outer layer conductor 6 ... Through conduction hole 7 ... Plating resist film 8 ... Solder resist film 9 ... Bump 10 ... Bare chip part 20 ... Flip chip component 30: Conventional printed wiring board.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 プリント配線基板のベアチップ部品を接
続する電極パッド部に、あらかじめメッキ方法によりバ
ンプを形成してあることを特徴とするバンプ付きプリン
ト配線基板。
1. A printed wiring board with bumps, wherein bumps are formed in advance on an electrode pad portion for connecting bare chip components of the printed wiring board by a plating method.
【請求項2】 プリント配線基板のベアチップ部品を接
続する電極パッド部の陥没している箇所に、半硬化状態
で凸形状となるようにバンプを形成することを特徴とす
るバンプ付きプリント配線基板。
2. A printed wiring board with bumps, wherein a bump is formed in a depressed portion of an electrode pad portion for connecting a bare chip component of the printed wiring board so as to be convex in a semi-cured state.
JP11002969A 1999-01-08 1999-01-08 Printed circuit board with bump Pending JP2000208910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11002969A JP2000208910A (en) 1999-01-08 1999-01-08 Printed circuit board with bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11002969A JP2000208910A (en) 1999-01-08 1999-01-08 Printed circuit board with bump

Publications (1)

Publication Number Publication Date
JP2000208910A true JP2000208910A (en) 2000-07-28

Family

ID=11544214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11002969A Pending JP2000208910A (en) 1999-01-08 1999-01-08 Printed circuit board with bump

Country Status (1)

Country Link
JP (1) JP2000208910A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007912A (en) * 2001-06-26 2003-01-10 Kyocera Corp Wiring board
WO2006134220A1 (en) * 2005-06-16 2006-12-21 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
US10741462B2 (en) * 2015-09-01 2020-08-11 Murata Manufacturing Co., Ltd. Resin substrate, component-mounting resin substrate, and method of manufacturing component-mounting resin substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007912A (en) * 2001-06-26 2003-01-10 Kyocera Corp Wiring board
JP4557461B2 (en) * 2001-06-26 2010-10-06 京セラ株式会社 Wiring board
WO2006134220A1 (en) * 2005-06-16 2006-12-21 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
GB2441265A (en) * 2005-06-16 2008-02-27 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
GB2441265B (en) * 2005-06-16 2012-01-11 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
US8225499B2 (en) 2005-06-16 2012-07-24 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
US10741462B2 (en) * 2015-09-01 2020-08-11 Murata Manufacturing Co., Ltd. Resin substrate, component-mounting resin substrate, and method of manufacturing component-mounting resin substrate

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