JP2000207208A - Condition executing processor and compiling processing method of the processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a condition processing executing device which can execute instructions in parallel even though the instructions have dependence relation by generating and executing a program, while making different condition execution registers correspond to mutually exclusively executable code parts in the program. SOLUTION: One basic block structures a control flow graph represented as one node of a graph (SD1). A node called a 'dominator' is determined from the control flow graph and a part sandwiched between 'dominators' is extracted (SD2). It is checked whether or not the part sandwiched between the 'dominators' satisfies condition (SD3). Different condition execution registers are made to correspond to respective code parts (SD4). Nodes are all unified into one node (basic block)(SD5). It is determined whether or not there is an unsolved part sandwiched between 'dominators' (SD6), and an extracting processing for code parts which are exclusively executed is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention analyzes the dependency of a plurality of instructions to determine whether parallel processing is possible, executes parallel processing if possible, and has a register called a condition execution register. Then, a condition execution register is made to correspond to each instruction, and a condition execution processing device for executing the instruction only when the value of the condition execution register is a predetermined value and a program to be executed on the condition execution processing device are obtained. In addition, the present invention relates to a compiling method for performing a semantic analysis of an input program (a source program) and generating an executable program.

[0002]

2. Description of the Related Art An example of a conventional conditional execution processing apparatus is described in Reference 1: David A. Paterson.
terson) and John L. Hennes
sy), Compiler Architecture: a Q
uantitative Approach ”(Morgan Kaufmann Publishers, In
c.) Published, 1996) Section 4.6 “Hardware Support for
Extracting More Parallelism '' and Section 4.1, `` Instru
ction-Level Parallelism: Concepts and Challenges ''
Is disclosed.

[0003] A first conventional example disclosed in this document 1 will be described. As a condition execution processing device according to the first conventional example, a device having a conditional transfer (conditional move) instruction is shown. In this device, in response to a condition transfer instruction having three registers as operands, the operation of transferring the value of the first register to the second register is performed only when the value of the third register satisfies a certain condition. Execute. In other words, referring to the example shown in Document 1,
In response to the condition transfer instruction “CMOVZ R2, R3, R1”, an operation of transferring the value of the register R3 to the register R2 when the value of the register R1 is equal to zero is executed in the condition execution processing device.

Further, the conditional execution processing device has a function of determining a dependency between operands of each instruction with respect to a plurality of instructions (for example,
Analyze the data created by one instruction when the other instruction uses it, and for instructions that do not depend on each other, make available in the circuit that executes the instruction (they are used for the execution of other instructions at that time). Can be performed simultaneously as long as there is no). In this case, a similar dependency analysis is performed for each operand also for the condition transfer instruction described above as an example.

The purpose of providing such a condition execution function (in this example, a condition transfer instruction) in the condition execution processor is to increase the chances of simultaneously executing a plurality of instructions. In other words, if the condition execution function is not provided, the condition judgment function must be realized by moving the execution control of the program like an if-else structure. This has the effect of impeding the analysis to perform, and thus prevents writing high-performance programs that include parallel execution. Of course, in the compile processing method for generating a program to be executed on the conditional execution processing device, it is necessary to generate a program using the conditional execution function in order to generate a high-performance program.

[0006] Next, an example of a conventional compiling method is described in Literature 2: "Roading Adams and Sue Gray", "Usaging Conditional Compilation".
Execution To Exploit Instruction Level Concurrency (Using Conditio
nal Execution to Exploit Instruction Level Concurr
ency) ”(Software-Practice and Experience)
Journal, September 1995, published by John Wiley & Sons, Inc.

The technique disclosed in Document 2 will be briefly described as a second conventional example. For convenience of explanation, only the part related to the present invention out of the technique disclosed in Document 2 will be described. In a compiling method according to a second conventional example, a processing device on which a generated program is executed is
It analyzes the dependencies of a plurality of instructions to determine whether they can be executed at the same time and if possible, executes them at the same time. It has a register called a condition execution register. It is assumed that a condition execution processing device is capable of executing the instruction only when the value of the execution register is a predetermined value.

Here, an operation of "executing the instruction only when the value of the condition execution register is" predetermined value "" will be described with reference to an example shown in Reference 2. The instruction “T B2 LD R20, 8 (SP)” executes the load instruction “LD R20, 8 (SP)” when the value of the condition execution register B2 is T (representing True). Indicates to execute. The “T” is a Boolean value used in the condition execution processing device of the second conventional example, and is a constant for which the expression method in the processing device has been determined. That is,
If the value of the condition execution register (B2 in this case) is a "predetermined value" (in this case, a constant called T),
The instruction (in this case, “LD R20, 8 (SP)”) will be executed.

In the compiling method of the second conventional example, a process for generating a high-performance program using a condition execution function, called a conditional compaction, is performed. First, according to the method of the conventional compiler technology, the entire program is divided into units called basic blocks, and then a control flow graph is constructed in which one basic block is represented as one node of the graph. Further, a basic block in which the last instruction included in the basic block is a conditional branch instruction is extracted from the basic blocks constituting the program.

Next, regarding these basic blocks, a basic block to which a conditional branch instruction, which is the last instruction, branches to,
The control flow graph analyzes the basic block to which control is transferred when the conditional branch instruction is not branched during program execution, and associates a conditional execution register with each instruction included in the basic block for each basic block. This is a method of generating a high-performance program by executing instructions and moving them to the basic block where the conditional branch instruction was originally the last instruction. That is, in the second conventional example, by using a conditional branch instruction, it is possible to move a code in a wide range in a program, and as a result, the number of instructions that can be executed simultaneously and the performance of the program are improved.

[0011]

By the way, in the condition execution processing device according to the first conventional example described above, when analyzing the dependencies between operands of each instruction for a plurality of instructions, a decision is made on the condition execution instruction. (R1 in the above example) does not have any restrictions on the values it holds, so if the original input program contains a large number of mutually exclusive code sections, In some cases, it may not be possible to generate such code, even though high performance operations, including execution, should be possible.

Such a case will be described with reference to FIG. FIG. 8 is an example of a program having a large number of code portions executed exclusively. This program has a double if-then-else structure, and as a result
Code parts 101, 1 constituting n part and else part
02, 103 and 104 are executed exclusively from each other.
That is, only one of the code portions 101, 102, 103, and 104 is executed, and two or more code portions are not executed together. Therefore, if there is an appropriate conditional execution instruction function that makes use of this exclusive execution characteristic, there is no dependency between instructions belonging to different code parts in the sense that instructions belonging to different code parts can be executed simultaneously. .

However, in the conditional execution process of the first conventional example, since there is no restriction on the value held by the register used for the determination in the conditional execution, the operands of these instructions use the same register. If so, the dependency between the registers must be recognized to determine that simultaneous execution of instructions is impossible, and a high-performance operation cannot be obtained. The case where the high-performance operation cannot be obtained will be described with reference to FIG. FIG.
Is an example of a code created based on the operation of the first conventional example of the conditional execution processing device with respect to the code of FIG. 8 (but before determining the execution timing of instructions for simultaneous execution of a plurality of instructions). It is.

To briefly explain the code notation in this example, first, one line of the code corresponds to one instruction. Then tmp1, tmp2, tmp3, tmp4, tmp5, c1, c2, c
3, r1, r2, r3, r4, and r10 all indicate registers of the condition execution processing device. Therefore, the instructions 201, 202, 203,
204 are code portions 101, 102, 10 respectively
3 and 104, the instructions originally belong to different code portions, and do not have any mutual dependency. However, the condition execution processing device according to the first conventional example determines that there is a dependency because these instructions are writing to the same register r10, and cannot execute these instructions simultaneously.

That is, when the execution timing of an instruction is determined based on the conditional execution processing of the first conventional example, the execution timing of the instruction is determined so that two instructions that are originally independent of each other are executed in parallel. Inability to do so makes high-performance operation impossible. Further, the above-mentioned compile processing method of the second conventional example uses a conditional branch instruction to enable a code to be moved in a wide range in a program, thereby increasing the possibility of executing a plurality of instructions simultaneously. However, the second conventional example has the same problem as the first conventional example, since the second conventional example does not consider an alternative condition execution register.

Accordingly, the present invention has been made in view of the above circumstances, and when the condition execution registers corresponding to a plurality of instructions are different, these instructions are not related to each other even though there is a dependency between the instructions. And a compile processing method in the apparatus.

[0017]

In order to achieve the above object, according to the first aspect of the present invention, the dependence of a plurality of instructions is analyzed to determine whether or not they can be executed at the same time. And a condition execution register, which has a register called a condition execution register, and allows a condition execution register to correspond to each instruction and execute the instruction only when the value of the condition execution register is a predetermined value. The processing device has a mechanism for controlling the number of condition execution registers holding a “predetermined value” at any time to be at most one, and a plurality of instructions correspond to each instruction. If the condition execution registers are different, even if there is a cause that it is determined that they cannot be executed simultaneously under normal analysis, And executes decree simultaneously.

According to a second aspect of the present invention, there is provided a compile processing method for performing semantic analysis of an input program (original program) and converting it into a program to be executed on a multiple-choice conditional execution apparatus. The code portions executed exclusively in the program are analyzed and extracted, and one condition execution register is associated with each instruction constituting each code portion. In the case of "value", an output code for executing the instruction is generated.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment (1) Configuration First, a first embodiment will be described with reference to FIGS. FIG. 1 is a functional block diagram showing the configuration of the condition execution processing device according to the first embodiment, and FIG. 2 is a functional block diagram showing the configuration of the dependency analysis unit 304. As shown in FIG. 1, the condition execution processing device 301 reads a program stored in a memory 307, executes an instruction constituting the program, performs an operation, and stores the operation result in the memory 307, the general-purpose register file 308. , And a device for writing to the condition execution register file 309,
An instruction fetch unit 302, an instruction decode unit 303, a dependency analysis unit 304, an instruction execution unit 305, and a result writing unit 306 are provided.

The instruction fetch unit 302 reads an instruction stored in the memory 307, and decodes the instruction
Analyzes the internal structure of the read instruction to analyze the type of the instruction and the contents of the instruction operand, and the instruction execution unit 305 executes the instruction according to the instruction execution timing determined by the dependency analysis unit 304 to execute the operation. Then, the result writing unit stores the operation result in the memory 307, the general-purpose register file 3
08 and the condition execution register file 309, respectively. The dependency analysis unit 304 includes an instruction decoding unit 303
The instruction execution timing is determined on the basis of the contents of the instruction operands analyzed by the above. As shown in FIG. 2, the instruction execution timing includes a condition execution register comparison unit 401, an operand comparison unit 402, and an instruction execution timing determination unit 403. .

Here, with reference to FIG.
Will be described. In this figure, a condition execution register comparison unit 401 compares the condition registers of a group of instructions that are condition execution instructions among a plurality of instructions to be subjected to dependency analysis. Operand comparison unit 402
Compares the operands other than the condition execution register. The instruction execution timing determination unit 403 determines the timing at which each instruction is executed based on the analysis results of the condition execution register comparison unit 401 and the operand comparison unit 402.

(2) Operation Next, the operation in the first embodiment will be described. Since the condition execution processing device having the above configuration is characterized by the operation of the dependency analysis unit 304 and the operation of writing a value to the condition execution register file 309, the dependency analysis unit 304 will be described below with reference to FIGS. And the operation of writing a value to the condition execution register 309 will be described. First, FIG. 3 is a flowchart showing the operation of the dependency analysis unit 304. The dependency analysis unit 304 determines an instruction execution timing for an instruction group in which the processing of the instruction decoding unit 303 has been completed and the type of the operand has been analyzed.
To do so, it is necessary to analyze the dependencies of instructions belonging to these instruction groups with respect to combinations of all two instructions.

First, unprocessed ones are selected for all the instruction combinations (step SA1), and it is checked whether the condition execution registers of the respective instructions are the same (step SA2). If both instructions are associated with a conditional execution register, that is, if both instructions are conditional execution instructions and the condition execution registers are different, each instruction is executed exclusively in the program. Therefore, the process proceeds to step SA3, and it is determined that there is no dependency between these instructions.

On the other hand, if the condition execution registers are the same,
Alternatively, if at least one of the instructions is not a conditional execution instruction, the process proceeds to step SA4, and it is determined whether or not both instructions have a dependency by a conventional dependency analysis method. Thereafter, in step SA5, it is determined whether or not all combinations of instructions have been checked. If not, the determination result is "NO", and the process returns to step SA1. The result of the determination is "YES", and the process proceeds to step SA6 to determine the instruction execution timing according to the conventional instruction scheduling method.

Next, the operation of writing a value to the condition execution register file 309 will be described with reference to FIG. When writing a value to a certain condition execution register in the condition execution register file, the process first proceeds to step SB1, sets the value of the condition execution register to a value to be written, and then proceeds to step SB2. In step SB2, it is checked whether or not the value to be written to the condition execution register is equal to a "predetermined value". Here, if they are equal, the determination result is “YES”, and the process proceeds to Step SB3 to change the values of all the condition execution registers other than the condition execution register to values other than the “predetermined value”. I do. This ensures that the number of condition execution registers that hold the "predetermined value" is at most one. Accordingly, in the description of the operation of the dependency analysis unit 304, if the condition execution registers of the two instructions are different, it is impossible that both instructions are executed at the same time, and it can be immediately determined that there is no instruction dependency.

(3) Compile Processing Method Next, a program compile processing method executed on the conditional execution processing device according to the first embodiment will be described. First, with reference to FIG. 5, the overall compile process in the first embodiment will be described. In the compiling process shown in FIG. 5, first, a semantic analysis is performed on the input program by a conventional method to generate a data format inside the compiler called an intermediate code (step SC).
1). Next, in step SC2, an output code is generated for the intermediate code. Since this processing is also performed by a conventional method, the generated output code does not include a conditional execution instruction. In step SC3, the output code is analyzed to extract code portions to be executed exclusively from each other. In step SC4, different condition execution registers correspond to the code portions to be executed exclusively from each other. As a result, an output code using the conditional execution instruction is generated.

Next, referring to FIG.
The process performed in step 3, ie, the process of extracting code portions that are executed exclusively from each other, will be described. In order to extract code portions that are executed exclusively from each other, the process first proceeds to step SD1, and the output code that does not include the conditional execution instruction is subjected to the method of the conventional compiler technology.
The entire program is divided into units called basic blocks, and a control flow graph is constructed in which one basic block is represented as one node of the graph. When the control flow graph is constructed in this manner, the process proceeds to step SD2, where a node called “ruler” is determined from the control flow graph, and a portion sandwiched between “rulers” is extracted.

[0028] The "ruler (dominato)"
"r)" is a concept generally known in the compiler technical field, for example, Reference 3: Alfred V. Aho, Ravi Sethi, Jeffrey D. Ullman .Ullman, Compilers: Principles, Techniques, and Tool
s) "(Addison Wesle
y Publishing Company), 1986) Section 10.4 "Lo
ops in Flow Graphs. "

Now, there are generally a plurality of portions sandwiched between the “rulers” extracted in step SD2.
Therefore, in step SD3, it is checked whether or not the portion sandwiched between the “rulers” satisfies all of the following two conditions (a) and (b). The two conditions are (a)
For each node other than the "ruler", there must be one edge flowing into each node. (B) For each node other than the "ruler" and having two or more outflow edges, The constituent instruction is a branch instruction only.

When these conditions (a) and (b) are satisfied, the nodes of the branching section sandwiched between the “rulers” and having one outgoing edge are all mutually exclusive. Is the part of the code that will be executed. Then, the process proceeds to step SD4, and by making each code portion correspond to a different condition execution register, the instruction constituting each code portion is made a condition execution instruction, and then the process proceeds to step SD4.
The process proceeds to step 5, and the “ruler” at both ends in the portion sandwiched between “ruler” and all the nodes rewritten using the conditional execution instruction are integrated into one node (basic block). .

Such processing is possible because the nodes in the portion sandwiched between the "rulers" are all code portions that are executed exclusively from each other except for the node containing only the branch instruction. This is because it is correctly rewritten using all the nodes, and even if all the nodes are integrated, it is executed correctly. Next, in Step SD6, it is determined whether or not there is an unanalyzed part between the “rulers”.
If there is an unanalyzed one, the judgment result is “YES”
Then, the processing of steps SD3 to SD5 is repeated, and when there is no unanalyzed data, the determination result is "NO", and the extraction processing of the code part to be executed exclusively is completed.

As described above, according to the first embodiment, in the process of setting a value in the condition execution register of the condition execution processing device, the number of condition execution registers holding a "predetermined value" Is controlled to be at most one,
Even if the contents of the condition execution register corresponding to the condition execution instruction are different, the instructions are processed in parallel, so the program must be created by associating different condition execution registers with the code parts that can be executed mutually exclusively in the program. Execution by the conditional execution processing device enables high-performance execution.

According to the first embodiment, in a compile processing method for automatically generating a program to be executed on a subject execution processing device, a code portion that can be executed exclusively in the program is automatically executed. Code that automatically associates these code parts with different conditional execution registers can be generated automatically, so that code parts that can be executed exclusively in a program can be executed simultaneously. , And high-performance execution becomes possible.

<Second Embodiment> Next, a second embodiment will be described with reference to FIG. The second shown in FIG.
The second embodiment is different from the first embodiment in that the general-purpose register and the condition execution register file 30 are different from the first embodiment.
2 has been provided. That is, in the second embodiment, one register file is configured by both the general-purpose register group and the condition execution register group. However, the operation related to the writing of the condition execution register is the first operation.
This is exactly the same as the first embodiment, and the same operation as the first embodiment is performed for the condition execution register portion of the general-purpose register and the condition execution register file 302.

[0035]

According to the present invention, in the process of setting a value in the condition execution register of the condition execution processing device, the number of the condition execution registers holding the "predetermined value" is at most one.
And execute the instructions in parallel even if the contents of the condition execution registers corresponding to the condition execution instructions are different. By creating a program corresponding to the program and executing the program by the condition execution processing device, high-performance execution is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of a dependency analysis unit 304.

FIG. 3 is a flowchart illustrating an operation of a dependency analysis unit 304.

FIG. 4 is a flowchart illustrating a write operation to a condition execution register file 309;

FIG. 5 is a flowchart illustrating a compiling process executed by the condition execution processing device.

FIG. 6 is a flowchart for explaining a code part extraction processing method that is executed mutually exclusively.

FIG. 7 is a block diagram illustrating a configuration of a second embodiment.

FIG. 8 is a diagram for explaining a conventional technique.

FIG. 9 is a diagram for explaining a conventional technique.

[Explanation of symbols]

301 Conditional execution processing device according to the first embodiment 302 Instruction fetch unit 303 Instruction decode unit 304 Dependency analysis unit 305 Instruction execution unit 306 Result writing unit 307 Memory 308 General-purpose register file 309 Condition execution register file 401 Condition execution register comparison unit 402 Operand Comparison Unit 403 Instruction Execution Timing Determination Unit 901 Condition Execution Unit 902 General-purpose Register and Condition Execution Register File

Claims (2)

[Claims] An instruction is analyzed to determine whether or not it can be executed at the same time. If possible, the instruction is executed at the same time. A register called a condition execution register is provided. Correspondingly, in a condition execution processing device capable of executing the instruction only when the value of the condition execution register is a predetermined value, a condition for holding a "predetermined value" at any time It has a mechanism to control the number of execution registers to be at most one. If a plurality of instructions have different condition execution registers corresponding to each instruction, ordinary instructions such as a dependency between instructions A condition execution processing device which executes these instructions at the same time, even if there is a cause determined to be impossible to execute simultaneously under analysis. 2. A multi-choice conditional execution device for performing semantic analysis of an input program (primitive program) in order to obtain a program to be executed on the conditional execution device according to claim 1. In the compile processing method for converting into a program (code) to be executed on the above, mutually exclusive code portions in the program are analyzed and extracted, and one instruction is included in each code portion. A compile processing method in which a condition execution register is associated, and an output code is generated to execute the instruction when the condition execution register has a "predetermined value".