JP3196625B2 - Parallel compilation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiler for inputting a source program and outputting a target program, and more particularly to a compiler having an instruction set for performing the same kind of operation for each of a plurality of fields in a word. The present invention relates to a parallel compilation method for generating a target program using a set.

[0002]

2. Description of the Related Art There is a vector processor which performs the same kind of operation on a plurality of data with a single processor. The vector processor performs the same kind of arithmetic processing on each element of the array data in a pipeline manner. Here, the array data to be subjected to the vector operation can be arranged at an arbitrary position on the storage device. Generally, the execution speed of a portion to which a vector instruction is applied is accelerated by several tens or more times as compared with the execution by a normal scalar instruction. For this reason, various compilers have been proposed for generating a target program for a vector processor using vector instructions from a source program described on the assumption that the program is executed by a scalar instruction, that is, various vectorizing compilers.

The vectorizing compiler precisely examines an array operation portion described in a loop format in a source program, and converts a possible portion into a vector instruction sequence. At this time, the order of execution of these operations may be changed from the order of operation in the source program due to the conversion to the vector instruction sequence, so that the conversion is performed so that an erroneous operation processing result is not obtained. The compiler performs a dependency analysis process. Dependency analysis is to investigate the definition reference relationship of variables such as array elements. For details, see "Supercompilers for
Parallel and Vector Computers "(H. Zima et al., 1991
Year, Addison-Wesley Publishing Company). Further, since a vector instruction requires a long time to start, if the length of an array to be vector-processed is short, the performance is reduced. Therefore, the vectorization compiler determines whether or not vectorization can be performed in consideration of whether or not the length of the operation target array is sufficient.

On the other hand, as another type of processor that performs the same operation on a plurality of data with a single processor, a processor having an instruction set for performing the same operation on a plurality of fields in a word has been proposed. In this specification, such an operation instruction is referred to as a bit slice operation instruction, and a processor having the bit slice operation instruction in an instruction set is referred to as a bit slice operation type processor. As a bit slice operation instruction, for example, as shown in FIG.
That is, it is regarded as a set of two 16-bit fields, and addition is performed for each field. In FIG. 3, registers 6 and 7 are the source of the operation, and register 8 is the destination of the operation.
Bit length. The arithmetic unit 9 in the processor is composed of four equivalent arithmetic subunits 91, 92, 93, 94, and each subunit independently performs the same type of 16-bit arithmetic. The bit slice operation instruction stores the result of the operation using the first field S ₁₁ of the register 6 and the first field S ₂₁ of the register 7 in the first field D ₁ of the register 8 and the second field S ₁ of the register 6. ₁₂
And a second field S ₂₂ of the register 7 stores the result of the operation to the source in the second field D ₂ of the register 8, hereinafter, the same processing is performed for the third and fourth fields.

[0005] A bit slice operation is completed in almost the same time as a normal inter-word operation, and does not require a long time for activation unlike a vector instruction. For this reason, application to real image processing or computer graphics processing, which does not necessarily require high-precision arithmetic, has been attempted.

[0006]

However, conventionally, there is no compiler that generates a target program for a bit slice operation type processor from a source program described for a normal processor, and therefore uses an assembler language or a machine language. Then, programming work to directly code the target program was necessary.

The present invention has been proposed in view of the above circumstances, and an object of the present invention is to provide a parallelized compiling method capable of generating a target program for a bit slice operation type processor from a source program. It is in.

Further, since the bit slice operation and the vector operation are similar in that both are usually described as an array operation in a source program, a compiler for a bit slice operation type program includes a vectorization compiler. Technology and ideas can be diverted to some extent. For example, when a bit slice operation instruction is used, the operation order is changed from the original source program. Therefore, the above-described dependency analysis in the vectorizing compiler is also an essential function when generating a bit slice operation instruction. However, the execution form differs greatly between the bit slice operation and the vector operation. For example, in a vector operation, array data to be subjected to a vector operation can be arranged at any position on a storage device, whereas in a bit slice operation, access to the storage device must be along a word boundary. . That is, the registers 6 and 7 in FIG.
The first address of the data to be read into the memory must be along a word boundary. This is because, if not along a word boundary, extra processing such as alignment is necessary, and the execution speed improvement by the bit slice operation instruction is usually only about several times. This is because such extra processing overhead cancels out and a target program with high execution efficiency cannot be obtained. The vectorizing compiler considers whether or not the length of the operation target array is sufficient from the characteristics of the vector operation described above, but considers how the operation target array is arranged on the storage device. Is not considered. In addition, since the rate of speed improvement by vectorization is large, a compiling policy is adopted in which vectorization is performed even if the number of instruction steps increases somewhat.

As described above, the compiler for generating the target program for the bit slice operation type processor is similar to the compile method of the vectorizing compiler in that a portion described in the form of a loop in the source program is converted into the target program. There is a part that did. However, due to the difference in characteristics between the vector instruction and the bit slice operation instruction as described above, if the vectorization method is applied to bit slice operation instruction generation as it is, the speed improvement due to the use of the bit slice operation instruction will increase the access to the storage device. And an overhead related to program conversion, and a target program with high execution efficiency cannot be obtained. In particular, in the field of performing low-precision parallel operations using bit slice operation instructions,
In many cases, the start address of data required for calculation dynamically changes, and the head address of data does not always coincide with a word boundary. Therefore, it is problematic to uniformly replace the start address of the data with a bit slice operation instruction.

[0010] Therefore, another object of the present invention is to consider a characteristic of a bit slice operation instruction and to determine whether or not an actual bit slice operation instruction can be efficiently executed. Is to provide.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a compiler for a processor having a bit slice operation instruction for dividing a single word into a plurality of fields and performing the same kind of operation on each field. Loop unrolling means for unrolling, code string rearranging means for rearranging unrolled instruction strings while maintaining a dependency, and bit slice code generating means for generating a bit slice operation instruction by pattern matching from the rearranged instruction strings And

Further, the loop unrolling means includes:
Assign the first sequence number to the code sequence before unrolling,
When unrolling is performed by the number of fields of the bit slice operation instruction, a second sequence number corresponding to the k is assigned to the code sequence generated by the k-th unrolling. , While maintaining the definition reference relationship of the variables appearing in the loop,
Is used as a first key and a second key is used as a second key to rearrange instruction sequences in a loop.

Further, the bit slice code generation means may execute the bit slice operation even if the instruction sequence conforms to the bit slice operation instruction if the head address of the data to be accessed in the instruction sequence is not along a word boundary. It has a configuration in which conversion into an operation instruction is not performed.

Still further, in a preferred embodiment of the present invention, a syntax analysis unit for reading a source program and performing syntax analysis to generate an intermediate code sequence, and detecting a loop structure from the intermediate code sequence to generate the intermediate code sequence And a code generation unit that generates and outputs a target program from the converted intermediate code sequence, and an optimization processing unit that converts an intermediate code sequence having a structure of performing parallel processing with a bit slice operation instruction. A loop unrolling unit that detects a loop structure to be subjected to parallel processing from the intermediate code sequence, and unrolls the loop structure by the number of fields of the bit slice operation instruction,
A code string rearranging means for rearranging the unrolled code string so that codes performing the same kind of operation are adjacent to each other within a range that does not change the definition reference relationship of each variable defined in the loop structure. Bit slice code generation means for detecting a code pattern conforming to the bit slice operation instruction from the code sequence by pattern matching and converting the code pattern into a corresponding bit slice data type intermediate code.

In the parallelized compiling method of the present invention configured as described above, first, the loop unrolling means expands the loop structure in the source program, and then the code string rearranging means executes the operation execution result. The code sequence in the loop is rearranged within a range in which the validity can be maintained, and then the bit slice code generation unit generates a bit slice operation instruction by extracting a pattern matching the bit slice operation instruction from the rearranged instruction sequence.

The number of times of loop unrolling is adjusted to the number of fields of a bit slice operation instruction of a processor that executes a target program output by the compiler. For example, when an instruction for performing a four-field parallel operation as shown in FIG. 3 is provided, the loop is unrolled four times.

The order of the unrolled code sequence is rearranged so that codes performing the same kind of operation are adjacent to each other. Here, the same type of operation refers to an operation in which the operation code of the intermediate code is the same and only the operand is different. The instruction order is changed within a range in which the program execution result does not change from the original program while referring to the variable definition reference relationship obtained by the dependency analysis. In a preferred embodiment of the present invention for such rearrangement, the loop unrolling means assigns the first sequence number to the code sequence before unrolling, and generates the code sequence by the k-th unrolling at the time of unrolling. A second sequence number corresponding to k is assigned to the generated code sequence, and the code sequence rearranging means assigns the first sequence number to the first key, while maintaining the definition reference relationship of the variable appearing in the loop. The instruction sequence in the loop is rearranged using the second sequence number as the second key.

After rearrangement, the same kind of operation appears adjacently in the code string, so that a code pattern that can be converted into a bit slice operation instruction can be easily detected. At this time, the detected code pattern is internally represented as an intermediate code string using a bit slice data type, not a simple integer data type or array element type. In the intermediate code string represented by the bit slice data type, the correspondence relationship between the bit slice operation instruction set to be generated as the target code and the relationship between the address of the storage device to be accessed and the loop control variable are clear. For this reason, even if the instruction sequence conforms to the bit slice operation instruction, the conversion to the bit slice operation instruction is not performed if the head address of the data to be accessed in the instruction sequence is not along a word boundary. Control can be easily performed, and a target program with high execution efficiency can be generated.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The compiler A of this embodiment receives a source program B described in a high-level language such as C language, generates and outputs a target program C for a bit-slice operation type processor. Generate D.
The compiler A reads a source program B and performs a syntax analysis to generate an intermediate code sequence D. The compiler A detects a loop structure from the intermediate code sequence D and detects an intermediate code sequence D.
And a code generation unit G that generates and outputs a target program C from the converted intermediate code sequence D. It is composed of

FIG. 2 is a block diagram showing a configuration example of the optimization processing unit F. The optimization processing unit F of this example has a configuration in which a preprocessing device 1, a loop unrolling device 2, a code sequence rearranging device 3, and a bit slice code generating device 5 are connected in this order. It is connected to the dependency analyzer 4.

The source program B given to the compiler A is converted into an appropriate intermediate code sequence D by the syntax analyzer E, and then input to the preprocessor 1 of the optimization processor F.

The preprocessing device 1 performs normalization of a loop and replacement of an induction variable, in addition to the conventional scalar optimization processing. In the loop normalization, the loop structure is converted so that the value of the loop control variable increases from 0 to a natural number N by one. In the replacement of the induction variable, the occurrence of the induction variable in the loop is replaced with a linear form using the loop control variable. For conventional scalar optimization processing and induction variables, see, for example, "Compilers Principles, Techniques, and, Tools"
(AVAho et al., 1986, Addison-Wesley Publishers)
Chapter 9 and Chapter 10.

The loop unrolling device 2 searches for a loop structure to be subjected to parallel processing from the intermediate code sequence output from the preprocessing device 1, and unrolls those loops U times. Here, U is the number of fields of the bit slice operation instruction of the target processor. Also, the criterion for determining whether or not a loop is a target loop for parallel processing is not necessarily accurate. For example, an array operation process is included in the loop structure, and a procedure call or a function call that is not suitable for parallelization is performed. May not be included in the condition. An accurate determination as to whether or not the loop structure is suitable for parallelization using a bit slice operation instruction is made in a subsequent stage.

When a loop-independent simple variable is used in a loop, the variable can be arrayed here, and the execution efficiency of the bit slice operation instruction can be improved by arraying the variables. it can. Regarding arraying of simple variables, for example, see "Supercompilers for Para
llel and Vector Computers "in section 6.5.

The code sequence rearranging device 3 appropriately rearranges the loop-unrolled intermediate code sequence so that codes performing the same kind of operation are adjacent in the intermediate code sequence. At the time of rearrangement, the analysis result by the dependency analysis device 4 is referred to assure that the execution result of the program after rearrangement is the same as that before the rearrangement. That is, rearrangement is performed within a range that does not change the definition reference relationship of each variable defined in the loop.

The dependency analyzer 4 checks the definition reference relationship of each instruction in the loop. The dependency analysis method may be the method used in the conventional vectorizing compiler, etc.
Since instruction rearrangement in the code sequence rearrangement device 3 is limited to rearrangement in the body of the loop after unrolling, it is sufficient to investigate the definition reference relationship before and after (U-1) times before and after the loop is repeated.

The bit slice code generation device 5 scans the rearranged intermediate code sequence to detect an intermediate code pattern that can be adapted to the bit slice operation instruction, and converts them into a corresponding bit slice data type intermediate code. As a result of the rearrangement, the pattern conforming to the bit slice operation instruction exists at an adjacent position in the intermediate code string, and therefore, the detection is easy.

The bit slice code generator 5 checks the following items simultaneously with the detection of the instruction pattern. (A) A bit slice operation instruction for operating the intermediate code sequence with the bit length exists. (A) When accessing an array variable stored in a main storage device or the like, the head address of the data must be located at an address boundary (alignment) suitable for a bit slice operation instruction. Here, the head address of the data is calculated from the head address where the array variable is arranged and the array subscript expression expressed in a linear format such as a loop control variable. (C) In the case of (a), the access interval (slide) of the data element is equal to a divisor of the number of fields of the bit slice operation instruction of the target processor, and is preferably 1.

The item (a) is checked because it cannot be replaced without such a bit slice operation instruction. The reason why the item (a) is checked is that if such conditions are not satisfied, efficient execution cannot be performed even if the bit slice operation instruction is actually used. Further, the item (c) is checked because the access interval of the data element is not a divisor of the number of fields of the bit slice operation instruction, and the bit slice operation instruction cannot be applied. If there is, even if a bit slice operation instruction is actually used, efficient execution cannot be performed.

However, some check items may be further added depending on the bit slice operation instruction set of the target processor.

[0032] If the target loop intermediate code string can not be converted into bit slice data type intermediate code during exists partially confusion bit slice operation and the normal operation Once also the overhead when executing scalar, bits of the loop structure Abort conversion to slice data type intermediate code. However, if a portion that can be converted to the bit slice data type intermediate code and a portion that cannot be converted are continuous in the loop, the analysis result of the dependency analysis device 4 is referred to again, and then the application of the loop division method is attempted. . For the loop division method, for example, see "Supercompilers
for Parallel and Vector Computers "in section 6.2.

Next, a method of rearranging intermediate codes in the loop unrolling device 2 and the code sequence rearranging device 3 using two sort keys will be described. FIG. 4 shows the flow of processing from the application of the loop structure represented by the intermediate code to the conversion to the bit slice data type intermediate code. The processing procedure of FIG. 4 is roughly divided into two parts. One is a loop unrolling process 20 and the other is a code sequence rearranging process 30. The loop unrolling process 20 is performed by the loop unrolling device 2 in FIG. 2, and the code sequence rearranging process 30 is performed by the code sequence rearranging device 3 in FIG. Hereinafter, the processing procedure will be described with reference to the code examples of FIGS.

FIG. 5 shows an example of a source program in C language. FIG. 6 shows the main part of the for loop in the intermediate code sequence output from the preprocessing device 1 when the program of FIG. The constituent parts are extracted. t _1, t _{2, and} t ₃ are intermediate terms that temporarily hold the operation result, and the left arrow indicates that the operation result on the right side is assigned to the left side.

In the loop unrolling process 20, first, it is determined whether or not the loop is suitable for conversion for a bit slice operation (21). This determination is made in order to improve the compile processing speed by excluding a loop for which conversion is not possible or meaningless from the processing target. The following processing is performed only on the loop structure determined to be a conversion target.

At the time of unrolling, two types of sequence numbers are assigned to each intermediate code constituting the loop body. That is, first shake sequence number K ₁ for each intermediate code constituting the loop body (22). The sequence numbers are uniquely assigned in ascending order from the upstream side to the downstream side of the intermediate code string. In the example shown in FIG. 6, the numerical value of the first column the figure is a sequence number K _1.

Next, the loop is unrolled U times while giving the sequence number K ₂ = k to each of the intermediate codes generated in the k-th unrolling (23). The sequence number and K _2. As a result of the unrolling, each intermediate code has two sequence numbers, K ₁ and K ₂ .
FIG. 7 shows the result of applying this unrolling procedure to the program of FIG.

In the code string rearrangement process 30, first, a dependency analysis 31 is performed. The purpose of the dependency analysis here is to what extent the order of the code strings in the loop body after unrolling can be changed, so that analysis that does not span between loop iterations (iteration) is sufficient. is there.

[0039] Then, within a range that does not alter the operation result, reorder K ₁ first key, the loop in the intermediate code of K ₂ as the second key in ascending order (32). As a result, the intermediate codes in the loop are rearranged in the order of operation when executed using the bit slice operation instruction. FIG. 8 shows the state after rearranging the code strings in FIG. In the case of the example of FIG. 7, there is no dependency that prevents the rearrangement.
In FIG. 8, the keys are completely rearranged in ascending order.

After the rearrangement, the efficiency of execution by the bit slice operation instruction is examined, and if it is inappropriate, the conversion is stopped (33). The check items for estimating the execution efficiency are described above. When accessing an array stored in a main storage device or the like, there is an item as to whether or not the head address of the data is located at an access boundary (alignment) suitable for a bit slice operation instruction. As described above, in the case of an array variable, the head address of the data is calculated from the head address where the array variable is arranged and the array subscript expression expressed in a linear format such as a loop control variable. If the starting address is unknown at this stage, it is assumed that the starting element of the array will be arranged along a word boundary in later code generation.
What is necessary is just to calculate the head address of the data and check it. If there is a part of the intermediate code string that cannot be converted to the bit slice data type intermediate code, the conversion to the bit slice operation instruction is all stopped, or the application of the above-described loop division processing is attempted.

With respect to the loop structure determined to have no problem in terms of execution efficiency, the intermediate code sequence is scanned in order from the top to find a pattern suitable for the bit slice operation instruction from the adjacent intermediate code sequence, and to execute the bit slice operation. It is converted into an intermediate code sequence using a data type (34). FIG. 10 shows an example of a rule for generating a bit slice data type intermediate code corresponding to pattern detection, and FIG. 11 shows a description of the bit slice data type intermediate term notation used here. The intermediate code string generated from the code string in FIG. 8 is as shown in FIG.

The compiler described above can easily generate a bit slice data type intermediate code by unrolling and rearranging the code strings, and the generated intermediate code can be easily associated with a bit slice operation instruction set. , It is possible to appropriately determine whether conversion to a bit slice operation instruction is possible in consideration of overhead and the like. In addition, the above-described unrolling and code string rearrangement processing can be easily performed by sorting using two sort keys.

The embodiment of the present invention has been described above.
The present invention is not limited to the above embodiments, and various other additions and changes are possible. For example, the rearrangement of the code sequence is performed at the stage of the intermediate code, but the rearrangement may be performed at the stage of the code sequence (instruction sequence) generated by the code generation unit G and replaced with a corresponding bit slice operation instruction. It is possible.

[0044]

As described above, according to the present invention,
A compiler capable of automatically generating a target program for a bit slice operation type processor from a source program is obtained. As a result, it is possible to relieve the user from the task of programming the target processor of the bit slice arithmetic processor in the assembler language or the machine language.

In the configuration in which the first order number and the second order number are assigned to perform the rearrangement, the rearrangement in which codes for performing the same kind of operation are adjacent to each other is easily performed by the sort processing using two sort keys. be able to.

Further, when the head address of the data to be accessed in the instruction sequence is not along a word boundary, the conversion into the bit slice operation instruction is not performed. On the contrary, the execution efficiency can be prevented from lowering.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an optimization processing unit.

FIG. 3 is an explanatory diagram of an operation of a processor having a bit slice operation instruction.

FIG. 4 is a flowchart showing a procedure for rearranging intermediate codes using two sort keys in the loop unrolling apparatus and the code string rearranging apparatus.

FIG. 5 is a diagram illustrating an example of a source program.

FIG. 6 is a diagram showing a part of an intermediate code string after the source program of FIG. 5 is processed by a preprocessing device.

FIG. 7 is a diagram showing an intermediate code sequence after unrolling the intermediate code sequence of FIG. 6;

FIG. 8 is a diagram showing an intermediate code sequence after rearranging the order of the intermediate code sequence in FIG. 7;

FIG. 9 is a diagram showing a bit slice data type intermediate code generated from the intermediate code sequence of FIG. 8;

FIG. 10 is a diagram showing a pattern for converting an intermediate code sequence into a bit slice data type intermediate code and conversion rules.

FIG. 11 is an explanatory diagram of an intermediate term notation in a bit slice data type intermediate code.

[Explanation of symbols]

 A: Source program B: Compiler C: Object program D: Intermediate code sequence E: Syntax analysis unit F: Optimization processing unit G: Code generation unit 1: Preprocessing device 2: Loop unrolling device 3: Code sequence rearrangement device 4 ... Dependency analyzer 5 ... Bit slice code generator 6,7 ... Source register 8 ... Destination register 9 ... Operation unit 20 ... Loop unrolling process 30 ... Code sequence rearrangement process 91,92,93,94 ... Arithmetic subunit

Continuation of front page (56) References JP-A-6-28324 (JP, A) U.S. Pat. No. 5,121,498 (US, A) Kohn L. et al, "The Visual Instruction Set (VIS) in Ultra spark" Proc. of IEEE COMPCON SPRING 1995, p. 462-469 Bauer B.R. E. FIG. "Parallel C Extensions (Parallelized Code Retains It's Serial Structure)" Dr. Dobb's Journal (1992.8) "Fisher A.L.O.P.O.D.O.P. Of 3rd.Sym p.on the Frontiers of Massively Parallel Compound (1990) P.507-510 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9 / 45,15 / 16,17 / 16

Claims (4)

(57) [Claims] 1. A parallelized compiling method for a processor having a bit slice operation instruction for dividing a single word into a plurality of fields and performing the same kind of operation on each field, wherein a loop describing an array operation is unrolled. Including loop unrolling means, code sequence rearranging means for rearranging the unrolled instruction sequence while maintaining a dependency, and bit slice code generating means for generating a bit slice operation instruction by pattern matching from the rearranged instruction sequence A parallel compilation method comprising an optimization processing unit. 2. The loop unrolling means assigns a first sequence number to a code sequence before unrolling, and when unrolling is performed by the number of fields of a bit slice operation instruction, the loop is generated by a k-th unrolling. The code sequence is configured to assign a second sequence number corresponding to the k, and the code sequence rearrangement unit assigns the first sequence number to the first sequence number while maintaining a definition reference relationship of a variable appearing in the loop. 2. The apparatus according to claim 1, wherein the instruction sequence in the loop is rearranged using one key and a second sequence number as a second key.
The parallelized compilation method described. 3. The bit slice code generation means,
Even if the instruction sequence conforms to the bit slice operation instruction,
3. The parallel compiling method according to claim 1, wherein a conversion to a bit slice operation instruction is not performed when a head address of data accessed in the instruction sequence is not along a word boundary. . 4. A syntactic analysis unit which reads a source program and performs syntax analysis to generate an intermediate code sequence, detects a loop structure from the intermediate code sequence, and processes the intermediate code sequence in parallel with a bit slice operation instruction. An optimization processing unit for converting into an intermediate code sequence having a structure, a code generation unit for generating and outputting a target program from the converted intermediate code sequence, and wherein the optimization processing unit includes: Loop unrolling means for detecting a loop structure to be subjected to parallel processing from the sequence, and unrolling the loop structure by the number of fields of the bit slice operation instruction, and an unrolled code sequence in the loop structure. Code that rearranges codes that perform the same kind of operation so that they are adjacent to each other within the range that does not change the definition reference relationship of each defined variable A column rearranging unit, and a bit slice code generating unit that detects a code pattern conforming to the bit slice operation instruction from the rearranged code sequence by pattern matching and converts them to a corresponding bit slice data type intermediate code. Characterized parallel compilation method.