JP5227646B2 - Compiler and code generation method thereof - Google Patents

Description

  The present invention relates to a compiling technique, and more particularly, to a compiling technique for using a SIMD instruction for performing memory access and operation on a plurality of data.

  2. Description of the Related Art Architectures having instructions that can hold a plurality of data on one register and execute parallel operations on the plurality of data have become common. For example, in the multimedia instruction extension SSE described in Non-Patent Document 1, a plurality of data can be collectively handled using a 16-byte register. For example, in the case of 4-byte single-precision floating-point data, operations on four data can be executed in parallel on one register. Such an instruction is called a SIMD (single-instruction-multiple-data) instruction, and optimization for generating code using the SIMD instruction is called SIMD optimization.

  As a method for realizing SIMD optimization, a method that performs transformation using a vectorization method on a loop that includes an arithmetic expression that uses an array element reference of stride 1 (referred to as a vectorization method), a loop, Regardless, there are two types of methods (referred to as an instruction combination method) that perform conversion by finding a set of adjacent elements from neighboring references and combining them. The vectorization method is described in Chapter 5 of Non-Patent Document 1. The instruction combination method is described in Non-Patent Document 2.

  An example of conversion by the vector method is shown in FIG. Focus on the innermost k-loop in the source program (described in C language) in FIG. Access to the array a is a continuous reference of stride 1 because the loop control variable k is an array index of the lowest dimension, and this loop can be vectorized. Assuming that 4 types of data can be accessed simultaneously by the SIMD instruction for the type of array a (int type) (SIMD parallelism 4), 4 times the loop expansion (unrolling) is applied to the k loop. And convert to SIMD. The code image after conversion is shown in FIG. In the sentence in the k loop, the subscript 'k: k + 3' of the array a is a notation indicating access of four elements from k to k + 3, that is, k, k + 1, k + 2, and k + 3. The left side shows assignment to four elements starting with a [i] [j] [k], and the right side shows data in which four v2s are put together in one register. In this way, processing corresponding to the original four sentences is performed in one sentence in the loop to be converted to SIMD. Since the original loop length of the k loop is 5, the remainder from the quadruple loop expansion is 1. For the remainder element a [i] [j] [4], a code for performing a normal substitution process after the loop is generated.

  Next, an example of conversion by the instruction combination method is shown in FIG. In the source program (described in C language) in FIG. 7A, attention is paid to three sentences in the loop. Assuming that the SIMD parallelism of array a is 2, a [i] [0] and a [i] [1] can be accessed simultaneously by adjacent elements, so the first two sentences are combined. The code image after conversion is shown in FIG.

Aart J.C.Bik, The Software Vectorization Handbook, Intel Press, 2004. Samuel Larsen and Saman Amarasinghe, Exploiting Superword Level Parallelism with Multimedia Instruction Sets, Proc. Of the SIGPLAN 2000 Conference on Programming Language Design and Implementation, 2000.

  When the data length in the range subject to SIMD optimization is short, if the data length is not divisible by the SIMD parallelism, SIMD conversion is not applied to the fractional part. In fact, there is a long data string that can be continuously applied to SIMD, and if the part selected for optimization (for example, the reference of the innermost loop) is a short data string that is part of the data string, Since SIMD conversion is not applied to the fractional part, the SIMD conversion application rate decreases and the effect on improving execution performance is reduced. For example, in the case of the source program shown in FIG. 5 (a), the access range of the k loop and the j loop is the same as the declaration of the third and second dimensions of the array a, and all elements of a are continuously connected by the triple loop. Refer to it. In this case, the store instruction to a can be reduced to a quarter by applying SIMD with a parallel degree of 4. However, in the conversion as shown in FIG. 5B, the k loop after loop expansion only executes one iteration, and a data string of length 5 is executed with two instructions, so the number of store instructions is reduced. The rate is 2/5, and the execution performance is not improved sufficiently. In addition, since the array a is continuously referred to in the source program of FIG. 7 (a), the store instruction can be reduced by half, but the reduction rate in the conversion of FIG. 7 (b) is 3 Two minutes.

  The object of the present invention is to perform the SIMD conversion in consideration of the outer loop when the target data string according to the conventional SIMD conversion method is a part of a long continuous data string straddling the outer loop. There is no way to provide a way to generate SIMD code.

  The present invention includes a structure analysis unit that analyzes a target loop to obtain an inner data length and a SIMD parallelism, an expansion number calculation unit that calculates a loop expansion number of an outer loop that surrounds the inner data portion, and an expansion number calculation unit. It comprises loop unrolling means for unfolding a loop according to the obtained number of unfolding, and SIMD code converting means for generating SIMD code for the unrolled loop.

  In the expansion number calculation means, a remainder value (called a fraction) when the inner data length is divided by the SIMD parallelism is calculated, and a value obtained by dividing the SIMD parallelism and the common multiple of the fraction by the fraction is used as the expansion number.

  In the acquisition of the inner data length, the inner constant loop length is analyzed for the vectorization method target loop, and the data length of the inner data string composed of continuous references in the inner loop is analyzed for the instruction combination method target loop.

  According to the present invention, when applying SIMD to a short data belonging to the inner loop and a continuous data string between iterations of the outer loop, the inner short data length is not divisible by the SIMD parallelism. SIMD conversion is no longer applied, and the execution performance of the generated code can be improved by improving the application rate of SIMD instructions.

  Hereinafter, embodiments of the present invention will be described.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 shows a configuration diagram of a computer system in which the compiler according to the present embodiment operates. This computer system includes a CPU (Central Processing Unit) 201 as control means, a display device 202 as display means, a keyboard 203 as input means, a main storage device 204 as storage means, and an external storage device 205 as storage means. It is composed of The keyboard 203 accepts a compiler activation command from the user. The compiler end message and error message are displayed on the display device 202. The external storage device 205 stores a source program 209 and an object program 210. The main memory 204 stores a compiler 206, intermediate code 207 and a loop table 208 that are necessary in the compilation process. Compile processing is performed by the CPU 201 executing the compiler 206.

  The compiler according to the present invention includes a SIMD optimization unit 211. Characteristic processing units in the optimization unit include an inner data length analysis unit 212, a SIMD parallelism analysis unit 213, a loop expansion number calculation unit 214, and a loop expansion conversion unit 215 (the inner data length analysis unit 212 and SIMD parallel processing). The degree analysis unit 213 is collectively referred to as a structure analysis unit.) Since the processing of these SIMD optimization units is a characteristic part of the present invention, it will be described in detail later.

  FIG. 3 shows a processing procedure of the compiler 206 operating in the system of FIG.

  In step 301, the compiler 206 performs a syntax analysis with the source program 209 as an input, and outputs an intermediate code 207. In the following compiling process, the intermediate code is converted. Examples of syntax analysis methods and intermediate code are described in, for example, “Aho, Sethi, Ullman,“ Compilers: Principles, Techniques, and Tools ”, Addison-Wesley, 1986”.

  Next, in the loop analysis of step 302, the compiler 206 obtains a set of loops included in the program and records it in the loop table 208. The loop analysis method is described, for example, on page 67 of Michael Wolfe, “High Performance Compilers for Parallel Computing”, Addison-Wesley Publishing Company, 1996.

  Next, in step 303, the SIMD optimization unit 211 of the compiler 206 performs SIMD optimization 303. The processing procedure of this step is a feature of the present invention and will be described later.

  Next, the compiler 206 performs register allocation in step 304, generates code in step 305, converts the intermediate code 207 into the object program 210, and outputs it. Register allocation and code generation methods are described in the above-mentioned Aho et al.

  Here, the loop table 208 generated by the loop analysis in step 302 will be described. FIG. 8 shows an example of the loop table 208. The loop table 208 stores a loop number 801, a parent loop 802, a child loop 803, a control variable 804, an initial value 805, a final value 806, an increment value 807, and a loop length 808.

  The loop number 801 is a number for identifying a loop in the compiler. The parent loop 802 is the loop number of the innermost loop among the outer loops surrounding the target loop. If the target loop is the outermost loop, “none” is registered. The child loop 803 is the loop number of the outermost loop among the inner loops of the target loop. If the target loop is the innermost loop, “none” is registered. The control variable 804 is a loop control variable that controls repetition of the target loop. An initial value 805, a final value 806, and an increment value 807 are an initial value, a final value, and an increment for each repetition of the control variable 804, respectively. The loop length 808 is the number of loop repetitions. The loop length is obtained from the initial value, the end value, and the increment value of the loop control variable.

  Hereinafter, the details of the processing of the SIMD optimization 303, which is a feature of the present invention, will be described. FIG. 1 shows details of the processing procedure of the SIMD optimization 303.

  The SIMD optimization in this embodiment is performed using a loop as a processing unit. Therefore, in step 101, the compiler 206 determines whether or not there is an unprocessed loop. If there is an unprocessed loop, the compiler 206 extracts one unprocessed loop as a processing target and proceeds to step 102. If there is no unprocessed loop, the process ends.

  In step 102, the compiler 206 determines whether it is a target loop for SIMD optimization. If it is not the target loop, the process returns to step 101 and proceeds to the processing of the next loop.

  Details of the processing procedure of step 102 will be described with reference to FIG. In this embodiment, the two methods of the vectorization method and the instruction combination method described in the background section are targeted.

  In this embodiment, the innermost loop is the processing target. In step 901, it is determined whether it is the innermost loop. Whether it is the innermost loop or not can be determined by referring to the child loop column 803 of the loop table 208 and whether there is no child loop. If it is the innermost loop, the process proceeds to step 902. If it is not the innermost loop, the process proceeds to step 909, where it is determined that it is not a SIMD optimization target, and the process ends.

  Steps 902, 903, and 904 are processing for determining the conditions of the vectorization method.

  In step 902, it is determined whether the increment of the control variable is 1 based on the increment value column 807 of the loop table.

  In step 903, it is determined whether or not there is dependence on loop transportation.

  In step 904, the code in the loop body is examined to determine whether the condition is satisfied. First, it is a condition that all operations and operand types match. Since the SIMD parallelism indicating data handled simultaneously by the SIMD operation is normally defined for each type by the target architecture, in this embodiment, for simplicity, only the case where the types are all the same is targeted. Next, it is determined whether the operation in the loop is an operation having a SIMD instruction. For example, when the SIMD operation instruction included in the target architecture is only addition and multiplication, a loop including division is excluded from SIMD optimization targets. Next, when the operand is an array reference, it is checked whether it is a continuous reference of stride 1. In addition, operands other than array references are conditional on loop invariable variables.

  When all of the conditions of steps 902, 903, and 904 are satisfied, the process proceeds to step 905, where it is determined that the object is a SIMD optimization target by the vectorization method, and the process ends.

  When the conditions are not satisfied in Steps 902, 903, and 904, the process proceeds to Step 906, and the conditions for SIMD optimization by the instruction combination method are determined. In the instruction combination method, normally, a set of memory references such as array references with the same type of arithmetic expression is searched from the loop body, and is set as a target of SIMD combination. For example, 'a [i] + b [i + 1] + v0' and 'a [i + 1] + b [i + 2] + v1' are to be combined. In this embodiment, for simplicity, only the case where the whole sentence is the same type is targeted. For this reason, in step 906, the code in the loop body is checked to see if all sentences are isomorphic. If it is the same type, check whether the following condition is satisfied. First, it is the same as the determination in step 904 that all operations and operand types match, that all operations have SIMD instructions, and that operands other than array references are loop-invariant. For array references, it is checked whether or not it is stride 1 between adjacent sentences. For example, this condition is satisfied when the first sentence is a [i], the second sentence is a [i + 1], and the third sentence is a [i + 2]. Moreover, it is on condition that there is no dependence between adjacent sentences.

  If the condition of step 906 is satisfied, the process proceeds to step 907, where it is determined that the target is a SIMD optimization target by the instruction combination method, and the process ends. If the condition is not satisfied, the process proceeds to step 908, where it is determined that it is not a SIMD optimization target, and the process ends.

  Note that the SIMD optimization target determination in step 102 is a part belonging to the prior art, and the determination by the processing procedure in FIG. 9 does not limit the scope of the present invention. For example, in addition to the array reference of stride 1, a continuous area on a memory such as an adjacent member in the structure is also a target of SIMD coupling. In addition, when all operations are not SIMD instruction targets, SIMD optimization may be applicable in addition to the conditions in FIG. 9, such as being divided into SIMD application application parts and non-application parts.

  Above, description of FIG. 9 and step 102 is complete | finished.

  In step 103, the SIMD parallelism analysis unit 213 of the compiler obtains the SIMD parallelism. The SIMD parallelism for each data type is determined by the target architecture. For example, if the data is an integer type of 4 bytes and the SIMD calculation register is 16 bytes, then 4 parallels. Check the type of operation in the loop and find the degree of parallelism for that type.

  In step 104, the inner data length analysis unit 212 of the compiler analyzes the inner data portion to obtain the inner data length N and the expansion outer loop. The processing procedure of this step will be described in detail with reference to FIG.

  In step 401, 1 is set as the initial value of the inner data length N, and the initial value of the variable UNROLLLOOP for obtaining the expansion outer loop is not set.

  In step 402, it is determined whether or not the loop to be processed can be vectorized. In the determination in step 102 (FIG. 9), the case determined as the SIMD optimization target by the vectorization method in step 905 can be vectorized. If vectorization is possible, the process proceeds to step 403 to perform processing for SIMD conversion by the vector method. If vectorization is not possible, the process proceeds to step 410, and processing for SIMD conversion by the instruction combination method is performed.

  In step 403, the innermost loop of the current process target is set in OUTERLOOP for the vector system target loop.

  Steps 404, 405, 406, 407, 408, and 409 are processes for performing processing by tracing the parent loop and expanding the expansion outer loop outward.

  In step 404, it is determined whether there is a parent loop of OUTERLOOP. This determination is performed in the parent loop column 802 of the loop table 208. If there is a parent loop, the process proceeds to step 405. If not, the process of tracing the loop outward is terminated, and the process proceeds to step 412.

  In step 405, OUTERLOOP is set in LOOP, and the parent loop of the current OUTERLOOP is set in OUTERLOOP.

  In step 406, the loop length of LOOP is checked. The loop length can be acquired from the loop length column 808 of the loop table 208. If the loop length is a constant, the value is set to N1, and the process proceeds to step 407. If it is not a constant, go to Step 412.

  In step 407, the product of the constants N and N1 is calculated, and it is determined whether or not this value is below a certain value. For the constant value used in this determination, an upper limit value that is appropriate as the short data length of the inner data portion may be selected. For example, a value about several times the maximum value of the SIMD parallelism of the target architecture is selected. If the value is less than or equal to a certain value, the process proceeds to step 408, and if not, the process proceeds to step 412.

  In step 408, it is determined whether each array reference to be converted to SIMD is continuous between iterations of OUTERLOOP. It is determined whether or not the i-th last reference of OUTERLOOP and the i + 1-th first reference are consecutive. For example, in the example of the source program in FIG. 5 (a), when OUTERLOOP is a j loop, comparing a [i] [j] [4] with a [i] [j + 1] [0] Since the elements of the lower dimension are 0 to 4, these elements are continuous. If continuous, the process proceeds to step 409; otherwise, the process proceeds to step 412.

  In step 409, the expansion target loop is updated to the outside, and the processing proceeds to the next outer loop. That is, the value of N is updated to N * N1, and OUTERLOOP is set to UNROLLLOOP. Thereafter, the process returns to step 404 to perform the updated OUTERLOOP process.

  Step 410 is processing of a loop to be converted into SIMD by the instruction combination method. Analyzes the continuous reference string in the processing target loop and sets its data length to N1.

  In step 411, the innermost loop to be processed is set in OUTERLOOP. Thereafter, the process proceeds to step 407 and the same processing as that of the vectorization method target loop is performed.

  In step 412, it is determined whether UNROLLLOOP is not set.

  If not set, the process proceeds to step 413, where the determination result is “no inner data portion” and the process is terminated.

  If UNROLLLOOP is set, the process proceeds to step 414, where the inner data length is N and the expansion outer loop is UNROLLLOOP.

  Above, description of the processing procedure of FIG. 4 and step 104 is complete | finished.

  In step 105, the loop expansion number calculation unit 214 of the compiler checks whether there is an inner data part based on the determination result in step 104. If there is no inner data part, the present invention is not applicable, so the process proceeds to step 112, the normal SIMD optimization process according to the prior art is performed, the process of this loop is terminated, and the process returns to step 101.

  In step 106, the loop expansion number calculation unit 214 of the compiler determines whether or not the inner data length N obtained in step 104 is divisible by the SIMD parallelism. If it is divisible, the process proceeds to step 112, the normal SIMD optimization process is performed, and the process of this loop is terminated. If it is not divisible, the process proceeds to step 107.

  In step 107, the loop expansion number calculation unit 214 of the compiler checks whether there is a loop in the inner data portion. Since the inner data portion is inside the expansion outer loop, the child loop 803 of the loop table 208 in FIG. 8 is used to determine whether or not the expansion outer loop has a child loop. If there is an inner loop, the process proceeds to step 108 to cancel the inner loop. When the inner loop is a multiple loop (when the child loop of the expansion outer loop further has a child loop), all the loops constituting the multiple loop are eliminated in order from the innermost side. If there is no loop in the inner data portion, the process proceeds to step 109.

  In step 109, the loop expansion number calculation unit 214 of the compiler calculates the loop expansion number of the expansion outer loop. First, the inner data length N is divided by the SIMD parallelism, and the remainder is defined as “fraction”. Next, the SIMD parallelism and the common multiple of the fraction are obtained, and the quotient obtained by dividing the value by the fraction is used as the number of expansions of the expansion outer loop. In the calculation of the common multiple, if the least common multiple is obtained, the number of expansions can be minimized. As a simple calculation method, there is a method of adopting a product of SIMD parallelism and fraction as a common multiple.

  In step 110, according to the number of expansions obtained in step 109, the loop expansion conversion unit 215 of the compiler performs loop expansion processing of the expansion outer loop.

  In step 111, the compiler 206 converts the code in the innermost loop after expansion into a code to which SIMD is applied. Thus, the processing of one loop is completed, the processing returns to step 101, and the processing of the next loop is performed.

  This is the end of the detailed description of the processing procedure in FIG. 1 and step 303.

  Next, a processing procedure when the present embodiment is applied to the source program (described in C language) of FIG.

  The loop numbers are 1, 2, and 3 in order from the outside. Information of each loop is as described in FIG.

  In the determination of the SIMD optimization target loop in step 102, since the loops 1 and 2 are not the innermost loop, the condition is not satisfied. The processing of loop 3 (k loop) will be described. In step 902, it is determined that the increment of the control variable is 1. Since this loop has no dependency, it is determined in step 903 that there is no loop transportation dependency. In step 904, the code in the loop is examined. The statement in the loop body has no operations, only array references and loop invariant variable v2. The type is int type and matches. The array reference a [i] [j] [k] is a continuous reference of stride 1 because the subscript k in the lowest dimension matches the loop control variable. Since the condition is satisfied, it is determined in step 905 that it is a SIMD optimization target. In step 103, for example, if the SIMD register size of the target architecture is 16 bytes, the data size of the int type is 4 bytes, and the parallelism of the SIMD instruction for the int type is 4, the SIMD parallelism is set to 4.

  In step 104, the inner data portion is analyzed. Since the k loop to be processed can be vectorized in step 402, the process proceeds to step 403, and the k loop is set in OUTERLOOP. After the determination in step 404, in step 405, a k loop is set in LOOP and a j loop is set in OUTERLOOP. In step 406, it is determined that the loop length of the k loop is a constant 5, and in step 407, it is determined whether the value 5 of N * N1 is equal to or less than a certain value. In the present embodiment, for example, if a constant value is 32, it is determined that the value is below a certain value, and the process proceeds to step 408. In step 408, it is checked whether the array reference a [i] [j] [k] is continuous between iterations of OUTERLOOP (j loop). The first reference of the j loop is a [i] [0] [4], and the first reference of the j loop is a [i] [1] [0]. Since these are adjacent elements, it is determined that they are continuous. In step 409, N is set to 5 and jroll is set to UNROLLLOOP.

  Returning to step 404, the parent loop of OUTERLOOP is checked, and in step 405, LOOP is updated to j loop and OUTERLOOP is updated to i loop. Since the loop length of the j loop is 3 and the product of N is 15 and 32 or less, the process proceeds to step 408. The first reference of the i loop is a [0] [2] [4], and the first reference of the j loop is a [1] [0] [0]. Since these are adjacent elements, it is determined that they are continuous. In step 409, N is updated to 15 and UNROLLLOOP is updated to i loop, and the process returns to step 404. Since there is no parent loop of the i loop, the process proceeds to step 412. Since UNROLLLOOP is set, the process proceeds to step 414. The inner data length is 15, the expansion outer loop is i loop, and the process of step 104 is finished.

  In step 105, it is determined that there is an inner data portion, and in step 106, it is determined whether the inner data length 15 is divisible by SIMD parallelism 4. Since it is not divisible, the process proceeds to step 107. Since there are j loop and k loop in the inner data portion, the inner loop is eliminated in step 108. First, after eliminating the inner k-loop, further canceling the j-loop. A code example after the cancellation is shown in FIG.

  In step 109, the fraction is 3 which is the remainder of 15 divided by 4. The number of expansions is 4 by dividing the SIMD parallelism 4 and the least common multiple 12 of the fraction 3 by the fraction 3. In step 110, the i loop is expanded four times. The expanded code string is shown in FIG.

  In step 111, conversion to a SIMD code is performed. Here, four assignment statements to array a are collected in order from the top, and converted into one statement. An example of the code after conversion is shown in FIG. In this code, a [i] [0] [1: 3] indicates substitution of a into 4 elements. Further, (v2, v2, v2, v2) indicates a value obtained by arranging four variables v2. (a [i] [0] [4], a [i] [1] [0: 2]) is a [i] [0] [4] followed by a [i] [1] Indicates that all three elements from [0] to a [i] [1] [2] are assigned together. The same applies hereinafter.

  This is the end of the description of the conversion example for the source code example in FIG.

  Next, a processing procedure when this embodiment is applied to the source program (described in C language) in FIG. 7A will be described.

  The loop number of i loop is 4. The information of this loop is as described in FIG.

  In the determination of the SIMD optimization target loop in step 102, it is determined in step 902 that the increment of the control variable is 1, and since this loop has no dependency, it is determined in step 903 that there is no loop transportation dependency. In the determination in step 904, since the array reference a [i] [0] is not stride 1, the condition is not satisfied, and the process proceeds to step 906.

  In step 906, the three sentences in the loop are compared, and each sentence is determined to be the same type because the left side is an array reference and the right side is a variable. All types match with double type. Focusing on array references, three sentence references are consecutive. From these determinations, it is determined that the condition of step 906 is satisfied, and in step 907, the SIMD optimization target by the instruction combination method is selected.

  In step 103, if the parallelism of the SIMD instruction for the double type is 2, the SIMD parallelism is set to 2.

  In step 104, the inner data portion is analyzed. In step 402, since the i loop to be processed cannot be vectorized, the process proceeds to step 410, and the continuous reference string in the processing target loop is examined. Since the reference sequence of this loop is a [i] [0], a [i] [1], a [i] [2], 3 is set to the data length N1. In step 411, the i loop is set to OUTERLOOP.

  Proceeding to step 407, since N * N1 is 3, it is determined to be below a certain level.

  In step 408, the continuity between i-loop iterations is examined. The last data in the reference string of the array a at the first time of the i loop is a [0] [2]. The first data of the second time is a [1] [0]. Since these are adjacent elements when compared with the declaration of the array a, it is determined that they are continuous.

  In step 409, N is set to 3, and iROLL is set to UNROLLLOOP.

  Returning to Step 404, since there is no parent loop of i loop, the process proceeds to Step 412, and since UNROLLLOOP is set, the process proceeds to Step 414. The processing of step 104 is completed with the inner data length set to 3 and the expansion outer loop set to i loop.

  In step 105, it is determined that there is an inner data portion, and in step 106, it is determined whether the inner data length 3 is divisible by SIMD parallelism 2. Since it is not divisible, the process proceeds to step 107. Since there is no loop in the inner data portion, the process proceeds to step 109.

  In step 109, the fraction is 1 which is a remainder obtained by dividing 3 by 2. The number of expansions is 2 by dividing the SIMD parallelism degree 2 and the least common multiple 2 of the fraction 1 by the fraction 1. In step 110, the i-loop is expanded twice. FIG. 7B shows the code string after development.

  In step 111, conversion to a SIMD code is performed. Here, two assignment statements to the array a are collected in order from the top and converted into one statement. An example of the code after conversion is shown in FIG.

  This is the end of the description of the conversion example for the source code example in FIG.

  The code generation method of the present invention can be used in a compiler that performs code generation for a target machine equipped with a SIMD instruction that performs memory access and calculation for a plurality of data.

It is a figure which shows the process sequence of SIMD optimization by embodiment of this invention. 1 is a configuration diagram of a computer system in which a compiler according to an embodiment of the present invention operates. The example of the process sequence of the compiler of embodiment of this invention is shown. It is a figure which shows the process sequence which analyzes an inner data part and data length in SIMD optimization by embodiment of this invention. An example of a source program and a conversion example of SIMD optimization according to the prior art are shown. 2 shows an example of a code conversion process according to the present invention. An example of a source program and an example of code conversion according to the prior art and the present invention are shown. It is an example of the loop table of this embodiment. In SIMD optimization by embodiment of this invention, it is a figure which shows the process sequence which determines a SIMD optimization object loop.

Explanation of symbols

204 ... Main memory, 206 ... Compiler, 207 ... Intermediate code, 208 ... Loop table, 209 ... Source program, 211 ... SIMD optimization unit, 212 ... Inside data Long analysis unit, 213... SIMD parallelism analysis unit, 214... Loop expansion number calculation unit, 215... Loop expansion conversion unit

Claims (9)

A computer code generation method for generating a code using a SIMD instruction for performing parallel operation on a plurality of data from a source program or intermediate code,
Analyzing the loop of the intermediate code, the inner data length, which is the length of the inner data section including the SIMD instruction application target data string with a constant length less than a certain value, and how many pieces of data are parallelized by the SIMD instruction A structural analysis step for obtaining a SIMD parallelism indicating whether to process,
A fraction which is a remainder when the inner data length obtained in the structural analysis step is divided by the SIMD parallelism is calculated, and a value obtained by dividing the common multiple of the SIMD parallelism and the fraction by the fraction is obtained. An expansion number calculation step for obtaining the number of loop expansions of the outer loop surrounding the inner data portion;
A loop unrolling step for unfolding the loop according to the number of unfolding loops obtained in the unfolding number calculating step;
A code generation method characterized in that a computer executes. The code generation method according to claim 1,
Before Kioyake multiples the code generation method of a computer which is a least common multiple of the SIMD parallelism and fractional. The code generation method according to claim 1,
Before Kioyake multiples the code generation method of a computer which is a value obtained by multiplying the fraction in SIMD parallelism. The code generation method according to claim 1,
A step of determining whether to perform the structure analysis step, the expansion number calculation step, and the loop expansion step with respect to the loop with reference to a loop table that describes information on the outer loop and the inner loop with respect to the loop of the intermediate code code generation method of a computer, wherein a computer further execute. A compiler that causes a computer to generate code using a SIMD instruction that performs parallel operations on multiple data from a source program or intermediate code,
Analyze the loop of the code and process the inner data length, which is the length of the data string of the inner data section including the data string subject to SIMD instruction application with a constant length less than a certain value, and how many pieces of data are processed in parallel by the SIMD instruction A structural analysis step to obtain a SIMD parallelism representing whether to do;
A fraction that is a remainder when the inner data length obtained in the structural analysis step is divided by the SIMD parallelism is calculated, and a value obtained by dividing the common multiple of the SIMD parallelism and the fraction by the fraction is calculated. An expansion number calculation step for obtaining the number of loop expansions of the outer loop surrounding the inner data portion;
A loop expansion conversion step of expanding a loop according to the number of loop expansions determined in the expansion number calculation step;
A compiler characterized by causing a computer to execute. The compiler of claim 5, comprising:
Before Kioyake multiples, compiler, characterized in that said SIMD parallelism, which is the least common multiple of the fraction. The compiler of claim 5, comprising:
Before Kioyake multiples, compiler, wherein the a value obtained by multiplying the fraction in SIMD parallelism. The compiler of claim 5, comprising:
Whether the structure analysis step, the expansion number calculation step, and the loop expansion conversion step are to be performed on the loop with reference to a loop table that describes information about the outer loop and the inner loop with respect to the loop of the intermediate code A compiler that further causes a computer to execute a step of determining whether or not. A computer that generates code using SIMD instructions for performing parallel operations on multiple data from a source program or intermediate code,
Analyzing the loop of the intermediate code, the inner data length, which is the length of the inner data section including the SIMD instruction application target data string with a constant length less than a certain value, and how many pieces of data are parallelized by the SIMD instruction A structural analysis unit for obtaining SIMD parallelism indicating whether to process,
A fraction which is a remainder when the inner data length obtained in the structural analysis step is divided by the SIMD parallelism is calculated, and a value obtained by dividing the common multiple of the SIMD parallelism and the fraction by the fraction is obtained. An expansion number calculation unit for obtaining the number of loop expansions of the outer loop surrounding the inner data part;
A loop expansion conversion unit that expands a loop according to the number of loop expansions determined in the expansion number calculation step;
A computer comprising:

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