JP3367438B2 - Conditional execution processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention analyzes the dependency relationship of a plurality of instructions to determine whether or not parallel processing is possible, executes parallel processing if possible, and has a register called a condition execution register. However, the present invention relates to a condition execution processing device that associates a condition execution register with each instruction and executes the instruction only when the value of the condition execution register is a predetermined value.
It

[0002]

2. Description of the Related Art As an example of a conventional condition execution processing device, Reference 1: David A. Paterson (David A. Paterson)
terson and John L. Hennes
sy) "Compiler Architecture: a Q
uantitative Approach ”(Morgan Kaufmann Publishers, In
c.) Issued, 1996) Section 4.6 “Hardware Support for
Extracting More Parallelism "and Section 4.1" Instru
ction-Level Parallelism: Concepts and Challenges ''
Is disclosed in.

A first conventional example disclosed in Document 1 will be described. As a condition execution processing device according to the first conventional example, a device having a conditional move instruction is shown. In this device, in response to a conditional transfer instruction having three registers as operands, the operation of transferring the value of the first register to the second register is performed only when the value of the third register satisfies a certain condition. Run. That is, to explain by citing the example shown in Document 1,
For the conditional transfer instruction "CMOVZ R2, R3, R1", the operation of transferring the value of register R3 to register R2 when the value of register R1 is equal to zero is executed in the conditional execution processing device.

Further, the conditional execution processing device has a dependency between operands of each instruction for a plurality of instructions (for example,
Analyze the data created by one instruction when the other instruction is used), and for the instructions that do not depend on each other, the circuit that executes the instruction is free (used at that time for the execution of other instructions). Not) can be done at the same time as long as there is. In this case, the same dependency analysis is performed for each operand even for the conditional transfer instruction described above as an example.

The purpose of providing such a condition execution function (condition transfer instruction in this example) in the condition execution processing device is to increase the chances of simultaneously executing a plurality of instructions. That is, if there is no conditional execution function, the function of conditional judgment must be realized by moving the execution control of the program like the if-else structure, but in general, the transfer of the execution control of the program is executed by the simultaneous execution of multiple instructions. This has the effect of hindering the parsing to do so that it prevents writing high performance programs that include parallel execution. Naturally, the compile processing method for generating a program to be executed on this conditional execution processing device needs to generate a program using this conditional execution function in order to generate a high performance program.

Next, an example of a conventional compiling method is described in Reference 2: Rod Adams and Sue Gray, "Using Conditional."
Execution to Exploit Instruction Level Concurrency (Using Conditio
nal Execution to Exploit Instruction Level Concurr
ency ”(Software-Practice and Experience)
Published in a magazine, September 1995, published by John Wiley & Sons, Inc.).

The technique disclosed in Document 2 will be briefly described as a second conventional example. For convenience of description, only the part of the technique disclosed in Document 2 related to the present invention will be described. The compiling method in the second conventional example is as a processing device in which a program to be generated is executed.
It analyzes the dependencies of multiple instructions and determines whether they can be executed at the same time. If possible, they are executed at the same time, and there is a register called the condition execution register. It is assumed that the condition execution processing device can execute the instruction only when the value of the execution register is a predetermined value.

Here, the operation of "execute the instruction only when the value of the condition execution register is a" predetermined value "" will be described with reference to the example shown in Document 2. The instruction "T B2 LD R20, 8 (SP)" is the load instruction "LD R20, 8 (SP)" when the value of the conditional execution register B2 is T (representing True). Indicates to execute. The "T" is a Boolean type value used in the condition execution processing device of the second conventional example, and is a constant for which the expression method in the processing device is fixed. That is,
If the value of the condition execution register (B2 in this case) is a "predetermined value" (constant T in this case),
The relevant instruction (in this case, "LD R20, 8 (SP)") will be executed.

In the compiling method of the second conventional example, a process called conditional compaction for generating a high performance program using a conditional execution function is performed. First, according to the method of the conventional compiler technique, the entire program is divided into units called basic blocks, and then a basic flow block is constructed to represent a control flow graph as one node of the graph. Further, from the basic blocks constituting the program, a basic block whose last instruction included in the basic block is a conditional branch instruction is extracted.

Next, for these basic blocks, the basic block to which the conditional branch instruction, which is the last instruction, branches,
By analyzing the basic block to which control is transferred when a branch is not performed for this conditional branch instruction at the time of program execution by the control flow graph and making each conditional instruction included in each basic block correspond to the conditional execution register This is a method for generating a high-performance program by using execution instructions and moving them to the basic block where the conditional branch instruction was the last instruction originally. That is, in the second conventional example, by using a conditional branch instruction, it is possible to move the code in a wide range in the program, and as a result, the number of instructions that can be executed simultaneously is increased and the performance of the program is improved.

[0011]

By the way, in the condition execution processing apparatus according to the first conventional example described above, when analyzing the dependency between the operands of each instruction with respect to a plurality of instructions, the determination is made in the condition execution instruction. For the register used for (register R1 in the above example), there is no restriction on the value that it holds, so if there are many code parts that are mutually exclusive in the original input program, it is essentially parallel. While it should be possible to perform high performance operations, including execution, it may not be possible to generate such code.

Such a case will be described with reference to FIG. FIG. 8 is an example of a program having a large number of exclusively executed code portions. This program has a double if-then-else structure, resulting in the
Code portions 101 and 1 constituting the n-part and the else-part
02, 103, and 104 are mutually exclusive.
That is, only one of the code portions 101, 102, 103, 104 is executed, and no two or more code portions are executed together. Therefore, there is no dependency between instructions belonging to different code portions in the sense that instructions belonging to different code portions can be executed simultaneously if there is an appropriate conditional execution instruction function that makes use of this characteristic of exclusive execution. .

However, in the condition execution processing of the first conventional example, since there is no restriction on the value held by the register used for judgment in the condition execution, the operands of these instructions use the same register. If so, it is unavoidable to recognize the dependency relationship between the registers and judge that the simultaneous execution of instructions is impossible, so that a high-performance operation cannot be obtained. A case where this high-performance operation cannot be obtained will be described with reference to FIG. Figure 9
Is an example of code created based on the operation of the condition execution processing device of the first conventional example with respect to the code of FIG. 8 (however, before execution timing determination of instructions for simultaneous execution of a plurality of instructions). Is.

The code notation in this example will be briefly described. First, one line of code corresponds to one instruction. Then tmp1, tmp2, tmp3, tmp4, tmp5, c1, c2, c
3, r1, r2, r3, r4 and r10 all represent registers of the condition execution processing unit. Therefore, the commands 201, 202, 203,
204 are code portions 101, 102, 10 respectively.
Since the codes are generated from Nos. 3 and 104, they are instructions that originally belong to different code parts, and there is no dependency between them. However, the condition execution processing device according to the first conventional example cannot judge that these instructions are executed at the same time, because these instructions are written to r10 which is the same register, and it is determined that there is a dependency relationship.

That is, when the instruction execution timing is determined based on the conditional execution processing of the first conventional example, the instruction execution timing is determined so that two instructions that are originally independent of each other are executed in parallel. Therefore, high performance operation is impossible. In addition, the above-described second conventional compilation processing method enables the movement of the code in a wide range in the program by using the conditional branch instruction, thereby increasing the possibility of executing a plurality of instructions at the same time. Although this has the effect of improving the performance of the program, the second conventional example does not consider the multi-selective condition execution register, and therefore has the same problem as the first conventional example.

Therefore, the present invention has been made in view of the above-described circumstances, and when the condition execution registers corresponding to a plurality of instructions are different, these instructions have a dependency relationship even though the instructions have a dependency relationship. The purpose is to provide a condition processing execution device that can execute in parallel.
It

[0017]

In order to achieve the above object, according to the invention described in claim 1, the dependency relationship of a plurality of instructions is analyzed to determine whether or not they can be simultaneously executed, and if possible, they are simultaneously executed. Conditional execution that has a register called a conditional execution register and can execute an instruction only when the conditional execution register is associated with each instruction and the value of this conditional execution register is a predetermined value In the processor , write the value of the conditional execution register.
After setting this value, the value to be written is
Check if they are equal to the "determined value", and both values are equal
If it is correct, all conditions other than the relevant condition execution register
Change the value of the execution register to a value other than "predetermined value"
Writing means to a value in the plurality of instructions, when conditional execution register corresponds to each instruction are different, this
It is determined that there is no dependency between these instructions, and each instruction execution
And dependency analysis means for determining the iming .

The invention according to claim 2 is a compiling process for performing a semantic analysis of an input program (source program) and converting it into a program (code) to be executed on a multi-choice type conditional execution processing device. there was extracted by analyzing each other code portions are executed exclusively in the program, the correspondence Rukoto one conditional execution register respectively instructions constituting each code portion, condition execution
A compile process that produces output code that uses the instructions
A conditional execution processing apparatus according to claim 1, characterized in that.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> (1) Configuration First, a first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a functional block diagram showing the configuration of the condition execution processing device according to the first embodiment, and FIG. 2 is a functional block diagram showing the configuration of the dependency analysis unit 304. As shown in FIG. 1, the condition execution processing device 301 reads a program stored in the memory 307, executes the instructions constituting the program to perform an operation, and outputs the operation result to the memory 307 and the general-purpose register file 308. , And a device for writing to the condition execution register file 309,
An instruction fetch unit 302, an instruction decoding unit 303, a dependency analysis unit 304, an instruction execution unit 305, and a result writing unit 306 are provided.

The instruction fetch unit 302 reads out the instructions stored in the memory 307, and the instruction decoding unit 303.
Analyzes the internal structure of the read instruction to analyze the type of the instruction and the content of the instruction operand, and the instruction execution unit 305 executes the instruction in accordance with the instruction execution timing determined by the dependency analysis unit 304 to perform an operation. Then, the result writing unit stores the calculation result in the memory 307 and the general-purpose register file 3.
08 and the condition execution register file 309, respectively. The dependency analysis unit 304 includes an instruction decoding unit 303.
The instruction execution timing is determined on the basis of the content of the instruction operand analyzed by, and is composed of a condition execution register comparison unit 401, an operand comparison unit 402, and an instruction execution timing determination unit 403, as shown in FIG. .

Here, referring to FIG. 2, the dependency analysis unit 304
The configuration of will be described. In this figure, the condition execution register comparison unit 401 compares the condition registers of an instruction group that is a condition execution instruction among a plurality of instructions for which dependency analysis is to be performed. Operand comparison unit 402
Compares the operands other than the condition execution register. The instruction execution timing determination unit 403 determines the timing to execute each instruction based on the analysis results of the condition execution register comparison unit 401 and the operand comparison unit 402.

(2) Operation Next, the operation of the first embodiment will be described. Since the condition execution processing device having the above-described configuration is characterized by the operation of the dependency analysis unit 304 and the operation of writing a value to the condition execution register file 309, the dependency analysis unit 304 will be described below with reference to FIGS. 3 and 4. And the operation of writing a value to the condition execution register 309 will be described. First, FIG. 3 is a flowchart showing the operation of the dependency analysis unit 304. The dependency analysis unit 304 determines the instruction execution timing for the instruction group in which the processing of the instruction decoding unit 303 ends and the type of the operand is analyzed.
To this end, it is necessary to analyze the dependency relationships of all the two instruction combinations for the instructions belonging to these instruction groups.

Therefore, first, for all instruction combinations, unprocessed ones are selected (step SA1), and it is checked whether the condition execution registers of the respective instructions are the same (step SA2). If both instructions are associated with the conditional execution registers, that is, both instructions are conditional execution instructions, and if the conditional execution registers are different, the instructions execute mutually exclusive in the program. Since it belongs to the code portion to be processed, the process proceeds to step SA3, and it is determined that there is no dependency between these instructions.

On the other hand, whether the condition execution registers are the same,
Alternatively, if at least one of the instructions is not a conditional execution instruction, the process proceeds to step SA4, and it is determined by the conventional dependency analysis method whether or not both instructions have a dependency. After that, in step SA5, it is determined whether or not all combinations of instructions have been checked. If the check has not been completed, the determination result is "NO", and the process returns to step SA1 described above, but when the check is finished, The result of the determination is "YES", and the process proceeds to step SA6 to determine the instruction execution timing according to the conventional instruction scheduling method.

Next, a value writing operation to the condition execution register file 309 will be described with reference to FIG. When writing a value to a certain condition execution register in the condition execution register file, the process first proceeds to step SB1, the value of the condition execution register is set to a value to be written, and then the process proceeds to step SB2. In step SB2, it is checked whether or not the value to be written in the condition execution register is equal to the "predetermined value". Here, if the two are equal, the determination result is "YES", the process proceeds to step SB3, and the values of all condition execution registers other than the condition execution register are set to values other than the "predetermined value". To do. This guarantees that at most one condition execution register holds the "predetermined value". Therefore, in the above description of the operation of the dependency analysis unit 304, if the condition execution registers of two instructions are different, both instructions cannot be executed at the same time, and it can be immediately determined that there is no instruction dependency.

(3) Compilation Processing Method Next, a program compilation processing method executed on the conditional execution processing apparatus according to the first embodiment will be described. First, with reference to FIG. 5, an overall compilation process according to the first embodiment will be described. In the compiling process shown in FIG. 5, first, the input program is subjected to semantic analysis by a conventional method to generate a data format inside the compiler called intermediate code (step SC).
1). Next, in step SC2, an output code is generated for this intermediate code. Since this processing is also performed by the conventional method, the generated output code does not include the conditional execution instruction. Then, in step SC3, the output code is analyzed to extract the code portions that are mutually exclusively executed, and in the following step SC4, different condition execution registers are associated with the code portions that are mutually exclusively executed. By doing so, an output code that uses the conditional execution instruction is generated.

Next, referring to FIG. 6, the above step SC
The process performed in step 3, that is, the process of extracting code portions that are mutually exclusive will be described. In order to extract the code portions that are executed mutually exclusively, first proceed to step SD1, and for the output code that does not include the conditional execution instruction, according to the conventional compiler technology method,
The whole program is divided into units called basic blocks, and a control flow graph is constructed in which each basic block is represented as one node in the graph. When the control flow graph is constructed in this way, the process proceeds to step SD2 to determine a node called "master" from the control flow graph and to extract a portion sandwiched between "masters".

The term "dominant (dominato)
r) ”is a generally known concept in the compiler technical field, for example, Document 3: Alfred V. Aho, Ravi Sethi, Jeffrey D. Ullman. .Ullman) "Compilers: Principles, Techniques, and Tool (Compilers: Principles, Techniques, and Tool)
s) "(Addison Wesle
y Publishing Company), 1986) Section 10.4 “Lo
"ops in Flow Graphs".

Now, generally, there are a plurality of portions sandwiched between the "rulers" extracted in the above step SD2.
Therefore, in step SD3, it is checked whether or not the portion sandwiched between the "rulers" satisfies all of the following two conditions (a) and (b). The two conditions are (a)
There is one edge that flows into each node for all nodes other than the "ruler". (B) For each node other than the "ruler" that has two or more edges flowing out, The instruction to be configured is only a branch instruction.

When these conditions (a) and (b) are satisfied, the nodes of the subdivisions sandwiched between the "rulers" and having one outflowing edge are all mutually exclusive. Part of the code that will be executed. Therefore, the process proceeds to step SD4, and by making different condition execution registers correspond to each code part, the instructions forming each code part are made into condition execution instructions, and then step SD
5. Proceed to 5 and integrate all the "rulers" at both ends in the part sandwiched between the "rulers" and the nodes rewritten using the conditional execution instruction to form one node (basic block). .

Such processing is possible because the nodes in the part sandwiched between the "masters" are code parts that are executed exclusively with each other except for the node having only the branch instruction, and all the condition execution instructions are executed. It is rewritten by using it, and it is executed correctly even if all the nodes are integrated. Next, in step SD6, it is determined whether or not there is an unanalyzed portion between the "rulers",
If there is an unanalyzed item, the judgment result is "YES".
Then, the processes of steps SD3 to SD5 are repeated, and when there are no unanalyzed items, the determination result is "NO", and the extraction process of the code portion to be exclusively executed is completed.

As described above, according to the first embodiment, in the process of setting a value in the condition execution register of the condition execution processing device, the number of condition execution registers holding a “predetermined value”. Control so that there is at most one,
Even if the contents of the conditional execution register corresponding to the conditional execution instruction are different, the instructions are processed in parallel, so the program can be created by associating different conditional execution registers with the code parts that can be executed mutually exclusive in the program. Execution by the condition execution processing device enables high-performance execution.

Further, according to the first embodiment, in the compiling processing method for automatically generating the program to be executed on the case execution processing device, the code portions which can be mutually exclusive in the program are automatically executed. It is possible to generate a code that automatically associates different condition execution registers with these code parts, so that the code parts that can be executed mutually exclusive in the program can be automatically executed as a program. Are generated dynamically, and high-performance execution becomes possible.

<Second Embodiment> Next, a second embodiment will be described with reference to FIG. Second shown in FIG.
The embodiment is different from the above-described first embodiment in that the general-purpose register and condition execution register file 30
2 is provided. That is, in the second embodiment, one register file is configured by both the general-purpose register group and the condition execution register group. However, regarding the operation related to the writing of the condition execution register,
The same operation as that of the first embodiment is performed for the condition execution register part of the general-purpose register and the condition execution register file 302.

[0035]

According to the present invention, in the process of setting a value in the condition execution register of the condition execution processing device, the number of condition execution registers holding the "predetermined value" is at most 1.
Control so that even if the contents of the conditional execution registers corresponding to the conditional execution instructions are different, the instructions are processed in parallel. By creating a corresponding program and executing it by the condition execution processing device, high-performance execution becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a block diagram showing a configuration of a dependency analysis unit 304.

FIG. 3 is a flowchart showing the operation of the dependency analysis unit 304.

FIG. 4 is a flowchart for explaining a write operation to a condition execution register file 309.

FIG. 5 is a flowchart for explaining a compiling process executed by the condition execution processing device.

FIG. 6 is a flowchart for explaining a method of extracting code parts that are mutually exclusively executed.

FIG. 7 is a block diagram showing a configuration of a second embodiment.

FIG. 8 is a diagram for explaining a conventional technique.

FIG. 9 is a diagram for explaining a conventional technique.

[Explanation of symbols]

301 Condition Execution Processing Device 302 According to First Embodiment 302 Instruction Fetch Unit 303 Instruction Decoding Unit 304 Dependency Analysis Unit 305 Instruction Execution Unit 306 Result Writing Unit 307 Memory 308 General Purpose Register File 309 Condition Execution Register File 401 Condition Execution Register Comparison Unit 402 Operand comparison unit 403 Instruction execution timing determination unit 901 Condition execution processing device 902 according to second embodiment General-purpose register and condition execution register file

Claims (2)

(57) [Claims] 1. A method of analyzing a dependency relationship of a plurality of instructions, determining whether or not they can be executed simultaneously, executing them simultaneously if possible, and having a register called a condition execution register, each instruction being provided with a condition execution register. Correspondingly, in the condition execution processing device capable of executing the instruction only when the value of the condition execution register is a predetermined value, the value of the condition execution register is set to a value to be written.
Later, this value to be written is a "predetermined value"
If both values are equal, then
Of all condition execution registers other than the condition execution register
Write with a value other than "predetermined value"
If the condition execution register corresponding to each instruction is different between the only means and a plurality of instructions, there is no dependency between these instructions.
Dependency that determines each instruction execution timing by determining that there is no
Conditional execution processing apparatus characterized by comprising a analyzing means. 2. A compiling process for performing semantic analysis of an input program (original program) and converting it into a program (code) to be executed on a multi-choice type conditional execution processing device, wherein the compiling processes are mutually performed. extracted by analyzing the code portion to be executed exclusively, by corresponding <br/> pickled Rukoto one conditional execution register respectively instructions constituting each code portion, output using the conditional execution instruction code
The condition execution processing device according to claim 1, wherein the condition execution processing device performs a compile process for generating .