JP2000206670A - Integrated circuit design method and integrated circuit design support apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce trouble, labor and cost and to efficiently form the mask patterns corresponding to diversified design rules by associating and displaying the layout dimensions dependent upon a layout apparatus and the post-shrinkage dimensions obtained from the mask patterns formed by layout design. SOLUTION: The shrinkage rate at the time of formation of the mask patterns corresponding to the desired design rules by shrinking the mask patterns formed by the layout design is first inputted from a keyboard 7 in an arithmetic processor 2. The layout dimensions in the mask pattern data assigned by a mouse 8 and the post-shrinkage dimensions obtained by shrinking the mask patterns formed by the layout design are displayed on a CRT9. Next, the processing for changing the layout dimensions of circuit elements and the post-shrinkage dimensions corresponding thereto is executed. The processing for embodying the functions necessary for another layouts, such as adding of the fresh circuit elements, is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit design method for designing a layout of a mask pattern for manufacturing an integrated circuit and an integrated circuit design support apparatus used for designing a layout of a mask pattern for manufacturing an integrated circuit. ,
In particular, it is advantageous in terms of labor, labor, and cost, and
The present invention relates to an integrated circuit design method and an integrated circuit design support device suitable for efficiently generating a mask pattern corresponding to various design rules.

[0002]

2. Description of the Related Art Conventionally, in designing an integrated circuit, a mask pattern used in actual LSI manufacturing is designed based on a desired system specification through a function design, a logic design, a circuit design, and a layout design. For a large-scale integrated circuit having hundreds of thousands or more of elements, manual design is practically impossible due to its complexity, and a layout device such as a CAD is usually used for this design.

In recent years, there has been a trend to manufacture LSIs using mask patterns corresponding to finer design rules in order to reduce costs and speed up circuit operations. In this case, a method of generating mask pattern data corresponding to a design rule includes, for example, creating a new finer design rule at the layout design stage, generating a library for each design rule, and There is a method that uses a library corresponding to the design rules while managing the data in a database or the like. In addition, for example, as a method of generating a mask pattern without changing a design rule, there is a method of directly shrinking (reducing) a layout-designed mask pattern using an optical unit or the like.

[0004]

However, in the former method of generating mask pattern data, since a layout apparatus generally does not support various design rules, a huge library is created for each design rule. And changes in design rules are frequent, creating a database that manages them requires enormous effort, labor, and cost.

On the other hand, in the latter method of generating a mask pattern, cells, paths, pins, etc. (hereinafter, cells, etc.) in a mask pattern before shrinking are all shrunk at a uniform shrink rate. Therefore, there is a possibility that a violation of the design standard rule occurs in the mask pattern after shrinking. In addition, as a result of shrinking, in the mask pattern after shrinking, cells and the like smaller than the minimum design dimensions of the cells and the like used in the actual circuit are generated, or the cells and the like are set to be smaller than the minimum distance between the cells and the like. Some cells were placed or cells whose resistance and capacitance were different from the design values were generated.

To avoid this, the layouter (layer) calculates the layout dimensions of the cells and the like in the mask pattern data before the shrink from the dimensions after the shrink of the cells and the like obtained by the shrink, and calculates the layout after the shrink. The layout dimensions must be changed so that the dimensions become the design dimensions of the cells and the like used in the actual circuit design, and so that the cells obtained by shrinking satisfy the design values. Therefore, not only is the layouter laborious and labor intensive, but also in order to efficiently generate a mask pattern corresponding to the design rules, one must rely on the intuition and experience of the layouter.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve such a conventional problem, and is advantageous in terms of labor, labor, and cost, and efficiently forms a mask pattern corresponding to various design rules. It is an object of the present invention to provide an integrated circuit design method and an integrated circuit design support device suitable for generating an integrated circuit.

[0008]

According to a first aspect of the present invention, there is provided an integrated circuit designing method according to the present invention.
An integrated circuit design method for laying out a mask pattern for manufacturing an integrated circuit using a layout apparatus, the method comprising obtaining a layout dimension dependent on the layout apparatus and shrinking the mask pattern laid out by the layout apparatus. And the associated post-shrink dimensions are displayed.

In such a method, for example, CAD
When laying out mask pattern data using software, first, the layouter sets the shrink rate when shrinking the mask pattern for which layout is designed to generate a mask pattern corresponding to a desired design rule. Then, the post-shrink dimension of the post-shrink mask pattern is calculated based on the layout dimension in the mask pattern data and the set shrink rate, and the layout dimension and the calculated post-shrink dimension are displayed in association with each other. .

Specifically, in the mask pattern data displayed on the display, for example,
When one of the arranged cells or the like is designated by a mouse or the like, a shrink dimension corresponding to the layout dimension of the designated cell or the like is calculated, and the layout dimension of the designated cell or the like, the calculated shrink dimension, Both dimensions are shown on the display.

After the layout of the mask pattern data is completed, a mask pattern is generated based on the laid-out mask pattern data, and the generated mask pattern is shrunk based on a predetermined shrink rate. Thus, a mask pattern corresponding to a desired design rule is generated. This claim 1
In the described invention, a layout dimension is a dimension that determines the configuration of mask pattern data in a layout apparatus, and includes, for example, dimensions such as a gate width and a gate length of a transistor in the mask pattern data. On the other hand, the dimension after shrink refers to a mask pattern designed by a layout device.
This is the actual dimension that determines the configuration of the post-shrink mask pattern generated by shrinking at a predetermined shrink rate. For example, if the layout size is 50 μm,
Assuming that the shrink ratio is 0.75, the post-shrink dimension at this time is 37.5 μm.

Displaying is not limited to displaying on a display, but also includes displaying on paper by outputting data to a printer. On the other hand, an integrated circuit design support apparatus according to claim 2 of the present invention is an integrated circuit design support apparatus used when performing layout design of a mask pattern for manufacturing an integrated circuit, wherein the layout size depends on the layout apparatus. And a post-shrink dimension obtained by shrinking the mask pattern layout-designed by the layout apparatus.

With such a configuration, for example, CAD
When laying out mask pattern data using software, first, the layouter sets the shrink rate when shrinking the mask pattern for which layout is designed to generate a mask pattern corresponding to a desired design rule. Then, the post-shrink dimension of the post-shrink mask pattern is calculated based on the layout dimension in the mask pattern data and the set shrink rate, and the layout dimension and the calculated post-shrink dimension are displayed in association with each other. .

Specifically, in the mask pattern data displayed on the display, for example,
When one of the arranged cells or the like is designated by a mouse or the like, a shrink dimension corresponding to the layout dimension of the designated cell or the like is calculated, and the layout dimension of the designated cell or the like, the calculated shrink dimension, Both dimensions are shown on the display.

After the layout of the mask pattern data is completed, a mask pattern is generated based on the laid-out mask pattern data, and the generated mask pattern is shrunk based on a predetermined shrink rate. Thus, a mask pattern corresponding to a desired design rule is generated. This claim 2
In the above-described invention, the layout dimensions, the shrink dimensions, and the display are the same as those in the first aspect of the present invention.

According to a third aspect of the present invention, there is provided an integrated circuit design supporting apparatus according to the second aspect, wherein the layout size is given.
Based on the given layout dimension, the corresponding post-shrink dimension is calculated. With such a configuration, when laying out the mask pattern data, if the layouter gives the layout dimension so that the layout dimension becomes a desired one, the given layout dimension and the set layout dimension are set. Based on the shrink rate, a corresponding post-shrink dimension is calculated.

Specifically, in the mask pattern data displayed on the display, for example,
When one of the arranged cells or the like is designated with a mouse or the like and the desired layout dimension is input from a keyboard or the like so that the layout dimension of the designated cell or the like becomes a desired one, the corresponding shrink is performed. The post-dimension is calculated, and both the layout dimension input for the specified cell or the like and the calculated post-shrink dimension are displayed on the display.

Further, according to a fourth aspect of the present invention, there is provided an integrated circuit design supporting apparatus according to the second or third aspect, wherein the desired design dimension is provided when a desired design dimension is provided. The layout dimension corresponding to the post-shrink dimension is calculated based on the design dimension so that the post-shrink dimension becomes the design dimension.

With this configuration, when laying out the mask pattern data, the layouter is designed so that the dimension after shrinking becomes a desired design dimension.
Assuming that the design dimensions are given, the layout dimensions corresponding to the given design dimensions and the set shrink rate are calculated. Specifically, in the mask pattern data displayed on the display,
For example, the layouter specifies one of the arranged cells or the like with a mouse or the like, and the desired design dimension is set so that the post-shrink dimension in the mask pattern after the shrink of the specified cell or the like becomes the desired design dimension. Is input from a keyboard or the like, the corresponding layout dimensions are calculated, and both the design dimensions input for the specified cells and the calculated layout dimensions are displayed on the display.

In this case, when a desired design dimension is input, the size of a cell or the like in the mask pattern data is changed based on the layout dimension calculated based on the input design dimension. It may be.
In the present invention, the design dimension is an ideal circuit dimension of a cell or the like used when manufacturing an integrated circuit. That is, when laying out the mask pattern data, the layouter changes the layout dimensions so that the post-shrink dimensions become the design dimensions.

According to a fifth aspect of the present invention, there is provided an integrated circuit design supporting apparatus according to the fourth aspect, wherein the mask pattern data is calculated when the mask pattern data is laid out on a grid at a predetermined interval. When circuit elements such as cells related to the layout dimensions are not properly arranged on the grid, the calculated layout dimensions are corrected so that the circuit elements are appropriately arranged on the grid, and the corrected layout is Based on the dimensions, the corresponding post-shrink dimensions are calculated.

With this configuration, when laying out the mask pattern data, assuming that the layouter gives a desired design dimension, the mask turn is performed so that the shrink dimension becomes the given design dimension. A layout dimension in the data is calculated. However, when laying out on a grid at a predetermined interval, when circuit elements related to the calculated layout dimensions are not properly arranged on the grid, calculation is performed so that the circuit elements are appropriately arranged on the grid. The layout dimensions are corrected, and the corresponding post-shrink dimensions are calculated based on the corrected layout dimensions and the set shrink rate.

More specifically, when laying out on a grid at a predetermined interval, in the mask pattern data displayed on the display, for example, the layouter specifies one of the arranged cells or the like with a mouse or the like, When the desired design dimension is input from a keyboard or the like so that the post-shrink dimension of the designated shrinkable mask pattern of the cell or the like becomes the desired design dimension, a layout dimension corresponding to this is calculated.

However, when the cells and the like related to the calculated layout dimensions are not properly arranged on the grid, that is, when the layout dimensions of the cells and the like do not become an integral multiple of the grid interval, the layout dimensions of the cells and the like are not equal to the grid interval. Based on the increased or decreased layout dimension that has been increased or decreased to be an integral multiple, a corresponding post-shrink dimension is calculated based on the increased or reduced layout dimension, and the increased or reduced layout dimension and the calculated post-shrink dimension are: Both dimensions are shown on the display.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment by an integrated circuit design method and an integrated circuit design support apparatus according to the present invention. In this embodiment, an integrated circuit design method and an integrated circuit design support apparatus according to the present invention are applied to a case where a layout pattern of a mask pattern for manufacturing an integrated circuit is designed and shrinked.

In FIG. 1, a computer 1 is connected to the outside, and has an arithmetic processing unit 2 for controlling operations and the entire system based on a control program, a main storage device 3 capable of electrically reading and writing data, and an external device. An input / output control unit 4 for inputting / outputting data between an external device and the main storage device 3, and a CRT control device 5 for converting data stored in a specific area of the main storage device 3 into an image signal and outputting the image signal
The arithmetic processing device 2, the main storage device 3, the input / output control device 4, and the CRT control device 5 are mutually connected by a bus which is a signal line for transmitting data. ing.

The input / output control device 4 includes, as external devices,
An auxiliary storage device 6 capable of magnetically reading and writing data, a keyboard 7 as a human interface capable of inputting data to the outside, and a mouse 8 as a pointing device are connected to each other. Further, a CRT 9 for displaying an image signal on a screen is connected to the CRT control device 5.

The main storage device 3 is a ROM in which a control program for the arithmetic processing device 4 is stored in a predetermined area in advance.
A RAM that stores data read from the ROM or the auxiliary storage device 6 and a calculation result required in the calculation process of the calculation processing device 4, and a VRAM that stores display data to be displayed on the CRT 2. . In addition, VRAM
Are independently and mutually accessible by the arithmetic processing unit 2 and the CRT control unit 5.

The CRT control device 5 controls the VR of the main storage device 3
The data stored in the AM is sequentially read from the head address at a predetermined cycle, and the read data is converted into an image signal and output to the CRT 9. The arithmetic processing unit 4 includes a microprocessing unit MPU and the like. When laying out mask pattern data on a grid at a predetermined interval, a predetermined program stored in a predetermined area of a ROM of the main storage device 3 is started. , The processing shown in the flowchart of FIG. 2 is executed.

Here, the processing executed by the arithmetic processing unit 4 when laying out mask pattern data on a grid at a predetermined interval is configured as follows. First, in the figure, in step S1, the shrink rate when the mask pattern designed for layout is shrunk to generate a mask pattern corresponding to a desired design rule is input from the keyboard 7, and in step S2
And the layout processing 1 for displaying the layout dimensions in the mask pattern data designated by the mouse 8 and the shrink dimensions obtained by shrinking the layout-designed mask pattern is executed, and the process proceeds to step S3. It has been migrated.

In step S3, a layout process 2 for changing the layout dimensions of the circuit elements and the corresponding post-shrink dimensions is executed, and the flow advances to step S4 to change the layout to another layout such as adding a new circuit element. A layout process 3 for realizing necessary functions is executed, and the process proceeds to step S5 to determine whether there is a request to end the layout of the mask pattern data. Then, the process proceeds to step S6, where the laid out mask pattern data is stored in the auxiliary storage device 6, and a series of processes is completed.

On the other hand, if it is determined in step S5 that there is no request to end the layout of the mask pattern data, the process proceeds to step S2. The layout process 1 in step S2 is configured as shown in the flowchart of FIG. In the figure, in step S11, it is determined whether or not a circuit element in the mask pattern data has been designated by clicking the mouse 8, and when it is determined that the circuit element has been designated, the process proceeds to step S12, where the designated circuit element is designated. Based on the layout dimensions and the shrink rate of the above, the corresponding shrink dimensions are calculated, and the process proceeds to step S13, where the layout dimensions of the designated circuit element and the calculated shrink dimensions are displayed on the CRT 9, The process returns to the process shown in the flowchart of FIG.

On the other hand, if it is determined in step S11 that the circuit element in the mask pattern data is not specified, the process returns to the processing shown in the flowchart of FIG. Also, the layout processing 2 in step S3
Are configured as shown in the flowchart of FIG.

First, in the figure, in step S21, it is determined whether there is a request to change the layout dimension or the post-shrink dimension of the circuit element, and it is determined that there is a request to change the post-shrink dimension of the circuit element. In some cases, the process proceeds to step S22, where the post-shrink dimensions of the circuit element to be changed are input from the keyboard 7, and the process proceeds to step S23, where the corresponding post-shrink dimensions and shrink rate of the input circuit element are used. The layout dimensions are calculated, and the process proceeds to step S24.

In step S24, it is determined whether or not the circuit elements relating to the calculated layout dimensions are properly arranged on the grid. If it is determined that the circuit elements are not properly arranged on the grid, the process proceeds to step S25. Step S2 corrects the layout dimensions so that the circuit elements related to the calculated layout dimensions are appropriately arranged on the grid.
Then, based on the corrected layout dimensions of the circuit elements and the shrinkage ratio, the corresponding post-shrinkage dimensions are calculated, and the flow proceeds to step S27.

In step S27, the layout dimensions and the post-shrink dimensions of the circuit elements are displayed on the CRT 9, and the process returns to the processing shown in the flowchart of FIG. On the other hand, when it is determined in step S24 that the circuit elements related to the calculated layout dimensions are appropriately arranged on the grid, the process proceeds to step S27.

On the other hand, if it is determined in step S21 that there is a request to change the layout dimensions of the circuit elements, the flow shifts to step S28, where the layout dimensions of the circuit elements to be changed are input from the keyboard 7, and
The process then proceeds to step S29, where the corresponding post-shrink dimensions are calculated based on the input layout dimensions and shrinkage of the circuit elements, and the process proceeds to step S27.

On the other hand, if it is determined in step S21 that there is no request to change the layout dimensions and the shrink dimensions of the circuit elements, the process returns to the processing shown in the flowchart of FIG. Next, the operation of the above embodiment will be described with reference to the drawings. FIG.
FIG. 6 is a diagram showing the correspondence between mask pattern data to be laid out and a new mask pattern obtained by shrinking a mask pattern generated thereby, and FIG.
FIG. 7 is a diagram illustrating a layout state of mask pattern data displayed on the CRT 9. FIG. 7 illustrates a case in which layout dimensions are corrected when circuit elements related to the calculated layout dimensions are not properly arranged on a grid. FIG.

For example, in a layout device capable of laying out circuit elements on a grid of 0.8 μm intervals, as shown in FIG. 5A, mask pattern data of a 0.8 μm rule is laid out and generated by this. As shown in FIG. 5B, when a new mask pattern is to be generated by shrinking a 0.8 μm mask pattern so as to be a 0.6 μm rule mask pattern, first a layouter is used. Is 0.6 μm / 0.8 μm, that is, 0.7
5 is input from the keyboard 7.

Then, the mask pattern data can be laid out. Here, the layouter is shown in FIG.
As shown in (a), when the cell A is designated by clicking the mouse 8, the layout dimension of the cell A, for example, 50.4 μm is multiplied by the shrink ratio 0.75, and the post-shrink dimension 37.8 μm is calculated. The layout dimension 50.4 μm of the designated cell A and the calculated post-shrink dimension 37.8 μm of the cell A ′ are displayed corresponding to the position of the mouse pointer on the CRT 9.

On the other hand, when the design dimension used for the actual circuit design of the cell A is 40 μm, to obtain a layout dimension such that the current post-shrink dimension 37.8 μm of the cell A ′ becomes the design dimension 40 μm, The layouter is shown in FIG.
As shown in (b), the cell A is designated by clicking the mouse 8, and when the input of the post-shrink dimension is requested in step S22, 40 μm is inputted from the keyboard 7 as a desired design dimension.

Then, the input post-shrink dimension of 40 μm is divided by the shrink rate of 0.75 to calculate a layout dimension of 53.3... Μm. However, as shown in FIG. 7A, the calculated layout dimension 53.3... Μm is not an integral multiple of the grid interval of 0.1 μm.
Cell A is not properly placed on the grid. Therefore, the layout size of cell A is set to 5 on the layout apparatus.
It cannot be changed to 3.3 .mu.m. In order to properly arrange the cell A on the grid, FIG.
As shown in (b), the calculated layout dimension 53.3... Μm of the cell A is an integral multiple of the grid interval 0.1 μm, and the calculated layout dimension 53.3.
The difference from m is corrected to 53.3 μm, which is as small as possible.

Next, the corrected layout dimensions 53.
The post-shrink dimension 39.975 μm is calculated by multiplying 3 μm by the shrink rate 0.75, and the layout dimension of the corrected cell A is 53.3 μ as shown in FIG.
m and the calculated post-shrink dimension 39.9 of cell A ′
75 μm is displayed corresponding to the position of the mouse pointer on the CRT 9.

At this time, the post-shrink dimension closest to the desired design dimension is selected. In addition,
The design size used for the actual circuit design of cell A is 42 μm
Is the input post-shrink dimension 42 μm
Is calculated from the following formula. Since the layout dimension 56 μm is an integral multiple of the grid interval 0.1 μm, this is not corrected, and the calculated layout dimension 56 μm of the cell A and the input cell A ′ The post-shrink size of 42 μm is displayed corresponding to the position of the mouse pointer on the CRT 9.

On the other hand, in order to obtain a post-shrink dimension such that the current layout dimension of cell A 53.3 μm is 60 μm, the layouter clicks mouse 8 as shown in FIG. 6D. Thus, the cell A is designated, and when the input of the layout dimension is requested in step S28, the desired layout dimension is set to 6
Input 0 μm from the keyboard 7.

Then, the input layout dimension 6
0 μm is multiplied by a shrink ratio of 0.75 to calculate a post-shrink dimension of 45 μm. As shown in FIG.
The input layout size of the cell A of 60 μm and the calculated design size of the cell A ′ of 45 μm are displayed corresponding to the position of the mouse pointer on the CRT 9. On the other hand, when the layout of the mask pattern data is completed, the layouter issues a request to finish the layout work to the keyboard 7.
When input from the mouse 8 or the mouse 8, the laid out mask pattern data is stored in the auxiliary storage device 6.

Thereafter, a mask pattern for manufacturing an integrated circuit is generated based on the laid out mask pattern data, and this mask pattern is shrunk at a shrink rate of 0.75 to generate a 0.6 μm rule mask pattern. Is done. Then, a desired integrated circuit is manufactured based on the mask pattern data of the 0.6 μm rule.

As described above, when the mask pattern data is laid out, the layout dimensions of the circuit elements and the post-shrink dimensions corresponding to the layout dimensions of the circuit elements are displayed in association with each other. In comparison, it is possible to reduce the labor, labor, and cost, and efficiently generate a mask pattern corresponding to various design rules.

In particular, when a design dimension of a desired circuit element is inputted, a layout dimension is calculated based on the inputted design dimension such that a shrinked dimension of the circuit element becomes a desired design dimension. By doing so, the trouble of back-calculating the layout dimensions so that the post-shrink dimensions become the desired design dimensions can be omitted, so that the layout can be made more efficient.

Further, when the layout dimensions of the desired circuit element are input, the corresponding post-shrink dimensions are calculated on the basis of the input layout dimensions. Since the post-shrink dimensions corresponding to the changed layout dimensions can be obtained without changing the dimensions, the layout can be made more efficient.

Further, when the circuit elements related to the calculated layout size are not properly arranged on the grid, the calculated layout size is increased or decreased so as to be an integral multiple of the grid interval, and the increased or reduced layout size is reduced. By calculating the corresponding post-shrink dimensions based on this, the desired design of the circuit element among the post-shrink dimensions corresponding to the layout dimensions such that the circuit elements are properly arranged on the grid is calculated. Since the post-shrink dimensions close to the dimensions can be selected, the layout can be made more efficient.

In particular, when the circuit elements relating to the calculated layout dimensions are not properly arranged on the grid, the layout is set so as to be an integral multiple of the grid interval and to minimize the error from the calculated layout dimensions. By correcting the dimensions, it is possible to obtain a design dimension that is a layout dimension that is appropriately arranged on the grid and that minimizes an error from a desired design dimension.

In the above embodiment, both the layout processing 1 of step S2 and the layout processing 2 of step S3 are provided. However, the present invention is not limited to this. , Step S3
And layout processing 2 of the above. Further, in the above embodiment, when the circuit elements related to the calculated layout dimensions are not appropriately arranged on the grid, the calculated layout dimensions are set to integer multiples of the grid interval of 0.1 μm and the calculated layout dimensions. Although the dimensions that minimize the error are displayed, it is easy to configure a system that automatically corrects the layout data at the same time.

Further, in the above embodiment, the layout size or the post-shrink size is configured to be displayed on the CRT 9. However, the present invention is not limited to this.
A printer may be connected to the printer and data relating to the layout dimensions or the post-shrink dimensions may be output to the printer, so that these are displayed on paper. Further, in the above-described embodiment, in executing the processing shown in the flowcharts of FIGS. 2 to 4, the case where a program stored in advance in the ROM of the main storage device 3 is executed has been described. The program is stored in a RAM of the main storage device 3 from a recording medium on which the program indicating these procedures is recorded.
May be read and executed.

Here, the recording medium is RAM, ROM,
Any recording medium such as an FD, a compact disk, a hard disk, a magneto-optical disk, or paper, which can be read by a computer regardless of an electronic, magnetic, optical, or other reading method. It includes a recording medium. Further, in the above-described embodiment, the processing shown in the flowcharts of FIGS. 2 to 4 has been described in the case where the processing is implemented by software. Instead, electronic circuits such as a comparison circuit, an arithmetic circuit, and a logic circuit are replaced with electronic circuits. You may comprise so that it may combine.

[0056]

As described above, according to the integrated circuit design method or the integrated circuit design support apparatus according to the present invention, it is possible to reduce the labor, labor, and cost as compared with the related art, and to realize various design. The effect is obtained that a mask pattern corresponding to the rule can be efficiently generated.

Further, according to the integrated circuit design support apparatus of the third aspect of the present invention, the post-shrink dimensions corresponding to the changed layout dimensions can be obtained without actually changing the layout dimensions of the cells and the like. Therefore, the effect that layout efficiency can be further improved can be obtained. Further, according to the integrated circuit design support device of the present invention, since the work of back-calculating the layout dimensions so that the post-shrink dimensions become the desired design dimensions can be omitted, the layout efficiency can be further improved. Is obtained.

Further, according to the integrated circuit design support apparatus according to the fifth aspect of the present invention, among the post-shrink dimensions corresponding to the layout dimensions such that the cells and the like are appropriately arranged on the grid, the cells and the like are included. Since the post-shrink dimensions close to the desired design dimensions can be selected, it is possible to obtain an effect that the layout can be made more efficient.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment.

FIG. 2 is a flowchart showing processing executed when laying out mask pattern data.

FIG. 3 is a flowchart showing a layout process 1 in step S2 in FIG.

FIG. 4 is a flowchart showing a layout process 2 in step S3 in FIG.

FIG. 5 is a diagram showing a correspondence between mask pattern data to be laid out and a new mask pattern obtained by shrinking a mask pattern generated thereby.

FIG. 6 is a diagram showing a layout state of mask pattern data displayed on a CRT 9;

FIG. 7 is a diagram for explaining a case where layout dimensions are corrected when circuit elements related to calculated layout dimensions are not properly arranged on a grid.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 computer 2 arithmetic processing unit 3 main storage device 4 input / output control device 5 CRT control device 6 auxiliary storage device 7 keyboard 8 mouse 9 CRT

Claims (5)

[Claims] An integrated circuit design method for designing a layout of a mask pattern for manufacturing an integrated circuit using a layout apparatus, the layout pattern depending on the layout apparatus, and the mask pattern designed by the layout apparatus. And a post-shrinking dimension obtained by shrinking the information. 2. An integrated circuit design support device used when designing a layout of a mask pattern for manufacturing an integrated circuit, the layout size depending on the layout device, and the mask pattern designed by the layout device. An integrated circuit design support apparatus characterized in that a post-shrink dimension obtained by shrinking is displayed in association with. 3. The apparatus according to claim 2, wherein when the layout dimension is given, the post-shrink dimension corresponding to the given layout dimension is calculated based on the given layout dimension. Integrated circuit design support equipment. 4. Given a desired design dimension,
The layout dimension corresponding to the post-shrink dimension is calculated based on the given design dimension, so that the post-shrink dimension becomes the design dimension. 3. The integrated circuit design support device according to 3. 5. When laying out mask pattern data on a grid at a predetermined interval, when a circuit element such as a cell relating to the calculated layout dimension is not properly arranged on the grid, the circuit element is placed on the grid. Wherein the calculated layout dimensions are corrected so as to be appropriately arranged, and the post-shrink dimensions corresponding to the corrected layout dimensions are calculated based on the corrected layout dimensions. 4. The integrated circuit design support device according to 4.