JP2000201141A - Parallel signal transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a transmission speed without limiting the number of units in a parallel signal transmission system connecting plural plug-in units. SOLUTION: The parallel signal transmission system comprises a signal line for an N-bit parallel signal and two or more plug-in units connected to the signal line. Each plug-in unit is provided with an intra-unit clock generation circuit and an M-frequency division circuit and allowed to delay respective bits in the N-bit parallel signal by a delay circuit 111 having (M+1) stages, generate a differential signal between outputs from adjacent stages of the circuit 111, generate exclusive OR of differential signals generated in each bit, and select the sampling timing of the N-bit parallel signal, based on the exclusive OR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel signal transmission system, and more particularly, to a parallel signal transmission system capable of improving a transmission speed when a plurality of plug-in units are connected.

[0002]

2. Description of the Related Art FIG. 11 shows a configuration diagram of a conventional communication device. The communication device illustrated in FIG. 11 includes a unit 1101 that generates a reference clock commonly used in all units and transmits the reference clock to a plurality of units, and units 1102 and 1103 that operate using the received reference clock. , Unit 1101 to unit 110
2 and signal line 11 for transmitting a reference clock to 1103
11 and N signal lines 110 for transmitting communication signals
4

A unit 1101 includes a reference clock generation circuit 1114, which generates a clock signal having a precision required for the device by using a crystal oscillator or the like. The generated clock signal is supplied to a signal processing unit 1115 that processes a signal to be communicated in the unit 1101. The signal processing unit 1115 performs desired signal processing using the supplied reference clock, and outputs a signal to be transmitted to another unit to the flip-flop (F / F) 1112. After the flip-flop 1112 uses the reference clock to match the output timing to the reference clock,
The signal is output to the signal line 1104 using the signal line 1105.

On the other hand, when the unit 1101 receives a signal from another unit, the flip-flop 1113
Receives the signal on the signal line 1104 from the signal line 1106, holds the signal using the reference clock 1111 and reads out the held signal by the signal processing unit 1115.

[0005] The unit 1102 operates using the reference clock received from the unit 1101, and therefore does not have a reference clock generation circuit, and supplies the clock signal received from the signal line 1111 to the signal processing unit 1118. The signal processing unit 1118 performs desired signal processing using the supplied clock signal, and outputs a signal to be transmitted to another unit to the flip-flop (F / F) 1117.
The flip-flop 1117 adjusts the output timing to the same timing as the reference clock using the clock signal, and outputs the signal to the signal line 1104 using the signal line 1107. On the other hand, when the unit 1102 receives a signal from another unit, the flip-flop 1116 receives the signal on the signal line 1104 from the signal line 1108, holds the signal using a clock signal, and outputs the held signal. An operation of reading by the signal processing unit 1118 is performed.

The configuration of the unit 1103 is the unit 110
This is the same as the configuration of FIG.

FIG. 12 shows a unit 1101 to a unit 1
6 is a time chart for explaining signal transmission to the communication device 102; (A) shows a reference clock signal. (B) is a flip-flop 11 using the reference clock of (a).
12 is an output signal. A change point of the output signal appears when a delay time (T0) of the flip-flop has elapsed from the rise of the reference clock. (C) is a waveform assuming that the unit 1101 itself receives the output of the unit 1101 in order to explain the operation of the unit placed near the unit 1101. A change point of the input signal of the flip-flop 1113 appears after the transmission delay time (T1) from the waveform of (b). On the other hand, flip-flop 111
Since the input clock signal of No. 3 also receives the same delay as the data signal, the input clock signal of the flip-flop 1113 has the timing shown in (d) and can be retimed before the change point of (c). Transmission is possible. (E) shows the reception signal of the flip-flop 1116 in the unit 1102 which is far from the unit 1101. The delay time (T2) is longer than T1. As shown in FIG.
Since the 16 clock inputs also receive the same delay time (T2), the phase difference between (e) and (f) is the same as (c) and (d).

As described above, the signal transmission from the unit 1101 for generating the reference clock to other units does not depend on the transmission distance and the signal speed, and is performed when the signal speed is increased and when the number of units is increased. There is no problem when the distance is increased.

FIG. 12G shows the same reference clock as in FIG. (H) is a flip-flop 11 for transmitting a signal
17 shows an input clock signal of the seventeenth embodiment. This indicates that the reference clock reaches the flip-flop 1117 after the elapse of the transmission delay time (T2) between the units. (I) shows the output signal of the flip-flop 1117. After the clock signal (h), a signal change point appears after the delay time (T0) of the flip-flop. (J) shows an input data signal of the flip-flop 1113 in the unit 1101. (I)
After the transmission delay time (T2).
113 is reached. Flip-flop 111
Since the input clock signal of No. 3 is the reference clock signal of (a), retiming is possible at the portion shown in (j).

[0010]

However, as shown in FIG.
Is a waveform when the delay time is T2. In general, the delay time between units in the device depends on the size of the device and the number of units, and varies in various ways. Flip-flop 1113 when there is a difference in delay time between units
Is shown in (k). In (k), the time range of the arrival time due to the difference in the transmission distance is shown as T3. If the rise of the reference clock falls within the range of T3, normal signal transmission becomes impossible.

FIG. 12 (l) shows an example in which the transmission frequency is approximately doubled. (L) indicates a reference clock.
(M) is a waveform corresponding to (k). Since the time range (T3) of the arrival time due to the difference in the transmission distance is longer than the period of the reference clock, retiming is not possible in the flip-flop 1113.

As described above, in the conventional technique, when the number of units used in the apparatus is increased, the time range of the arrival time due to the difference in the transmission distance is widened, so that the number of usable units is limited. For this reason, when increasing the transmission speed, the period needs to be longer than the arrival time due to the difference in transmission distance, and the transmission speed is limited.

For example, if the signal speed on the signal line 1104 is 1
Assuming 10 nanoseconds per meter and the length of signal line 1104 at 50 centimeters, the difference in delay time when 1101 is installed at the end of the device is about 10 nanoseconds. Assuming that the margin for retiming by the flip-flop is 10 nanoseconds and the variation of the delay time of the buffer in the unit input / output unit is 5 nanoseconds, the shortest cycle is (10 + 10 + 5 =) 25 nanoseconds. That is, the upper limit of the transmission frequency under the above assumption is 40 MHz.

Therefore, an object of the present invention is to improve the transmission speed without limiting the number of units in a parallel signal transmission system in which a plurality of plug-in units are connected.

[0015]

According to the present invention, there is provided a parallel signal transmission system comprising an N-bit parallel signal signal line and two or more plug-in units connected to the signal line. The plug-in unit includes a clock generation circuit in the unit and an M frequency dividing circuit, and delays each bit of the N-bit parallel signal by a (M + 1) -stage delay circuit. A differential signal between the outputs of the stages is generated, an exclusive OR of the differential signal generated for each bit is generated, and a sampling timing of the N-bit parallel signal is selected based on the exclusive OR. .

Further, the difference signal in the present invention may be only the difference signal between the output of the first stage and the output of the next stage of the delay circuit.

That is, in the present invention, when signal transmission is performed between a plurality of units, the timing to be retimed using data to be transmitted without using a single clock signal as a signal transmission reference is used. The decision increases the frequency of signal transmission in the device and increases the number of units that can be used in the device.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a parallel transmission system according to a first embodiment of the present invention. As shown in FIG. 1, the parallel transmission system according to the first embodiment of the present invention includes units 101 and 102 each performing predetermined signal processing.
And 103, and N signal lines 1 for transmitting communication signals
04.

All the units have the same internal configuration, and FIG. 1 uses the unit 101 to explain the internal configuration. In the unit 101, there is an in-unit clock generation circuit 114 that generates a clock signal to be used as a reference inside the unit, and generates a clock signal with an accuracy required for the device using a crystal oscillator or the like. The generated clock signal is supplied to the delay circuit 111 and the M frequency dividing circuit 115. The operation of the delay circuit 111 will be described later. The M frequency dividing circuit 111 divides the frequency of the received clock into a frequency of 1 / M and supplies a clock signal to the signal processing unit 117 and the flip-flop 116 that outputs a signal from the unit 101.

In the following description, the dividing ratio M is assumed to be 4 for simplicity. The signal processing unit 117 performs desired signal processing using the supplied clock signal, and outputs a signal to be transmitted to another unit to the flip-flop (F / F) 116. The flip-flop 116 adjusts the output timing using the frequency-divided clock signal, and then outputs the signal to the signal line 104 using the signal line 105. On the other hand, when the unit 101 receives a signal from another unit, the delay circuit 111 transmits the signal on the signal line 104 to the signal line 1.
06 and using the in-unit reference clock,
Gives a plurality of predetermined delays. The signals to which the different delay times are given are selected by the selection circuit 113 to be optimal signals, and are input to the signal processing unit 117. Judgment unit 11
2 indicates a signal to be selected by the selection unit 113.
The information used for the determination is transmitted from the delay circuit 111 to the determination unit. The internal configuration of the units 102 and 103 is the same as that of the unit 101. Signal lines 108 and 110 are used for signal input to the unit, and signal lines 107 and 109 are used for signal output from the unit.

FIG. 2 shows a configuration example of the delay circuit 111, the selection circuit 113, and the determination circuit 112 in FIG.
This figure is an example in the case where four signal lines 104 are formed. Four signals (0) received from the signal line 104,
(1), (2) and (3) correspond to the corresponding delay circuits 20 respectively.
1, 202, 203 and 204. Further, a clock signal received from the internal reference clock generation circuit is also input to the delay circuits 201, 202, 203, and 204.

FIG. 3 is a block diagram showing the internal configuration of each delay circuit. As shown in FIG. 3, the flip-flops 301 to 305 generate a delay signal. Generally, at least (M + 1) delay circuits are required for the division ratio M. The exclusive OR 306 to 309 are used to generate a difference signal, that is, a difference signal 1-2 between the delay signal 1 and the delay signal 2 and a difference signal 2- between the delay signal 2 and the delay signal 3.
3. A difference signal 3-4 between the delay signal 3 and the delay signal 4 and a difference signal 4-5 between the delay signal 4 and the delay signal 5 are generated. Since the difference signal is an exclusive OR of the results of sampling at two adjacent timings, when the data change point is between these two timings, it becomes logic "1", and at the two adjacent timings. If the same value is obtained, it becomes logic "0".

As shown in FIG. 4, the input data phase with respect to the reference clock in the unit can be checked by the difference signal. In order to check the phase and select an optimal delay signal, the four difference outputs are input to the determination circuit 112. In the determination circuit 112, the exclusive OR of the difference signal 1-2 using the OR circuit 209, the exclusive OR of the difference signal 2-3 using the OR circuit 210, and the difference signal using the OR circuit 211 are used. The exclusive OR of the difference signal 4-5 is generated by using the exclusive OR and OR circuit 212 of 3-4. The decision circuit 213 determines a delay signal to be selected according to the logic shown in the following table.

[0025]

[Table 1] On the other hand, the delay signals output from 201 to 204 in delay circuit 111 are input to corresponding selectors 205 to 208 in selection circuit 113 as shown in FIG. The selectors 205 to 208 select the delay signal according to the determination of the determination circuit 211 and send the signal to the signal processing unit.

FIG. 5 is a timing chart showing the operation in the unit 101. (A) is an in-unit reference clock generated by 114. The clock input to the flip-flop 116 is shown in FIG. In the present embodiment, since the dividing ratio in the M dividing circuit 115 is assumed to be 4,
The waveform has a cycle four times as long as the reference clock in the unit in FIG. From the signal processing unit 117 to the flip-flop 11
The signal input to 6 is shown in (c). Assuming that the receiving unit is the unit 102, for example, the unit 1
It is assumed that the reference clock in 02 is (d). The frequency is the same as the unit 101. When the signal of (c) is sampled by the clock of (d), the waveform of (e) is obtained.
A portion indicated by a circle in the waveform of (e) corresponds to a delay signal.
By making an exclusive OR of adjacent delay signals,
The change point detection signal shown in (f) is obtained. Since the portion of the waveform (f) where the logic is "1" indicates the data change point, stable data reception is possible by selecting the sampling timing at the center of the change point.

Next, the reason for using the exclusive OR 209, 210, 211, 212 between a plurality of parallel signals when determining the sampling timing from the difference signal will be described.

FIG. 6 shows an example in which four parallel signals are transmitted, and the parallel signals (0), (1), (2),
The case where the change points between (3) do not match, that is, the case where the timing between the parallel signals is not uniform.
In this case, if the timing is determined using only a single signal, for example, only the parallel signal (3), it can be seen that the margin of the parallel signal (2) is not sufficient in FIG. .

As shown in FIG. 7, in the present embodiment, since exclusive ORs 209, 210, 211, and 212 are used, a change point may be different between a plurality of signals constituting a parallel signal. Also, all change points can be transmitted to the determination circuit 213 by exclusive OR. The determination circuit 213 can determine the timing using the change point information of all the signals, and can obtain the optimal phase.

The embodiment of the present invention has been described above. However, the present invention is not limited to this, and the delay circuits 801, 802, 803, and 80 are used as in the second embodiment shown in FIG.
The circuit shown in FIG.

In the delay circuit 801 shown in FIG. 9, the portion for generating the delay signals 1 to 5 is the same as that of the delay circuit shown in FIG. 3, but the difference signal is only the difference signal between the delay signal 1 and the delay signal 2. There is a feature in generating. FIG.
In the determination circuit 112, the exclusive OR of the difference signals of the four parallel signals is generated by the OR circuit 805. The generated exclusive OR signal is transferred to the shift register 8
The determination circuit 213 can be operated by performing the expansion by 06.

FIG. 10 shows a third embodiment of the present invention. In the first and second embodiments of the present invention, the connection from the unit to the signal line for transmitting signals between the units uses separate signal lines for transmission and reception, but the third embodiment uses a common signal line. It is characterized in that a single signal line is used as the signal line.

The fourth embodiment is a method in which a signal line for identifying a change point is added to a signal from a signal processing unit to be transmitted so that a change point of a transmission signal can be always identified.
A signal to be added is, for example, a signal “010101”.

In all the embodiments described above, the number of bits of the parallel signal is assumed to be 4 bits. However, the present invention is not limited to a 4-bit signal, and can be applied to a signal of a plurality of bits. When the number of parallel signals increases, it is not necessary to determine timing using all signal lines, and a method of selecting a plurality of signals may be used.

[0035]

According to the present invention described above, the first effect is that the reference clock which is commonly used for all the units in the apparatus is not used, so that the difference in transmission delay time between the units is caused. Since there is no restriction on signal transmission, the number of units that can be mounted on the device can be increased.

The second effect is that the reference clock which is commonly used for all the units in the apparatus is not used.
Since the transmission frequency is not restricted, the transmission frequency can be increased.

The third effect is that since a reference clock which is commonly used for all units in the apparatus is not used,
Wiring in the device is simplified.

The fourth effect is that a reference clock which is commonly used for all units in the apparatus is not used.
It is not necessary to use a special unit for generating the reference clock, and the configuration of the apparatus is simplified.

A fifth effect is that the timing is determined by using information on the change points of a plurality of parallel signals, so that stable signal transmission is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a parallel signal transmission system according to the present invention.

FIG. 2 is a block diagram of a delay circuit, a selection circuit, and a determination circuit;

FIG. 3 is a block diagram of a delay circuit;

FIG. 4 is a time chart showing a relationship between a difference signal and an input data phase.

FIG. 5 is a time chart for explaining the operation of the signal transmission unit.

FIG. 6 is a time chart for explaining a parallel signal whose change points do not match;

FIG. 7 is a time chart for explaining sampling timing determined by using all side addition point information;

FIG. 8 shows a second embodiment of the present invention.

FIG. 9 is a block diagram of a delay circuit used in the second embodiment.

FIG. 10 shows a third embodiment of the present invention.

FIG. 11 is a block diagram of a conventional parallel signal transmission system.

FIG. 12 is a time chart for explaining signal transmission between conventional transmission units.

[Explanation of symbols]

 101, 102, 103 Transmission unit 104, 105, 106 Signal line 111 Delay circuit 112 Judgment unit 113 Selection circuit 114 In-unit clock generation circuit 115 M frequency dividing circuit 116 Flip-flop (F / F) 117 Signal processing unit

Claims (5)

[Claims] 1. A parallel signal transmission system comprising: an N-bit parallel signal signal line; and two or more plug-in units connected to the signal line, wherein the plug-in unit includes a clock generation circuit in the unit, An M-frequency dividing circuit, wherein each bit of the N-bit parallel signal is delayed by an (M + 1) -stage delay circuit, and a differential signal between outputs of adjacent stages of the delay circuit is generated. A parallel signal transmission system comprising: generating an exclusive OR of the generated difference signal; and selecting a sampling timing of the N-bit parallel signal based on the exclusive OR. 2. A parallel signal transmission system comprising: an N-bit parallel signal signal line; and two or more plug-in units connected to the signal line, wherein the plug-in unit includes an internal clock generation circuit, An M-frequency dividing circuit, wherein each bit of the N-bit parallel signal is delayed by an (M + 1) -stage delay circuit, and a difference signal between the first-stage output and the next-stage output of the delay circuit is generated; A parallel signal transmission system, wherein an exclusive OR of the differential signal generated for each of the N bits is generated, and a sampling timing of the N-bit parallel signal is selected based on the exclusive OR. 3. The parallel signal transmission system according to claim 1, wherein a data transmission line and a data reception line in the plug-in unit are shared. 4. The parallel signal transmission system according to claim 1, wherein an identification signal line for a signal for identifying a data change point is provided in the plug-in unit. 5. The data change point identification signal according to claim 1, wherein the logic value changes from “1” to “0” for each sampling cycle of the plug-in unit. 2. The parallel signal transmission system according to any one of 2.