JP2000201036A - High frequency amplifier circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the gate voltage of a control transistor in proportion to an AGC potential, and to reduce a voltage by providing a prescribed circuit constitution by using dual FET for both a main transistor and the transistor for controlling a gain. SOLUTION: A common part 21 of transistors TC1 and TC2 of a control transistor Q2 in a dual gate structure is connected through a resistor R2 with a gate G1 of a main body transistor Q1, and a gate G2 of the main transistor Q1 is connected with a gate 1 of the control transistor Q2. When an AGC potential is impressed to the gate G2, the voltage of the gate G1 of the control transistor Q2 is decreased according as the AGC potential is decreased, and currents running through the control transistor Q2 are decreased, and a potential VC of the common part 21 is increased according to the decrease of a voltage. As a result, a voltage is supplied to the gate G1 of the main transistor Q1 so that the function of a forward AGC function can be obtained. Thus, the voltage of the gate 1 of the control transistor is decreased in proportion to the decrease of the AGC potential so that distortion characteristics at the time of attenuating a gain can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency amplifier circuit device, and more particularly to a dual-gate field-effect transistor with a built-in controllable bias circuit, which is applied to a high-frequency amplifier circuit device having an AGC (Auto Gain Control) function such as a TV / VTR tuner. And effective technology.

[0002]

2. Description of the Related Art As one of high-frequency amplifier circuits (high-frequency amplifier circuits) having an AGC function, there is a dual-gate MOSFET for a built-in bias tuner. A dual-gate MOSFET for a built-in bias tuner is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-175761. The technologies disclosed in the above publications are all dual-gate FETs.
Controllable bias circuit (control MOSFET) composed of
And a controllable amplifier circuit (main body MOSFET), and controls the voltage of the gate 2 of the main body MOSFET by a control MOSF.
The configuration is such that the current input to the gate 2 of the ET, the current flowing through the control MOSFET is reduced, and a voltage is supplied to the gate 1 of the main body MOSFET by a voltage drop. This technology is a monolithic (all-in-one type) high-frequency amplifier circuit comprising a controllable amplifier circuit and a controllable bias circuit for controlling the controllable amplifier circuit, and uses a dual-gate FET having a small gate width Wg as a control transistor. Utilizing the structure, a voltage from the drain terminal is applied to the drain of the control FET through a resistor or an FET load. Further, the gate 2 of the main body FET is connected to the gate 2 of the control FET, the current flowing through the resistor or the FET load is changed, and the potential of the gate 1 is moved in the opposite direction to the change of the gate 2. This operation has the same effect as increasing the potential between the gate and the source in the + direction when a single FET is used. In addition, since the source is not provided with a resistor, low voltage operation is possible and there is an advantage that the resistor and the capacitor can be omitted.

[0003]

SUMMARY OF THE INVENTION In the present inventor,
It has been studied to lower the voltage of a high-frequency amplifier circuit in which a body transistor formed of a dual-gate FET is bias-controlled by a control transistor formed of a dual-gate FET. The present invention has been obtained as a result of this study. An object of the present invention is to provide a high-frequency amplifier circuit device having a built-in bias circuit capable of operating at a low voltage.
The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[0004]

The following is a brief description of an outline of typical inventions disclosed in the present application. (1) A high-frequency amplifier circuit device having a main transistor constituted by a dual-gate field-effect transistor and a control transistor constituted by a dual-gate field-effect transistor for controlling a gain of the main transistor, wherein The drain terminal of the control transistor is connected to a first reference potential, the source terminals of the body transistor and the control transistor are connected to a second reference potential, and the gate 1 of the body transistor is connected to a second reference potential via a back-to-back diode. Connected to a common portion of the control transistor 1 and the transistor 2 in the control transistor via a resistor, and the gate 2 of the main body transistor is connected to a second reference potential via a back-to-back diode. Previous The drain terminal of the control transistor is connected to the gate 2 of the control transistor and connected to the source terminal via a diode. A diode is connected between the drain terminal and the source terminal of the main transistor. It is connected. Gate 1, Gate 2,
The drain and the source are each an external terminal.

(2) In the configuration of the means (1), a bleeder resistor is connected between the gate 2 of the control transistor and the source terminal of the control transistor.

(3) In the configuration of the means (1), a resistor is provided between the gate 1 of the control transistor, the gate 2 of the body transistor, the gate 1 of the control transistor, and the source terminal of the control transistor. .

According to the means (1), the gate 1 of the main body transistor is connected to the common portion (VC) of the control transistor and the transistor 1 and the transistor 2 via the resistor, and the gate 2 of the main body transistor is connected. When the AGC potential is applied to the gate 2 of the main body transistor, the current flowing through the control transistor decreases with a decrease in the AGC potential because the gate is connected to the gate 1 of the control transistor. The potential (VC) increases, and as a result, a voltage is supplied to the gate 1 of the body transistor. Since the voltage at the gate 1 of the control transistor decreases in proportion to the decrease in the AGC potential, it is possible to achieve an improvement in distortion characteristics at the time of gain attenuation. Also, lower voltage can be achieved.

According to the means of (2), the voltage of the gate 2 of the control transistor is bleeder (divided) by using a resistor.
Therefore, the maximum voltage output from the VC can be limited.

According to the means (3), since the voltage of the gate 1 of the control transistor is bleeding using a resistor, the minimum voltage output from the VC can be limited. That is, when the voltage of the gate 1 of the control transistor increases, the VC voltage decreases and the channel 1 of the main body transistor is closed more than necessary, which causes a problem. Therefore, the voltage of the gate 1 of the control transistor can be adjusted by resistance division. Also, by dividing the AGC supply voltage of the main body transistor (the voltage of the gate 2) by resistance, it is also possible to make the curve by the VC voltage and the gate 1 voltage of the control transistor equivalently gentle.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIGS. 1 to 10 relate to a high-frequency amplifier circuit device according to an embodiment (Embodiment 1) of the present invention. FIG. 1 is a circuit diagram of a high-frequency amplifier circuit device,
FIG. 2 is a plan view in which a part of the high-frequency amplifier circuit device is cut away.

In the first embodiment, the main body transistor and the control transistor are dual gate field effect transistors. The field effect transistor has, for example, a MOS structure. Note that the present invention can be similarly applied to a dual-gate field-effect transistor using a GaAs compound semiconductor.

The high-frequency amplifier circuit device 30 of the first embodiment
Has a structure in which two leads 32 project from each side of a package 31 made of a rectangular insulating resin. A lead 32 protruding from one side of the package 31 includes a gate 1 (G1) and a gate 2 (G2),
The lead 32 protruding from the other side is composed of a source (S) and a drain (D). The source lead has an inner end located at the center of the package 31 and forms a wide chip fixing portion 33. This chip fixing part 33
Is fixed to the semiconductor element 34. The wire bonding pad 35 (see FIG. 3) provided on the upper surface of the semiconductor element 34 and each lead 32 are electrically connected via a conductive wire 36.

The circuit shown in FIG. 1 is incorporated in the semiconductor element 34. This circuit comprises a body transistor Q1 composed of a dual gate field effect transistor.
A control transistor Q2 composed of a dual-gate field-effect transistor for controlling the gain of the body transistor Q1, two resistors R1 and R2, two diodes D1 and D2 having a back-to-back structure, It is composed of diodes D3 and D4 provided between the source and the drain of the control transistor Q2, respectively. The drain (D) is connected to a first reference potential (power supply potential Vcc), and the source (S) is connected to a second reference potential (ground).

The drain (D) of the body transistor Q1,
Source (S), Gate 1 (G1), Gate 2 (G2)
Are external terminals of the high-frequency amplifier circuit device 30. A diode D1 having a back-to-back structure is inserted and connected between the gate 1 (G1) and the source (S).
A diode D2 having a back-to-back structure is inserted and connected between 2) and the source (S). A diode D4 is inserted and connected between the drain (D) and the source (S) of the main body transistor Q1.

Gate 1 (G1) of control transistor Q2
Is connected to the gate 2 (G2) of the body transistor Q1, and the gate 2 (G2) of the control transistor Q2 is connected to the resistor R
1 is connected to the drain (D) of the control transistor Q2. A diode D5 is inserted and connected between the drain (D) and the source (S) of the control transistor Q2.

Also, this is one of the features of the present invention. The common portion 21 (see FIG. 4) of the transistor 1 (Tc1) and the transistor 2 (Tc2) of the control transistor Q2 having the dual gate structure is connected via the resistor R2. Connected to the gate 1 (G1) of the main body transistor Q1. The potential of the common portion 21 becomes VC.

In such a high-frequency amplifier circuit device 30,
The high frequency signal Rf is applied to the gate 1 (G1), and the AGC voltage is applied to the gate 2 (G2) to control the output of the main body transistor Q1.

Gate 2 (G2) of main body transistor Q1
Are connected to the gate 1 (G1) of the control transistor Q2, and the common portion of the control transistor Q2 is connected to the gate 1 (G1) of the main body transistor Q1.
When the AGC potential applied to the gate 2 (G2) of the main body transistor Q1 sequentially decreases, the control transistor Q
Since the voltage applied to the gate 1 (G1) of the second transistor G1 decreases, the current flowing through the control transistor Q2 decreases, and the potential of VC increases due to the voltage drop. As a result, a voltage is supplied to the gate 1 of the main body transistor Q1. That is, the main body transistor Q1 has the forward AGC function, and the distortion characteristics can be improved.

FIG. 10 is a graph showing the correlation between VG1 and VG2 in the high-frequency amplifier circuit device 30 according to the first embodiment. In the high-frequency amplifier circuit device composed of a single dual-gate field-effect transistor, the voltage VG1 of the gate 1 is initially high, but sharply decreases due to the increase of the voltage VG2 of the gate 2, as indicated by a curve shown as a conventional graph in the same graph. After that, the characteristic is constant, but in the case of the high-frequency amplifier circuit device 30 of the first embodiment, the voltage VG of the gate 1 is
1 shows a characteristic that decreases in proportion to an increase in the voltage VG2 of the gate 2. That is, according to the bias circuit according to the first embodiment, it is possible to achieve an improvement in distortion characteristics at the time of gain attenuation.

Next, the semiconductor device 3 according to the first embodiment will be described.
4 will be described. FIG. 3 is a plan view of the semiconductor device. FIG. 4 is a schematic cross-sectional view of a semiconductor device, in which each device (transistor, diode, resistor) is shown in the same cross section. FIG. 5 is a schematic diagram showing each electrode and the like of the control transistor.

Each element and wire bonding pad 35 are arranged on the semiconductor element 34 as shown in FIG. Drain, source, gate 1 and gate 2 wire bonding pads 35 are arranged at each corner of the rectangle. A diode D1 having a back-to-back structure is arranged between the gate 1 and the source, and a diode D2 having a back-to-back structure is arranged between the gate 1 and the gate 2. In the center, the main body transistor Q
1 is provided. The control transistor Q2 has a gate 2
Between the gate and the drain. Also,
A resistor R1 and a resistor R2 are provided between the gate 2 and the drain. The resistor R1 is laid out in parallel below the Al wiring.

FIG. 4 is a schematic sectional view of the semiconductor element 34. The semiconductor element 34 is formed based on a first conductivity type silicon substrate, for example, a p ⁺ type silicon substrate 1. That is, a p-type layer 2 is provided on the main surface of the silicon substrate 1, and an n-type layer or a p-type layer formed on the surface of the p-type layer 2 is formed.
The body transistor Q1, the control transistor Q2, the resistors R1, R2, and the diode D
1, D2, etc. are formed.

In FIG. 4, a diode D1, a main body transistor Q1, a control transistor Q2, and a resistor R1 having a back-to-back structure are incorporated from left to right. A gate insulating film 6 partially used as a gate insulating film is provided on the surface of the p-type layer 2. On the gate insulating film 6, a main body transistor Q
1 and a gate 1 (G1) electrode 8 and a gate 2 (G2) electrode 7 of the control transistor Q2.

The insulating film, the gate insulating film 6 and the gate 2
An interlayer insulating film 10 is provided so as to cover the (G2) electrode 7 and the gate 1 (G1) electrode 8. The interlayer insulating film 10 and the gate insulating film 6 are removed for leading out the electrodes of each element to form a contact portion. And
A wiring film 11 made of Al or the like formed on the interlayer insulating film 10 is filled in the contact portion, and a semiconductor region, a gate 2 (G2) electrode 7 and a gate 1 (G
1) It is electrically connected to the electrode 8.

The entire surface of the semiconductor element 34 is covered with a passivation film 12 made of an insulating film except for a portion to be a wire bonding pad 35. The wiring film 11 is exposed at the wire bonding pad 35 portion.

Back-to-back diode D1
As shown in the left end of FIG. 4, the n-type layer 3 provided on the surface of the p-type layer 2 and the center of the n-type layer 3 and the junction between the n-type layer 3 and the p-type layer 2 It is formed by the p ⁺ diffusion region 4 formed over the entire surface. This diode D1 is a back-to-back type diode having a pnp structure.

The main body transistor Q1 has three n-type regions 9 formed separately in the surface layer portion of the p-type layer 2 and a gate 2 () formed between the n-type regions 9 with a gate insulating film 6 interposed therebetween. G2) electrode 7 and gate 1 (G1) electrode 8. Further, the three n-type regions 9
In the n-type regions 9 at both ends, n ⁺ -type regions 5 are provided. One n ⁺ -type region 5 is connected to a source electrode, and the other n ⁺ -type region 5 is connected to a drain electrode. The source electrode and the drain electrode are connected to the wiring film 11.
Is formed by Thereby, transistor 1
A dual gate field effect transistor including (T1) and transistor 2 (T2) is configured.

The control transistor Q2 has the same configuration as the main body transistor Q1. That is, the control transistor Q2 includes three n-type regions 9 formed separately in the surface layer of the p-type layer 2 and a gate 2 (G2) formed between the n-type regions 9 with the gate insulating film 6 interposed therebetween. ) Electrode 7
And the gate 1 (G1) electrode 8. Further, n ⁺ -type regions 5 are provided in the n-type regions 9 at both ends of the three n-type regions 9. One n ⁺ -type region 5 is connected to a source electrode, and the other n ⁺ -type region 5 is connected to a drain electrode. The source electrode and the drain electrode are formed by the wiring film 11.
Thereby, transistor 1 (Tc1) and transistor 2
A dual gate field effect transistor made of (Tc2) is formed. The n ⁺ type region 5 between the transistor 1 (Tc1) and the transistor 2 (Tc2)
(Potential: VC). FIG. 5 is a schematic diagram showing a drawing pattern of the common portion 21 of the control transistor Q2.

The resistor R1 is formed by an n-type region 9 elongated in the surface layer of the p-type layer 2 and n ⁺ -type regions 5 formed at both ends of the n-type region 9. The wiring film 11 is connected on the n ⁺ type region 5. The resistor may be formed by forming the n ⁺ type region 5 to be elongated. Note that the n-type region 9 in the resistor R1 is displayed in black (the same applies hereinafter).

Next, a method for manufacturing the semiconductor element 34 will be described. As shown in FIG. 6, after preparing ap ⁺ -type silicon substrate 1, a p-type layer 2 is formed on the main surface of the silicon substrate 1. Thereafter, the entire surface of the p-type layer 2 has a thickness of 100 nm.
An insulating film 20 made of SiO ₂ is formed. Thereafter, n-type layer 3 and p ⁺ diffusion region 4 are formed by a photoresist method and an ion implantation method. 6 and subsequent figures, only a part of the cross section of the silicon substrate 1 is shown. That is, only a portion where one semiconductor element 34 is formed is shown.

Next, the insulating film 20 is removed. Next, as shown in FIG. 7, an n ⁺ -type region 5 is formed by conventional photolithography and ion implantation techniques, and a contact region of a source region and a drain region of the main body transistor Q1 and a source region and a drain region of the control transistor Q2 are formed. Area contact area and common part 2
1 and an electrode contact region of the resistor R1 and the like. Next, a gate insulating film 6 is formed on the main surface side of the silicon substrate 1 and a gate metal film is formed on the gate insulating film 6. The gate metal is patterned by a conventional technique (dry etching) to form the gate 1 (G1) electrode 8 and the gate 2 (G2) electrode 7 of the main body transistor Q1 and the control transistor Q2. Next, an n-type region 9 is formed using a photoresist film (not shown) and the gate 1 (G1) electrode 8 and the gate 2 (G2) electrode 7 as a mask.

Next, as shown in FIG. 8, the gate 2 (G
2) An interlayer insulating film 10 is formed on the gate insulating film 6 so as to cover the electrode 7 and the gate 1 (G1) electrode 8. Thereafter, the interlayer insulating film 10 and the gate insulating film 6 are selectively removed by etching to form a contact portion (contact region).
25 are formed.

Next, as shown in FIG.
Is formed on the main surface side of the silicon substrate 1. Each wiring film 11 is in electrical contact with an electrode or a semiconductor region at a contact portion of each element. Next, as shown in FIG. 9, a passivation film 12 made of an insulating film is selectively provided on the main surface side of the silicon substrate 1. At this time, although not shown, the wire bonding pad 35 is exposed from the passivation film 12 (see FIG. 3). Next, by dividing the silicon substrate 1, the semiconductor element 34 shown in FIG.
To manufacture.

According to the first embodiment, the following effects are obtained. (1) The gate 1 of the main body transistor Q1 is connected to the common part (VC) of the transistor 1 (Tc1) and the transistor 2 (Tc2) in the control transistor Q2 via the resistor 2, and the gate 2 of the main body transistor Q1 is Since it is connected to the gate 1 of the control transistor Q2, the AGC is connected to the gate 2 of the main body transistor Q1.
When the potential is applied, the current flowing through the control transistor Q2 decreases with the decrease in the AGC potential, so that the potential VC of the common portion 21 increases due to the voltage drop, and as a result, the voltage is applied to the gate 1 of the main body transistor Q1. Will be supplied. For example, during AGC control, when VG2 is changed from 4V to 0V, the VG1 potential automatically increases from the initial voltage to the power supply voltage.

As described above, according to the first embodiment, the AGC
The gate 1 of the control transistor Q2 is proportional to the decrease in the potential.
, The distortion characteristics at the time of gain attenuation can be improved. Also, lower voltage can be achieved. The high-frequency amplifier circuit device 30 according to the first embodiment includes a TV,
This is effective when used as a high-frequency amplifier circuit having an AGC function for a tuner such as a VTR.

(Embodiment 2) FIG. 11 is a circuit diagram of a high-frequency amplifier circuit device according to another embodiment (Embodiment 2) of the present invention. In the high-frequency amplifier circuit device 30 according to the second embodiment,
As shown in FIG. 11, the gate 2 of the control transistor Q2
Is used as a bleeder (voltage division) via the resistor R3, so that the maximum voltage of the potential VC output from the common portion 21 can be limited. Also, the control transistor Q
It is also possible to set a maximum voltage proportional to the voltage applied to the second gate 2. As a result, the distortion characteristics can be improved by setting the optimum VC.

(Embodiment 3) FIG. 12 is a circuit diagram of a high-frequency amplifier circuit device according to another embodiment (Embodiment 3) of the present invention, and FIG. 13 is a graph showing a correlation between potentials VC and VG2 of a common portion. is there. High-frequency amplifier circuit device 3 of the third embodiment
At 0, as shown in FIG. 12, since the gate 1 of the control transistor Q2 is used as a bleeder using the resistors R4 and R5, the minimum voltage region of the potential (VC) output from the common portion 21 is Can be minimized. When the gate 1 voltage increases, the VC voltage decreases and the body FET
Inconvenience occurs because channel 1 is closed more than necessary. Therefore, it is also possible to adjust the gate 1 voltage of the control transistor Q2 by resistance division. Further, by dividing the AGC supply voltage of the main body transistor Q1 by resistance, it is possible to make the change equivalently gentle as shown in FIG. In FIG. 13, a curve in which a triangle mark is plotted is a characteristic of a high-frequency amplifier circuit device using a single dual-gate field-effect transistor.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

[0040]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) In a high-frequency amplifier circuit device in which gain is controlled by a control transistor composed of a dual-gate field-effect transistor for a main transistor composed of a dual-gate field-effect transistor, the gate 1 of the main transistor is composed of a control transistor and a transistor. Connected to the common part of the two via a resistor,
Since the gate 2 of the main body transistor is connected to the gate 1 of the control transistor, when the AGC potential is applied to the gate 2 of the main body transistor, the current flowing through the control transistor decreases as the AGC potential decreases. Due to the voltage drop, the potential (VC) of the common portion rises, and as a result, a voltage is supplied to the gate 1 of the body transistor. Since the voltage of the gate 1 of the control transistor decreases in proportion to the decrease of the AGC potential, it is possible to achieve an improvement in the distortion characteristic at the time of gain attenuation.
Low voltage can also be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-frequency amplifier circuit device according to an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a plan view in which a part of the high-frequency amplifier circuit device according to the first embodiment is cut away.

FIG. 3 is a plan view of a semiconductor element in the high-frequency amplifier circuit device according to the first embodiment.

FIG. 4 is a schematic sectional view of the semiconductor element.

FIG. 5 is a schematic diagram showing electrodes and the like of a control transistor in the semiconductor element.

FIG. 6 is a schematic cross-sectional view showing a state in which an n-type layer or ap ⁺ diffusion region is provided in a part of a p-type layer provided on a main surface of a silicon substrate in manufacturing the semiconductor element.

FIG. 7 is a cross-sectional view showing an n ⁺ type region,
FIG. 3 is a schematic cross-sectional view showing a state where a gate insulating film, an n-type region, a gate 1 (G1) electrode, and a gate 2 (G2) electrode are provided.

FIG. 8 is a schematic cross-sectional view showing a state in which a gate insulating film and an interlayer insulating film are provided on the main surface side of the silicon substrate and a contact portion 25 is formed in the manufacture of the semiconductor element.

FIG. 9 is a schematic cross-sectional view showing a state in which a wiring film is provided and a passivation film is formed in the manufacture of the semiconductor element.

FIG. 10 shows V of the high-frequency amplifier circuit device according to the first embodiment.
It is a graph which shows the correlation of G1 and VG2.

FIG. 11 is a circuit diagram of a high-frequency amplifier circuit device according to another embodiment (Embodiment 2) of the present invention.

FIG. 12 is a circuit diagram of a high-frequency amplifier circuit device according to another embodiment (Embodiment 3) of the present invention.

FIG. 13 is a graph showing a correlation between potentials VC and VG2 of a common portion of the high-frequency amplifier circuit device according to the third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... p-type layer, 3 ... n-type layer, 4 ... p ⁺
Diffusion region, 5 ... n ⁺ type region, 6 ... Gate insulating film, 7 ... Gate 2 (G2) electrode, 8 ... Gate 1 (G1) electrode, 9 ...
n-type region, 10 interlayer insulating film, 11 wiring film, 12 passivation film, 20 insulating film, 21 common part, 2
5 ... contact part, 30 ... high frequency amplifier circuit device, 31 ...
Package, 32: Lead, 33: Chip fixing part, 34
... Semiconductor element, 35 ... Wire bonding pad, 36
... wires, D1, D2, D4, D5 ... diodes, Q1
... body transistor, Q2 ... control transistor, R1
R5: resistance.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03F 3/195 (72) Inventor Akira Masuda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Co., Ltd. F-term in Hitachi Semiconductor Business Unit (reference) AA19 BA02 BB03 BB04 BB07 CA02 CA03 CA05 CA20 FA01 JA01 QA04 SA01

Claims (5)

[Claims] 1. A high-frequency amplifier circuit device comprising: a main body transistor constituted by a dual gate field effect transistor; and a control transistor constituted by a dual gate field effect transistor for controlling a gain of the body transistor. The gate 2 of the transistor is connected to the gate 1 of the control transistor, and the transistor 1 and the transistor 2 in the control transistor are connected.
Characterized in that the common part is connected to the gate 1 of the main body transistor via a resistor. 2. A high-frequency amplifier circuit device comprising: a main body transistor constituted by a dual-gate field-effect transistor; and a control transistor constituted by a dual-gate field-effect transistor for controlling a gain of the body transistor. The drain terminals of the transistor and the control transistor are connected to a first reference potential,
The source terminals of the main body transistor and the control transistor are connected to a second reference potential, and the gate 1 of the main body transistor is connected to the second reference potential via a back-to-back diode and the resistance of the main body transistor is connected via a resistor. Transistor 1 and transistor 2
And a gate 2 of the main body transistor is connected to a second reference potential via a back-to-back diode and connected to a gate 1 of the control transistor, and a drain terminal of the control transistor is connected to a control transistor. A high-frequency amplifier circuit device, wherein the diode is connected between the drain terminal and the source terminal of the main body transistor. 3. The high-frequency amplifier circuit device according to claim 1, wherein the gate, the gate, the drain, and the source of the main body transistor are external terminals, respectively. 4. The high-frequency amplifier circuit according to claim 1, wherein a bleeder resistor is connected between the gate 2 of the control transistor and the source terminal of the control transistor. apparatus. 5. A resistor is provided between the gate 1 of the control transistor and the gate 2 of the body transistor and between the gate 1 of the control transistor and the source terminal of the control transistor. Item 4. The high-frequency amplifier circuit device according to any one of items 3.