JP2000201031A - Light receiving circuit - Google Patents
Light receiving circuitInfo
- Publication number
- JP2000201031A JP2000201031A JP11001645A JP164599A JP2000201031A JP 2000201031 A JP2000201031 A JP 2000201031A JP 11001645 A JP11001645 A JP 11001645A JP 164599 A JP164599 A JP 164599A JP 2000201031 A JP2000201031 A JP 2000201031A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ternary
- apd
- reverse bias
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Light Receiving Elements (AREA)
- Amplifiers (AREA)
- Optical Communication System (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、光受信回路に係
り、特に３元ＡＰＤを受光素子とする光受信回路に関す
るものである。The present invention relates to an optical receiving circuit, and more particularly to an optical receiving circuit using a ternary APD as a light receiving element.
【０００２】[0002]
【従来の技術】従来より、光受信回路の受光素子とし
て、ＧａＩｎＡｓアバランシェフォトダイオード（以
下、３元ＡＰＤという）が知られている。図２に、この
３元ＡＰＤの逆バイアス電圧Ｖと増倍率Ｍとの関係を示
し、図３に、３元ＡＰＤの増倍率Ｍと帯域との関係を示
す。３元ＡＰＤは、ＳｉＡＰＤ等と比べて暗電流が小さ
いという特徴を有しているが、図２のように増倍率Ｍが
温度によって大きく変動し、また図３のように増倍率Ｍ
がＭｍｉｎを下回ると、その帯域が急激に劣化するとい
う欠点をもっている。2. Description of the Related Art Conventionally, a GaInAs avalanche photodiode (hereinafter, referred to as a ternary APD) has been known as a light receiving element of an optical receiving circuit. FIG. 2 shows the relationship between the reverse bias voltage V and the multiplication factor M of the ternary APD, and FIG. 3 shows the relationship between the multiplication factor M and the band of the ternary APD. The ternary APD has a feature that the dark current is smaller than that of a Si APD or the like. However, as shown in FIG. 2, the multiplication factor M greatly varies depending on the temperature, and as shown in FIG.
Is below Mmin, the band is rapidly deteriorated.
【０００３】そこで、従来の光受信回路では、このよう
な３元ＡＰＤの欠点を以下のようにして克服していた。
図４は、特開平５−１０２７４４号公報に開示された、
従来の光受信回路のブロック図である。図４の光受信回
路は、光信号を光電変換して電流信号を出力する３元Ａ
ＰＤ２１と、光電流を電圧信号に変換する前置増幅回路
２２と、その出力を等価増幅する等化増幅回路２３と、
等化増幅回路２３の出力信号の高周波成分を取り出すハ
イパスフィルタ２４と、ハイパスフィルタ２４で取り出
した高周波成分の振幅ピーク値を検出するピーク検出回
路２５と、３元ＡＰＤ２１の受光電力に応じて逆バイア
ス電圧を決定する逆バイアス制御回路２６と、逆バイア
ス制御回路２６の制御に従って３元ＡＰＤ２１に逆バイ
アス電圧を印加する逆バイアス印加回路２７とを有して
いる。Therefore, the conventional optical receiving circuit overcomes such a disadvantage of the ternary APD as follows.
FIG. 4 is disclosed in JP-A-5-102744.
FIG. 11 is a block diagram of a conventional optical receiving circuit. The optical receiving circuit shown in FIG.
A PD 21, a preamplifier circuit 22 for converting a photocurrent into a voltage signal, an equalizing amplifier circuit 23 for equivalently amplifying the output thereof,
A high-pass filter 24 for extracting a high-frequency component of the output signal of the equalizing amplifier 23, a peak detection circuit 25 for detecting the amplitude peak value of the high-frequency component extracted by the high-pass filter 24, and a reverse bias according to the received light power of the ternary APD 21. It has a reverse bias control circuit 26 that determines a voltage, and a reverse bias application circuit 27 that applies a reverse bias voltage to the ternary APD 21 under the control of the reverse bias control circuit 26.
【０００４】逆バイアス制御回路２６は、通常、３元Ａ
ＰＤ２１の受光電力が大きくなるに従って、３元ＡＰＤ
２１の増倍率Ｍを下げるように、つまり３元ＡＰＤ２１
に印加する逆バイアス電圧を下げるように動作する。こ
のとき、増倍率Ｍを低下させる制御によって増倍率Ｍが
Ｍｍｉｎより小さくなると、等化増幅回路２３の出力信
号のうち高周波成分が低下し、帯域不足となる。図４の
光受信回路の出力信号、すなわち等化増幅回路２３の出
力信号をアイパターンで観測すると、増倍率ＭがＭｍｉ
ｎ〜Ｍｍａｘの範囲にあれば、図５（ａ）のようにアイ
は十分に開く。これに対し、増倍率ＭがＭｍｉｎより小
さくなると、帯域不足のために図５（ｂ）のようにアイ
が閉じる。The reverse bias control circuit 26 usually has a three-way A
As the light receiving power of the PD 21 increases, the ternary APD
21 to reduce the multiplication factor M, that is, the three-way APD 21
Operates to reduce the reverse bias voltage applied to. At this time, if the multiplication factor M becomes smaller than Mmin by the control for decreasing the multiplication factor M, the high-frequency component of the output signal of the equalization amplifier circuit 23 is reduced, and the band becomes insufficient. When the output signal of the optical receiving circuit in FIG. 4, that is, the output signal of the equalizing amplifier 23 is observed in an eye pattern, the multiplication factor M is Mmi.
If it is in the range of n to Mmax, the eye is sufficiently opened as shown in FIG. On the other hand, when the multiplication factor M is smaller than Mmin, the eye closes as shown in FIG.
【０００５】そこで、図４の光受信回路では、ハイパス
フィルタ２４によって等化増幅回路２３の出力信号の高
周波成分を取り出し、ピーク検出回路２５で高周波成分
の振幅ピーク値を検出する。そして、逆バイアス制御回
路２６は、このピーク検出回路２５によって検出された
ピーク値が所定のしきい値以下になると、３元ＡＰＤ２
１の増倍率Ｍを上げるように、つまり３元ＡＰＤ２１に
印加する逆バイアス電圧を上げるように動作する。こう
して、図４の光受信回路では、増倍率ＭがＭｍｉｎを下
回ることによる帯域の急激な劣化を防止して、図５
（ｂ）のようにアイが閉じることを防止している。In the optical receiving circuit shown in FIG. 4, a high-pass filter 24 extracts a high-frequency component of the output signal of the equalizing amplifier 23, and a peak detecting circuit 25 detects an amplitude peak value of the high-frequency component. When the peak value detected by the peak detection circuit 25 falls below a predetermined threshold value, the reverse bias control circuit 26 outputs the ternary APD2.
The operation is performed so as to increase the multiplication factor M of 1, that is, to increase the reverse bias voltage applied to the ternary APD 21. In this way, the optical receiving circuit of FIG. 4 prevents the band from abruptly deteriorating due to the multiplication factor M falling below Mmin.
The eye is prevented from closing as shown in FIG.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
光受信回路では、受光電力が大きくなったときに、増倍
率ＭをＭｍｉｎより大きくするために、３元ＡＰＤ２１
に過大な電流が流れることがあり、３元ＡＰＤ２１の劣
化を早めてしまうという問題点があった。また、経年変
化により３元ＡＰＤ２１が特性劣化して受光電力が低下
した場合にも、ダイナミックレンジを確保しようとして
増倍率Ｍを上げるため、３元ＡＰＤ２１の劣化をさらに
早めてしまうという問題点があった。また、３元ＡＰＤ
２１の増倍率Ｍは、図２のように温度によって大きく変
動する。しかし、従来の光受信回路では、このような温
度特性を考慮していないため、３元ＡＰＤ２１の増倍率
Ｍを最適値に設定できず、光受信回路の出力信号振幅が
不足することがあるという問題点があった。本発明は、
上記課題を解決するためになされたもので、３元ＡＰＤ
の増倍率を最適値に設定することができる光受信回路を
提供することを目的とする。However, in the conventional optical receiving circuit, when the received light power becomes large, the ternary APD 21 is used in order to make the multiplication factor M larger than Mmin.
However, there is a problem that an excessive current may flow through the APD 21 and the deterioration of the ternary APD 21 is accelerated. Further, even when the ternary APD 21 deteriorates in characteristics due to aging and the received light power decreases, the multiplication factor M is increased in order to secure a dynamic range, and the ternary APD 21 is further deteriorated. Was. In addition, three yuan APD
The multiplication factor M of 21 greatly varies depending on the temperature as shown in FIG. However, since such a temperature characteristic is not taken into consideration in the conventional optical receiving circuit, the multiplication factor M of the ternary APD 21 cannot be set to an optimum value, and the output signal amplitude of the optical receiving circuit may be insufficient. There was a problem. The present invention
It was made to solve the above-mentioned problems, and it is a three-way APD
It is an object of the present invention to provide an optical receiving circuit capable of setting the multiplication factor of the optical receiver to an optimum value.
【０００７】[0007]
【課題を解決するための手段】本発明の光受信回路は、
３元ＡＰＤ（１）の光電流を電圧信号に変換する前置増
幅回路（２）と、前置増幅回路の出力信号を増幅するＡ
ＧＣ増幅回路（３）と、前置増幅回路の出力信号の高周
波成分を取り出すハイパスフィルタ（４）と、この高周
波成分の振幅ピーク値を検出するピーク検出回路（５）
と、３元ＡＰＤの温度を検出する温度検出回路（８）
と、３元ＡＰＤの逆バイアス電圧と増倍率との関係を各
温度ごとに記憶したメモリ（９）と、温度検出回路で検
出された３元ＡＰＤの温度に対応する逆バイアス電圧と
増倍率との関係をメモリから読み出し、この関係と３元
ＡＰＤの受光電力とピーク検出回路で検出された振幅ピ
ーク値に基づいて、３元ＡＰＤの逆バイアス電圧を決定
する逆バイアス制御回路（６）と、逆バイアス制御回路
で決定された逆バイアス電圧を３元ＡＰＤに印加する逆
バイアス印加回路（７）とを有するものである。An optical receiving circuit according to the present invention comprises:
A preamplifier circuit (2) for converting a photocurrent of the ternary APD (1) into a voltage signal, and an A for amplifying an output signal of the preamplifier circuit
GC amplifier circuit (3), high-pass filter (4) for extracting high-frequency components of the output signal of the preamplifier circuit, and peak detection circuit (5) for detecting the amplitude peak value of the high-frequency components
And a temperature detection circuit (8) for detecting the temperature of the ternary APD
And a memory (9) storing the relationship between the reverse bias voltage and the multiplication factor of the ternary APD for each temperature, and the reverse bias voltage and the multiplication factor corresponding to the temperature of the ternary APD detected by the temperature detection circuit. A reverse bias control circuit (6) for reading out the relationship from the memory, determining the reverse bias voltage of the ternary APD based on the relationship, the received light power of the ternary APD, and the amplitude peak value detected by the peak detection circuit; A reverse bias application circuit (7) for applying the reverse bias voltage determined by the reverse bias control circuit to the ternary APD.
【０００８】また、上記ＡＧＣ増幅回路（３）の出力信
号からクロック成分を抽出するクロック抽出回路（１
０）と、このクロック成分のレベルを検出するレベル検
出回路（１１）と、上記ＡＧＣ増幅回路の出力信号を一
定振幅にするために、レベル検出回路で検出されたクロ
ック成分のレベルを所定のしきい値と比較して、ＡＧＣ
増幅回路の利得を制御する比較回路（１２）とを有する
ものである。A clock extracting circuit (1) for extracting a clock component from an output signal of the AGC amplifier (3).
0), a level detecting circuit (11) for detecting the level of the clock component, and a predetermined level for the clock component detected by the level detecting circuit in order to make the output signal of the AGC amplifier circuit have a constant amplitude. AGC compared to the threshold
A comparison circuit (12) for controlling the gain of the amplifier circuit.
【０００９】[0009]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。図１は本発明の実施
の形態を示す光受信回路のブロック図である。本実施の
形態の光受信回路は、光信号を光電変換して電流信号を
出力する３元ＡＰＤ１と、３元ＡＰＤ１の光電流を電圧
信号に変換する前置増幅回路２と、前置増幅回路２の出
力信号を増幅するＡＧＣ増幅回路３と、前置増幅回路２
の出力信号の高周波成分を取り出すハイパスフィルタ４
と、ハイパスフィルタ４で取り出した高周波成分の振幅
ピーク値を検出するピーク検出回路５と、３元ＡＰＤ１
の現在の温度に対応する逆バイアス電圧と増倍率との関
係を後述するＲＯＭから読み出し、この関係と３元ＡＰ
Ｄ１の受光電力と後述する振幅ピーク値に基づいて、３
元ＡＰＤ１の逆バイアス電圧を決定する逆バイアス制御
回路６と、逆バイアス制御回路６の制御に従って３元Ａ
ＰＤ１に逆バイアス電圧を印加する逆バイアス印加回路
７と、３元ＡＰＤ１の温度を検出する温度検出回路８
と、３元ＡＰＤ１の逆バイアス電圧Ｖと増倍率Ｍとの関
係（以下、Ｖ−Ｍ特性と呼ぶ）を各温度ごとに記憶した
ＲＯＭ９と、ＡＧＣ増幅回路３の出力信号からクロック
成分を抽出するクロック抽出回路１０と、このクロック
成分のレベルを検出するレベル検出回路１１と、レベル
検出回路１１で検出されたクロック成分のレベルを所定
のしきい値Ｖｔｈと比較し、ＡＧＣ増幅回路３の利得を
制御する比較回路１２とを有している。Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an optical receiving circuit showing an embodiment of the present invention. The optical receiving circuit according to the present embodiment includes a ternary APD 1 that photoelectrically converts an optical signal and outputs a current signal, a preamplifier circuit 2 that converts a photocurrent of the ternary APD 1 into a voltage signal, and a preamplifier circuit. AGC amplifier circuit 3 for amplifying the output signal from
High-pass filter 4 for extracting the high-frequency component of the output signal of
A peak detection circuit 5 for detecting the amplitude peak value of the high-frequency component extracted by the high-pass filter 4;
The relationship between the reverse bias voltage corresponding to the current temperature and the multiplication factor is read from a ROM described later, and this relationship and the three-dimensional AP
Based on the received light power of D1 and the amplitude peak value described later, 3
A reverse bias control circuit 6 for determining a reverse bias voltage of the original APD 1;
Reverse bias application circuit 7 for applying a reverse bias voltage to PD 1 and temperature detection circuit 8 for detecting the temperature of ternary APD 1
And a ROM 9 storing the relationship between the reverse bias voltage V of the ternary APD 1 and the multiplication factor M (hereinafter referred to as VM characteristics) for each temperature, and extracting a clock component from the output signal of the AGC amplifier circuit 3. A clock extraction circuit 10, a level detection circuit 11 for detecting the level of the clock component, and a level of the clock component detected by the level detection circuit 11 are compared with a predetermined threshold value Vth, and the gain of the AGC amplification circuit 3 is adjusted. And a comparison circuit 12 for controlling.
【００１０】次に、本実施の形態の光受信回路の動作に
ついて説明する。入力された光信号は、３元ＡＰＤ１に
よって光電流信号に変換される。３元ＡＰＤ１から出力
された光電流信号は、前置増幅回路２によって増幅され
電圧信号に変換される。逆バイアス印加回路７は、逆バ
イアス制御回路６の制御に従って３元ＡＰＤ１に逆バイ
アス電圧を印加する。Next, the operation of the optical receiving circuit according to the present embodiment will be described. The input optical signal is converted by the ternary APD 1 into a photocurrent signal. The photocurrent signal output from the ternary APD 1 is amplified by the preamplifier circuit 2 and converted into a voltage signal. The reverse bias application circuit 7 applies a reverse bias voltage to the ternary APD 1 under the control of the reverse bias control circuit 6.
【００１１】逆バイアス制御回路６は、通常、３元ＡＰ
Ｄ１の受光電力が大きくなるに従って、３元ＡＰＤ１の
増倍率Ｍを下げるように、つまり３元ＡＰＤ１に印加す
る逆バイアス電圧を下げるように動作する。こうして、
光受信回路の出力信号レベル（ＡＧＣ増幅回路３の出力
信号レベル）が一定となるように逆バイアス印加回路７
を制御している。The reverse bias control circuit 6 usually has a three-way AP
As the light receiving power of D1 increases, the multiplication factor M of the ternary APD 1 is reduced, that is, the reverse bias voltage applied to the ternary APD 1 is reduced. Thus,
The reverse bias applying circuit 7 is controlled so that the output signal level of the optical receiving circuit (the output signal level of the AGC amplifier circuit 3) becomes constant.
Is controlling.
【００１２】このとき、増倍率Ｍを低下させる制御によ
って増倍率ＭがＭｍｉｎより小さくなると、前置増幅回
路２の出力信号のうち高周波成分が低下し、図５（ｂ）
のようにアイが閉じて帯域不足となる。本実施の形態で
は、このような帯域の劣化を防止するために、ハイパス
フィルタ４によって前置増幅回路２の出力信号の高周波
成分を取り出し、ピーク検出回路５で高周波成分の振幅
ピーク値を検出する。At this time, when the multiplication factor M is smaller than Mmin by the control for decreasing the multiplication factor M, the high-frequency component of the output signal of the preamplifier circuit 2 is reduced, and FIG.
The eye closes and the band becomes insufficient. In the present embodiment, in order to prevent such band degradation, the high-pass filter 4 extracts the high-frequency component of the output signal of the preamplifier circuit 2, and the peak detection circuit 5 detects the amplitude peak value of the high-frequency component. .
【００１３】そして、逆バイアス制御回路６は、このピ
ーク検出回路５によって検出されたピーク値が所定のし
きい値以下になると、３元ＡＰＤ１の増倍率Ｍを上げる
ように、つまり３元ＡＰＤ１に印加する逆バイアス電圧
を上げるように逆バイアス印加回路７を制御する。この
ようにして、増倍率ＭがＭｍｉｎを下回ることによる帯
域の急激な劣化を防止し、図５（ｂ）のようにアイが閉
じることを防止している。When the peak value detected by the peak detection circuit 5 falls below a predetermined threshold value, the reverse bias control circuit 6 increases the multiplication factor M of the ternary APD 1, ie, the ternary APD 1 The reverse bias applying circuit 7 is controlled so as to increase the applied reverse bias voltage. In this way, rapid deterioration of the band due to the multiplication factor M falling below Mmin is prevented, and the eyes are prevented from closing as shown in FIG. 5B.
【００１４】ただし、３元ＡＰＤ１の増倍率Ｍは、図２
のように温度によって大きく変動するため、このような
温度特性を考慮しないと、以上のような制御を適切に行
うことができなくなる。そこで、逆バイアス制御回路６
は、温度検出回路８で検出された３元ＡＰＤ１の現在の
温度に対応するＶ−Ｍ特性をＲＯＭ９から読み出す。そ
して、逆バイアス制御回路６は、このＶ−Ｍ特性に基づ
いて前述のように逆バイアス電圧を決定する。こうし
て、３元ＡＰＤ１の増倍率Ｍを最適値に設定することが
できる。なお、上記Ｖ−Ｍ特性は、使用する個々の３元
ＡＰＤ１に応じてＲＯＭ９に書き込まれる。However, the multiplication factor M of the three-way APD 1 is shown in FIG.
As described above, the above-described control cannot be performed properly unless such temperature characteristics are taken into account. Therefore, the reverse bias control circuit 6
Reads from the ROM 9 the VM characteristic corresponding to the current temperature of the ternary APD 1 detected by the temperature detection circuit 8. Then, the reverse bias control circuit 6 determines the reverse bias voltage based on the VM characteristics as described above. Thus, the multiplication factor M of the three-way APD 1 can be set to an optimum value. The above-mentioned VM characteristics are written in the ROM 9 according to each ternary APD 1 to be used.
【００１５】また、本実施の形態では、図４の等化増幅
回路２３と同等の機能をもつＡＧＣ増幅回路３の出力信
号からクロック成分を抽出するクロック抽出回路１０
と、このクロック成分のレベルを検出するレベル検出回
路１１と、レベル検出回路１１で検出されたクロック成
分のレベルを所定のしきい値Ｖｔｈと比較し、ＡＧＣ増
幅回路３の利得を制御する比較回路１２とを設けること
により、光受信回路の出力（ＡＧＣ増幅回路３の出力）
で一定振幅の信号が得られるようにした。Further, in this embodiment, a clock extraction circuit 10 for extracting a clock component from an output signal of an AGC amplification circuit 3 having the same function as that of the equalization amplification circuit 23 of FIG.
A level detecting circuit 11 for detecting the level of the clock component; a comparing circuit for comparing the level of the clock component detected by the level detecting circuit 11 with a predetermined threshold Vth to control the gain of the AGC amplifier circuit 3 12, the output of the optical receiving circuit (the output of the AGC amplifier circuit 3)
And a signal of a constant amplitude was obtained.
【００１６】[0016]
【発明の効果】本発明によれば、個々の３元ＡＰＤの特
性をメモリに書き込むため、３元ＡＰＤのばらつきを考
慮する必要がなくなり、３元ＡＰＤの温度が変動したと
しても、３元ＡＰＤの増倍率を最適値に設定することが
できる。その結果、３元ＡＰＤの劣化を早めることがな
くなる。According to the present invention, since the characteristics of the individual ternary APDs are written in the memory, there is no need to consider the variance of the ternary APDs. Can be set to an optimum value. As a result, the deterioration of the ternary APD is not accelerated.
【００１７】また、クロック抽出回路、レベル検出回
路、レベル検出回路及び比較回路を設けることにより、
光受信回路（ＡＧＣ増幅回路）の出力信号を一定振幅に
することができるので、出力信号振幅の不足を防止する
ことができる。また、３元ＡＰＤの特性が経年変化した
場合でも、電気で増幅してダイナミックレンジを一定と
するため、３元ＡＰＤの劣化を防止する効果を有する。Further, by providing a clock extracting circuit, a level detecting circuit, a level detecting circuit and a comparing circuit,
Since the output signal of the optical receiving circuit (AGC amplifier circuit) can have a constant amplitude, shortage of the output signal amplitude can be prevented. Further, even if the characteristics of the ternary APD change over time, the ternary APD is amplified by electricity to keep the dynamic range constant, and thus has the effect of preventing the ternary APD from deteriorating.
【図１】 本発明の実施の形態を示す光受信回路のブロ
ック図である。FIG. 1 is a block diagram of an optical receiving circuit showing an embodiment of the present invention.
【図２】 ３元ＡＰＤの逆バイアス電圧と増倍率との関
係を示す図である。FIG. 2 is a diagram illustrating a relationship between a reverse bias voltage and a multiplication factor of a ternary APD.
【図３】 ３元ＡＰＤの増倍率と帯域との関係を示す図
である。FIG. 3 is a diagram illustrating a relationship between a multiplication factor and a band of a ternary APD.
【図４】 従来の光受信回路のブロック図である。FIG. 4 is a block diagram of a conventional optical receiving circuit.
【図５】 光受信回路の出力信号のアイパターンを示す
図である。FIG. 5 is a diagram showing an eye pattern of an output signal of the optical receiving circuit.
１…３元ＡＰＤ、２…前置増幅回路、３…ＡＧＣ増幅回
路、４…ハイパスフィルタ、５…ピーク検出回路、６…
逆バイアス制御回路、７…逆バイアス印加回路、８…温
度検出回路、９…ＲＯＭ、１０…クロック抽出回路、１
１…レベル検出回路、１２…比較回路。DESCRIPTION OF SYMBOLS 1 ... Three-way APD, 2 ... Preamplifier circuit, 3 ... AGC amplifier circuit, 4 ... High-pass filter, 5 ... Peak detection circuit, 6 ...
Reverse bias control circuit, 7 reverse bias application circuit, 8 temperature detection circuit, 9 ROM, 10 clock extraction circuit, 1
1 ... Level detection circuit, 12 ... Comparison circuit.
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０４Ｂ 10/14 10/04 10/06 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (reference) H04B 10/14 10/04 10/06
Claims (2)
において、 ３元ＡＰＤの光電流を電圧信号に変換する前置増幅回路
と、 前置増幅回路の出力信号を増幅するＡＧＣ増幅回路と、 前置増幅回路の出力信号の高周波成分を取り出すハイパ
スフィルタと、 この高周波成分の振幅ピーク値を検出するピーク検出回
路と、 ３元ＡＰＤの温度を検出する温度検出回路と、 ３元ＡＰＤの逆バイアス電圧と増倍率との関係を各温度
ごとに記憶したメモリと、 温度検出回路で検出された３元ＡＰＤの温度に対応する
逆バイアス電圧と増倍率との関係をメモリから読み出
し、この関係と３元ＡＰＤの受光電力とピーク検出回路
で検出された振幅ピーク値に基づいて、３元ＡＰＤの逆
バイアス電圧を決定する逆バイアス制御回路と、 逆バイアス制御回路で決定された逆バイアス電圧を３元
ＡＰＤに印加する逆バイアス印加回路とを有することを
特徴とする光受信回路。1. An optical receiving circuit using a ternary APD as a light receiving element, comprising: a preamplifier circuit for converting a photocurrent of the ternary APD into a voltage signal; and an AGC amplifier circuit for amplifying an output signal of the preamplifier circuit. A high-pass filter for extracting a high-frequency component of an output signal of the preamplifier circuit; a peak detection circuit for detecting an amplitude peak value of the high-frequency component; a temperature detection circuit for detecting a temperature of the ternary APD; A memory in which the relationship between the bias voltage and the multiplication factor is stored for each temperature, and a relationship between the reverse bias voltage and the multiplication factor corresponding to the temperature of the ternary APD detected by the temperature detection circuit are read from the memory. A reverse bias control circuit that determines a reverse bias voltage of the ternary APD based on the received light power of the ternary APD and the amplitude peak value detected by the peak detection circuit; Optical receiving circuit; and a reverse bias applying circuit for applying a constant inverse bias voltage to the ternary APD.
するクロック抽出回路と、 このクロック成分のレベルを検出するレベル検出回路
と、 前記ＡＧＣ増幅回路の出力信号を一定振幅にするため
に、レベル検出回路で検出されたクロック成分のレベル
を所定のしきい値と比較して、ＡＧＣ増幅回路の利得を
制御する比較回路とを有することを特徴とする光受信回
路。2. The optical reception circuit according to claim 1, wherein a clock extraction circuit extracts a clock component from an output signal of the AGC amplification circuit, a level detection circuit that detects a level of the clock component, and the AGC amplification circuit. And a comparator circuit for controlling the gain of the AGC amplifier circuit by comparing the level of the clock component detected by the level detection circuit with a predetermined threshold value in order to make the output signal of the AGC amplifier have a constant amplitude. Light receiving circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001645A JP2000201031A (en) | 1999-01-07 | 1999-01-07 | Light receiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001645A JP2000201031A (en) | 1999-01-07 | 1999-01-07 | Light receiving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000201031A true JP2000201031A (en) | 2000-07-18 |
Family
ID=11507268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11001645A Pending JP2000201031A (en) | 1999-01-07 | 1999-01-07 | Light receiving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000201031A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002084235A (en) * | 2000-09-07 | 2002-03-22 | Fujitsu Ltd | Apd bias voltage control circuit |
| US7332702B2 (en) | 2002-08-05 | 2008-02-19 | Sumitomo Electric Industries, Ltd. | Optical receiver and a method for manufacturing the same |
| US7792434B2 (en) | 2005-09-07 | 2010-09-07 | Sumitomo Electric Industries, Ltd. | Optical receiver |
| WO2012104448A1 (en) * | 2011-01-31 | 2012-08-09 | Universidad De Malaga | Laser receiving apparatus based on an avalanche photodiode thermally regulated with embedded control |
| JP2013016638A (en) * | 2011-07-04 | 2013-01-24 | Hamamatsu Photonics Kk | Photodiode array module |
| JP2015177148A (en) * | 2014-03-18 | 2015-10-05 | 株式会社東芝 | Photodetector |
| JP2016516179A (en) * | 2013-02-22 | 2016-06-02 | アレヴァ・エヌセーＡｒｅｖａ Ｎｃ | Method for controlling the gain and zero of a multi-pixel photon counter device, and an optical measurement system implementing the method |
| CN104871456B (en) * | 2012-10-29 | 2017-05-03 | 菲尼萨公司 | Integrated circuits in optical receivers |
-
1999
- 1999-01-07 JP JP11001645A patent/JP2000201031A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002084235A (en) * | 2000-09-07 | 2002-03-22 | Fujitsu Ltd | Apd bias voltage control circuit |
| US7332702B2 (en) | 2002-08-05 | 2008-02-19 | Sumitomo Electric Industries, Ltd. | Optical receiver and a method for manufacturing the same |
| US7792434B2 (en) | 2005-09-07 | 2010-09-07 | Sumitomo Electric Industries, Ltd. | Optical receiver |
| WO2012104448A1 (en) * | 2011-01-31 | 2012-08-09 | Universidad De Malaga | Laser receiving apparatus based on an avalanche photodiode thermally regulated with embedded control |
| ES2386732A1 (en) * | 2011-01-31 | 2012-08-28 | Universidad De Málaga | Laser receiving apparatus based on an avalanche photodiode thermally regulated with embedded control |
| JP2013016638A (en) * | 2011-07-04 | 2013-01-24 | Hamamatsu Photonics Kk | Photodiode array module |
| CN104871456B (en) * | 2012-10-29 | 2017-05-03 | 菲尼萨公司 | Integrated circuits in optical receivers |
| JP2016516179A (en) * | 2013-02-22 | 2016-06-02 | アレヴァ・エヌセーＡｒｅｖａ Ｎｃ | Method for controlling the gain and zero of a multi-pixel photon counter device, and an optical measurement system implementing the method |
| JP2015177148A (en) * | 2014-03-18 | 2015-10-05 | 株式会社東芝 | Photodetector |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0786859B1 (en) | Power amplifying circuit and method | |
| JP4532563B2 (en) | Optical receiver and identification threshold value generation method thereof | |
| CA2363400A1 (en) | System and method for inverting automatic gain control (agc) and soft limiting | |
| US6362911B1 (en) | Burst mode optical receiver using two amplifiers having different bandwidth | |
| US8144813B2 (en) | Receiving method and receiving circuit | |
| KR20020003873A (en) | Automatic gain control method, automatic gain control processor, and demodulator | |
| KR100640413B1 (en) | Optical receiver for receiving burst-mode signal | |
| JP2000201031A (en) | Light receiving circuit | |
| US4987298A (en) | Automatic gain control apparatus which adjusts bias and gain to maximize signal to noise ratio | |
| US6798282B1 (en) | Method and system for transimpedance amplifiers with high current input while maintaining high transimpedance gain and bandwidth | |
| JP2003125012A (en) | Ask demodulator with agc | |
| KR20050089845A (en) | Method for automatically setting the gain of an interrogator receiver within a non-contacting identification system | |
| JP3114821B2 (en) | Optical receiver circuit for ternary APD | |
| KR101139450B1 (en) | system and its operating method | |
| JPS6047783B2 (en) | Automatic gain control method | |
| JP2501319B2 (en) | Optical receiver circuit for angle modulation signal | |
| JPH11196053A (en) | Optical receiving circuit | |
| JP3005472B2 (en) | Receiving machine | |
| JPH05122153A (en) | Photodetecting circuit | |
| JPH0736500B2 (en) | AGC control method | |
| JPH024033A (en) | Optical receiver | |
| JPH1155194A (en) | Bias control system for optical receiver | |
| JPH0516728Y2 (en) | ||
| JPH079450Y2 (en) | Optical receiver circuit | |
| JPS6111016B2 (en) |