JP2000200911A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistance by restraining fine line effects by forming a silicide layer by carrying out ion implantation for obtaining an amorphous layer. SOLUTION: Arsenic, which is a dopant whose mass is relatively large and is easy to form an amorphous layer, is subjected to ion implantation so that a range RP reaches a position which is deeper than the silicon layer of source/ drain regions. Implantation is carried out at a dose of about 3×1014 cm-2 at 70 keV. An amorphous layer 11 is formed over the entire source/drain regions and in an upper part of a polysilicon layer which is a gate electrode. A thick amorphous layer can be formed in source/drain regions and a gate electrode. As a result, formation of a thick silicide layer becomes possible, to reduce resistance and to restrain fine line effect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device characterized by a silicide forming process.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, in particular, MOS devices, it is one of important issues to reduce the resistance of source / drain and gate electrodes. Conventionally, in order to reduce the resistance of the source / drain and the gate electrode, a method of forming silicide on the source / drain and the gate electrode has been adopted.
iSi ₂ is most widely used.

However, in such a method of forming a silicide, the thin line effect that the resistance of the silicide rapidly increases when the line width of the source / drain and the gate is reduced becomes remarkable. Therefore, when this method is applied to a micro device of the sub-half micron generation, the effect of reducing the resistance is not sufficient.

For this reason, after forming the source / drain and the gate and before forming the silicide, a technique called amorphization implantation (1992 VLSI) in which arsenic is implanted into the entire surface to make the upper portions of the source / drain and the gate amorphous.
Symp. on Tech. p. 66-67), and examples of its application are disclosed in JP-A-8-330253.

An example in which the amorphization implantation method is applied to the manufacture of a CMOS device will be described with reference to FIG.

As shown in FIG. 3A, ion implantation is performed on a surface of a semiconductor substrate in which a CMOS is formed by a known method by using arsenic or the like, which is a relatively large dopant that easily forms an amorphous layer. Is implanted with an energy and a dose such that the range Rp remains near the surface of the source / drain 9, 10. As a result, FIG.
As shown in FIG. 7, an amorphized layer 11 is formed on the source / drain 9, 10 and the gate electrode 7. Thereafter, as shown in FIG. 3C, a silicide layer 12 is formed on the source / drain and the gate electrode by a known method. Here, the reason for controlling Rp to stay near the surface during arsenic ion implantation is that when Rp reaches a position deeper than the source / drain, arsenic, which is an impurity, penetrates the source / drain and causes a junction leak. This is because the element characteristics fluctuate or deteriorate.

According to this method, as shown in FIG. 3B, the upper portions of the source / drain and the gate electrode are made amorphous, and the silicide reaction is promoted. Can be suppressed to some extent.

[0008]

However, this method has a problem that the parasitic resistance of the entire PMOS source / drain 10 is deteriorated by implanting arsenic. This is, as shown in FIG.
Since arsenic is implanted only in the vicinity of the source / drain surface of the GaN layer, the arsenic is implanted between the silicide layer and the source / drain silicon layer during or after the formation of the silicide layer. Segregates at the interface. In addition, a large amount of arsenic segregated is large because a considerable amount of arsenic for making amorphous is implanted so that Rp remains in the source / drain regions. Since such arsenic segregation causes a parasitic resistance, it causes a problem that the transistor performance is reduced and the reliability and the yield are reduced.

[0009] In the recent manufacture of devices having a shallow junction, it becomes more difficult to ion-implant a considerable amount of impurities into the source / drain as the source / drain becomes shallower. Problems such as junction leaks can easily occur through the source / drain. As a result, fluctuations or deterioration of the device characteristics occur, and the reliability and the yield decrease.

An object of the present invention is to manufacture a fine semiconductor device which suppresses the thin line effect of the silicide layer to reduce the resistance of the source / drain and gate electrodes, suppresses the parasitic resistance, and has excellent element characteristics. It is to provide a method.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device using an SOI substrate having an SOI structure in which a silicon layer is formed on an insulator. And forming a source / drain, performing ion implantation for amorphization so that Rp reaches a position deeper than the silicon layer, and forming a silicide layer. It relates to a manufacturing method.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described.

A main feature of the present invention is that in the ion implantation step for amorphization, the ion implantation is performed so that Rp reaches a position deeper than the silicon layer in the source / drain region of the SOI substrate.

Here, Rp refers to the average projection (penetration depth) of ion implantation.

In the step of performing ion implantation for amorphization, it is preferable to perform amorphization ion implantation so that Rp stays in the insulator. Further, it is preferable to perform the amorphizing ion implantation such that the peak of the concentration distribution of the dopant (impurity) in the depth direction due to the amorphizing ion implantation is located in the insulator. As a result, the concentration of impurities in the source / drain due to the amorphous ion implantation can be suppressed,
The generation of parasitic resistance at the interface between the source / drain and the silicide due to the impurity can be suppressed.

In the present invention, arsenic, antimony, germanium, indium and the like can be used as dopants (impurities) for ion implantation for amorphousization.

In the present invention, the refractory metal used for forming the silicide layer is Ti (titanium), Co
(Cobalt), Ni (nickel) or the like can be used.

In the present invention, it is preferable to perform thermal annealing after forming the silicide layer. This step is performed to convert the silicide layer from the C49 phase to the low-resistance C54 phase.

The present invention is suitable for forming a MOS transistor, particularly a CMOS circuit, on an SOI substrate.

The present invention can be carried out, for example, by the following process.

A step of forming a gate insulating film, a gate electrode and a source / drain on an SOI substrate; a step of performing ion implantation for amorphization so that Rp reaches a position deeper than the silicon layer; and depositing a high melting point metal. And a step of performing heat treatment for forming a silicide layer can be performed in this order. Note that the step of depositing the high melting point metal may be performed before the step of performing ion implantation for amorphization.

Hereinafter, preferred embodiments of the present invention will be described more specifically with reference to the drawings.

As shown in FIG. 1A, a buried insulating film 2 made of a silicon oxide film or the like having a thickness of about 100 nm is formed on a semiconductor substrate 1 such as a silicon substrate, and a silicon layer is further formed thereon. SOI (Silicon On Insul
ator) An SOI substrate having a structure is prepared, a silicon layer on the surface of the SOI substrate is thinned to about 50 nm,
A field oxide film (element isolation film) 3 is formed by a known method such as an OS method to perform element isolation. Next, using a photoresist as a mask, boron for forming NMOS and PM
Phosphorus for forming OS is 10 ¹⁷ to 10 ¹⁸ cm ⁻³ , respectively.
The P-layer 4 and the N-layer 5 are formed by implantation so as to have a concentration of about the same.

Next, an oxide film to be a gate oxide film 6 is formed to a thickness of about 6 nm, and a polysilicon layer to be a gate electrode 7 is formed to a thickness of about 150 nm by a CVD method. The polysilicon layer and the oxide film are anisotropically etched in a lithography process to form a gate electrode 7 and a gate oxide film 6. Subsequently, an insulating film such as a silicon oxide film is deposited to a thickness of 100 nm by, for example, a CVD method, and is etched back by anisotropic etching to form a sidewall 8. As described above, the structure shown in FIG. 1B is formed.

Next, ion implantation is performed using a photoresist, and in the formation of a PMOS, boron is ion-implanted, for example, at an implantation energy of 4 keV so as to have a concentration of 5 × 10 ²⁰ cm ^−3, to activate impurities. Is performed, for example, at 1000 ° C. for 10 seconds to form a PMOS P + layer 10 serving as a source / drain. NMOS
In the formation of arsenic, for example, an implantation energy of 30 k
Ion implantation is performed so that the concentration becomes 3 × 10 ²⁰ cm ⁻³ at eV, and annealing for activating impurities is performed, for example, by 1000.
Perform at 20 ° C for 20 seconds to make NMOS as source and drain
N + layer 9 is formed (FIG. 1C).

Next, arsenic, which is a relatively large dopant that easily forms an amorphized layer, is doped with an ion implantation range Rp from the source / drain silicon layer (the thickness of the silicon layer is about 50 nm in this case). For example, implantation is performed at 70 keV with a dose of about 3 × 10 ¹⁴ cm ⁻² so as to reach a deep position (FIG. 2D). Then, an amorphous layer 11 is formed over the entire source / drain and over the polysilicon layer serving as the gate electrode.
(E)).

Thereafter, TiSi _{2 is} deposited on the polysilicon of the source / drain 9 and 10 and the gate electrode 7 by a known method.
The silicide layer 12 is formed as shown in FIG.
(F)).

As a method of forming the silicide layer 12, for example, Ti is sputtered and deposited to a thickness of 20 nm, and C49 phase TiSi ₂ is formed by RTA (rapid thermal annealing) at 700 ° C. in a nitrogen atmosphere. At the same time, TiN formed on the insulating film is, for example, NH ₄ OH +
It is selectively etched away by a H ₂ O ₂ + H ₂ O solution. Then, RTA at 800 ° C. in a nitrogen atmosphere
Convert iSi ₂ from C49 phase to low resistance C54 phase.
Thereafter, metal wiring and the like are formed by a known method.

In the present invention, since the substrate having the SOI structure is used, even if Rp by ion implantation reaches a position deeper than the silicon layer having the SOI structure, that is, the source / drain layer, the lower layer of the source / drain layer (silicon layer) is formed. Is an insulator, so it is unlikely to cause a junction leak.

In the ion implantation for making amorphous, the implantation energy and the dose are determined by Rp and SOI.
By controlling the ion implantation to reach a position deeper than the silicon layer (source / drain) of the structure,
Arsenic (impurities) in the source / drain can be made relatively low in concentration by amorphization implantation. In general, when ion implantation is performed, the implanted impurity has a Gaussian distribution. At this time, the peak of the impurity concentration distribution in the depth direction is set, for example, in the insulator at a position deeper than the silicon layer (source / drain) having the SOI structure. If you take it, S
The vicinity of the surface of the silicon layer having the OI structure becomes a tail of the impurity distribution, and the impurity concentration can be effectively reduced.

When an SOI substrate is applied to a conventional manufacturing method, segregation of arsenic is likely to occur because the thermal diffusion of arsenic is small. However, according to the present invention, the arsenic of the amorphous implantation is made to have a relatively low concentration and is distributed over the entire region of the source / drain, so that segregation of arsenic can be suppressed and the source / drain of the PMOS can be suppressed. Parasitic resistance can be suppressed.

Since ions can be implanted with high energy, a thick amorphous layer can be formed on the source / drain and gate electrodes. Therefore, a thick silicide layer can be formed, the resistance of the source / drain and the gate electrode can be reduced, and the thin line effect of increasing the sheet resistance with a small line width can be suppressed.

[0033]

According to the manufacturing method of the present invention, a fine semiconductor device having excellent semiconductor characteristics can be provided with a high yield.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a manufacturing method of the present invention.

FIG. 2 is a process sectional view of the manufacturing method of the present invention.

FIG. 3 is a process sectional view of a conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Buried insulating film 3 Element isolation film 4 P-layer 5 N-layer 6 Gate oxide film 7 Gate electrode 8 Side wall 9 N + layer 10 P + layer 11 Amorphization layer 12 Silicide layer 31 N-type semiconductor substrate 32 P-type Well

Claims (8)

[Claims] 1. An SO having a silicon layer formed on an insulator.
In a method for manufacturing a semiconductor device using an SOI substrate having an I structure, a step of forming a gate insulating film, a gate electrode, and a source / drain on the SOI substrate; and forming an amorphous layer so that Rp reaches a position deeper than the silicon layer. A method for manufacturing a semiconductor device, comprising: a step of performing ion implantation for forming a semiconductor layer; and a step of forming a silicide layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of performing ion implantation for amorphization, the ion implantation is performed so that Rp remains in the insulator. 3. The semiconductor according to claim 2, wherein in the step of performing ion implantation for amorphization, the ion implantation is performed such that a peak of a concentration distribution in a depth direction of the ion-implanted dopant is located in the insulator. Device manufacturing method. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the dopant for ion implantation for amorphization is selected from arsenic, antimony, germanium, and indium. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal used for forming the silicide layer is titanium. 6. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing thermal annealing after forming the silicide layer. 7. An element formed on an SOI substrate has a MOS structure.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is a transistor. 8. An element formed on an SOI substrate has a CMO
The method for manufacturing a semiconductor device according to claim 1, wherein the method is an S circuit.