JP2000195278A - Nonvolatile ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of a reference cell due to excess accessings and to prolong service life of an element by making the number of access times of the reference cell and a main cell the same. SOLUTION: Main local bit lines, corresponding to respective main global bit lines, are arranged in respective sub-cell array parts. Switching elements SW11, SW12, etc., are arranged between the main local bit lines and the main global bit lines. Similarly in the case of reference global bit lines BLRG-1, BLRG-12, etc., respective reference local bit lines BLLR1-1, BLLR2-1, etc., BLLR1-2, BLLR2-2, etc., are connected to both bit lines via the switching elements SWR11, SWR12, etc. The optional sub-cell array part among the sub- cell array parts 61-1, 61-2, etc., is selected, and the main local bit line is connected to the main global bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile ferroelectric memory device.

[0002]

2. Description of the Related Art Generally, a ferroelectric memory which has a data processing speed comparable to that of a DRAM widely used as a semiconductor memory element and stores data even when a power supply is turned off, that is, a ferroelectric random access memory (FRAM). Memory) is attracting attention as a next-generation storage element. An FRAM is a storage element having almost the same structure as a DRAM, and uses a ferroelectric as a material of a capacitor and uses high remanent polarization, which is a characteristic of the ferroelectric. Due to such remanent polarization characteristics, data is not lost even when the electric field is removed.

FIG. 1 is a characteristic diagram showing a general ferroelectric hysteresis roof. As shown in FIG. 1, even when the polarization induced by the electric field removes the electric field, a certain amount (d, a)
State) is maintained. The d and a states corresponded to 1 and 0, respectively, and were applied as storage elements.

Hereinafter, a conventional nonvolatile ferroelectric memory device will be described with reference to the accompanying drawings. FIG. 2 is a configuration diagram of a conventional nonvolatile ferroelectric memory including two unit cells. Word lines (W) formed in one direction
/ L), a plate word line (P / L) formed alongside the word line (W / L1) (hereinafter, referred to as “plate line”), a word line (W / L) and a plate line (P). / L) and a plurality of bit lines (..., Bit_n, Bit_n +
1,. . . ), And unit cells (C111, C121,...) Are formed between each bit line and the word line (W / L) and plate line (P / L). That is, the unit cell includes one transistor (T1) and one ferroelectric capacitor (FC1).

A driving circuit using such a conventional ferroelectric memory device will be described below. FIG. 3 shows a driving circuit for driving a conventional ferroelectric memory element. Conventional 1T
A drive circuit for driving a ferroelectric memory having a / 1C structure includes a reference voltage generation unit 1 for generating a reference voltage; a plurality of transistors (Q1 to Q4); a capacitor (C1);
A reference voltage stabilizing unit 2 for stabilizing the reference voltages of two adjacent bit lines; and a plurality of transistors (Q6 to Q6)
7) a first reference voltage storage unit 3 including capacitors (C2 to C3) and the like and storing reference voltages of logic values “1” and “0” in adjacent bit lines, respectively; and a transistor Q5; A first equalizing unit 4 for equalizing two adjacent bit lines; a first equalizing unit 4 connected to different word lines and plate lines to store data;
A plurality of transistors (Q10
To Q15), a first sense amplifier unit 6 comprising a P-sense amplifier (PSA) and sensing data of a cell selected by a word line among a plurality of cells of the first main cell array unit 5; A second line connected to the line and plate line for storing data
A plurality of transistors (Q28);
To Q29) and capacitors (C9 to C10).
And a second reference voltage storage unit 8 storing a reference voltage of “0”; a plurality of transistors (Q16 to Q25), an N-sense amplifier (NSA), and the like, for sensing data of the second main cell array unit 7. And a second sense amplifier section 9 for outputting the data.

The data input / output operation of the conventional ferroelectric memory device having the above-described structure is as follows. FIG. 4 is a timing chart showing an operation in a write mode of a conventional ferroelectric memory device, and FIG. 5 is a timing chart showing an operation in a read mode. First, in the write mode, the chip enable signal (CSBpad) applied from the outside is activated from high to low, and at the same time, the write mode starts when the write enable signal (WEBpad) is applied from high to low. Next, when the decoding of the address from the write mode starts, the pulse applied to the word line transitions from “low” to “high”, and the cell is selected. As described above, in the section in which the word line maintains the "high" state, the "high" signal of the fixed section and the "low" signal of the fixed section are sequentially applied to the plate line. Then, the logic value “1” is set in the selected cell.
Alternatively, a “high” or “low” signal synchronized with a write enable signal (WEBpad) is applied to the bit line to write “0”. In other words, when a "high" signal is applied to the bit line and the signal applied to the word line is in the "high" state and the signal applied to the plate line is "low", the ferroelectric capacitor is A logic value "1" is recorded. When a "low" signal is applied to the bit line and the signal applied to the plate line is a "high" signal, a logic value "0" is recorded in the ferroelectric capacitor.

An operation for reading data stored in a cell in such a write mode operation is as follows. First, a chip enable signal (CSBpa) is externally provided.
When d) is activated from "high" to "low", all bit lines are equipotentially set to "low" voltage by the equalization signal before the word line is selected.

That is, in FIG. 3, when a "high" signal is applied to the equalizing section 4 and a "high" signal is applied to the transistors (Q18, Q19), the bit line becomes the transistor (Q1).
Since it is grounded through 9), it is equalized to a low voltage (Vss). Then, the transistors (Q5, Q18, Q1)
After turning off 9) to deactivate each bit line, the address is decoded, and the "low" signal is transited to the "high" signal in the word line by the decoded address to select the cell. A "high" signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value "1" stored in the ferroelectric memory. If a logic value "0" is stored in the ferroelectric memory, the corresponding data is not destroyed.

As described above, the destroyed data and the undestructed data output different values according to the principle of the hysteresis loop as described above, and the sense amplifier senses a logic value "1" or "0". That is, when the data is destroyed, the data is changed from d to f as in the hysteresis loop of FIG. 1, and when the data is not destroyed, the data is changed from a to f. . Therefore, when the sense amplifier is enabled after a predetermined time, if the data is destroyed, it is amplified and outputs a logic value "1", and if the data is not destroyed, a logic value "0" is output. .

After the data is output by the sense amplifier in this manner, it is necessary to restore the destroyed data to the original data. For this purpose, the plate line is set to the "high" state while the "high" signal is applied to the word line. Inactivate from "high" to "low".

In the conventional ferroelectric memory device having such a 1T / 1C structure, at the time of data input / output operation, the number of reference cells must be larger than that of the main cell.

[0012]

The above-mentioned conventional ferroelectric memory device has the following problems. In the state where the characteristics of the ferroelectric film are not yet perfect, one reference cell is configured to be used for reading operation more than several hundred times more than the main cell, so that the reference cell operates more than the main cell. Must. Therefore, the characteristics of the reference cell rapidly deteriorate, and the reference voltage becomes stable. This degrades the operating characteristics of the device and shortens its life.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. By making the number of accesses of a main cell and a reference cell substantially equal, the bit line induced voltage by the reference cell is reduced. It is an object of the present invention to provide a nonvolatile ferroelectric memory device in which the operation characteristics are improved by maintaining the bit line induced voltage by the main cell constant and the life is extended.

[0014]

According to the present invention, there is provided a nonvolatile ferroelectric memory device comprising: a plurality of sub-cell arrays; and a plurality of main global bits formed in a direction crossing each of the sub-cell arrays. A line and at least one pair of reference global bit lines, a main local bit line and a reference local bit line formed corresponding to each main global bit line and the reference global bit line, and between each local bit line and the global bit line. A main cell array unit including a switching element configured to sense a signal applied through one bit line of a pair of reference global bit lines and output a reference voltage. Consists of a reference sense amplifier A reference bit line controller; a plurality of main sense amplifiers formed on one side of the reference bit line controller and connected to each main global bit line to receive a reference voltage and sense a signal applied through the global bit line; A main bit line control unit formed on one side of a main cell array unit;
A word line driving unit for outputting a driving signal for cell selection; and a word line driving unit formed on another side of the main cell array unit,
A plate line driving unit that outputs a driving signal for cell selection together with a driving signal of the word line driving unit is included.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile ferroelectric memory device according to the present invention will be described with reference to the accompanying drawings. FIG. 6 is a block diagram showing a cell array of the nonvolatile ferroelectric memory device according to the first embodiment of the present invention. In this specification, terms indicating directions such as left, right, up, and down are only on the drawings and do not indicate absolute directions. As shown in FIG. 6, a main cell array section 61, a word line driving section 63 disposed on the left side of the main cell array section 61, a plate line driving section 65 disposed on the right side of the main cell array section 61, and a main cell array section It includes a main bit line controller 67 disposed below 61 and a reference bit line controller 69 disposed on the right side of the main bit line controller 67. Here, the main cell array unit 61 internally includes a plurality of cell arrays.

When the structure shown in FIG. 6 is repeated, the structure shown in FIG. 7 is obtained.

FIG. 8 is a detailed block diagram of the main cell array section according to the present invention. As described above, the main cell array section is composed of a plurality of cell array sections (hereinafter, "sub-cell array section"). As described above, the main cell array section includes a number of sub cell array sections (61_1, 61_2,
61_3,. . . 61_n), and the two sub-cell array units are not activated simultaneously.

FIG. 9 is a diagram showing FIG. 8 in more detail. As shown in FIG. 9, each subcell array unit (61_
1, 61_2,. . . ), A plurality of global bit lines (BLG_n, BLG_n + 1,...) Are formed. Then, each subcell array unit (61_
1, 61_2,. . . ), Local bit lines (BLL1_n, BLG_n, BLGn + 1,...) Are connected to the respective global bit lines (BLG_n, BLGn + 1,.
BLL2_n,. . . , BLLn_n) are formed. Each local bit line is connected to a switching element (SW11, SW12,... SW1).
n) (SW21, SW22, ... SW2n) (SWn
1, SWn2,. . . SWnn) to the global bit line.

FIG. 10 shows one sub-cell array section in more detail. As shown in FIG. 10, a large number of word line pairs including word lines (W / L) and plate lines (P / L) are arranged in parallel. Then, the word lines (W / L1, P / L1,... W / Ln, P /
Ln) A plurality of global bit lines (..., BLG_n, BLG_n + 1, ...) are formed in a direction intersecting with the pair. As described above, these global bit lines include local bit lines (... BLL1).
_N, BLL1_n + 1. . . ) Are arranged in parallel via switching elements (... SW11, SW12...). Each local bit line has a word line (W / L) and a plate line (P /
L) and a unit cell (C1)
11, C112,. . . . C11n / C121, C12
2,. . . . C12n / C1n1, C1n2,. . . .
C1nn) are connected. The switching element is connected between the end of the local bit line and the global bit line in the sub-cell array. The switching device transmits data of a selected cell among a plurality of cells connected to the local bit line to the global bit line.

The process of selecting a cell in the sub-array section configured as described above will be described below. As described above, the main cell array section is formed by repeating the sub cell array section having the configuration shown in FIG.

Of the plurality of sub cell array sections, only one sub cell array section is activated. At this time, a pair of word lines (W / L) and plate lines (P / L) are activated. You. Therefore, when a certain pair of word lines and plate lines are activated, data of the unit cells connected to the activated word lines (W / L) and plate lines (P / L) are transmitted through the local bit lines. It is transmitted to the global bit line. The global bit line transmits cell data transmitted from the local bit line through the switching device to a bit line controller (not shown). A sense amplifier (not shown) is connected to the bit line control unit for each global bit line. Therefore, only data output from one of the plurality of sense amplifiers is output to the outside through the data line.

FIG. 11 shows the "A" portion of FIG. 10 in more detail, and a unit cell is formed between a word line (W / L), a plate line (P / L), and a local bit line. The switching element is connected to the end of the local bit line, and is connected to the global bit line. The unit cell is
It is composed of one transistor and one ferroelectric capacitor, the gate of each transistor is connected to a word line, one terminal of the ferroelectric capacitor is connected to the drain (or source) of the transistor, and the other terminal is Connected to the plate line.

FIG. 12 is a detailed configuration diagram of FIG. 6, mainly showing the main cell array unit 61, the main bit line control unit 67, and the reference bit line control unit 69. As described above, the main cell array section 61 includes a plurality of sub cell array sections (61_1, 61_2, ...). Then, the sub-cell array units (61_1, 61_
2,. . . ) Are connected to the main bit line controller 67, and the reference global bit lines (BLRG_1, BLRG_2) are connected to the reference bit line controller 69. Here, the reference bit line control unit 69 receives two reference global bit lines (BLRG_1 and BLRG_2).

As shown in the drawing, a main local bit line corresponding to each main global bit line is arranged in each sub cell array portion. That is, the main global bit line (BLG)
_N) include a plurality of main local bit lines (BL
L1_n, BLL2_n,. . . ) Is connected.
A switching element (SW11, SW11) is connected between the main local bit line and the main global bit line.
SW21,. . . ) Is arranged.

The reference global bit line (BLRG_
, BLRG_2), and the reference local bit line (BLLR1_
1, BLLR2_1,. . . / BLLR1_2, BLL
R2_2,. . . /. . . / BLLR1_n, BLLR
2_n,. . . ) Is a switching element (SWR11, S
WR21 / SWR12, SWR22 / SWR1n, SW
R2n,. . . ) Is connected through.

Therefore, the sub cell array section (61_
1, 61_2,. . . ), An arbitrary sub-cell array portion is selected, a main local bit line in the sub-cell array portion is connected to a main global bit line,
Finally, the data is transmitted to the main bit line control unit 67.

Similarly, the reference local bit line in the sub-cell array unit is connected to the reference global bit line, and the data is finally transmitted to the reference bit line control unit 69.

On the other hand, FIG. 13 shows the details of the main bit line control unit and the reference bit line control unit in the block diagram of FIG. As shown in FIG. 13, each main global bit line (BLG_n,
BLG_n + 1,. . . ) Has a main sense amplifier (S
A1, SA2,. . . ) (67_1, 67_)
2,. . . ) Are concatenated. On the other hand, the reference line side has two reference global bit lines (BLRG_
1, BLRG_2) is one of the reference sense amplifiers (6
9_1) and a constant voltage (CONSTAN) is applied to the other reference global bit line (BLRG_1).
T VOLTAGE) is applied. The output of the reference sense amplifier (69_1) is connected to all the main sense amplifiers (67_1, 61_2,...), And the reference voltage (CREF) is applied to the main sense amplifier (67_1, 67_1).
61_2,. . . ) Are applied in common. Further, the main bit line controller 67 controls the main global bit lines (BLG_n, BLG_n +
1,. . . ), A bitline precharge circuit (BPC) (68_)
1, 68_2,. . . ) Is arranged. Therefore, the first global bit line only has a bit line precharge circuit (BPC) connected between its adjacent global bit line and the intermediate global bit line. Between the bit line precharge circuit section (BP
C) is connected. A bit line precharge circuit unit (BPC) is connected between the last global bit line and the previous global bit line, and a reference global bit line (BLRG_BLK).
2) and the bit line precharge circuit section (70_)
1) is connected.

FIG. 14 shows a bit line precharge circuit according to a first embodiment of the present invention in more detail. As shown in FIG. 14, directly connected between the global bit lines (BLG_n, BLG_n + 1,...) Are bit line equalization switch units (BQESW) (71_1, 71_2,...). , And each global bit line (BL
G_n, BLG_n + 1,. . . ) Have global bit lines (BLG_n, BLG_n +) between a line for transmitting a signal (BEQLEV) output from a bit line precharge level supply unit (not shown).
1,. . . ) Selectively transmits the signal (BEQLEV) to the bit line precharge switch section (BPCS).
W) (72_1, 72_2, ...). Bit line equalization switch units (71_1, 7
1_2,. . . ) And bit line precharge switch sections (72_1, 72_2,...) Are NMOS (NMO).
S) It is composed of a transistor. The level of the signal output from the bit line precharge level supply unit is
The threshold voltage is selected to be equal to or slightly larger than the threshold voltage of the NMOS transistor.

As a result, the output signal of the bit line precharge level supply unit precharges the level of the corresponding global bit line through the bit line precharge switch units (72_1, 72_2,...). Bit line equalization switch units (71_1, 71_
2,. . . ) Is turned on by the switch control signal, and sets two adjacent global bit lines to the same level. Although the bit line precharge level supply unit is not shown in FIG. 14, examples thereof are shown in FIGS.

FIG. 15 shows a first embodiment. As shown in FIG. 15, a source is connected to a power supply terminal (Vcc), and a first PMOS transistor (MP1) controlled by an activation signal (EQLEN) for activating a bit line precharge level supply unit; The second PMOS transistor (M) connected to the drain of the first PMOS transistor (MP1) and having the drain and the gate commonly connected.
P2); the drain is a first PMOS transistor (MP
The second PMOS transistor (MP2) is connected to the drain of 1).
And a first NM having a gate commonly connected to the gate of the second PMOS transistor MP2.
OS transistor (MN1); drain is second PMO
A second NMOS transistor (MN2) connected to the drain of the S transistor (MP2) and a gate connected to the source of the first NMOS transistor (MN1);
A gate and a drain are commonly connected to a source of the NMOS transistor (MN1), and a source is connected to a ground terminal (Vss); a third NMOS transistor (MN3); and a gate is connected to a source of the first NMOS transistor (MN1). Fourth NMO controlled by its source voltage
An S transistor (MN4); formed to face the fourth NMOS transistor (MN4);
A fifth NMOS transistor (MN5) commonly connected to the source of the NMOS transistor (MN4); and a drain connected to the fourth and fifth NMOS transistors (MN4, MN).
5) a sixth NMOS transistor MN6 connected to the common source, the source connected to the ground terminal;
The drain of the OS transistor (MN4) and the first PMOS
A fourth PMOS transistor MP4 connected between the drain of the transistor MP1; a fifth PM connected between the drain of the fifth NMOS transistor MN5 and the drain of the first PMOS transistor MP1;
An OS transistor MP5; a third PMOS transistor MP3 having a drain connected to the drain of the first PMOS transistor MP1 in parallel with the first NMOS transistor MN1 and having a drain and a gate commonly connected.
And; the third PMOS transistor (MP3) is configured in parallel with the third PMOS transistor (MP3), and has a gate.
A seventh NMOS transistor (MN7) commonly connected to the gate of the seventh NMOS transistor (MN7);
N7) is connected to the source and the drain is connected to the drain of the third PMOS transistor MP3.
An OS transistor (MN8); a ninth NMOS transistor (MN9) controlled by the drain voltage of the fourth PMOS transistor (MP4) and connected in series with the seventh NMOS transistor (MN7);
The bipolar transistor PNP1 has an emitter connected to the source of the MOS transistor MN9, and a collector and a base commonly connected to a ground terminal. Here, the gate of the fifth NMOS transistor (MN5) is
It is connected between a seventh NMOS transistor (MN7) and a ninth NMOS transistor (MN9), and is controlled by a bit line precharge voltage for precharging a bit line which is an output of this circuit. The operation of the bit line precharge level supply unit will be described below in more detail.

As shown in FIG. 15, when the activation signal (EQLEN) of the bit line precharge level supply unit transitions to low during normal operation, the first PMOS transistor (MP1) is activated and the potential of the node N1 rises to high. To level. First, the second NMOS transistor (MN2)
, That is, the node N2 is low, the second PMOS transistor (MP2) is turned on, and the level of the node N2 also rises. Therefore, the first NMOS transistor MN1 whose gate is connected to the node N2 is turned on, and the level of the node N3 rises. When the level of the node N3 rises above the threshold voltage of the third NMOS transistor MN3, the third NM
The OS transistor (MN3) turns on and discharges current to the ground terminal. Therefore, the level of the node N3 becomes the third level.
It is fixed to the threshold voltage of the NMOS transistor (MN3). Then, the second NMO depends on the level of the node N3.
The S transistor (MN2) turns on, and the level of the node N2 gradually decreases. When the level of the node N2 decreases, the on-resistance of the first NMOS transistor (MN1) increases, and the current supplied to the node N3 eventually decreases. Therefore, the first NMOS transistor (MN
1) and the second PMOS transistor (MP2) and the second N
Using the feedback loop of the MOS transistor (MN2) and the third NMOS transistor (MN3), the voltage of the node N3, which is the threshold voltage level of the transistor (MN3), is obtained.

On the other hand, since the node N7 is initially low,
The third PMOS transistor (MP3) turns on, and the level of the node N7 rises. When the level of the node N7 rises above the threshold voltage of the seventh NMOS transistor (MN7), the seventh NMOS transistor (MN7) turns on. Since the gate of the ninth NMOS transistor (MN9) is connected to the node N4, the ninth NMOS transistor (NM9) operates at a voltage corresponding to the internal resistance of the fourth NMOS (MN4) corresponding to the voltage of the node N4, and is connected thereto. Bipolar transistor (PNP)
Discharge current to ground through 1). The bipolar transistor (PNP1) is a PNP bipolar transistor. The collector and the base are commonly connected to the ground terminal, and the emitter is connected to the node N8, so that it functions as a PN diode. By the operation of the ninth NMOS transistor (MN9), the output terminal (BEQL)
EV) at the threshold voltage level. This will be further described below. Since the eighth NMOS transistor MN8 is turned on by the output terminal of the bit line precharge level supply unit that maintains the threshold voltage level, the voltage of the node N7 decreases. When the voltage of the node N7 decreases, the Nth
The ON resistance of the MOS transistor (MN7) increases, and the current applied to the output stage of the bit line precharge level supply unit decreases. Therefore, the seventh, eighth, and ninth Nth
MOS transistors (MN7, MN8, MN9) and third
PMOS transistor (MP3) and bipolar transistor (PNP1) operating as PN diode
The output voltage of the threshold voltage level can be obtained by utilizing the feedback loop of (1). Therefore, the level of the output terminal, that is, the output terminal of the bit line precharge level supply unit, is fixed to a threshold voltage level such as the level of the node N3. Here, the fourth, fifth and sixth NMOS transistors (MN4, MN5 and MN6) and the fourth and fifth PMOS transistors
Since the transistors (MP4, MP5) form an amplification unit, the fourth and fifth NMOS transistors (MN4, MN4)
The output of the node N4 is amplified by the input of 5).

In the bit line precharge level supply unit according to the present invention which operates as described above, the node N3
Of the output terminal (the output terminal of the bit line precharge level supply unit) will be examined.

The voltage at the node N3 is used as the gate input of the fourth NMOS transistor (MN4), and the output terminal voltage is used as the gate input of the fifth NMOS transistor (MN5). If the voltage at the node N3 is higher than the voltage at the output terminal, the voltage at the node N4 is reduced and the voltage at the node N5 is amplified so as to increase. The reduced voltage at the node N4 is applied to the ninth NMOS transistor (M
N9), the ON resistance of the ninth NMOS transistor (MN9) increases, so that the amount of current discharged to the ground decreases and eventually the level of the output terminal increases. If the voltage at the node N3 is lower than the voltage at the output terminal, the voltage at the node N5 decreases and the voltage at the node N4 increases. The increased voltage of the node N4 becomes the ninth
Since the on-resistance of the ninth NMOS transistor (MN9) is reduced by being fed back to the NMOS transistor (MN9), the amount of current discharged to the ground increases, and eventually the level of the output terminal decreases. At this time, in order to prevent the level of the output terminal from excessively decreasing, a bipolar transistor (PNP1) operating as a PN diode is connected between the node N8 and the ground terminal. That is, P
When the threshold voltage is lower than the threshold voltage of the N-diode, the PN diode is turned off, thereby preventing further emission of current.

FIG. 16 illustrates a bit line precharge level supply unit according to a second embodiment of the present invention.
In this circuit, as shown in FIG. 16, the source is a power supply terminal (V
CC), and is controlled by an activation signal (BQLEN) for activating a bit line precharge level supply unit.
And the source is the first PMOS transistor (MP
A second PMOS transistor (MP2) and a third PM, which are connected to the drain of (1) in a branched manner and have a gate connected in common.
An OS transistor (MP3); a first NMOS transistor (MN1) controlled by a drain voltage of a third PMOS transistor (MP3) and selectively outputting a ground voltage; and a second PMOS transistor (MP).
2) and the second NMOS transistor MN2 connected between the first NMOS transistor MN1 and controlled by an externally applied reference voltage REF_IN.
And the third PMOS transistor (MP3) and the first NMO
A third NMOS transistor MN3 connected between the S transistor MN1 and controlled by an output terminal (node 1) voltage; a first PMOS transistor MP1
PMOS transistor (MP4) and fifth PMOS transistor, which are branched and connected to the drain of
A transistor (MP5); a fourth NMOS transistor (MN4) controlled by a gate voltage of the fourth PMOS transistor (MP4) and a fifth PMOS transistor (MP5) and selectively outputting a ground voltage;
A fifth NMOS transistor (MN5) having a drain connected to the drain of the S transistor (MP1) and controlled by a drain voltage of the fifth PMOS transistor (MP5); a fifth NMOS transistor (MN5);
The sixth NMOS transistor MN2 is connected between the gate and the source of the NMOS transistor and is controlled by the drain voltage of the second NMOS transistor MN2.
An NMOS transistor (MN6); a seventh NMOS transistor (MN7) controlled by the drain voltage of the third PMOS transistor (MP3) and connected between the fourth PMOS transistor (MP4) and the fourth NMOS transistor (NM4); (M
N2), and the fifth PMOS transistor (MP5) and the fourth NMOS transistor (M
N4), an eighth NMOS transistor (M
N8); a ninth NMOS transistor (MN9) controlled by the drain voltage of the second NMOS transistor (MN2) and having a drain connected to the output terminal (node 1).
And a tenth transistor (MN10) connected between the source and the ground terminal (Vss) of the ninth NMOS transistor (MN9) and having a gate and a drain commonly connected. Here, the drain and the gate of each of the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) are commonly connected.

The bit line precharge level supply unit according to the second embodiment of the present invention thus configured compares the reference voltage input from the outside with the voltage of the output terminal (node 1), The level is controlled to be always constant. That is, since the level of the output terminal is connected to the bit line, the level may fluctuate. However, when the bit line precharge level supply unit is configured as in the second embodiment of the present invention, the input reference voltage is reduced. Since the level does not change, a stable output level is always obtained.

FIG. 17 illustrates a bit line precharge level supply unit according to a third embodiment of the present invention. FIG.
As shown in FIG. 7, the configuration is similar to the above-described second embodiment, but in order to further stabilize the level of the output terminal,
The following configuration is further added. That is, FIG.
As shown in (1), the power supply terminal (Vcc) is branched from the power supply terminal in parallel with the first PMOS transistor (MP1), and is controlled by an activation signal (BQLEN) for activating a bit line precharge level supply unit. 6th page
A MOS transistor MP6; a seventh PMOS transistor MP7 and an eleventh PMOS transistor sequentially connected between the sixth PMOS transistor MP6 and the ground terminal Vss.
An NMOS transistor (MN11). Here, the drain and the gate of the seventh PMOS transistor MP7 are commonly connected, and the gate and the drain of the eleventh NMOS transistor MN11 are commonly connected to the gate of the second NMOS transistor MN2.

In the bit line precharge level supply unit according to the third embodiment, when the output terminal level changes, the drain voltage of the first PMOS transistor (MP1) also changes. The first PMOS transistor (M
The fluctuation of the drain voltage of P1) eventually causes the level of the output terminal to fluctuate.
The power supply voltage (Vc) is set so that the voltage fluctuation of the PMOS transistor (MP1) does not affect the output terminal (node 1).
c) was applied. Therefore, the precharge level at the output terminal can be applied at a more stable level.

FIG. 18 is a simplified structural block diagram of a reference sense amplifier according to one embodiment. As shown in FIG. 18, the reference sense amplifier of the reference bit line control unit receives the signal of the reference global bit line (BLRG_2), shifts the level of the signal to the main sense amplifier (67_1, 67_2,...). It comprises a level shifter 80 for outputting a reference voltage (CREF) to be applied, and a pull-down control unit 80a for receiving a signal of a reference global bit line (BLRG_2) and pulling down the reference bit line.

As described above, other than the method of shifting the level using the level shifter 80 and outputting the reference voltage to the main sense amplifier, as shown in FIG. It is also possible to configure only the pull-up controller 81a and use the signal of the reference global bit line as it is as the reference voltage (CREF).

As shown in FIG. 19, when it is not necessary to use a level shifter, it is necessary to use a few hundred bits or less for an IC card or the like which does not require a large capacity. A sufficient reference voltage can be obtained even with a high signal. However, when the number of sense amplifiers is large, FIG.
As shown in FIG. 8, a reference voltage is generated by a low signal using a level shifter. Here, the level shifter shown in FIG. 18 will be described in more detail.

FIG. 20 shows a first embodiment of the level shifter shown in FIG. As shown in FIG. 20, an enable signal (LSE) for enabling the level shifter
N), a first PMOS transistor (MP1) having a source connected to the power supply terminal (Vcc);
A second PMOS transistor (MP2) and a third PMOS transistor (MP2) branched from the drain of the MOS transistor (MP1);
A first NMOS transistor (M) controlled by a MOS transistor (MP3) and a reference global bit line and connected to a second PMOS transistor (MP2).
N1); the first NMOS transistor (MN1) and the third
Second transistor formed between PMOS transistors (MP3)
An NMOS transistor (MN2); a third NMOS transistor (MN3) formed between the first NMOS transistor (MN1) and the ground terminal (Vss);
A third PMOS transistor (MP3) between the S transistor (MP1) and the second NMOS transistor (MN2)
And a fourth PMOS transistor (MP
4), a fourth NMOS transistor (MN4) controlled by an output signal of the third PMOS transistor (MP3) and having a drain connected to the first PMOS transistor (MP1); and a ground terminal and a fourth NMOS transistor (M).
N4) formed during a fifth NMOS transistor (M
N5); a fifth PMOS transistor (MP5) formed between the first PMOS transistor (MP1) and the output terminal (CREF); and a sixth NMOS transistor (MN) controlled by a signal on the global bit line.
6); the sixth NMOS transistor (MN6) and the first P
Sixth P formed between MOS transistors (MP1)
MOS transistor (MPG); the gate is the sixth PMO
Commonly connected to the gate of the S transistor (MP6),
A seventh PMOS transistor MP7 having a source connected to the drain of the first PMOS transistor MP1
The sixth NMOS transistor (MN6) and the seventh PMO
Seventh NMO formed between S transistors (MP7)
S transistor (MN7); ground terminal (Vss) and seventh transistor
An eighth NMOS connected in parallel with the sixth NMOS transistor MN6 between the NMOS transistors MN7
And a transistor (MN8).

Hereinafter, the operation of the level shifter according to the first embodiment configured as described above will be described. In FIG. 20, the first
The signal (LSEN) applied to the gate of the PMOS transistor (MP1) is a signal for activating the level shifter. That is, when the activation signal (LSEN) transitions to low, the level shifter operates and the output CRE is output.
An F signal is output. Then, when the chip is inactive, the LSEN signal is set to high to interrupt the current flow. LS
When EN goes low, the first PMOS transistor (MP1) is activated, causing the node N1 to go high. Since the node N3 is initially low, the fourth PMOS
The transistor (MP4) is turned on, and the level of the node N3 rises. Accordingly, although the fourth NMOS transistor MN4 is turned on and the level of the output terminal CREF rises, the level of the output terminal can be equal to or lower than the voltage of the reference global bit line BLRG # 2. Here, the first, second, and third NMOS transistors (MN1, MN2, MN3) and the second, third P
Since the MOS transistors (MP2, MP3) constitute one amplifier, the first NMOS transistor (MN1)
And the input of the second NMOS transistor (MN2), the output of the node N3 is amplified.

Since the sixth, seventh, and eighth NMOS transistors (MN6, MN7, MN8) and the sixth and seventh PMOS transistors (MP6, MP7) also constitute one amplifying section, the sixth NMOS transistor (MN6) and the seventh NM
The output of the node N5 is amplified by the input of the OS transistor (MN7). Here, the sizes of the first and sixth NMOS transistors (MN1 and MN6) are equal to the second and seventh NMOS transistors.
If the voltage is higher than that of the S transistors (MN2, MN7), the voltage of the output terminal (CREF) can be made larger than the voltage of the global bit line in proportion to the difference in element size. Conversely, the first and sixth NMOS transistors (MN1, MN
6) the second and seventh NMOS transistors (MN
2, MN7), the voltage of the output terminal (CREF) can be made smaller than the voltage of the global bit line in proportion to the difference in element size. And the first and sixth NMO
If the sizes of the S transistors MN1 and MN6 and the sizes of the second and seventh NMOS transistors MN2 and MN7 are the same, the voltage at the output terminal can be the same as the voltage of the global bit line.

Here, the operation of the level shifter when the first and sixth NMOS transistors (MN1 and MN6) and the second and seventh NMOS transistors (MN2 and MN7) have the same size will be described.

First, when the voltage of the global bit line is higher than the output terminal (CREF), the first and second NMOSs are used.
The transistors (MN1, MN2) reduce the voltage at the node N2 and increase the voltage at the node N3. The increased voltage at the node N3 is fed back to the fourth NMOS transistor MN4 to reduce the on-resistance of the fourth NMOS transistor MN4, so that both the current flowing into the output terminal CREF increases, and eventually the output terminal CREF. To increase the voltage.

Thereafter, the voltage of the node N5 is reduced and the voltage of the node N6 is increased by the sixth and seventh NMOS transistors (MN6, MN7). The reduced voltage of the node N5 is applied to the fifth NMOS transistor (MN5).
Is fed back to the fifth PMOS transistor (MP5) to reduce the on-resistance of the fifth NMOS transistor (MN5), so that the amount of current flowing into the output terminal increases, and eventually the voltage at the output terminal increases. 4th NMOS
The transistor (MN4) and the fifth PMOS transistor (MP5) are inserted to make the voltage rise faster.

If the voltage of the global bit line is lower than the voltage of the output terminal (CREF), the first NMOS
The voltage at the node N2 is increased by the transistor (MN1) and the second NMOS transistor (MN2), and the voltage at the node N3 is amplified so as to decrease. The reduced voltage of the node N3 is applied to the fourth NMOS transistor (MN
4) to increase the on-resistance of the fourth NMOS transistor (MN4).
The amount of current flowing into EF) decreases. Therefore, the voltage of the output terminal (CREF) decreases.

Thereafter, the sixth NMOS transistor (MN
6) and the seventh NMOS transistor (MN7) increase the voltage at node 5 and decrease the voltage at node 6. The increased voltage of the node N5 is applied to the fifth NMOS transistor (MN5) and the fifth PMOS transistor (MP
The on-resistance of the fifth NMOS transistor (MN5) is reduced and the on-resistance of the fifth PMOS transistor (MP5) is increased. Therefore, the amount of current flowing into the output terminal (CREF) decreases,
As a result, the voltage of the output terminal is decreased. Thus, the fifth N
The voltage drop occurs earlier by the MOS transistor (MN5).

FIG. 21 shows a second embodiment of the level shifter of the present invention. As shown in FIG. 21, the first source is controlled by an enable signal (LSEN) for enabling a level shifter and a source is connected to a power supply terminal (Vcc).
A PMOS transistor (MP1); and a second branch-connected from the drain of the first PMOS transistor (MP1).
A PMOS transistor MP2 and a third PMOS transistor MP3; a first NMOS transistor MN1 connected to the second PMOS transistor MP2 and controlled by a reference global bit line signal BLRG_2; MN1) and a first NMOS
A second NMOS transistor MN2 connected between the transistor MN1 and the third PMOS transistor MP3; a second PMOS transistor MP2 connected between the first and second NMOS transistor sources and the ground terminal Vss; A third NMOS transistor (MN3) controlled by the drain voltage of the transistor;
Connected to the drain of the MOS transistor (MP1),
A fourth PMOS transistor MP4 and a fifth PMOS transistor MP5 whose gates are commonly connected.
A fourth NMOS transistor (MN4) controlled by a reference global bit line (BLRG_2) signal and having a drain connected to the drain of the fourth PMOS transistor (MP4); and a drain controlled by the voltage of the output terminal (node 1). 5 PMOS transistor (MP
5) is connected to the drain of the fifth NMOS transistor MN4, and the source is commonly connected to the source of the fourth NMOS transistor MN4.
A MOS transistor (MN5); a sixth NMOS transistor controlled by the drain voltage of the fifth NMOS transistor (MN5) and connected between the sources of the fourth and fifth NMOS transistors (MN4, MN5) and the ground terminal (Vss).
A transistor (MN6); a sixth PMOS transistor (MP6) controlled by an externally applied reference voltage control signal (REFCON) and having a source connected to the drain of the first PMOS transistor (MP1); A seventh NMOS transistor (MN7) connected to the drain of the third PMOS transistor (MP6) and controlled by the drain voltage of the third PMOS transistor (MP3); and a drain of the third PMOS transistor (MP3) controlled by the drain voltage of the fourth NMOS transistor (MN4). And an eighth NMOS transistor MN8 connected between the source of the seventh NMOS transistor MN7 and a reference voltage control signal REFCO
N) and controlled by a seventh NMOS transistor (MN
9th NM connected sequentially between 7) and the ground terminal (Vss)
An OS transistor (MN9) and a tenth NMOS transistor (MN10); and a fourth NMOS transistor (MN
N4) is controlled by the drain voltage, and the source is the first P
A seventh branch is connected from the drain of the MOS transistor (MP1), and the drain is connected to the output terminal (node 1).
And a PMOS transistor (MP7).

FIG. 22 shows the sense amplifier according to the present invention in detail. First, FIG. 7 in which the configuration of FIG.
The main bit line control unit 67 is disposed between the upper and lower two main cell array units 61. Therefore, it is desirable that the sense amplifier configuring the main bit line control unit 67 be configured to be able to sense both the data of the upper main cell array unit 61 and the data of the lower main cell array unit 61. That is, the upper main cell array unit and the lower main cell array unit are configured to share one bit line control unit.

In the drawing, BLGT is a main global bit line connected to the upper cell array, and BLGT
B is a main global bit line connected to the lower cell array unit. CREF is a reference global bit line connected to the upper reference cell.
REFB is a reference global bit line connected to a lower reference cell.

Referring to the structure, the first NMOS transistor (MN) whose source is connected to BLGT and BLGB
1) and; the source is connected to CREF and CREFB;
The gate of the second NMOS transistor MN2 is commonly connected to the gate of the first NMOS transistor MN1.
A third NMOS transistor (MN3) amplifying the BLGT or BLGB signal input through the first NMOS transistor (MN1); a fourth NMOS transistor (MN4) amplifying the CREF or CREFB signal input through the second NMOS transistor (MN2); The first PMOS transistor MP1 and the second PMOS transistor MP2 are commonly connected to the power supply terminal Vcc, and the drains are respectively connected to the output terminal of the first NMOS transistor MN1 and the output terminal of the second NMOS transistor MN2. ) And (1st PMO
The drain of the S transistor is connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor);
Output terminal of MOS transistor (MN1) and second NMOS
Third PM for equalizing the output terminals of the transistor (MN2)
OS transistor (MP3). Here, the first N
A fifth NMOS transistor (MN5) is connected between the source of the MOS transistor (MN1) and the BLGT, and the source of the first NMOS transistor (MN1) and the BLGB.
A sixth NMOS transistor (MN6) is further connected therebetween.

The second NMOS transistor (MN
A seventh NMOS transistor (MN7) is connected between the source of 2) and CREF, and an eighth NMOS transistor (MN8) is further connected between the source of the second NMOS transistor (MN2) and CREFB. Then, a data bus (DA) is supplied by a column selection signal (COLSEL).
TA BUS) and a ninth NMOS transistor (MN9) for selectively switching the output terminal of the sense amplifier;
There is further provided a data bar bus (Data Bar Bus) and a tenth NMOS transistor (MN10) for switching the output terminal of the sense amplifier. Here, a fifth NMOS transistor (MN5) is responsible for switching between the sense amplifier and the BLGT, and a sixth NMOS transistor (MN5).
The transistor (MN6) performs switching between the sense amplifier and BLGB. The seventh NMOS transistor (MN7) performs switching between the sense amplifier and CREF, and the eighth NMOS transistor (MN8).
Is responsible for switching between the sense amplifier and CREFB.

The first configuration of the sense amplifier configured as described above
The operation of the embodiment will be described. The operation of the sense amplifier according to the first embodiment described below is for sensing data stored in the upper main cell. That is, as shown in FIG. 22, the activation signal (BSEL) for activating the fifth NMOS transistor (MN5) and the activation signal (RSEL) for activating the seventh NMOS transistor (MN7), the fifth and seventh NMOS transistors ( When the MN5 and MN7) are activated, the sixth and eighth NMOS transistors (MN6 and MN8) enter an inactive state.

On the contrary, when the sixth and eighth NMOS transistors (MN6 and MN8) are activated, the fifth and seventh NMs are activated.
The OS transistors (MN5, MN7) are deactivated. The sense amplifier is inactivated by the column selection signal (COLSEL) during the initial amplification period, and the external data bus and the internal node of the sense amplifier are cut off. At this time, in order to activate the sense amplifier, the potentials of the nodes SN3 and SN4 are made equal by the sense amplifier equalization signal (SAEQ).

First, the first NMOS transistor (MN
1) and the second NMOS transistor (MN2) are in an inactive state. When nodes SN3 and SN4 become equipotential,
The data of the main cell is transmitted to the upper global bit line (BLGT). Then, the signal is transmitted to the node SN1 through the fifth NMOS transistor (MN5). The reference voltage is transmitted to CREF, and thereafter, the seventh NMO
The signal is transmitted to node SN2 through S transistor (MN7). After the data of the main cell and the reference voltage are sufficiently transmitted to the nodes SN1 and SN2, respectively, the reference voltage of the sense amplifier is changed to the ground voltage. This makes the 3N
The voltage of the node SN2 connected to the gate of the MOS transistor MN3 and the fourth NMOS transistor MN
Since the voltage of the node SN1 connected to the gate of 4) is different, the current flowing through the third NMOS transistor (MN3) and the current flowing through the fourth NMOS transistor (MN4) are also different. Node SN
It appears as a voltage difference between 3 and SN4.

The voltages induced at the nodes SN3 and SN4 are equal to the voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP1).
It is amplified again by the PMOS transistor (MP2). First PMOS transistor (MP1) and second PMO
The signal is sufficiently amplified by the S transistor (MP2). afterwards,
The fifth and seventh NMOS transistors (MN5, MN7) are deactivated.

Further, the first and second NMOS transistors (MN1, MN2) are activated, and the nodes SN3 and SN3 are activated.
4 is fed back to SN1 and SN2 to maintain the amplification. When the feedback roof is completed, the ninth and tenth NMOS transistors (MN9, MN
N10) is activated so that data transmission between the external data bus and data bar bus and the sense amplifier is performed.

The fifth NMOS transistor (MN
5) is activated again to change the voltage of the node SN1 to BLGT.
To the main cell and fed back to the main cell to store it again. According to such an operation of the sense amplifier, the third N
The MOS transistor (MN3) and the fourth NMOS transistor (MN4) constitute the first amplifying unit 100, and the first PM
The OS transistor (MP1) and the second PMOS transistor (MP2) constitute the second amplifier 103. here,
Reference sign SEN is a sense amplifier activation signal, which is a low active signal. SALE signal is a signal for activating the first NMOS transistor (MN1) and the second NMOS transistor (MN2), and is a high active signal.

FIG. 23 shows a second embodiment of the sense amplifier of the present invention. The second amplifier 103 is different from the sense amplifier according to the first embodiment. That is,
The second amplifying unit 103 according to the first embodiment includes first and second PMOS transistors. The drain of the first transistor is connected to the gate of the second transistor.
The configuration is such that the drain of the transistor is connected to the gate of the first transistor.

On the other hand, the second amplifier 103 according to the second embodiment is formed by a latch circuit. That is, PM
The first inverter 103a and the second inverter 103b each include an OS and an NMOS. The common gate of the PMOS and the NMOS transistor that configure the first inverter 103a is the PMOS that configures the second inverter 103b. Connected to the drain of the transistor. Then, P constituting the second inverter 103b
The common gate of the MOS and NMOS transistors is
It is connected to the drain of the PMOS transistor forming the inverter 103a. In the second embodiment, the second
The amplifier 103 is a sense amplifier enable signal (SEN)
Connected to the input end of

In the sense amplifier according to the second embodiment of the present invention, the second amplifier 103 is composed of two inverters, and the first and second inverters 103a, 103a,
03b except that the NMOS transistor 03b is connected to the sense amplifier enable signal (SEN) input terminal.
Since the configuration is the same as the configuration of the sense amplifier according to the embodiment,
The description is omitted below.

FIG. 24 shows an operation timing chart of the first embodiment of such a sense amplifier. FIG. 25 is an operation timing chart of the sense amplifier in the read mode, and FIG. 26 is an operation timing chart of the sense amplifier in the write mode.

As shown in FIG. 24, a word line (W /
L) and the plate line (P / L) are simultaneously transitioned to high, and the sense amplifier enable signal (SEN) is activated to low.

Then, the first and second NMOs shown in FIG.
When the signal (SALE) for activating the S transistors (MN1 and MN2) is activated to a high level, the column selection signal transitions to high. Here, as shown in FIG. 25, the operation of the sense amplifier in the read mode is performed in a section in which both the word line (W / L) and the plate line (P / L) are high, as shown in FIG. 2 A signal (SA) for activating the NMOS transistors (MN1, MN2)
When (LE) changes to a high level, the column selection signal sequentially changes to a high level. Here, the transition operation of the column selection signal is sequentially performed until the section t10.

Unlike the read mode, in the case of the write mode, as shown in FIG. 26, the transition operation of the column selection signal is high for both the word line (W / L) and the plate line (P / W). It is sequentially performed only in a section between t6 and t7 in a certain section. That is, the column selection signals (COLSEL1, COLSEL2, COLSEL)
3,... COLSELn), the signal (SALE) for activating the first and second NMOS transistors (MN1 and MN2) shown in FIG. Then, t
The transition is sequentially made high in the section from 6 to t7. in this way,
After all of the column selection signals have transitioned to high, the word line (W / L) transitions to low once, and when the word line (W / L) transitions again from low to high,
The plate line (P / L) is transitioned low.

FIG. 27 is an operation timing chart of the sense amplifier according to the second embodiment of the present invention. As shown in FIG. 27, the sense amplifier enable signal (SEN)
Word line (W / L) and plate line (P / L)
Is activated low when it transitions high. That is, by activating the sense amplifier enable signal (SEN) earlier than the aforementioned SALE signal,
Sensing speed has been improved.

FIG. 28 is an operation timing chart showing a comparison between a REFCON signal used in the second embodiment of the level shifter according to the present invention and a signal used in the sense amplifier. As shown in FIG. 28, a control signal (REFCO) for stabilizing the output terminal level of the level shifter is provided.
It can be seen that the sense amplifier enable signal (SEN) is activated to be low at the same time that the signal N) transitions to low. That is, before the SALE signal is activated to a high level, the sense amplifier receiving the reference voltage (CREF) from the level shifter can perform a stable sensing operation by previously compensating for the level fluctuation of the output terminal of the level shifter by the REFCON signal. .

Next, FIG. 2 is a view showing the configuration of the cell array of the nonvolatile ferroelectric memory device according to the second embodiment of the present invention.
9, a second embodiment will be described. Comparing the cell array shown in FIG. 29 with the array of FIG. 6, it can be seen that the main bit line control unit and the reference bit line control unit are configured not only below the main cell array unit but also above it. This is to make more efficient use of the layout. That is, as shown in FIG. 29, the main cell array unit 201; the first main bit line control unit 203a and the second main bit line control unit 20 formed on the upper and lower sides of the main cell array unit 201, respectively.
3b; a word line driving unit 205 formed on the left side of the main cell array unit 201; a plate line driving unit 207 formed on the right side of the main cell array unit 201;
The first reference bit line control unit 209a and the second reference bit line control unit 209b are formed on the right side of the second main bit line control units 203a and 203b.

FIG. 30 shows the above structure in more detail centering on the main cell array portion. As shown in FIG. 30, among the main global bit lines configured in the main cell array unit 201, odd-numbered main global bit lines (BLG_n, BLG_n + 2, BLG
_N + 4,. . . ) Are connected to a lower second main bit line control unit 203b, and the even-numbered main global bit lines (BLG_n + 1, B
LG_n + 3, BLG_n + 5,. . . ) Is connected to the first main bit line control unit 203a configured on the upper side. Then, the reference global bit line (BLRG)
_1, BLRG_2) are reference bit line control units 209 formed above and below the main cell array unit 201.
a and 209b, the reference bit line controllers 209a and 209b connect two reference global bit lines (BLRG_1 and BLRG_2) together.

As described above, the main cell array section 201 includes a plurality of sub cell array sections (201_1, 201_1).
_2,. . . ). Each sub-cell array section has a main local bit line connected to a main global bit line. In the figure, a plurality of main local bit lines (BLL1_n, BLL2_) are added to the first main global bit line (BRG_n).
n,. . . BLLn_n). And
Reference global bit lines (BLRG_1, BLRG
_2) is also connected to the reference local bit line as shown. The main local bit line formed for each sub-cell array unit is connected to the main global bit line and the switching elements (SW11 to SW11) as in the previous example.
Wnn). Therefore,
As the switching device is selectively turned on / off, the main local bit line is connected to or disconnected from the main global bit line. Here, the switching elements (SW11, SW1) in an arbitrary sub-cell array unit, for example, the first sub-cell array unit 201_1
2, SW13,. . . SW1n), when any of the turned-on switching elements is connected to an odd-numbered main global bit line (BLG_n or BLG2_n + 2 or BLG_n + 4,...), The data of the main local bit line is transferred to the second main bit line. The signal is transmitted to a main sense amplifier (not shown) in the control unit 203b. If it is connected to an even-numbered main global bit line (BLG_n + 1 or BLG_n + 3 or BLG_n + 5,...), The first
Data is transmitted to a sense amplifier (not shown) in the main bit line control unit 203a.

FIG. 31 shows the first main bit line control unit and the first reference bit line control unit in the configuration of FIG. 29 in more detail. As shown in FIG. 31, the first reference bit line control unit 209a includes one reference sense amplifier 204a, and the first main bit line control unit 203a includes odd-numbered main global bit lines (BLG_n + 1, BLG_n + 3, BLG).
_N + 5,. . . ) For each main sense amplifier (206
_N + 1, 206_n + 3, 206_n + 5,. . . )
Is configured. The odd-numbered main global bit lines (BLG_n, BLG_n + 2, BLG_n)
n + 4,. . . ) Is connected to a second main bit line controller (not shown), so that the second main bit line controller also has a main sense amplifier (not shown).

As in the first embodiment of the present invention shown in FIG. 13, a bit line precharge circuit section (208a_208) is provided between adjacent main global bit lines.
1, 208a_2,. . . ) Are connected. The last main global bit line among the main global bit lines and the reference global bit line (B) connected to the reference sense amplifier 204a.
The bit line precharge circuit unit 210a is also connected between LRG_2). Here, the first reference bit line control unit 207a may be connected to two reference global bit lines (BLRG_1 and BLRG_2).
One of them is connected to the reference sense amplifier 204a,
On the other hand, a constant voltage is applied.

The first main bit line control unit 20
3a, the main sense amplifier (206_n + 1, 206
_N + 3,. . . ) Is commonly applied with a reference voltage (CREF) provided from the reference sense amplifier 204a.

FIG. 32 shows the details of the second main bit line control unit and the second reference bit line control unit in the configuration of FIG. 29 mainly. As shown in FIG. 32, the configurations of the second main bit line control unit 203b and the second reference bit line control unit 209b are the same as those of the first main bit line control unit 203a and the first reference bit line control unit 209a. Are identical. That is, the second reference bit line control unit 209b includes one reference sense amplifier 204b, and the second main bit line control unit 203b includes one main sense bit for each odd-numbered main global bit line (BLG_n, BLG_n + 2,...). Sense amplifier (206_n, 206_n +
2,. . . ) Is placed. One reference global bit line (BLRG_2) is connected to the reference sense amplifier 204b.
, And a constant voltage is applied to the other line. A bit line precharge circuit section (208b__) is provided between adjacent main global bit lines.
1, 208_b2,. . . ) Is connected, and the reference voltage (CRE) provided by the reference sense amplifier 204b is supplied to the main sense amplifiers (206_n, 206_n + 2,...).
F) are commonly applied. The detailed configuration of the sub-cell array unit according to the second embodiment of the present invention is the same as that of the first embodiment of the present invention shown in FIG. The configuration of the sense amplifier, the level shifter, and the bit line precharge level supply unit in the nonvolatile memory device according to the second embodiment of the present invention are the same as those of the first embodiment of the present invention.
This is the same as the embodiment.

[0078]

According to a first aspect of the present invention, there is provided a nonvolatile memory device comprising a main cell array section, a main bit line control section, a reference bit line control section, a word line drive section, and a plate line drive section. Since the number of accesses between the reference cell and the main cell is the same, it is possible to prevent deterioration of the reference cell due to excessive access, thereby extending the life of the element.

The invention according to claims 8 to 10 is provided with a bit line precharge level supply unit for supplying the precharge level of the bit line at the level of the threshold voltage of the NMOS transistor. The sense amplifier can be used more efficiently than the conventional one in which the charge level is the ground voltage.

The invention according to claim 11 has no problem when the number of bit lines is small, that is, when the number of sense amplifiers is small. Because the number will increase,
The level required by the sense amplifier can be supplied through a level shifter.

According to a twelfth aspect of the present invention, when data is first amplified by a transistor in a main sense amplifier, SN1 and SN3 are separated by MN1, and SN
2 and SN4 are separated from each other by MN2,
During the primary amplification by MN3 and MN4, the bit lines are kept disconnected from each other, and cross coupling between adjacent bit lines and reference lines is maintained.
Is minimized, so that noise is reduced. Thereafter, when MN1 and MN2 are turned on, the data signal from which noise has been maximally removed performs a latch amplification operation, and can be sensed with stable data.

According to the seventeenth aspect, the main bit line control section and the reference bit line control section are respectively formed at the upper and lower portions of the main cell array section so that the main cells can be shared, so that the layout can be performed more effectively.

[Brief description of the drawings]

FIG. 1 is a characteristic diagram showing a hysteresis loop of a general ferroelectric substance

FIG. 2 is a diagram showing a cell configuration using a conventional nonvolatile ferroelectric memory device.

FIG. 3 shows a driving circuit for driving a conventional ferroelectric memory device.

FIG. 4 is a timing chart showing a write mode operation of a ferroelectric memory device according to the related art;

FIG. 5 is a timing chart showing an operation in a read mode;

FIG. 6 shows a first example of the nonvolatile ferroelectric memory device according to the present invention.
Cell array configuration diagram according to the embodiment

FIG. 7 is a block diagram showing a cell array when FIG. 6 is repeatedly configured.

FIG. 8 is a configuration diagram of a main cell array unit including a plurality of sub cell array units.

FIG. 9 is a configuration diagram of a main cell array unit in FIG. 6;

FIG. 10 is a detailed configuration diagram of a subcell array unit in FIG. 8;

FIG. 11 is an enlarged view of “A” part in FIG. 10;

FIG. 12 is a drawing showing in more detail a main bit line control unit and a reference bit line control unit of a main cell array unit in the configuration blocks of FIG. 6;

FIG. 13 is a drawing showing the main bit line control unit and the reference bit line control unit in detail in the configuration blocks of FIG. 6;

FIG. 14 is a diagram showing a bit line precharge circuit unit according to the first embodiment of the present invention in more detail;

FIG. 15 is a diagram showing a first embodiment of a bit line precharge level supply unit according to the present invention;

FIG. 16 is a view illustrating a bit line precharge level supply unit according to a second embodiment of the present invention;

FIG. 17 is a view illustrating a bit line precharge level supply unit according to a third embodiment of the present invention;

FIG. 18 is a block diagram showing a simplified configuration of a reference sense amplifier according to the present invention.

FIG. 19 is a configuration block diagram of another embodiment of the reference sense amplifier according to the present invention;

FIG. 20 is a view showing a first embodiment of a level shifter according to the present invention.

FIG. 21 is a view showing a second embodiment of the level shifter according to the present invention.

FIG. 22 is a diagram showing in detail a first embodiment of a sense amplifier using the nonvolatile ferroelectric memory device according to the first embodiment of the present invention;

FIG. 23 is a view showing a second embodiment of the sense amplifier using the nonvolatile ferroelectric memory device according to the first embodiment of the present invention;

FIG. 24 is an operation timing chart of the sense amplifier of FIG. 22;

FIG. 25 is an operation timing chart in the read mode by the sense amplifier of FIG. 22;

FIG. 26 is an operation timing chart in the write mode by the sense amplifier of FIG. 22;

FIG. 27 is an operation timing chart of the sense amplifier of FIG. 23;

FIG. 28 is a drawing comparing and explaining a signal used in the sense amplifier of FIG. 23 and a REFCON signal used in the level shifter of FIG. 21;

FIG. 29 is a configuration diagram of a cell array in the nonvolatile ferroelectric memory device according to the second embodiment of the present invention;

FIG. 30 is a diagram showing the main cell array portion in detail in the configuration of FIG. 29 in more detail;

FIG. 31 is a diagram illustrating a first main bit line control unit and a first reference bit line control unit in the configuration of FIG. 29 in more detail;

FIG. 32 is a diagram illustrating a second main bit line control unit and a second reference bit line control unit in the configuration of FIG. 29 in more detail;

[Explanation of symbols]

61, 201: Main cell array section 63: Word line drive section 65: Plate line drive section 67: Main bit line control section 69: Reference bit line control section 61_1, 61_2, 61_3, ...: Sub cell array section 75_1, 75_2,. ...: Main sense amplifier 77a: Reference sense amplifier 71_1, 71_2 ...: Bit line equalizing switching unit 72_1, 72_2 ...: Bit line precharge switching unit 100: First amplifying unit 103: Second amplifying unit

Claims (17)

[Claims] 1. A plurality of sub-cell arrays, a plurality of main global bit lines and at least one pair of reference global bit lines formed in a direction crossing each sub-cell array, and a main global bit line and a reference in each sub-cell array. A main cell array portion including a main local bit line and a reference local bit line formed corresponding to the global bit line, and a switching element connecting each local bit line and the global bit line; adjacent to the main cell array portion A reference bit line control unit formed of a reference sense amplifier for sensing a signal applied through one of the pair of reference global bit lines and outputting a reference voltage; adjacent to the reference bit line control unit Shape A main bit line control unit that is connected to each main global bit line and senses a signal applied through the global bit line by receiving a reference voltage and arranged for each main global bit line; adjacent to the main cell array unit A word line driver for outputting a drive signal for cell selection; and a plate formed adjacent to the main cell array unit for outputting a drive signal for cell selection together with a drive signal for the word line driver. A nonvolatile ferroelectric memory device comprising a line driver. 2. A sub-cell array unit comprising: a word line and a plate line forming a pair; a word line pair formed in a direction crossing a global bit line; and a local bit formed corresponding to each global bit line. 2. The nonvolatile ferroelectric memory device according to claim 1, further comprising a plurality of unit cells connected to the local bit line based on a line, a local bit line and a word line pair. 3. A unit cell comprising: a ferroelectric capacitor having a gate terminal connected to a word line (W / L), a source terminal connected to a local bit line, and a drain terminal connected to a plate line; 3. The method according to claim 2, wherein the first and second components are FC1).
3. The nonvolatile ferroelectric memory device according to 1. 4. The nonvolatile ferroelectric device according to claim 1, wherein the main bit line controller further comprises a bit line precharge circuit for precharging adjacent global bit lines at a predetermined level. Body memory device. 5. The nonvolatile ferroelectric memory according to claim 1, wherein a constant voltage is applied to the other of the reference global bit lines that is not connected to the reference sense amplifier. apparatus. 6. The reference bit line control unit includes a bit line precharge circuit unit formed between the last main global bit line of the reference global bit line connected to the reference sense amplifier and the main global bit line. 2. The nonvolatile ferroelectric memory device according to claim 1, further comprising: 7. A bit line precharge circuit unit includes: a plurality of global bit lines; a bit line equalization switch unit formed between the global bit lines; and a precharge signal for precharging the bit lines. 7. The non-volatile ferroelectric memory device according to claim 6, further comprising a plurality of bit line precharge switch units for switching to a global bit line. 8. The nonvolatile ferroelectric memory device according to claim 7, wherein the level of the bit line precharge signal is equal to or slightly higher than the threshold voltage of the NMOS transistor. 9. The precharge signal has a source connected to a power supply terminal (V
cc) and is controlled by an activation signal (BQLEN) for activating a bit line precharge level supply unit (MPL1).
And a second PMOS transistor having a source connected to the drain of the first PMOS transistor and a gate connected in common.
An S transistor (MP2) and a third PMOS transistor (MP3), a first NMOS transistor (MN1) controlled by a drain voltage of the third PMOS transistor and selectively outputting a ground voltage, and a second NMOS transistor and a first NMOS transistor. A reference voltage (R)
A second NMOS transistor (MN2) controlled by EF_IN), a third NMOS transistor (MN2) connected between the third PMOS transistor and the first NMOS transistor, and controlled by an output terminal voltage.
An NMOS transistor (MN3); a fourth PMOS transistor (MP4) and a fifth PMOS transistor (MP5) that are branched and connected to a drain of the first PMOS transistor and have a gate commonly connected.
A fourth NMOS transistor (MN4) controlled by a gate voltage of the fourth PMOS transistor and the fifth PMOS transistor to selectively output a ground voltage; a source connected to a drain of the first PMOS transistor; Fifth NMOS transistor (MN5) controlled by drain voltage
And a sixth NMOS transistor (MN) connected between the gate and the drain of the fifth NMOS transistor and controlled by the drain voltage of the second NMOS transistor.
6), the fourth PMOS transistor and the fourth NMOS transistor being controlled by a drain voltage of the third PMOS transistor.
A seventh NMOS transistor MN7 connected between the second NMOS transistor and a fifth NMOS transistor MN7, the fifth NMOS transistor being connected to a drain voltage of the second NMOS transistor;
An eighth NMOS transistor MN8 connected between the transistors, a ninth NMOS transistor MN9 controlled by a drain voltage of the second NMOS transistor and having a drain connected to an output terminal, a source of the ninth NMOS transistor and ground. The tenth terminal is connected between the ends, and the gate and the drain are commonly connected.
An NMOS transistor (MN10); a sixth PMOS transistor (MP6) branched and connected between a power supply terminal and the first PMOS transistor and controlled by an activation signal (BQLEN) for activating a bit line precharge level supply unit. And a seventh PMOS transistor MP7 sequentially connected between the ground terminal of the sixth PMOS transistor and the first PMOS transistor.
A nonvolatile ferroelectric memory device supplied from a bit line precharge level supply unit including one NMOS transistor (MN11). 10. An eleventh NMOS transistor (MN1)
The gate of 1) is commonly connected to the drain, and the second NM
The nonvolatile ferroelectric memory device according to claim 9, wherein the voltage is applied to a gate of the OS transistor (MN2). 11. The reference sense amplifier includes a level shifter that shifts a level of a signal applied through a reference global bit line, and a pull-down control unit that pulls down the reference global bit line, wherein the level shifter includes a level shifter. Enable signal (LSEN) to enable
A first PMOS transistor MP1 whose source is connected to the power supply terminal Vcc, a second PMOS transistor MP2 and a third PMOS transistor branched from the drain of the first PMOS transistor.
A MOS transistor MP3, a first NMOS transistor MN1 connected to the second PMOS transistor and controlled by a reference global bit line signal BLRG_2, and a source commonly connected to the source of the first NMOS transistor; The first NMOS transistor and the third PM
Second NM connected between OS transistor MP3
An OS transistor (MN2), a third NMOS transistor connected between the sources of the first and second NMOS transistors and a ground terminal (Vss), and controlled by a drain voltage of the second PMOS transistor (MP2);
A MOS transistor (MN3), a fourth PMOS transistor (MP4) and a fifth PMOS transistor (MP5) having a source commonly connected to the drain of the first PMOS transistor (MP1) and a gate commonly connected, and a reference global bit line. A fourth NMOS transistor (MN4) having a drain connected to the drain of the fourth PMOS transistor (MP4), and a drain controlled by a voltage at an output terminal, and a drain controlled by the (BLRG_2) signal;
A fifth NMOS transistor MN5 connected to a drain of the OS transistor and having a source commonly connected to a source of the fourth NMOS transistor; and a source controlled by a drain voltage of the fifth NMOS transistor, and a source of the fourth and fifth NMOS transistors. A sixth NMOS transistor MN6 connected between the ground terminal Vss and a reference voltage control signal REFCON applied from the outside;
A sixth PMOS transistor MP6 having a source connected to the drain of the first PMOS transistor, and a seventh NMOS transistor having a source connected to the drain of the sixth PMOS transistor and controlled by a drain voltage of the third PMOS transistor. (MN7)
And an eighth NMOS transistor (MN8) connected between the drain of the third PMOS transistor and the drain of the seventh NMOS transistor, and controlled by a reference voltage control signal (REFCON). A ninth NMOS transistor MN9 sequentially connected between the seventh NMOS transistor and a ground terminal (Vss).
And a tenth NMOS transistor (MN10); a seventh NMOS transistor (MP7) controlled by a drain voltage of the fourth NMOS transistor, a source of which is branched from the drain of the first PMOS transistor and a drain connected to the output terminal. The nonvolatile ferroelectric memory device according to claim 1, wherein: 12. The main sense amplifier is connected to a first NMOS transistor having a source connected to a global bit line connected to an upper main cell and a global bit line connected to a lower main cell, and is connected to an upper reference cell. A source is connected to the reference global bit line and a reference global bit line connected to a lower reference cell, and a gate amplifies a signal voltage input through the first NMOS transistor and a second NMOS transistor commonly connected to a gate of the first NMOS transistor. A third NMOS transistor, a fourth NMOS transistor for amplifying a reference voltage input through the second NMOS transistor, and a second latch circuit configured to amplify the voltage amplified by the third and fourth NMOS transistors secondarily.
2. The nonvolatile ferroelectric memory device according to claim 1, further comprising an amplifier. 13. A latch circuit comprising a first inverter and a second inverter each comprising a PMOS and an NMOS, wherein a PMOS and an NMO constituting a first inverter are provided.
The common gate of the S transistor is connected to the drain of the PMOS transistor forming the second inverter,
PMOS and NMOS constituting the second inverter
13. The nonvolatile ferroelectric memory device according to claim 12, wherein a common gate of the transistors is connected to a drain of a PMOS transistor forming the first inverter. 14. The nonvolatile memory according to claim 13, wherein the drains of the NMOS transistor of the first inverter and the NMOS transistor of the second inverter are commonly connected and connected to a sense amplifier enable signal input terminal. Ferroelectric memory device. 15. A fifth NMOS transistor is further provided between a source of the first NMOS transistor and a global bit line connected to an upper main cell,
A sixth NM is connected between the source of the first NMOS transistor and the global bit line connected to the lower main cell.
An OS transistor is further configured, and a seventh NMOS transistor is further configured between a source of the second NMOS transistor and a reference global bit line connected to the upper reference cell, and connected to a source of the second NMOS transistor and the lower main cell. The nonvolatile ferroelectric memory device of claim 12, further comprising an eighth NMOS transistor between the global ferroelectric memory and the global bit line. 16. The output terminal of the sense amplifier further includes a ninth NMOS transistor selectively switching to a data bus according to a column selection signal and a tenth NMOS transistor selectively switching to a data bar bus. 13. The nonvolatile ferroelectric memory device according to claim 12, wherein: 17. A plurality of sub-cell arrays, a plurality of main global bit lines and at least one pair of reference global bit lines formed in a direction crossing each sub-cell array, and each of the main global bit lines and the reference global bit lines. A main cell array portion including a main local bit line and a reference local bit line formed by the above and a switching element formed between each local bit line and its global bit line; a pair formed adjacent to the main cell array portion; A first reference bit line control unit including a first reference sense amplifier that senses a signal applied through one of the reference global bit lines and outputs a first reference voltage; formed adjacent to the main cell array unit And the same as the first reference voltage. A second reference bit line control unit including a second reference sense amplifier for outputting one voltage; formed adjacent to the first reference bit line control unit, for each even-numbered main global bit line of the plurality of main global bit lines And a main sense amplifier configured to receive a first reference voltage and sense a signal applied through the global bit line.
A main bit line control unit formed adjacent to the second reference bit line control unit, connected to each odd-numbered main global bit line among the plurality of main global bit lines, receiving the second reference voltage, and receiving the second reference voltage; A second main bit line control unit including a main sense amplifier that senses a signal applied through the second main bit line control unit; a word line driving unit formed adjacent to the main cell array unit and outputting a drive signal for cell selection;
A nonvolatile ferroelectric memory device comprising: a plate line driving unit formed adjacent to a main cell array unit and outputting a driving signal for cell selection together with a driving signal output from a word line driving unit. .