JPH08167286A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To provide a semiconductor memory with a small chip area and with a high-speed read. CONSTITUTION: In a DRAM of multi-bit constitution, single end type amplifier driving circuits 231-233 and a double and type amplifier driving circuit 234 are provided corresponding to memory cell blocks B1-B4. Read buses/RBUS 1/RBUS4 are provided one by one corresponding to the amplifier driving circuits 231-234 respectively. Output buffers 251-254 are activated in response to a detection signal/ϕd generated when the operation of a differential amplifier in the amplifier driving circuit 234 is ended.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which data is simultaneously read from a plurality of memory cells in response to one address signal.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the overall structure of a conventional dynamic random access memory (DRAM) of x4 structure, which is one of semiconductor memory devices. Figure 6
Referring to, this DRAM includes memory cell arrays 10 and 11, row decoders 20 and 21, a column decoder 22, and input / output line pairs IO1, / IO1 to IO4, / IO.
4, amplification drive circuits 1 to 4, and read data bus RBUS
1, / RBS1 to RBUS4, / RBUS4, output buffers 5 to 7, and data output terminals 261 to 264. These are formed on one semiconductor chip CH.

Memory cell array 10 is composed of memory cell blocks B1 and B2. Memory cell array 1
1 is composed of memory cell blocks B3 and B4. Each of the memory cell arrays 10 and 11 includes a plurality of word lines. In FIG. 6, only word line WL1 in memory cell array 10 is representatively shown, and only word line WL2 in memory cell array 11 is representatively shown.

Each of the memory cell blocks B1 to B4 has a plurality of bit line pairs intersecting the word lines, and a plurality of memory cells provided corresponding to the intersections of the word lines and the bit line pairs. A plurality of sense amplifiers provided corresponding to the bit line pairs and a plurality of column selection gates provided corresponding to the bit line pairs are provided. Figure 6
Then, bit line pairs BL1, / BL1 to BL4, / BL4
, Memory cells MC1 to MC4, and sense amplifier 141
To 144 and column select gates CS1 to CS4 are representatively shown in memory cell blocks B1 to B4, respectively. The memory cells MC1 to MC4 are N channels M
Access transistor 121 including an OS transistor
To 124 and cell capacitors 131 to 134, respectively.

FIG. 7 is a circuit diagram showing a specific structure of the amplification drive circuit 1 shown in FIG. In addition, another amplification drive circuit 2
4 to 4 are also configured similarly to the amplification drive circuit 1. Referring to FIG. 7, amplification drive circuit 1 includes a differential amplifier 30 and bus drivers 32 and 33. The differential amplifier 30 includes P-channel MOS transistors 301, 302, 30.
5, 306 and N-channel MOS transistor 303,
And 304 and 307. Differential amplifier 30 is activated in response to activation signal φa, and when activated, amplifies the potential difference between input / output lines IO1 and / IO1. The bus driver 32 is a P-channel MOS transistor 321.
And an N-channel MOS transistor 322 and an inverter 323. Transistor 321 precharges read bus / RBUS1 to power supply potential Vcc in response to precharge signal / φp. The transistor 322 is
In response to the potential (output potential) of output node N1 of differential amplifier 30, read bus / RBUS1 is discharged to ground potential Vss. The bus driver 33 includes a P-channel MOS transistor 331 and an N-channel MOS transistor 332.
And an inverter 333. Transistor 331
Is a read bus R in response to the precharge signal / φp.
BUS1 is precharged to the power supply potential Vcc. Transistor 332 discharges read bus RBUS1 to ground potential Vss in response to the potential (output potential) of output node N2 of differential amplifier 30.

FIG. 8 is a circuit diagram showing a specific structure of the output buffer 5 of FIG. In addition, other output buffers 6 to
8 is also configured similarly to the output buffer 5. Referring to FIG. 8, output buffer 5 includes N channel MOS transistors 361 and 362 and logic gates 363 and 3 respectively.
64 and inverters 366 to 369. Output buffer 5 is activated in response to activation signal / φe, and when activated, output data DQ in response to mutually complementary read data on read buses RBUS1 and / RBUS1.
Outputs 1. The output data DQ1 is output to the outside of the semiconductor chip CH via the data output terminal 261.
The other output data DQ2 to DQ4 are also output to the outside of the semiconductor chip CH via the data output terminals 262 to 264 similarly to the output data DQ1.

Next, the operation of the DRAM of the above x4 structure will be described. FIG. 9 is a timing chart showing the read operation of memory cell MC1 in FIG.

First, in the initial state prior to time t1, as shown in FIG. 9 (i), H (logical high) level activation signal / φe is applied to each of output buffers 5-8. Therefore, the output buffers 5 to 8 are inactive. More specifically, H level activation signal / φe is applied to logic gate 363 in output buffer 5 of FIG.
And 364, the transistor 36 is irrelevant regardless of the potentials of the read buses RBUS1 and / RBUS1.
Both 1 and 362 are non-conducting. Therefore, the data output terminal 261 of this output buffer 5 is in a high impedance state. The other output buffers 6 to 8 are also in the same state as this output buffer 5.

Further, as shown in FIG. 9E, an L (logical low) level precharge signal / φp is applied to each of the amplification drive circuits 1 to 4. For example, in amplification drive circuit 1 in FIG. 7, L-level precharge signal / φp is applied to the gate electrode of transistor 321 in bus driver 32 and to the gate electrode of transistor 331 in bus driver 33. Therefore, read buses RBUS1 and / RBUS1 are both precharged to H level.

Then, the row decoder 20 selects one word line, and the row decoder 21 selects one word line. For example, when word lines WL1 and WL2 are selected, data is read out to the bit line pair from all memory cells connected to those word lines WL1 and WL2,
The read data is amplified and latched by the sense amplifier.

Next, the column decoder 22 selects one column selection line. For example, when the column selection line CSL is selected,
Four column select gates C connected to the column select line CSL
S1 to CS4 become conductive. As a result, the data on the bit line pair BL1, / BL1 is transmitted to the input / output line pair IO1, / IO1 via the column selection gate CS1. The data of the bit line pair BL2, / BL2 is transmitted to the input / output line pair IO2, / IO2 via the column selection gate CS2. The data on the bit line pair BL3, / BL3 is the column selection gate CS3.
Is transmitted to the input / output line pair IO3, / IO3 via. Then, the data on the bit line pair BL4, / BL4 is transmitted to the input / output line pair IO4, / IO4 via the column selection gate CS4. I / O line pairs IO1, / IO1 to IO4, / IO
The data of No. 4 are amplified by amplification drive circuits 1 to 4, respectively, and further read buses RBUS1, / RBUS1 to RB
It is supplied to the output buffers 5 to 8 via US4 and / RBUS4. The output data DQ1 to DQ4 are output from the output buffers 5 to 8 via the data output terminals 261 to 264.
Is output.

The read operation in the case where H level data is stored in the memory cell MC1 will be described in detail with reference to FIG. When the potential of the word line WL1 rises at time t1 as shown in FIG.
As shown in (b), the potential of the bit line BL1 slightly rises. Next, at time t2, the sense amplifier 1
When 41 is activated, bit lines BL1 and / BL1
The potential difference between the two is amplified, whereby the potential of the bit line BL1 becomes H level and the potential of the bit line / BL1 becomes L level.

Then, at time t3, activation signal / φe falls as shown in FIG. 9 (i), whereby output buffers 5-8 are activated. However, at time t3
Since the potentials of read buses RBUS1 and / RBUS1 in FIG. 9 remain at the H level as shown in FIGS. 9 (g) and 9 (h), transistors 361 and 362 in output buffer 5 in FIG. 8 are both non-conductive. There is. Therefore, the output buffer 5 does not operate even though it is activated, and its data output terminal 261
Remains in a high impedance state.

Next, at time t4, the column select line CSL
9 rises as shown in FIG. 9, the column select gate CS1 becomes conductive, which causes the potential of the input / output line IO1 to change to the input / output line / IO1 as shown in FIG. 9D.
It becomes higher than the potential of.

Next, at time t5, precharge signal / φp rises as shown in FIG. 9 (e) and activation signal φa rises as shown in FIG. 9 (f). The illustrated precharging transistors 321 and 331 are rendered non-conductive, and the dynamic amplifier 30 is activated. As a result, at time t6, the potential of read bus / RBUS1 becomes L level as shown in FIG. 9 (g). The potential of the read bus RBU1 is
As shown in FIG. 9H, the H level is maintained. Therefore, the transistor 361 in the output buffer 5 shown in FIG. 8 is rendered conductive, and as a result, as shown in FIG. 9 (i), the H-level output data DQ1 is output.
Is output.

As described above, in the conventional DRAM,
Read bus RBUS1, / RBUS1 to RBUS4, / R
Since the BUSs 4 form respective complementary pairs, it is possible to have three states in which both are H level, one is H level and the other is L level, and one is L level and the other is H level. Therefore, the read buses RBUS1, / RB
While one and the other potentials of US1 to RBUS4 and / RBUS4 are both at H level, output buffers 5 to 8 do not operate even if activation signal / φe at L level is applied. Therefore, ineffective data will not be output until the effective data is output. Then, as soon as the potential of one of the paired read buses becomes H level, the output bus operates immediately, so that valid data from the differential drive circuit is immediately output through the output buffer.
Since there is no waiting time in the output buffer, the data read time is short.

[0017]

However, in the above-mentioned configuration, the number of read buses needs to be twice the number of bits of data to be read at the same time. That is, eight read buses are required in the DRAM of the x4 configuration shown in FIG. Therefore, 32 read buses are required for the DRAM of x16 configuration, and 64 read buses are required for the DRAM of x32 configuration.
A book read bus is required. Therefore, the semiconductor chip C
There is a problem that the area of H increases and the manufacturing cost of DRAM increases.

This problem cannot be solved only by setting the number of read buses corresponding to one memory cell block to one. This is because if only one read bus is used, invalid data may be output or the waiting time in the output buffer may increase.

Incidentally, in Japanese Patent Laid-Open No. 5-20870,
For the purpose of reducing the number of data output buses and reducing the chip area, the output data of the data amplifier is transmitted to one input end of the data output circuit by one data output bus and the other input of the data output circuit is transmitted. A semiconductor integrated circuit configured to transmit the data of the data output bus via an inverting circuit is disclosed at the end. However, in this semiconductor integrated circuit, the intermediate potential from the intermediate potential generation circuit is supplied to the data output bus before transmitting the data, and the data output bus is set to the intermediate potential.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device having a multi-bit structure which enables a high-speed read operation and has a small chip area. And

[0021]

A semiconductor memory device according to a first aspect of the present invention comprises a plurality of memory cell blocks, a selection means, a reading means, a plurality of amplification means, a detection means, a plurality of data buses,
And a plurality of output means. Each of the plurality of memory cell blocks includes a plurality of memory cells. The selecting means selects one memory cell in each of the plurality of memory cell blocks in response to one address signal supplied from the outside. The reading means reads the data from the memory cell selected by the selecting means. The plurality of amplifying means are provided corresponding to the plurality of memory cell blocks.
Each of the plurality of amplifying means amplifies the data read from one memory cell in the corresponding memory block. The detection means is at least one of the plurality of amplification means.
Detects that it has completed its operation and generates a predetermined detection signal. The plurality of data buses are provided corresponding to the plurality of amplifying means. Each of the plurality of data buses is connected to the corresponding amplifying means. The plurality of output means are provided corresponding to the plurality of data buses. Each of the plurality of output means is activated in response to the detection signal supplied from the detection means, and supplies the data supplied from the corresponding amplification means via the data bus to the outside.

According to another aspect of the semiconductor memory device of the present invention, a plurality of memory cell blocks, row selecting means, a plurality of input / output line pairs,
A column selection means, a plurality of differential amplification means, a detection means, a plurality of data buses, a plurality of first potential supply means, a plurality of second potential supply means, and a plurality of output means are provided. Each of the plurality of memory cell blocks includes a plurality of word lines, a plurality of bit line pairs, a plurality of bit line pairs, and a plurality of memory cells. The plurality of bit line pairs cross the word lines. The plurality of memory cells are provided corresponding to the intersections of the word lines and the bit line pairs. Each of the plurality of memory cells is connected to one of the bit line pair corresponding to the corresponding word line. In the row selected state, one word line is selected in each of the plurality of memory cell blocks in response to one row address signal supplied from the outside. The plurality of input / output line pairs are provided corresponding to the plurality of memory cell blocks. Each of the plurality of memory cell blocks further includes a plurality of column select gates. A plurality of column selection gates are provided corresponding to a plurality of bit line pairs. Each of the plurality of column selection gates is connected between the corresponding bit line pair and the corresponding input / output line pair. The column selection means renders one column selection gate conductive in each of the plurality of memory cell blocks in response to one column address signal supplied from the outside. The plurality of differential amplification means are provided corresponding to the plurality of input / output line pairs. Each of the plurality of differential amplification means amplifies the potential difference between the corresponding input / output line pair. The detection means detects that at least one of the plurality of differential amplification means has completed its operation, and generates a predetermined detection signal. The plurality of data buses are provided corresponding to the plurality of differential amplification means. The plurality of first potential supply means are provided corresponding to the plurality of data buses. Each of the plurality of first potential supply means supplies the first potential to the corresponding data bus in response to a predetermined precharge signal. The plurality of second potential supply means are provided corresponding to the plurality of data buses. Each of the plurality of second potential supply means supplies the second potential to the corresponding data bus in response to the output potential of the corresponding differential amplifier means. The plurality of output means are provided in response to the plurality of data buses. Each of the plurality of output means is activated in response to the detection signal supplied from the detection means, and supplies output data to the outside in response to the potential of the corresponding data bus.

A semiconductor memory device according to a third aspect of the present invention further comprises an output control line in addition to the configuration of the above second aspect. The output control line is for supplying a detection signal from the detection means to each of the plurality of output means. The detection means includes third potential supply means and fourth potential supply means. The third potential supply means supplies the third potential to the output control line in response to the control signal. The fourth potential supply means supplies the fourth potential to the output control line in response to the output potential of one differential amplification means.

[0024]

In the semiconductor memory device according to claim 1, 1
One memory cell is selected in each memory cell block in response to one address signal. Data is read from the selected memory cell and amplified by the amplifying means corresponding to each memory cell block. When one amplification means completes its operation, a predetermined detection signal is generated. In response to this detection signal, the output means is activated, and the data supplied from the amplifying means via the data bus is output to the outside. Therefore, one data bus is provided for one memory cell block. However, the data amplified by the amplification means is immediately output through the output means. Therefore, the chip area can be further reduced without reducing the data read speed.

According to another aspect of the semiconductor memory device of the present invention, one word line is selected in each memory cell block in response to one row address signal, and each memory cell block is further responded to in one column address signal. At, one column select gate becomes conductive. Therefore,
Data is read from each memory cell block one by one,
It is supplied to the differential amplifying means via the input / output line pair. The differential amplification means amplifies the supplied data and further supplies it to the output means via the data bus. When one differential amplification means completes its operation, a predetermined detection signal is generated.
The output means is activated in response to the detection signal, and the output data is supplied to the outside. In this way, the output means is activated immediately after one differential amplifier means completes its operation, so that invalid data on the read bus is not output via the output means, and the differential amplifier is used. The valid data from the means is immediately output via the output means. for that reason,
The chip area can be further reduced without reducing the data read speed.

In the semiconductor memory device according to the third aspect, in addition to the operation of the second aspect, the third potential is supplied to the output control line in response to the output potential of one differential amplifying means. As a result, the detection signal is supplied to the output means immediately when the one differential amplifying means completes its operation. Therefore, there is almost no waiting time in the output means.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described in detail below with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a DRA according to an embodiment of the present invention.
It is a block diagram which shows the whole structure of M. Referring to FIG. 1, this DRAM is formed on one semiconductor chip CH. This DRAM has memory cell arrays 10 and 1
1, row decoders 20 and 21, and column decoder 22
And input / output line pairs IO1, / IO1 to IO4, / IO4
And single-ended amplification drive circuits 231-233,
Double end type amplifier drive circuit 234 and read bus / RB
US1 to / RBUS4, output control line 24, output buffers 251 to 254, and data output terminals 261 to 264
With.

The memory cell array 10 is composed of memory cell blocks B1 and B2 as in FIG. The memory cell array 11 is composed of memory cell blocks B3 and B4 as in FIG. Memory cell array 12
Are memory cell blocks B1 and B2
It is arranged over. In the memory cell array 11, a plurality of word lines are arranged over the memory cell blocks B3 and B4. In FIG. 1, only one word line WL1 in the memory cell array 10 is representatively shown,
In addition, one word line WL2 in the memory cell array 11
Only shown.

Each of the memory cell blocks B1 to B4 has a plurality of bit line pairs arranged to intersect the word lines and a plurality of memories arranged in a matrix corresponding to the intersections of the word lines and the bit line pairs. A cell, a plurality of sense amplifiers provided corresponding to the bit line pairs, and a plurality of column selection gates provided corresponding to the bit line pairs. In FIG. 1, the memory cell MC1 in the memory cell block B1, the sense amplifier 141, and the column selection gate CS
1 and 1 are typically shown. Also, the memory cell block B
2, the bit line pair BL2, / BL2 and the memory cell MC
2, the sense amplifier 142 and the column selection gate CS2 are representatively shown. In memory cell block B3, bit line pair BL3, / BL3, memory cell MC3, sense amplifier 143, and column selection gate CS3 are representatively shown. In the memory cell block B4, the bit line pair BL4, / BL
4, memory cell MC4, sense amplifier 144, and column selection gate CS4 are representatively shown.

The memory cells MC1 to MC4 include access transistors 121 to 124 and a cell capacitor 1 respectively.
31-134. In the memory cell MC1,
Access transistor 121 is connected between bit line BL1 and cell capacitor 131, and its gate electrode is connected to word line WL1. Other memory cells MC2-4
Is also configured similarly to the memory cell MC1.

Sense amplifiers 141-144 are connected to bit line pairs BL1, / BL1-BL4, BL4, respectively. The sense amplifier 141 uses bit lines BL1 and / B
The potential difference between L1 is amplified and the bit line pair BL1, BL
Latch the data on 1. Other sense amplifiers 142-
144 is also configured similarly to the sense amplifier 141.

Column select gate CS1 is formed of N channel MOS transistors 151 and 161, and is connected between bit line pair BL1, / BL1 and input / output line pair IO1, IO1. The column selection gate CS2 is an N channel MOS
It is composed of transistors 152 and 162, and is connected between bit line pair BL2, / BL2 and input / output line pair IO2, / IO2. The column selection gate CS3 is an N channel M
It is composed of OS transistors 153 and 163, and has a bit line pair BL3 / BL3 and an input / output line pair IO3 / IO.
It is connected between 3 and. The column selection gate CS4 is composed of N channel MOS transistors 154 and 164, and has a bit line pair BL4, / BL4 and an input / output line pair IO4.
/ IO4.

This DRAM further includes a memory cell array 10, input / output line pairs IO1, / IO1 to IO4, / IO4.
And a plurality of column selection lines arranged over the memory cell array 11. In FIG. 1, one column selection line CSL
Only typically shown. Column selection gates CS1 to CS4
The gate electrodes of the transistors 151 to 154 and 161 to 164 therein are all connected to the column selection line CSL.
Therefore, the column selection gates CS1 to CS4 are connected to the column selection line C.
It becomes conductive in response to the potential of SL, and the bit line pair BL
The voltages between 1, / BL1 to BL4, / BL4 are transmitted to the input / output line pairs IO1, / IO1 to IO4, / IO4, respectively.

Row decoder 20 selects one of a plurality of word lines in memory cell array 10 in response to row address signal RAD. The row decoder 21 outputs the row address signal R
In response to AD, one of the plurality of word lines in the memory cell array 11 is selected. Therefore, the row decoder 20
And 21 select two word lines in response to one row address signal RAD supplied from the outside. The column decoder 22 selects one of the plurality of column selection lines in response to one column address signal CAD supplied from the outside.

Input / output line pairs IO1, / IO1 to IO4, /
IO4 is connected to amplification drive circuits 231 to 234, respectively. The amplification drive circuit 231 is provided with the input / output lines IO1 and / or
Amplify the potential difference between IO1 and thereby read bus / RB
Drive US1. The amplification drive circuits 232 and 233 also function similarly to the amplification drive circuit 231. Amplification drive circuit 2
Reference numeral 34 amplifies the potential difference between input / output lines IO4 and / IO4, thereby driving read bus / RBUS4 and generating detection signal / φd when the amplifying operation is completed.

FIG. 2 is a circuit diagram showing a specific structure of the single-end type amplifier drive circuit 231 shown in FIG. The amplification drive circuits 232 and 233 are also configured similarly to the amplification drive circuit 231.

Referring to FIG. 2, single-ended amplifier drive circuit 231 includes differential amplifier 30 and bus driver 32.
With. The differential amplifier 30 includes P-channel MOS transistors 301 and 302 cross-connected to each other,
N-channel MO connected in series with transistor 301
S-transistor 303, N-channel MOS transistor 304 connected in series with transistor 302, and P-channel MOS transistor connected in parallel with transistor 301
Transistor 305, P-channel MOS transistor 306 connected in parallel with transistor 302, and N-channel MOS transistor 307 connected in series with transistors 303 and 304 are provided. I / O line I
O1 is connected to the gate electrode of the transistor 303, and the input / output line / IO1 is connected to the gate electrode of the transistor 304. A predetermined activation signal φa is applied to the gate electrodes of transistors 305 to 307. Therefore,
This amplification drive circuit 231 is activated in response to activation signal φa, and when activated, input / output lines IO1 and / IO are activated.
The potential difference between 1 is amplified.

Bus driver 32 includes P channel MOS transistor 321 connected between the power supply node and read bus / RBUS1 and N channel MOS transistor 3 connected between read bus / RBUS1 and the ground node.
22 and an inverter 323 which logically inverts the potential (output potential) of the output node N1 of the differential amplifier 30 and supplies it to the gate electrode of the transistor 322. Transistor 321 is rendered conductive in response to a predetermined precharge signal / φp, whereby power supply potential Vcc is applied to read bus /.
Supply to RBUS1. That is, the transistor 321
Is for precharging read bus / RBUS1 to power supply potential Vcc. Transistor 322 becomes conductive in response to the output potential of differential amplifier 30, thereby supplying ground potential Vss to read bus / RBUS1. That is, the read bus / RB is included in the transistor 320.
It is for discharging US1. Therefore, bus driver 32 drives read bus / RBUS1 in response to the output potential of differential amplifier 30.

FIG. 3 is a circuit diagram showing a specific structure of the double end type amplifier drive circuit 234 shown in FIG.
Referring to FIG. 3, amplification drive circuit 234 drives differential bus 30 for amplifying the potential difference between input / output lines IO4 and / IO4, and read bus / RBUS4 in response to the output potential of differential amplifier 30. The bus driver 32 and the detection circuit 34 are provided. The differential amplifier 30 has a structure similar to that of the differential amplifier 30 shown in FIG. However, the input / output line IO4 is connected to the gate electrode of the transistor 303,
The gate electrode of the transistor 304 has an input / output line / IO4
Is connected. The bus driver 32 has a configuration similar to that of the bus driver 32 shown in FIG. However, the output node of the bus driver 32 is connected to the read bus / RBUS4.

The detection circuit 34 includes a P-channel MOS transistor 341 connected between the power supply node and the output control line 24, an N-channel MOS transistor 342 connected between the output control line 24 and the ground node. AND connected to the output nodes N1 and N2 of the differential amplifier 30
A gate 343 and a NOR gate 344 receiving the output of AND gate 343 and a predetermined activation signal / φe are provided. The transistor 341 is the above precharge signal / φp.
In response to the power supply potential Vcc
Are supplied to the output control line 24. That is, the transistor 341 is for precharging the output control line 24 to the power supply potential Vcc. The transistor 342 is N
In response to the output of the OR gate 344, it becomes conductive and supplies the ground potential Vss to the output control line 24. That is,
The transistor 342 is for discharging the output control line 24. Therefore, in the detection circuit 34, the potential of one of the output nodes N1 and N2 of the differential amplifier 30 is H.
When the potential of the other level becomes L level, the activation signal / φd of L level is generated.

Referring again to FIG. 1, read bus / RBUS
1 to / RBUS4 are output buffers 251 to 25, respectively.
4 is connected. The output control line 24 is connected to all the output buffers 251 to 254. The output buffers 251 to 254 have data output terminals 261 to 26, respectively.
4 is connected.

FIG. 4 shows the output buffer 25 shown in FIG.
It is a circuit diagram which shows the specific structure of 1. Output buffer 2
52 to 254 are also configured similarly to this output buffer 251.

Referring to FIG. 4, output buffer 251 is an N buffer connected between a power supply node and data output terminal 261.
A channel MOS transistor 361 and an N channel MO connected between the data output terminal 261 and the ground node.
Logic gate 363 receiving S transistor 362, the potential of read bus / RBUS1 and activation signal / φd.
An inverter 365 for logically inverting the potential of the read bus / RBUS1, a logic gate 364 receiving the output of the inverter 365 and the activation signal / φd, and an output of the logic gate 363 to the gate electrode of the transistor 361. And inverters 366 and 367 connected in series for the output of the logic gate 364.
Inverters 368 and 369 connected in series for supplying the two gate electrodes. Therefore, output buffer 251 is activated in response to activation signal / φd, and when activated, supplies output data DQ to data output terminal 261 in response to the potential of read bus / RBUS1.

Next, the operation of this DRAM will be described. First, in the initial state, L level activation signal φa is applied to differential amplifier 30 in amplification drive circuits 231 to 234. The L-level activation signal φa is supplied to the differential amplifier 30.
Since it is applied to the gate electrodes of the transistors 305 to 307 therein, the transistors 305 and 306 are turned on and the transistor 307 is turned off. Therefore, differential amplifier 30 is inactive, and the potentials of output nodes N1 and N2 are both at H level.

Further, an L level precharge signal / φp
Are provided to the transistors 321 and 341 in the bus driver 32 and the detection circuit 34. Therefore, since transistors 321 and 341 are in the conductive state, read buses / RBUS1 to / RBUS4 and output control line 24 are provided.
Are all precharged to H level. In addition, H
Since the level activation signal / φe is applied to the NOR gate 344 in the detection circuit 34, the AND gate 343.
Output of transistor 3 regardless of the output of
42 to the gate electrode. Therefore, the transistor 342 is off.

The H level detection signal / φd is the output control line 2
4 to logic gates 363 and 364 in the output buffers 251 to 254. Therefore, the output of logic gate 363 is always at the L level regardless of the potential of read bus / RBUS1. Further, it is always at the L level regardless of the potential of the read bus / RBUS1 of the output of the logic gate 364. Therefore, an L-level potential is applied to the gate electrodes of transistors 361 and 362, so that transistors 361 and 362 are both non-conductive. Therefore, all the data output terminals 261 to 264 are in a high impedance state.

Then, one row address signal R is externally applied.
When AD is supplied, the row decoder 20 selects one word line in the memory cell array 10, raises the potential of the word line, and the row decoder 21 selects one word line in the memory cell array 11. Then, the potential of the selected word line is raised. When the potential of the word line rises, all access transistors connected to the word line become conductive, and data is read from all memory cells connected to the selected word line to all bit line pairs. .

FIG. 5 is a timing chart showing a read operation when H-level data is stored in the memory cell MC1 in the memory cell block B1. Figure 5
As shown in (a), when the potential of word line WL1 rises from the L level to the H level at time t1, access transistor 121 in memory cell MC1 becomes conductive. Since H-level charges are accumulated in the cell capacitor 131, the charges are stored in the access transistor 121
Through the bit line BL1. Therefore,
As shown in (b), only the potential of the bit line BL1 slightly rises, which causes the bit lines BL1 and / B
A potential difference occurs between L1. Then, when sense amplifier 141 is activated at time t2, the potential of bit line BL1 rises to the H level and the potential of bit line / BL1 falls to the L level.

Then, as shown in FIG. 5 (h), when activation signal / φe falls from H level to L level at time t3, detection circuit 34 of FIG. 3 is activated. But,
Since the differential amplifier 30 of FIG. 3 has not been activated yet,
The potentials of output nodes N1 and N2 are both kept at H level. Therefore, the output of the AND gate 343 is maintained at the H level, so that the output of the NOR gate 344 is maintained at the L level. Therefore, since the transistor 342 is maintained in the non-conductive state, the activation signal / φd is maintained at the H level as shown in FIG. 5 (φ).

Then, one column address signal C is externally applied.
When AD is supplied, the column decoder 22 selects one column selection line and raises the potential of the selected column selection line. For example, as shown in FIG. 5C, the column selection line C
When the potential of SL rises from the L level to the H level at time t4, all column selection gates CS1 to CS4 are rendered conductive, whereby bit line pairs BL1, / BL1 to BL1.
4, the data on / BL4 is the input / output line pair IO1, respectively.
It is transmitted to / IO1 to IO4 and / IO4. Therefore, as shown in FIG. 5D, the potential of input / output line IO1 becomes higher than the potential of input / output line / IO1, and a potential difference occurs between input / output lines IO1 and / IO1.

At time t4 when the column selection line CSL is selected,
As shown in FIGS. 5E and 5F, both precharge signal / φp and activation signal φa rise from the L level to the H level. When the precharge signal / φp goes high, the transistor 32 in the bus driver 32
1 becomes non-conductive, so read bus / RBUS1 to //
The power supply potential Vcc is not supplied to BUS4. Also,
Since the transistor 341 in the detection circuit 34 also becomes non-conductive, the power supply potential Vcc is not supplied to the output control line 24 either. However, read bus / RBUS1 to / RBUS
4 and the output control line 24 are in an electrically floating state, their potentials are maintained at the H level. On the other hand, when the activation signal φa goes high, the differential amplifier 30 in the amplification drive circuits 231-234 is activated. For example, in amplification drive circuit 231 shown in FIG. 2, when activation signal φa at H level is applied to the gate electrodes of transistors 305 to 307 in differential amplifier 30, transistors 305 and 306 are rendered non-conductive, The transistor 307 is turned on. Here, the input / output line I applied to the gate electrode of the transistor 303
Since the potential of O1 is higher than the potential of the input / output line / IO1 given to the gate electrode of the transistor 304, the transistor 303 becomes conductive, which causes the output node N
The potential of 1 decreases. Since the potential of output node N1 is applied to the gate electrode of transistor 302, transistor 302 is rendered conductive. Therefore, the potential of output node N2 rises. In this way, the differential amplifier 30
Is activated, the potential of the output node N1 becomes L level, so that the potential of L level is applied to the gate electrode of the transistor 322 in the bus driver 32, whereby the transistor 322 becomes conductive. Therefore, read bus / RBUS1 is discharged by transistor 322, and the potential of read bus / RBUS1 falls from the H level to the L level at time t5, as shown in FIG. 5 (g).

The differential amplifier 3 in this amplification drive circuit 231
When the differential amplifier 30 in the amplification drive circuit 234 is activated similarly to 0, one of the potentials of the output nodes N1 and N2 becomes L level and the other potential is maintained at H level. The output of the AND gate 343 in the circuit 34 changes from H level to L level. At this time, since the activation signal / φe is already at the L level, NO
The output of the R gate 344 changes from the L level to the H level. This turns on the transistor 342,
The output control line 24 is discharged by the transistor 342. Therefore, as shown in FIG. 5 (i), detection signal / φd falls from the H level to the L level at time t5.

When detection signal / φe attains L level, output buffers 251 to 254 are all activated. For example, in output buffer 251 shown in FIG. 4, detection signal / φd of L level is applied to logic gates 363 and 364.
, The output of the logic gate 363 changes from the L level to the H level because the potential of the read bus / RBUS1 is at the L level. Therefore, the transistor 361
Becomes conductive, and the output data DQ becomes H level as shown in FIG. 5 (j).

On the other hand, when L-level data is stored in memory cell MC1 in memory cell block B1, the potential of read bus / RBUS1 remains the same even when differential amplifier 30 in amplification drive circuit 231 is activated. It is maintained at the H level. However, as in the above case, the amplification drive circuit 2
When differential amplifier 30 in 34 is activated and its operation is completed, detection signal / φd falls from H level to L level. Therefore, output buffer 251 is activated, and transistor 362 in output buffer 251 is rendered conductive, so that output data DQ attains L level.

Although the read operation from the memory cell block B1 has been described above, the read operation from the blocks B2 to B4 is similar to this.

Therefore, according to this embodiment, unlike the conventional DRAM shown in FIG. 6, since one read bus is provided corresponding to each memory cell block, its chip area is smaller than that of the conventional DRAM. Will be smaller than. Further, although one read bus is provided corresponding to each memory cell block, output buffers 251 to 254 are provided.
Is activated after the operation of the differential amplifier 30 in the amplification drive circuit 234 is completed, so that invalid data is not output. Further, similarly to the conventional case where two read buses are provided corresponding to each memory cell block, when valid data appears on read buses / RBUS1 to / RBUS4, output buffers 251 to 25 have already been output.
Since 4 is activated, the amplification drive circuits 231 to 23
Immediately after the operation of the differential amplifier 30 in 4 is completed, the output data DQ1 to DQ4 from the output buffers 251 to 264
Is output. Therefore, the chip area of this DRAM is small and the data reading speed is high.

The embodiment of the present invention has been described in detail above.
The scope of the present invention is not limited to the above embodiments.

For example, in the above-described embodiment, a plurality of word lines are arranged over two memory cell blocks and 2
It is shared by the two memory cell blocks,
A plurality of word lines may be arranged corresponding to each memory cell block. However, in this case, one row decoder is arranged corresponding to each memory cell block. Further, in the above-described embodiment, a plurality of column selection lines are arranged corresponding to four memory cell blocks, but a plurality of column selection lines may be provided corresponding to two memory cell blocks. A plurality of column selection lines may be provided corresponding to one memory cell array block. However, when a plurality of column selection lines are arranged corresponding to two memory cell blocks, 1 is set corresponding to two memory cell blocks.
One column decoder is arranged. When a plurality of column selection lines are arranged corresponding to one memory cell block, one column decoder is arranged corresponding to one memory cell block.

Further, in the above-mentioned embodiment, the DR of the x4 configuration is used.
An example of applying the present invention to AM has been described.
The present invention can be applied to any multi-bit DRAM such as a × 16 configuration. Furthermore, DRAM
Not only static random access memory (S
The present invention can also be applied to RAM) and the like, and the present invention can be implemented in a mode in which various improvements, modifications and variations are added based on the knowledge of those skilled in the art without departing from the spirit of the present invention. Is.

[0061]

According to the semiconductor memory device of the first aspect, since one data bus is provided corresponding to each memory cell block, two data buses are provided corresponding to each memory cell block. The chip area is smaller than that of the above case. Further, even though one data bus is provided corresponding to each memory cell block as described above, a plurality of output means are activated when the operation in at least one amplification state is completed, Ineffective data will not be output, and effective output data will be output as soon as the operation of the amplifying means is completed. Therefore, it is possible to read data at the same speed as when two data buses are provided corresponding to each memory cell block.

According to the semiconductor memory device of the second aspect,
Since one data bus is provided corresponding to each memory cell block, two data buses are provided corresponding to each memory cell block.
The chip area is smaller than when two data buses are provided. Further, even though one data bus is provided corresponding to each memory cell block as described above, a plurality of output means are activated when the operation of at least one differential amplifying means is completed, Ineffective data is not output, and effective data is output as soon as the operation of the differential amplifying means is completed. Therefore, it is possible to read data at the same speed as when two data buses are provided corresponding to each memory cell block.

According to the semiconductor memory device of the third aspect,
In addition to the effect of claim 2, a third signal is generated in response to the control signal.
Is supplied to the output control line, and the fourth potential is supplied to the output control line in response to the output potential of the one differential amplifying means. Therefore, the plurality of data buses are connected to the first and second data buses. The configuration is almost the same as the configuration for supplying the potential. Therefore, a semiconductor memory device having a simple structure can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a DRAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a single-end type amplification drive circuit in FIG.

FIG. 3 is a circuit diagram showing a specific configuration of a double end type amplifier drive circuit in FIG.

FIG. 4 is a circuit diagram showing a specific configuration of the output buffer in FIG.

5 is a timing chart showing a read operation of the DRAM shown in FIG. 1. FIG.

FIG. 6 is a block diagram showing an overall configuration of a conventional DRAM.

7 is a circuit diagram showing a specific configuration of the amplification drive circuit in FIG.

8 is a circuit diagram showing a specific configuration of an output buffer in FIG.

9 is a timing chart showing an operation of the conventional DRAM shown in FIG.

[Explanation of symbols]

10, 11 memory cell array, 20, 21 row decoder, 22 column decoder, 231-234 amplification drive circuit, 24 output control line, 251-254 output buffer, 30 differential amplifier, 32 bus driver, 34 detection circuit, MC1-MC4 Memory cell, BL1, / BL
1 to BL4, / BL4 bit line pair, WL1, WL2
Word lines, CS1 to CS4 column select gates, CSL column select lines, B1 to B4 memory cell blocks, IO1, /
IO1 to IO4, / IO4 I / O line pair, RBUS1,
/ RBUS to RBUS4, / RBUS4 Read bus, D
Q1 to DQ4 output data.

Claims (3)

[Claims] 1. A plurality of memory cell blocks each including a plurality of memory cells, and a selection for selecting one memory cell in each of the plurality of memory cell blocks in response to one address signal supplied from the outside. Means, a reading means for reading data from the memory cell selected by the selecting means, and a read means provided corresponding to the plurality of memory cell blocks, each of which is read from one memory cell in the corresponding memory cell block. A plurality of amplifying means for amplifying data, a detecting means for detecting that at least one of the plurality of amplifying means has completed its operation and generating a predetermined detection signal, and corresponding to the plurality of amplifying means A plurality of data buses, each of which is provided and connected to the corresponding amplifying means, and corresponds to the plurality of data buses. And a plurality of output means, each of which is activated in response to a detection signal supplied from the detection means and supplies the data supplied from the corresponding amplification means via the data bus to the outside. Semiconductor memory device. 2. A plurality of word lines, a plurality of bit line pairs intersecting the word lines, and word lines provided corresponding to the intersections of the word lines and the bit line pairs, respectively. A plurality of memory cell blocks including a plurality of memory cells connected to one of the corresponding bit line pairs, and one word in each of the plurality of memory cell blocks in response to one row address signal supplied from the outside. A row selection unit for selecting a line and a plurality of input / output line pairs provided corresponding to the plurality of memory cell blocks are provided, and each of the plurality of memory cell blocks further corresponds to the plurality of bit line pairs. A plurality of column selection gates, each of which is provided between the corresponding bit line pair and the corresponding input / output line pair, and which is supplied from the outside. Column selection means for making one column selection gate conductive in each of the plurality of memory cell blocks in response to a column address signal, and column input means provided corresponding to the plurality of input / output line pairs, each corresponding input / output line pair. A plurality of differential amplifying means for amplifying a potential difference between the output line pair; a detecting means for detecting that at least one of the plurality of differential amplifying means has completed its operation and generating a predetermined detection signal; A plurality of data buses provided corresponding to the plurality of differential amplification means; and a plurality of data buses provided corresponding to the plurality of data buses, each of which has a first potential on a corresponding data bus in response to a predetermined control signal. And a plurality of first potential supply means for supplying a plurality of data buses, and a plurality of second data buses provided to the corresponding data buses in response to the output potentials of the corresponding differential amplifier means. A plurality of second potential supply means for supplying a plurality of potentials and a plurality of data buses provided corresponding to the plurality of data buses, each of which is activated in response to a detection signal supplied from the detection means. A semiconductor memory device further comprising a plurality of output means for supplying output data to the outside in response to a potential. 3. An output control line for supplying a detection signal from the detection means to each of the plurality of output means, wherein the detection means is responsive to the control signal to provide a third output control line to the output control line. A third potential supply means for supplying a fourth potential, and a fourth potential supply means for supplying a fourth potential to the output control line in response to the output potential of the one differential amplification means. Item 3. The semiconductor memory device according to item 2.