JP2000188404A - Manufacture of thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower temperature for and shorten time required for amorphous silicon crystallization by forming a semiconductor film containing silicon in contact with catalyst for accelerating crystallization, crystallizing the semiconductor film by heating, implanting phosphorus in the crystallized semiconductor film and performing heat annealing. SOLUTION: A base film 31 of silicon oxide is formed on a substrate 30 by sputtering, and a mask 32A and 32B is formed using heat-resistant photoresist. The substrate 30 is placed in plasma 33, and a plasma process is performed. Thereafter, the mask is removed, and an amorphous silicon film is formed by CVD. Further, continuous annealing is performed to accelerate crystallization, and the substrate is patterned to form insular silicon regions 34A and 34B. To selectively perform plasma processing to obtain particularly high-mobility TFT, mask material is placed only in areas where a channel formation region is formed to prevent plasma from being applied thereto.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for obtaining a crystalline semiconductor used for a thin film device such as a thin film insulated gate field effect transistor (thin film transistor or TFT).

[0002]

2. Description of the Related Art Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate field effect transistor (TFT) is manufactured by a plasma CVD method or a thermal CV method.
The amorphous silicon film formed by the method D was crystallized in a device such as an electric furnace at a temperature of 600 ° C. or more for a long time of 12 hours or more. In particular, a longer heat treatment has been required to obtain sufficient characteristics (high electrolytic effect mobility and high reliability).

[0003]

However, such a conventional method has many problems. One is lower throughput and therefore higher cost. For example, assuming that the crystallization step requires 24 hours, if the processing time per substrate is 2 minutes, 720 substrates must be processed simultaneously. However, for example, in a commonly used tubular furnace, at most 50 substrates can be processed at a time, and when only one apparatus (reaction tube) is used, it takes 30 minutes per substrate. I have. That is, 1
In order to achieve a processing time of 2 minutes per sheet, as many as 15 reaction tubes had to be used. This meant that the size of the investment would increase, and that the investment would be significantly depreciated, which would return to the cost of the product.

[0004] Another problem was the temperature of the heat treatment. In general, substrates used for manufacturing TFTs are roughly classified into those made of pure silicon oxide such as quartz glass and non-alkali borosilicate glass such as Corning No. 7059 (hereinafter referred to as Corning 7059). Among them, the former has excellent heat resistance and can be handled in the same manner as a wafer process of a normal semiconductor integrated circuit, so that there is no problem regarding the temperature. However, its cost is high, and it increases exponentially rapidly as the substrate area increases. Therefore, at present, a relatively small area T
Used only for FT integrated circuits.

On the other hand, alkali-free glass has a sufficiently low cost as compared with quartz, but has a problem in terms of heat resistance, and generally has a strain point of about 550 to 650 ° C. Therefore, the heat treatment at 600 ° C. caused a problem of irreversible shrinkage and warpage of the substrate. In particular, it was remarkable for a large substrate having a diagonal exceeding 10 inches. For the above reasons, regarding crystallization of a silicon semiconductor film, a heat treatment condition of 550 ° C. or lower and within 4 hours has been indispensable for cost reduction. An object of the present invention is to provide a method for manufacturing a semiconductor which satisfies such a condition and a method for manufacturing a semiconductor device using such a semiconductor.

[0006]

SUMMARY OF THE INVENTION The present invention comprises a step of forming an insulating film on a substrate, a step of exposing the insulating film to plasma, and forming an amorphous silicon film on the insulating film after the step. Process and the silicon film
It is characterized by having a step of processing at 00 ° C to 600 ° C. Also, the present invention provides a step of forming an insulating film on a substrate, a step of selectively covering the insulating film with a mask material, a step of exposing the substrate to plasma, and an amorphous state on the insulating film after the step. Forming a silicon film at 400 ° C. to 600 ° C.
And a step of selectively etching the silicon film.

Further, the present invention provides a method of forming a thin film transistor, comprising: forming an insulating film on a substrate; selectively covering the insulating film with a mask material; and exposing the substrate to plasma. After the above steps,
A step of forming an amorphous silicon film on the insulating film, a step of treating the silicon film at 400 ° C. to 600 ° C., a step of selectively etching the silicon film, and a step of first covering the silicon film with a mask material. Making the portion formed a channel formation region of a thin film transistor.

The present inventor has made intensive studies and found a method for solving the above problems. The inventor of the present invention formed a base insulating layer on a substrate to prevent impurities from the substrate from entering the semiconductor layer, exposed the insulating layer once to plasma, and then formed amorphous silicon. It has been discovered that by depositing and thermally crystallization, a subsequently deposited silicon semiconductor film is significantly more easily crystallized.

This is explained as follows. Conventionally, 6
The reason why a long time was required as in the case of thermal crystallization at about 00 ° C. was, in part, because it took time to generate crystal nuclei. This time is called the incubation time by the present inventors. According to the observations made by the present inventors, no nuclei are formed at all in the first 6 hours of the crystallization step of 24 hours, and therefore, they are almost in an amorphous state. Nuclei spontaneously develop during the next 6 hours, after which crystallization begins. That is, the conventional method required a latency of 6 to 12 hours. However, the nuclei generated in this way were highly disordered, and the density of the nuclei varied from place to place. Therefore, if there is a region where crystallization is extremely advanced, there is a region where crystallization is not observed at all. Further, as time elapses, nuclei are generated in the region where crystallization is not observed, or the crystallized region is expanded, and the entire surface of the substrate is gradually crystallized. In this way,
It took more than 12 hours to crystallize the entire surface of the substrate.

[0010] When the underlying insulating film is treated with plasma, a substance called a catalyst for generating crystal nuclei is formed. The catalyst for generating a crystal nucleus is, for example, an electric charge or a defect caused by plasma damage, or an adherend of a material constituting a chamber or a substrate. Specifically, it has been clarified that nickel, iron, cobalt, and platinum, which have catalytic effects, have a particularly remarkable effect. Such a catalyst facilitates generation of crystal nuclei and shortens the incubation time. When the amount of the catalyst substance is large, a large number of crystal nuclei are generated. This is presumed from the fact that, for example, when the plasma treatment time is lengthened, the grain size of the obtained crystal becomes fine and the density of crystal nuclei is high.

Further, it should be noted that the generation density of crystal nuclei is extremely uniform. This can also be known by lightly etching and observing the surface of the silicon film crystallized according to the present invention. After plasma treatment, an amorphous silicon film was deposited, and the sample that had been heat-treated at 550 ° C. for 4 hours was slightly etched with hydrofluoric nitric acid, and the surface was observed with an optical microscope, an electron microscope, etc. It can be seen that they are made at substantially equal intervals. This hole is considered to be where the material that was susceptible to etching was present, ie
It shows the density of crystal nuclei in a silicon film. Therefore, it is presumed that the catalyst for generating the crystal nuclei was also distributed at the same density (concentration) as the holes.

Good results can be obtained when the plasma treatment is performed in a parallel plate type plasma generator.
In addition to the parallel plate type, for example, in a chamber using positive column discharge, good results can be obtained by applying an appropriate bias to the substrate. In each case, good results were obtained when nickel, iron or cobalt was used for the electrode for plasma generation. In addition, crystallization was easy when the substrate was heated to 100 to 500 ° C. during the plasma treatment. Specifically, it is preferable to heat to 200 ° C. or higher. This is because the above-mentioned catalyst material is easily obtained at a high temperature.

The plasma is generated in an atmosphere containing nitrogen, oxygen, argon, neon, and krypton, and particularly preferable results are obtained when the proportion is 10% by volume or more. When diluting the gas, it is preferable to dilute it with hydrogen or helium. Further, the silicon film from which particularly good results were obtained is intrinsic or substantially intrinsic. When a different element is analyzed by a known secondary ion mass spectrometry (SIMS) method, the concentrations of carbon, oxygen, and nitrogen are as follows. Each is 1 × 10 ¹⁹
cm ^-3 or less.

According to the present invention, the surface of the base insulating film is subjected to plasma treatment. However, once the substrate subjected to the plasma treatment is exposed to the air, dust, moisture and the like adhere to the substrate, which adversely affects the crystallinity of the silicon film. That is, variations within the substrate increase. In order to avoid such a problem, film formation or plasma processing is performed in a closed system, and at least the amorphous silicon film can be continuously formed without exposing at least the plasma-processed substrate to the atmosphere. It is necessary to have an environment. Further, it is preferable that the surface of the substrate or the insulating film is sufficiently cleaned before the plasma treatment. For example, the surface is present on the surface by ultraviolet irradiation or ozone treatment, or a combination of ultraviolet irradiation and ozone treatment. It is preferable to remove carbon, organic substances, and the like.

[0015]

[Embodiment 1] This embodiment uses a Corning 70
A method for crystallizing a planar amorphous silicon film on a 59 glass substrate will be described. First, R
A 2000-mm-thick silicon oxide underlayer was deposited by the F sputtering method. Then, the silicon oxide film was processed in a nitrogen plasma. The plasma processing apparatus is a parallel plate type apparatus, and its outline is shown in FIG. Note that a nickel alloy was used for the electrode. Chamber 11, gas introduction system 12, exhaust system
· 13 RF power source ··· 14, electrodes ··· 15 and 16, substrate
・ 17 RF plasma ・ ・ 18

The conditions for the plasma treatment are as follows. RF power 20 W or 60 W Reaction gas Nitrogen (flow rate is 100 SCCM) Reaction time 5 minutes Substrate temperature 200 ° C Reaction pressure 10 Pa (The ultimate vacuum is 10 ^-3 Pa or less)

After that, a thickness of 1
A 500 ° amorphous silicon film was formed. After dehydrogenation at 430 ° C. for 1 hour, 50
Solid phase growth was performed at 0 to 580 ° C for 10 minutes to 8 hours.

Note that, for example, in an apparatus having two or more chambers as shown in FIG. 5, the above steps may be continuously performed. In particular, in the above method, after the underlying silicon oxide film is subjected to plasma treatment, the film is once exposed to the atmosphere and then the amorphous silicon film is formed. Since the present invention is sensitive to the state of the surface, dust or the like adheres to the substrate when exposed to the air, which causes variations in the characteristics of the obtained crystalline silicon film.

The apparatus shown in FIG. 5 will be briefly described. The chamber 501 is a sputtering apparatus, and generates power by supplying power from an RF power supply 504 to two electrodes (sample holders) 502 and 503 (backing plate). On each electrode, a sample substrate 506 is placed.
And a target 505, in which case the target is silicon oxide. This chamber is provided with a gas system 507 for introducing a mixed gas of oxygen / argon and a gas system 508 for introducing a nitrogen gas. The gas system 507 is used during the film formation of silicon oxide, and the gas system 508 is used during the plasma processing. Gas is supplied. 509 is an exhaust system.

The chamber 521 is a parallel plate type plasma C
This is a VD device that generates power by supplying power from an RF power source 524 to two electrodes 522 and 523. A sample substrate 525 is placed on the electrode 522. In this chamber, a gas system 526 for introducing a mixed gas of silane / hydrogen is provided, and a film generated by the plasma reaction is formed on the substrate 525. Although not shown in the figures, these chambers have a mechanism for heating the substrate to an appropriate temperature. A preliminary chamber 510 is provided between the two plasma chambers, and a substrate 511 is placed in the preliminary chamber 510.

In the apparatus shown in FIG. 5, after the sputter deposition of silicon oxide is completed in the chamber 501, the atmosphere in the chamber is changed to nitrogen, and nitrogen plasma processing is subsequently performed. At this time, if a silicon oxide target is present, a silicon oxide film is further deposited by sputtering. In order to avoid this problem, the RF power may be reduced or the silicon oxide target may not be exposed to plasma. Fortunately, the RF power required for sputtering is 100 W or more, but as will be described later, the optimum power for plasma processing is 60 W or less, preferably 20 W. Deposition rarely occurred. However, in order to further enhance safety, it is necessary to provide a chamber for forming a silicon oxide film, a chamber for plasma processing, and a chamber for amorphous silicon independently of each other. The amorphous silicon film thus formed is also solid-phase crystallized under the above conditions.

After completion of the solid phase crystal growth, the degree of crystallization was evaluated by the Ar ⁺ laser Raman method. The results are shown in FIGS. In each case, the vertical axis represents the relative intensity when the Raman peak intensity of the standard sample (silicon single crystal) is set to 1. 5 for the sample without plasma treatment
There was no crystallization within 8 hours at 80 ° C. or less. However, it was observed that the sample subjected to the plasma treatment crystallized regardless of whether the RF power was 20 W or 60 W.

Upon careful observation, it can be seen that the progress of crystallization depends on the RF power. That is, low power (2
0W), crystallization is relatively difficult to proceed. Annealing is required for at least one hour to crystallize at 550 ° C. That is, the incubation time is one hour. However, thereafter, crystallization rapidly progresses and becomes almost saturated by annealing for 2 hours. It can be seen that the Raman peak has been crystallized to the same extent as that of the silicon single crystal as the standard sample.

On the other hand, with a high power (60 W), crystallization is relatively easy. For example, in annealing for 4 hours,
Crystallization has already been observed at 480 ° C., and it can be seen that crystallization (latent time 10 minutes) occurs in 10 minutes even after annealing at 550 ° C., and that saturation occurs in 1 hour. However, the degree of crystallization is low, and the Raman intensity is 70% of that of low power (20 W).
It is weak.

This difference can be explained as a difference in crystal nucleus generation density. That is, under low power conditions, the density of the nuclei is low because the concentration of the catalyst substance is low. Therefore, the crystallization temperature is high and the time is long. However, since the nucleus density is low, the crystallinity is good and the Raman intensity is strong. On the other hand, under the condition of high power, the concentration of the catalyst substance is high and the density of the nuclei is high, so that crystallization is easy. However, it is susceptible to interference of other nuclei, and the crystallinity is not good. But,
In each case, crystallization was able to be achieved at a low temperature for a short time as compared with the case where the plasma treatment was not performed. This is clearly the effect of the plasma treatment. In the present embodiment, as a method of controlling the concentration of the catalytic substance, the case of controlling the RF power is taken up. This is an important control item.

[Embodiment 2] This embodiment relates to a method for selectively performing crystallization by selectively performing a treatment of a base oxide film with plasma. FIG.
Shows the method. A 2000-nm-thick silicon oxide film 22 was formed on a substrate (Corning 7059) 21 by sputtering, and a heat-resistant photoresist 24 was spin-coated and patterned. Then, the substrate was exposed to nitrogen plasma as in Example 1, and the exposed portion 23 of the underlying oxide film was subjected to plasma processing. The conditions for the plasma treatment were the same as those in Example 1 except that the RF power was set to 60 W. (Fig. 2 (A))

At this time, since the substrate is kept at a temperature of 200 ° C. or higher, it is desired that the mask material has at least heat resistance enough to withstand it. It is desirable that the mask material can be removed without using plasma when removing the mask material. It is preferable in these respects to use a heat-resistant photoresist as a mask material. In addition, inorganic materials such as titanium nitride, silicon oxide, and silicon nitride can also be used.

After that, a thickness of 15
An amorphous silicon film 25 having a thickness of 00 ° was deposited, followed by annealing at 550 ° C. for 4 hours to perform crystallization. As a result, crystallization progressed centering on a portion not covered with the mask material during the previous plasma treatment, and crystalline silicon 26 was observed. This crystalline silicon expands to a portion covered with the mask material, and has a thickness of about 5 μm.
Advanced. No crystallization was observed in the other areas covered with the mask material.

It should be noted that when comparing the crystallinity of the plasma treated portion with the surrounding 5 μm portion, the latter obtained better crystallinity than the former. Was. This is because in the former, a plurality of nuclei grow crystals independently and they collide and restrict crystal growth, whereas in the latter, there are no nuclei, the direction of crystal growth is one direction, and any crystal growth This is because there is no restriction.

[Embodiment 3] In this embodiment, a plasma treatment is selectively performed to obtain a TFT having particularly high mobility. Specifically, a channel formation region of a TFT (an intermediate region between a source and a drain of an island-shaped semiconductor region,
A mask material is formed only on a portion where a region (below the gate electrode) is to be formed, so that plasma is not applied. However, as shown in Example 2, the region in which crystallization progresses depends on the annealing temperature and time, but since it is several to 10 μm, it is not appropriate that the channel length and channel width are both large. .

In the plasma treatment, defects are generated on the surface of the underlying silicon oxide due to the impact of the plasma, and various adherends adhere. Some of such defects / deposits serve as a catalyst for generating the crystal nuclei of the present invention, but when present in the channel forming region of the TFT, they cause a leak current. Further, in order to obtain a high mobility, it is preferable that the crystallinity is good, and as shown in Example 2, the periphery thereof is better than the portion subjected to the plasma treatment. The process of this embodiment will be described with reference to FIG.

On a substrate (Corning 7059) 30, a silicon oxide base film 31 (thickness 2000 °) was formed by a sputtering method. Then, masks 32A and 32B were formed using a heat-resistant photoresist. The size of the mask was the same as the size of the channel, and each was 5 μm × 15 μm. Alternatively, the patterning of the gate wiring may be used for the patterning of the mask. Since the crystallization is performed after patterning the amorphous silicon film as described later, the same effect can be obtained. Then, the substrate was placed in the plasma 33, and plasma processing was performed as shown in FIG. The used plasma processing apparatus is the same as in the first embodiment. The processing conditions are as follows. RF power 60 W Reaction gas Nitrogen (flow rate is 100 SCCM) Reaction time 5 minutes Substrate temperature 200 ° C Reaction pressure 10 Pa (The ultimate vacuum degree is 10 ^-3 Pa or less)

After the plasma processing, the masks 32A and 32B were removed. Thereafter, an amorphous silicon film having a thickness of 1500 ° was formed by a low pressure CVD method. Monosilane (SiH ₄ ) was used as a source gas. Further, annealing was continuously performed at 550 ° C. for 4 hours to promote crystallization. Next, this was patterned to form island-shaped silicon regions 34A and 34B. Furthermore, plasma CVD
A silicon oxide film 35 having a thickness of 1000 ° was formed as a gate insulating film by the method. As source gas, TEOS (tetraethoxy silane) and oxygen were used. Then, N-type polysilicon was deposited by a low-pressure CVD method, and this was patterned to form gate wiring / electrodes 36A and 36B. (FIG. 3 (B))

Next, impurity doping was performed by a plasma doping method. As doping gas, phosphine (PH ₃ ) is used for N-type, and diborane (B) is used for P-type.
₂ H ₆ ). The accelerating voltage is 80k for phosphine
eV and diborane were 65 keV. Further, the impurity was activated by annealing at 550 ° C. for 4 hours, thereby forming the impurity region 37. For the activation, a method using light energy such as laser annealing or flash lamp annealing can also be used.
(FIG. 3 (C))

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 38 in the same manner as in the normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 39A and 39B in the source and drain regions. Was formed.
(FIG. 3 (D)) FIG. 3 (E) shows a view of the completed TFT circuit viewed from above.
Shown in FIGS. 3A to 3D are cross-sectional views taken along a dashed line in FIG. The field effect mobility of the obtained TFT is 40 to 60 cm ² / Vs for the N channel type, and 30 to 50 c / s for the P channel type.
m ² / Vs.

[Embodiment 4] In this embodiment, a TFT of aluminum gate is manufactured by using the present invention. The process of this embodiment will be described with reference to FIG. A silicon oxide base film 41 on a substrate (Corning 7059) 40
(Thickness: 2000 mm) was formed by sputtering. Then, the substrate was placed in the plasma 42, and plasma processing was performed as shown in FIG. The plasma processing apparatus used is the same as that of the first embodiment. The processing conditions are as follows. RF power 20 W Reaction gas Argon (flow rate is 100 SCCM) Reaction time 5 minutes Substrate temperature 200 ° C Reaction pressure 10 Pa (The ultimate vacuum degree is 10 ^-3 Pa or less)

Thereafter, an amorphous silicon film 43 was formed to a thickness of 1500 ° by a low pressure CVD method. Monosilane (SiH ₄ ) was used as a source gas. In addition, 5
Annealing was performed at 50 ° C. for 4 hours to progress crystallization. (FIG. 4B) Then, this is patterned to form an island-shaped silicon region 4.
4 was formed. Further, a silicon oxide film 45 having a thickness of 1000 ° was formed as a gate insulating film by a plasma CVD method. As source gas, TEOS (tetraethoxy silane) and oxygen were used. Then, an aluminum film (thickness 5000 °) containing 1% silicon is deposited by a sputtering method, and is patterned to form a gate wiring / electrode 46.
Was formed. (FIG. 4 (C))

Next, the substrate was immersed in a 3% solution of tartaric acid in ethylene glycol, anodized by passing a current through the aluminum wiring 46 as an anode using platinum as a cathode. The current is initially applied so that the voltage increases at 2 V / min, and when it reaches 220 V, the voltage is made constant.
The current was stopped when the current became 10 μA / m ² or less. As a result, an anodic oxide 47 having a thickness of 2000 ° was formed. (FIG. 4 (D))

Next, impurity doping was performed by a plasma doping method. As doping gas, phosphine (PH ₃ ) is used for N-type, and diborane (B) is used for P-type.
₂ H ₆ ). The accelerating voltage is 80k for phosphine
eV and diborane were 65 keV. Further, this was laser-annealed to activate the impurity, thereby forming an impurity region 48. The laser used was a KrF laser (wavelength 248 nm), 250 to 3
Five shots of a laser beam having an energy density of 00 mJ / cm ² were irradiated. (FIG. 4E)

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 49 in the same manner as in the normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 50A, 50B in the source and drain regions. Was formed.
(FIG. 3 (F)) The field effect mobility of the obtained TFT is 40 for the N-channel type.
６０60 cm ² / Vs, 30 to 50 cm ^{2 for} P-channel type
/ Vs. A shift register manufactured using this TFT has a drain voltage of 17 V, 6 MHz,
Operation at 11 MHz at 0 V was confirmed.

[0041]

As described above, the present invention is epoch-making in that it promotes lowering the temperature and shortening the time of crystallization of amorphous silicon.
Since the apparatus and the method are very general and excellent in mass productivity, the profits brought to the industry are invaluable.

For example, in the conventional solid-phase growth method, at least 24 hours of annealing were required,
Assuming that the substrate processing time per substrate is 2 minutes, as many as 15 annealing furnaces were required.
Since the number of annealing furnaces can be reduced to less than 1/6, the number of annealing furnaces can be reduced to 1/6 or less. Improvement in productivity and reduction in capital investment due to this leads to a reduction in substrate processing cost, which in turn leads to a reduction in TFT price and thus a new demand. Thus, the present invention is industrially useful and deserves a patent.

[Brief description of the drawings]

FIG. 1 shows an example of an apparatus for implementing the present invention. (See Example 1)

FIG. 2 shows the steps of Example 2. (Example of selective crystallization)

FIG. 3 shows a manufacturing process diagram (cross-sectional view) of a TFT according to Example 3.

FIG. 4 shows a manufacturing process diagram (cross-sectional view) of a TFT according to Example 4.

FIG. 5 shows an example of an apparatus for implementing the present invention. (See Example 1)

FIG. 6 shows the dependence of the Raman scattering intensity of the silicon film obtained in Example 1 on the annealing time. (The peak ratio is the Raman scattering intensity of the standard sample (single crystal silicon) is 1
Relative strength when

FIG. 7 shows the annealing temperature dependence of the Raman scattering intensity of the silicon film obtained in Example 1. (The peak ratio is the Raman scattering intensity of the standard sample (single crystal silicon) is 1
Relative strength when

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Chamber 12 ... Gas introduction system 13 ... Exhaust system 14 ... RF power supply 15, 16 ... Electrode 17 ... Substrate (sample) 18 ... RF plasma 21 ... Substrate 22 ... underlying silicon oxide film 23 ... plasma-treated surface 24 ... mask material 25 ... amorphous silicon film 26 ... crystallized silicon film 27 ... non-crystallized silicon film 30. ··· Substrate 31 ··· Underlying silicon oxide film 32 ··· Mask material 33 ··· Plasma 34 ··· Crystalline silicon region 35 ··· Gate insulating film (silicon oxide) 36 ··· Gate electrode (N-type) 37) Impurity region (source, drain) 38 ... Interlayer insulator 39 ... Source electrode, drain electrode 40 ... Substrate 41 ... Underlying silicon oxide film 42 ... Plasma 43 ... Amorphous silicon region 44 crystalline silicon region 45 gate insulating film (silicon oxide) 46 gate electrode (aluminum) 47 anodic oxide (aluminum oxide) 48 impurity region (source) , Drain) 49 ... interlayer insulator 50 ... source electrode, drain electrode 501 ... sputter chamber 502 ... electrode (sample side) 503 ... electrode (target side) 504 ... RF
Power source 505 Target 506 Sample (substrate) 507 Gas (oxygen / Ar) system 508 Gas (nitrogen) system 509 Exhaust system 510 Preliminary chamber 511 Sample (substrate) 521: Plasma CVD chamber 522: Electrode (sample side) 523: Electrode (opposite side) 524: RF power supply 525: Sample (substrate) 526: Gas (silane) / Hydrogen) system 527 ...
Exhaust system

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa Inside Semiconductor Energy Laboratory Co., Ltd.

Claims (9)

[Claims] 1. A semiconductor film containing silicon is formed in contact with a catalyst for promoting crystallization of the semiconductor film, and the semiconductor film is crystallized by heating to form a crystalline semiconductor film. A method for manufacturing a thin film transistor, wherein phosphorus is introduced and thermal annealing is performed. 2. A method for manufacturing a thin film transistor having a channel formation region, a source region, and a drain region, comprising: forming a semiconductor film containing silicon in contact with a catalyst that promotes crystallization of the semiconductor film; A method for manufacturing a thin film transistor, comprising: crystallizing a semiconductor film to form a crystalline semiconductor film; introducing phosphorus into a source region and a drain region of the crystalline semiconductor film; and performing thermal annealing. Forming a first portion of the semiconductor film in contact with a catalyst that promotes crystallization of the semiconductor film; and heating the first portion of the semiconductor film by heating. And a step of introducing phosphorus into the crystalline semiconductor film and thermally annealing the crystalline semiconductor film to form a crystalline semiconductor film. 4. A method for manufacturing a thin film transistor having a channel formation region, a source region, and a drain region, the method comprising: forming a semiconductor film;
Forming a portion in contact with a catalyst that promotes crystallization of the semiconductor film; and heating the semiconductor film in one direction from the first portion to form a crystalline semiconductor film; A method for manufacturing a thin film transistor, comprising: introducing phosphorus into the source region and the drain region of a crystalline semiconductor film and performing thermal annealing. 5. A step of forming a semiconductor film, comprising: forming a first portion of the semiconductor film in contact with a catalyst for promoting crystallization of the semiconductor film; and heating the first portion of the semiconductor film by heating. A thin film transistor comprising: a step of horizontally promoting crystallization from a portion to a second portion to form a crystalline semiconductor film; and a step of introducing phosphorus into the crystalline semiconductor film and thermally annealing. Method of manufacturing. 6. A method for manufacturing a thin film transistor having a channel formation region, a source region, and a drain region, the method comprising: forming a semiconductor film;
Forming a portion in contact with a catalyst that promotes crystallization of the semiconductor film; and causing the semiconductor film to horizontally crystallize from the first portion to the second portion by heating to form a crystalline semiconductor film. And a thermal annealing after introducing phosphorus into the source region and the drain region of the crystalline semiconductor film. 7. The method according to claim 1, wherein the semiconductor film is an amorphous silicon film. 8. The method for manufacturing a thin film transistor according to claim 1, wherein said semiconductor film is intrinsic or substantially intrinsic. 9. The method according to claim 1, wherein the thermal annealing is performed at 550 ° C. for 4 hours.