JP2000183742A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the correction effect of an integral linearity error(ILE). SOLUTION: Voltage dividing resistors R0-R2n-1 are connected in series to be used for voltage division of a reference voltage. Comparison means C0-C22-2 compare the reference voltage that is divided with a level of an input signal. An encoder 20 generates a digital code depending on the comparison result from the comparison mean C0-C22-2 and provides an output of it. A correction current control means 10 supplies/draws a correction current to/from the voltage division resistors R0-R2n-1 on the basis of a rate of a resistance of the voltage divider resistors R0-R2n-1 from a reference voltage application position to a total resistance of the voltage divider resistors R0-R2n-1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog / digital converter, and more particularly to a flash type analog / digital converter.

[0002]

2. Description of the Related Art A flash (all-parallel) analog / digital converter is a kind of high-speed analog / digital converter. For n-bit conversion, 2 @ n -1 comparators are connected in parallel. , And encodes the output of the comparator to convert it into n-bit data.

There are various types of input stages of the comparator, for example, a type in which a differential pair transistor is driven via an emitter follower, and a type in which a differential pair transistor is directly driven without an emitter follower. .

The type in which a differential pair of transistors is directly driven without an emitter follower can reduce the number of elements as compared with a comparator via an emitter follower.
In addition, since the input voltage range can be easily set to a lower position, it is widely used in recent years.

On the other hand, when a comparator for directly driving a transistor of a differential pair is used, the total sum of input current (base current) flowing from the voltage dividing resistor for dividing the reference voltage to the comparator varies depending on the level of the analog input signal. And ILE (Integral Linearity Error) tended to deteriorate.

Therefore, for example, Japanese Patent Application Laid-Open No. 10-0780
In Japanese Patent Publication No. 37, the supply amount and the supply position of the correction current are determined based on the ratio of the resistance value from the reference voltage application position to the total resistance value, and the determined correction current is supplied from the correction current supply circuit to the voltage dividing resistor. To reduce the ILE.

[0007]

However, in the above-described prior art, since only the correction current is supplied,
There has been a problem that it is not possible to sufficiently respond to changes in input current. That is, a difference occurs between the input current of the comparator and the supplied correction current, and the ILE cannot be sufficiently reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an analog / digital converter having an improved ILE correction effect.

[0009]

According to the present invention, in order to solve the above-mentioned problems, in a flash type analog / digital converter, a plurality of voltage dividing resistors which are connected in series to divide a reference voltage and a voltage dividing resistor are provided. A plurality of comparing means for comparing the levels of the reference voltage and the input signal, an encoder for generating and outputting a digital code corresponding to the comparison result from the comparing means, and the voltage dividing from a position to which the reference voltage is applied. An analog / digital conversion device is provided, comprising: correction current control means for supplying and drawing a correction current to the voltage dividing resistor based on a ratio of a resistance value of the resistor to a total resistance value. You.

Here, the voltage dividing resistors are connected in series to divide the reference voltage. The comparing means compares the level of the divided reference voltage with the level of the input signal. The encoder generates and outputs a digital code according to the comparison result from the comparing means. The correction current control means supplies and draws a correction current to the voltage dividing resistor based on the ratio of the resistance value of the voltage dividing resistor from the reference voltage application position to the total resistance value.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the principle of the analog / digital converter of the present invention. The analog / digital (hereinafter, A / D) converter 1 is a flash type A / D converter.
It is a conversion device.

The voltage dividing resistors R0, R1,..., R2n -1 are:
When voltages VRT and VRB are applied to both ends thereof, the voltage dividing resistors R0, R1,.
A reference voltage consisting of a difference voltage between RT and VRB is divided.

Then, the divided reference voltages are supplied to one input terminal of comparison means (comparators) C0, C1,..., C2n-2. Further, the comparison means C0, C1,.
The other input terminal of C2n-2 has an analog input voltage V
Supply IN.

The output signals of the comparing means C0, C1,..., C2n-2 are supplied to the encoder 20. Each of the comparing means C0, C1,..., C2n-2 has a differential amplifier circuit composed of a differential pair of bipolar transistors.

The encoder 20 includes comparing means C0, C1,
.., Convert the output signal from C2n-2 into a binary number, and generate a digital code of n bits, for example, 8 bits. Incidentally, a differentiating circuit using a logical product circuit may be provided between the comparing means C0, C1,..., C2n-2 and the encoder 20, and the differential result may be supplied to the encoder 20.

The correction current control means 10 supplies and draws a correction current to the voltage dividing resistor based on the ratio of the resistance value of the voltage dividing resistor to the total resistance value from the reference voltage application position, and controls the ILE. Increase the correction effect. Details will be described later.

Next, the configuration of the A / D converter 1 of the present invention will be described. FIG. 2 is a diagram showing a layout of the A / D conversion device 1 and shows a case where 8-bit A / D conversion is performed. FIG. 3 is a simplified schematic diagram of FIG. 2, in which the 6-bit encoder 21 and the 8-bit encoder 22 shown in FIG. 2 are omitted.

In an actual circuit configuration, it is not practical to arrange 256 comparators on a straight line. Therefore, in the figure, 256 comparators are arranged in a manner of being folded back in 8 columns of 32 in each column. Hereinafter, each column of the comparator is referred to as a comparator bank CB.

A total of four 6-bit encoders 21 are arranged between four pairs of adjacent comparator banks CB, and output codes of these encoders 21 are supplied to an 8-bit encoder 22.

A voltage dividing resistor for dividing a reference voltage consisting of a difference voltage between the voltages VRT and VRB includes a metal wiring 11 wired along four pairs of adjacent two rows of comparator banks CB,
An output end for dividing the metal wiring 11 into a predetermined resistance value or the like is formed. Of the wiring parts 111 to 114, the wiring width is made large and the resistance value per unit length is made lower than the other wiring parts. ing.

The input signal VIN is supplied to a node N1.
Node N1 is connected to nodes N2 and N3. Node N2
Is connected to nodes N4 and N5. Node N3 is Node N
6. Connect to N7.

The input signal VIN from the node N4 is C0
It is supplied to both comparator banks C31 and C32 to C63. The input signal VIN from the node N5 is C64
To C95 and C96 to C127 comparator banks C
B. The input signal VIN from the node N6 is C
It is supplied to both comparator banks CB of 128 to C159 and C160 to C191. The input signal VIN from the node N7 is supplied to both comparator banks CB of C192 to C223 and C224 to C255.

Further, a correction current control means 10 for supplying and drawing a correction current for correcting the potential of the voltage dividing resistor to and from the metal wiring 11 is provided. Correction current control means 10
Output the correction current IA1 from the A1 terminal and
Is supplied to the position a1 of the wiring portion 113. The correction current IA2 is output from the terminal A2 and supplied to the position a2 of the metal wiring 11. The correction current IA3 is output from the terminal A3 and supplied to the position a3 of the wiring portion 114 of the metal wiring 11. The correction current IA4 is drawn from the terminal A4 from the position a4 of the wiring portion 111 of the metal wiring 11.

On the other hand, the resistance value R of the metal wiring 11 from the position where the voltage VRT is applied to the position where the voltage VRB is applied is represented by the position
It is divided into four equal parts by s2 and a2. The resistance value from the voltage VRT application position to the wiring portion 111 is R / 8, the resistance value from the voltage VRT application position to the wiring portion 112 is 3R / 8, and the resistance value from the voltage VRT application position to the wiring portion 113 is R / 8. Is 5R / 8, and the resistance from the voltage VRT application position to the wiring portion 114 is 7R / 8.

Next, the ILE will be described. FIG. 4 is a diagram showing a model in which a metal wiring is approximated by a resistor. (A)
FIG. 4B is a diagram showing a state in which current is drawn, and FIG.
FIG. 3 is a diagram for analyzing a potential distribution of a resistor.

Since the input stage of the comparator comprises a differential pair of transistors, the input current supplied from the register string to the comparators C0, C1,..., C2n-2 is such that the potential on the register string is in the range of VRT to VIN. Current.

Here, the register string is approximated by a linear resistor RS as shown in FIGS. The total length of the resistor RS is L2, the resistance per unit length of the resistor RS, that is, the resistance density is ρ, and the resistance of the resistor RS is R. The resistance density ρ is given by the following equation.

[0028]

Ρ = R / L2 (1) In addition, the current I is uniformly drawn when the distance x from one end of the resistor RS is 0 <x <L1. The current density i is given by the following equation.

[0029]

I = I / L1 (2) where 0 ≦ L1 ≦ L2. Further, x of the resistor RS
= L1, a current I2 flows from the other end of the resistor RS. The sign potential in the figure indicates the ground potential.

A current i1 flows from one end of the resistor RS to a position of a distance x on the resistor RS, and a current i2 flows from the other end.
Flows, and a current i is drawn. In this case, the following equation is established.

[0031]

## EQU3 ## i1 * ρx = i2 * (R-ρx) (3)

[0032]

## EQU00004 ## i1 + i2 = i (4) When i1 is deleted from equations (3) and (4),

[0033]

The following equation is obtained: i2 = ipx / R (5) Then, when the equation (5) is integrated in the range of x = 0 to L1, the following equation is established.

[0034]

I2 = I * L1 / 2 * L2 (6) Therefore, the potential VL1 at the distance x = L1 on the resistor RS.
Is represented by the following equation.

[0035]

VL1 = ((L1 / L2) -1) * (L1 / 2 * L2) * RI (7) Here, the ratio L1 / L2 = L, and when L1 = L2, the resistor RS When the maximum current value drawn from the resistor is defined as I0, I = (L1 / L2) * I0 holds, and the potential V (L) at the position of the ratio L on the resistor RS is expressed by the following equation.

[0036]

V (L) = R * IO * (L3−L2) / 2 (8) Next, the correspondence between Expression (8) and the A / D converter 1 in FIG. 3 will be described. A metal wiring 11 made of aluminum wiring or the like and an output terminal for dividing the metal wiring 11 for each predetermined resistance value divides a reference voltage consisting of a difference voltage between the current VRT and the current VRB.

The total sum of the resistance values of the metal wiring 11 is represented by R.
When a current flows from the metal wiring 11 to each comparator, the magnitude of each current is defined as the base current ib of the transistor at the input stage of the comparator.

That is, the potential on the metal wiring 11 becomes the voltage V
The current value input to each comparator from the position where RT to VIN (VRT>VIN> VRB) is set as ib. And 256
The maximum total value of the input current values from the metal wiring 11 in the comparators C0, C1,...
It is assumed that IO = 256 ib.

The resistance value r from the current VRT application position
And the ratio r / R between the sum and the sum R is L. Resistance value r is voltage VRT
Corresponds to the value obtained by adding the resistance values of the voltage dividing resistors from the application position.

FIG. 5 is a diagram showing the potential distribution of the resistor.
FIG. 9 is a graph of Expression (8), in which V (L) is plotted on the vertical axis and L is plotted on the horizontal axis. The figure shows a voltage error with respect to a position on the metal wiring when no correction current is supplied, and shows ILE when no correction current is supplied. This curve has a downward convex shape, and takes a minimum value of −512 Rib / 27 when L = ２.

Next, the correction current control means 10 will be described in detail. FIG. 6 is a diagram showing a circuit configuration of the correction current control means 10. First, the connection relation of each element will be described. The power supply voltage Vcc is connected to the collector and base of the npn transistor Q2, the collectors of the npn transistors Q8 and Q10, and the resistors r3, r4, r6, r7, r8 and r9.

The emitter of the transistor Q2 has npn
The collectors of the transistors Q1, Q3, Q6 are connected.
The base of the transistor Q1 is connected to the collector, and the bases of the transistors Q1, Q3 and Q6 are respectively connected.

The emitter of transistor Q1 is connected to the base of npn transistor Q5. The emitter of transistor Q3 is connected to the emitter of transistor Q6, the collector of transistor Q5 and the base of npn transistor Q7.

The emitter of the transistor Q5 is connected to the emitters of npn transistors Q7, Q9, Q11, Q12 and n
Connected to the collector of pn transistor Q4. The bias voltage Vbias is supplied to the base of the transistor Q4, and the emitter of the transistor Q4 is grounded via the resistor r1.

Transistors Q7, Q9, Q11, Q12
Are connected to each other. The transistors Q7, Q9,
The collectors of Q11 and Q12 are respectively connected. The emitters of the transistors Q8 and Q10 are connected to the base of the transistor Q8 and the collector of the transistor Q11, and the base of the transistor Q8 is connected to the base of the transistor Q10.

Pnp transistors P1, P3, P4, P
The emitters of 5, P6 and P7 are connected to resistors r3, r4 and r, respectively.
6, r7, r8, r9. The bases of the pnp transistors P1, P3, P4, P5, P6, P7 are respectively connected.

The collector of the transistor P1 is connected to the collector of the transistor Q12 and the base of the pnp transistor P2. The emitter of the transistor P2 is connected to the base and the collector of the transistor P3, and the collector of the transistor P2 is grounded.

The collector of npn transistor Q14 is connected to the emitter of transistor Q12. The emitter of npn transistor Q13 is grounded via base resistor r2. The collector of transistor P4 is connected to the collector and base of npn transistor Q16.

The base of transistor Q16 is connected to the bases of transistor Q14 and npn transistor Q18, and the emitter of transistor Q16 is connected to the collector of npn transistor Q15.

The base of the transistor Q15 is the base and collector of the transistor Q13, and the npn transistor Q
17 and the emitter of transistor Q14, and the emitter of transistor Q15 is grounded via resistor r5. The collectors of the transistors P5, P6, P7 are connected to the terminals A1, A2, A3, respectively.

The collector of the transistor Q17 is connected to the emitter of the transistor Q18, and the emitter of the transistor Q17 is grounded via the resistor r10. Transistor Q
The collector of 18 is connected to the A4 terminal.

Next, the operation will be described. Base current of transistor Q5 (corresponding to base current of comparator)
Is ib (Q5), and the collector current of transistor P1 is i
Assuming that c (P1) and the emitter current are ie (P1), the following relationship is established between the transistors Q1, Q3, Q5, and Q7.

[0053]

Vbe (Q7) = Vbe (Q5) + Vbe (Q1) −Vbe (Q3) (9) where Vbe (Q7) is the base of the transistor Q7−
The emitter-to-emitter voltage, Vbe (Q5), is
Is the base-emitter voltage of the transistor Q3, Vbe (Q1)
Is a base-emitter voltage of the transistor Q1.

From the transistor model of Ebers Moll, the following equation is established.

[0055]

Vbe = Vt * ln (ic / is) (10) where is is a proportional constant, Vt = kT / q, k is a Boltzmann constant, T is an absolute temperature, and q is an electron charge. is there.

Here, by substituting equation (10) into equation (9),

[0057]

Ln (ic (P1) / 4is) = ln ((β * ib (Q5)) / is) + ln (ib (Q5) / is) −ln ((β * ib (Q5)) / 2is) (11) where β is a current amplification factor, and β = ic / ib.
ic (P1) is the collector current of transistor P1, and ib (Q5) is the collector current of transistor Q5. Taking expP of equation (11),

[0058]

Ic (P1) / 4is = ((β * ib (Q5)) / is) * (ib (Q5) / is) * (2is / (β * ib (Q5))) (12) Arranging (12),

[0059]

Ic (P1) · ie (P1) = 8ib (13) where the magnitude of the base current ib of the transistor Q5 is 1
The comparators are set to be equal to the magnitude of the input current input from the register string.

The values of the correction currents IA1, IA2, IA3, and IA4 can be changed by the resistance values of r7, r8, r9, and r10. Here, as shown in the schematic diagram of FIG. 3, register string positions a1 (5/8), a2
(3/4), a correction current is supplied to a3 (7/8),
A correction current is drawn from the (1/8) position.

The correction current is IA1 = 32 ib at the point of 5/8 and IA2 = 64i at the point of 3/4.
b, IA3 = 32 ib is supplied at the point 7/8.
Then, IA4 = 16 ib is pulled in from the 1/8 position.

Next, the ILE correction effect will be described.
FIG. 7 is a diagram showing the ILE when only the correction current is supplied. That is, a case where only the correction currents IA1 to IA3 are supplied without drawing the correction current IA4 is shown. The vertical axis indicates ILE, and the horizontal axis indicates the position of the register string.

A curve connecting black diamonds indicates ILE when no correction current is supplied. The curve connecting the black squares shows the correction current IA1 = 32 ib at the position of the ratio L = 5/8.
Shows the increase in the potential of the metal wiring 11 due to the correction current IA1 when is supplied.

The curve connecting the black triangles has a ratio L = 3 /
4 shows an increase in the potential of the metal wiring 11 due to the correction current IA2 when the correction current IA2 = 64 ib is supplied to the position 4. ×
The curve connecting the marks indicates the correction current I at the position of the ratio L = 7/8.
The increase in the potential of the metal wiring 11 due to the correction current IA3 when A3 = 32 ib is supplied is shown.

The curve connecting the asterisks is for all corrections.
The potential increase of the metal wiring 11 due to the correction currents IA1, IA2, IA3 is shown. From the curve connecting the black circles, the error is | ILE | (max) = 2.4Rib.

FIG. 8 is a diagram showing the ILE when the correction current is supplied and drawn according to the present invention. The vertical axis is IL
E. The horizontal axis indicates the position of the register string. The curve connecting the black diamonds is the ILE when no correction current is supplied.
Is shown. The curve connecting the black triangles indicates the increase in the potential of the metal wiring 11 due to the correction current IA1 when the correction current IA1 = 32 ib is supplied at the position of the ratio L = 5/8.

The curve connecting the crosses shows the increase in the potential of the metal wiring 11 due to the correction current IA2 when the correction current IA2 = 64ib is supplied to the position of the ratio L = 3/4. The curve connecting the * marks shows the correction current IA3 = 3 at the position of the ratio L = 7/8.
Metal wiring 1 by correction current IA3 when 2ib is supplied
1 indicates an increase in potential.

The curve connecting the black squares has the ratio L = 1 /
The potential of the metal wiring 11 by the correction current IA4 when the correction current IA4 = 16 ib is drawn from the position 8 is shown. The curves connecting the black circles are for all corrections, and the correction currents IA1,
The increase in the potential of the metal wiring 11 due to IA2, IA3, and IA4 is shown.

From the curve 2 showing the error, the error is |
It can be seen that ILE | (max) = 1.5 Rib is suppressed. As described above, the A / D converter 1 of the present invention supplies the correction current to the register string based on the ratio between the resistance value of the voltage dividing resistor and the total resistance value from the reference voltage application position. Further, the correction current is drawn.

Therefore, by designing in consideration of the amount of supply or pull-in of the correction current based on the equation (8), it is possible to effectively reduce the ILE due to the comparator base current.

[0071]

As described above, the analog-to-digital converter according to the present invention uses the voltage dividing resistor based on the ratio of the resistance of the voltage dividing resistor to the total resistance from the reference voltage application position. The correction current is supplied and drawn.
This makes it possible to enhance the ILE correction effect.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of an analog / digital converter according to the present invention.

FIG. 2 is a diagram showing a layout of an A / D converter.

FIG. 3 is a simplified schematic diagram of an 8-bit flash A / D converter.

FIG. 4 is a diagram showing a model in which a metal wiring is approximated by a resistor. (A) is a figure which shows a mode that the electric current is drawn out, (B) is a figure for analyzing the electric potential distribution of a resistor.

FIG. 5 is a diagram showing a potential distribution of a resistor.

FIG. 6 is a diagram showing a circuit configuration of a correction current control unit.

FIG. 7 is a diagram illustrating an ILE when only a correction current is supplied.

FIG. 8 is a diagram illustrating an ILE when a correction current is supplied and drawn according to the present invention.

[Explanation of symbols]

1 ... A / D converter, 10 ... Correction current control means, 20 ... Encoder, R0-R2n -1 ...
... Divided resistors, C0-C2n-2 ... Comparison means, VRT, V
RB: Voltage, VIN: Analog input voltage.

Claims (3)

[Claims] 1. A flash type analog / digital converter, comprising: a plurality of voltage dividing resistors which are connected in series to divide a reference voltage; and a plurality of comparisons which compare levels of the divided reference voltage and an input signal. Means, an encoder that generates and outputs a digital code according to the comparison result from the comparison means, and, based on a ratio between the resistance value of the voltage dividing resistor and the total resistance value from the application position of the reference voltage, An analog / digital conversion device, comprising: a correction current control unit that supplies and draws a correction current to the voltage dividing resistor. 2. The correction current control means sets a maximum total value of input currents from the voltage dividing resistors of the comparison means to IO,
When the potential at a position where the ratio r / R of the value r obtained by adding the resistance value of the voltage dividing resistor from the application position of the reference voltage to the total resistance value R is L is V (L), V (L) = 2. The analog / digital converter according to claim 1, wherein said correction current is supplied and drawn based on a value of RIO * (L3 -L2) / 2 or a value in the vicinity thereof. 3. When the correction current control means performs 8-bit analog / digital conversion, the ratio r / R is 5
A current having a magnitude of IO / 8 is supplied to a position at or near a position / 8, and a current having a magnitude of IO / 4 is supplied to a position at or near a position where the ratio r / R is 3/4. At the position where the ratio r / R is 7/8 or in the vicinity thereof, IO / 8
3. An analog / digital conversion according to claim 2, wherein a current having a magnitude of I / O is supplied from a position at or near a position where the ratio r / R is 1/8. apparatus.