JP2000183732A - Pll jitter reduction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably oscillate a VCO at a constant frequency by reducing jitter in a frequency oscillated by the VCO in a PLL circuit that is applied to electronic devices in communication, broadcast, computer fields, etc. SOLUTION: A constant current source 4 is connected to an input side of a VCO 3 in the configuration of a conventional PLL circuit via a switch SW 2 controlled by a phase comparator 1. Switches SW1, SW2 are thrown to a position (b) in a PLL lock state. When a capacitor C stores charges in this state, a leakage current flows through a parasitic resistor in existence in the switch SW1 and the capacitor C and an input resistor of the VCO 3 and frequency jitter takes place. A constant current source 4 supplies a current equivalent to the leakage current to nullify a current discharged from the capacitor C and to make the oscillating frequency of the VCO 3 stable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit (Phas
e Locked Loop (phase locked loop)).

[0002]

2. Description of the Related Art The configuration of a conventional PLL circuit is shown in FIG.
R is a resistor, C is a capacitor, and these constitute a low-pass filter. SW is a switch having three contacts, which switches under the control of the output of the phase comparator 1. The phase comparator 1 compares the rising edge of the reference clock with the rising edge of the output of the frequency divider 2 and controls the switch SW accordingly. When the former rising edge is earlier than the latter rising edge, control is performed such that the switch SW is switched to the side a during the period from the former rising edge to the latter rising edge, and the switch SW is set to b during the other periods. Control to switch to the side. When the former rising edge is later than the latter rising edge, the switch SW is used during the period from the latter rising edge to the former rising edge.
Is controlled to be switched to the c side, and in other periods, the switch SW is controlled to be switched to the b side. Also,
When the former rising edge and the latter rising edge are simultaneous, control is performed so that the switch SW is switched to the b side. A VCO (Voltage Controlled Oscillator) 3 is an oscillator whose oscillation frequency is varied by a control voltage from a low-pass filter. The oscillation frequency is low when the voltage of the control signal is low, and the oscillation frequency is high when the voltage of the control signal is high. Will be higher. The frequency divider 2 functions to divide the oscillation frequency of the VCO 3 to lower the frequency.

Next, the operation of the PLL circuit will be described. In FIG. 3, when the rising edge of the reference clock is earlier than the rising edge of the output of the frequency divider 2, the phase comparator 1 sets the switch SW to the a side during the period from the former rising edge to the latter rising edge. Control to switch. Then, the capacitor C is charged through the resistor R, and the voltage of the capacitor C increases. Since this voltage controls the oscillation frequency of the VCO 3, an increase in the voltage acts to increase the oscillation frequency. On the other hand, when the rising edge of the reference clock is later than the rising edge of the output of the frequency divider 2, the phase comparator 1
Control is performed such that the switch SW is switched to the side c during the period from the latter rising edge to the former rising edge. Then, the charge charged in the capacitor C through the resistor R is discharged, and the voltage of the capacitor C decreases. Since this voltage controls the oscillation frequency of the VCO 3, the voltage drop acts to lower the oscillation frequency. The oscillation frequency controlled in this manner is divided by the frequency divider 2 and compared with the reference clock again by the phase comparator 1. Then, the feedback control of the oscillation frequency of the VCO 3 eventually causes the rising edge of the reference clock to coincide with the rising edge of the output of the frequency divider 2 (this is called a PLL locked state). When the PLL is locked, the switch SW remains switched to the b side. Thus, in an ideal case, the capacitor C
Is not charged or discharged and maintains a constant voltage.
Means that oscillation continues at a constant frequency.

[0004]

FIG. 4 shows an equivalent circuit when the PLL is locked. In the PLL locked state, the VCO 3 is required to oscillate stably at a constant frequency. However, even if the switch SW is switched to the b side, the electronic switch does not completely open, and the parasitic resistance R1 exists. Similarly, the capacitor C has a parasitic resistance R2 inside. Further V
CO3 has an input resistor R3. For this reason, the electric charge accumulated in the capacitor C is generated by these resistors R1, R2,
Discharged through R3, the voltage drops. Assuming that currents of I1, I2, and I3 flow through the respective resistors, a total current of I1 + I2 + I3 is discharged from the capacitor C. As a result, the voltage of the capacitor C decreases, and the oscillation frequency of the VCO 3 decreases. Then, the feedback control is repeated again. Such disturbance of the frequency due to parasitic resistance or the like is called jitter.

The present invention solves such a conventional problem, and provides a PLL jitter reduction circuit capable of reducing frequency jitter in a PLL circuit and stably oscillating a VCO at a constant frequency. The purpose is to:

[0006]

According to the present invention, in order to achieve the above object, a current equal to a discharge current of a capacitor is supplied from another source to cancel the current, and a voltage drop of the capacitor due to a parasitic resistance or the like is suppressed. Thus, the VCO is stably oscillated at a constant frequency by reducing the frequency jitter.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a reference frequency and a frequency obtained by dividing the output of a voltage controlled oscillator are compared by a phase comparator. Controls the voltage of the voltage controlled oscillator by the output of P
In the LL circuit, a constant current source is connected to the input side of the voltage controlled oscillator, and the constant current source is connected to the input side of the voltage controlled oscillator. It has an effect that it can oscillate stably at a frequency.

According to a second aspect of the present invention, a switch is provided between the voltage controlled oscillator and the constant current source for connecting and disconnecting the two, and the connection and disconnection of the switch is controlled by the output of the phase comparator. 2. The PLL jitter reducing circuit according to claim 1, wherein the circuit has a function that a current can be supplied from a constant current power supply only when necessary.

According to a third aspect of the present invention, a reference frequency and a frequency obtained by dividing the output of the voltage controlled oscillator are compared by a phase comparator. A PLL circuit for controlling a voltage of a controlled oscillator, wherein a pull-up resistor is connected to an input side of the voltage controlled oscillator, wherein a current equal to a discharging current of a capacitor is supplied from a constant current source. This has the effect that the VCO can stably oscillate at a constant frequency.

According to a fourth aspect of the present invention, a switch is provided between the voltage controlled oscillator and the pull-up resistor for disconnecting and connecting the two, and the disconnection of the switch is controlled by the output of the phase comparator. The P according to claim 3, wherein
This is an LL jitter reduction circuit, and has an effect that a current can be supplied from a constant current power supply only when necessary.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment) FIG. 1 shows a PL according to an embodiment of the present invention.
FIG. 4 is a schematic block diagram of an L circuit, in which the same components as those in the conventional example shown in FIG. 3 are denoted by the same reference numerals. In FIG. 1, R is a resistor, C is a capacitor, and these constitute a low-pass filter. SW1 is a switch having three contacts, and SW2 is a switch having two contacts, which are controlled and switched by the output of the phase comparator 1, respectively. The phase comparator 1 compares the rising edge of the reference clock with the rising edge of the output of the frequency divider 2, and controls the switches SW1 and SW2 accordingly. When the former rising edge is earlier than the latter rising edge, control is performed such that the switches SW1 and SW2 are respectively switched to the a side during the period from the former rising edge to the latter rising edge, and during the other periods, the switches are switched. SW1,
SW2 is controlled to be switched to the b side. When the former rising edge is later than the latter rising edge, control is performed such that the switch SW1 is switched to the c side and the switch SW2 is switched to the a side during a period from the latter rising edge to the former rising edge,
In other periods, the switches SW1 and SW2 are set to b respectively.
Control to switch to the side. If the former rising edge and the latter rising edge are simultaneous,
Control is performed so that the switches SW1 and SW2 are each switched to the b side. The VCO 3 is an oscillator whose oscillation frequency is varied by a control voltage from a low-pass filter. The oscillation frequency is low when the voltage of the control signal is low, and the oscillation frequency is high when the voltage of the control signal is high. The divider 2 is a VCO
The oscillation frequency of No. 3 is divided to lower the frequency. 4 is a constant current source, which is connected to VC
It is connected to the input side of O3.

Next, the operation of the PLL circuit will be described. In FIG. 1, when the rising edge of the reference clock is earlier than the rising edge of the output of the frequency divider 2,
The phase comparator 1 controls the switches SW1 and SW2 to switch to the side a during the period from the former rising edge to the latter rising edge. Then, the capacitor C is charged through the resistor R, and the voltage of the capacitor C increases. Since this voltage controls the oscillation frequency of the VCO 3, an increase in the voltage acts to increase the oscillation frequency. If the rising edge of the reference clock is later than the rising edge of the output of the frequency divider 2, the phase comparator 1
The switch SW1 is switched to the c side during the period from the latter rising edge to the former rising edge, and the switch SW2 is controlled to be held at the a side as it is. Then, the charge charged in the capacitor C through the resistor R is discharged, and the voltage of the capacitor C decreases. Since this voltage controls the oscillation frequency of the VCO 3, the voltage drop acts to lower the oscillation frequency. The oscillation frequency controlled in this manner is divided by the frequency divider 2 and compared with the reference clock again by the phase comparator 1. And VCO3
Feedback control of the oscillation frequency of
Eventually, a PLL lock state is established in which the rising edge of the reference clock coincides with the rising edge of the output of the frequency divider 2. When the PLL is locked, the switches SW1, S
W2 remains switched to the b side.

FIG. 2 is an equivalent circuit in a PLL locked state according to the present embodiment. Assuming that currents I1, I2, and I3 respectively flow through the resistors R1, R2, and R3 in the PLL locked state, a total of I1 + I2 +
A current of I3 will be emitted. However, since a current equal to I1 + I2 + I3 is supplied from the constant current source 4, the current discharged from the capacitor C is thereby canceled and becomes zero. For this reason, the voltage drop of the capacitor C is eliminated, the voltage becomes constant, and VC
The oscillation frequency of O3 is stabilized.

In the above description, an example in which the switch SW2 and the constant current source 4 are combined has been described. However, the present invention can be similarly implemented by using a pull-up resistor instead of the constant current source 4. In that case, the switch SW2 slightly affects the time until the PLL lock state depending on the presence or absence of the switch SW2.
Since the operation after the PLL lock state is the same, it is not always necessary.

[0015]

As described above, according to the present invention, the PLL
In the locked state, the control voltage to the VCO does not fluctuate due to the low-pass filter, so that the VCO can stably oscillate at a constant frequency.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram in a PLL locked state according to the embodiment of the present invention.

FIG. 3 is a schematic block diagram of a PLL circuit in a conventional example.

FIG. 4 is an equivalent circuit diagram in a PLL locked state in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparison circuit 2 Divider 3 VCO 4 Constant current source

Claims (4)

[Claims] In a PLL circuit, a reference frequency and a frequency obtained by dividing the output of a voltage controlled oscillator are compared by a phase comparator, and the voltage of the voltage controlled oscillator is controlled by the output of the phase comparator so that the two match. And a constant current source connected to the input side of the voltage controlled oscillator. 2. A switch according to claim 1, wherein a switch for connecting and disconnecting the voltage controlled oscillator and the constant current source is provided, and the connection and disconnection of the switch is controlled by an output of a phase comparator. PLL jitter reduction circuit. 3. A PLL circuit which compares a reference frequency with a frequency obtained by dividing the output of a voltage controlled oscillator by a phase comparator and controls the voltage of the voltage controlled oscillator by the output of the phase comparator so that the two match. Wherein a pull-up resistor is connected to the input side of the voltage controlled oscillator.
L jitter reduction circuit. 4. A switch according to claim 3, wherein a switch for connecting and disconnecting the voltage controlled oscillator and the pull-up resistor is provided, and the connection and disconnection of the switch is controlled by an output of the phase comparator. PLL jitter reduction circuit.