JP2000183303A - Semiconductor integrated circuit device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a highly reliable capacitor insulating film by preventing the reduction of a pattern accompanying the remove of a hard mask, or the generation of a rough upper face of the pattern, or chipping of a base insulating film. SOLUTION: A ruthenium film 55 and a silicon oxide film 56 being a base electrode 51 of the memory cell of a DRAM are formed, and then a photoresist film 57 is patterned on the silicon oxide film 56. The silicon oxide film 56 is etched by using the photoresist film 57 as a mask, so that a silicon oxide film 52 which is a hard mask can be formed. The photoresist film 57 is removed, and the ruthenium film 55 is etched by using the silicon oxide film 52 as a mask, so that a lower electrode 51 can be formed. A base titanium nitride film 47 is etched, and then a BST film 58 which is capacitor insulating film is piled without removing the silicon oxide film 52.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a ferroelectric (high) dielectric capacitor and a method of manufacturing the same, and more particularly, to a method of forming a conductive material forming a lower electrode of a capacitor with a high aspect ratio or a high anisotropy. The present invention relates to a technology that is effective when applied to a process of forming by nature.

[0002]

2. Description of the Related Art JP-A-10-98162 (Yunogami et al.) Discloses that when a thin film such as Pt is patterned by dry etching using a resist mask, a reaction product having a low vapor pressure is left on the side of the pattern. In order to form fine patterns with high dimensional accuracy,
At least the lower half side is substantially vertical, and using a photoresist of a predetermined pattern having a forward taper or roundness on the outer periphery of the head as a mask, a forward taper reaching the lower end is formed on the side of the thin film pattern. Describes a technique for patterning by dry etching.

Further, Japanese Patent Application Laid-Open No. 8-153707 (Tokashiki) discloses that in the process of forming a fine pattern of platinum or a conductive oxide, contamination such as carbon and halogen elements generated on the surface is removed. After selectively dry-etching the electrode containing ruthenium or ruthenium oxide for the purpose of making the electrode surface state equal to or very close to that at the time of forming the electrode material, oxygen, ozone, water vapor or nitrogen oxide gas is continuously Describes a technique for treating an electrode surface by using the method.

Japanese Patent Application Laid-Open No. Hei 9-266200 (Nakagawa et al.) Discloses the following manufacturing technique for the purpose of easily realizing fine processing of ferroelectrics and platinum. That is,
A laminated film of a lower platinum film, a ferroelectric film and an upper platinum film is formed on a semiconductor substrate and a device insulating film, and a titanium film having a thickness of 1/10 or less of the laminated film thickness is formed. After patterning the titanium film using a photoresist film, the layer thickness is etched with a mixed gas of oxygen and chlorine having an oxygen concentration of 40% using the patterned titanium film. Thereafter, the titanium film is removed by etching with chlorine gas.

[0005]

A large-capacity DRAM (Dynamic Random Access Memory) of 1 Gbit or later is used as a countermeasure for compensating for a decrease in the amount of stored charge due to miniaturization of a memory cell.
Ta ₂ O ₅ having a non-perovskite structure with a relative dielectric constant of about 20 and a relative dielectric constant of 100 or more, and an ABO ₃ type double oxide, that is, a perovskite type double oxide, for a capacitive insulating film of an information storage capacitor element (capacitor). BST that is a thing
High dielectric materials such as ((Ba, Sr) TiO ₃ ), PZT (PbZr _x Ti ₁ -x O ₃ ), PLT (Pb
_{La X Ti 1-X O 3} ), PLZT, PbTiO 3, Sr
The use of ferroelectrics having a crystal structure such as a perovskite structure such as TiO ₃ and BaTiO ₃ has been studied. On the other hand, in the field of non-volatile memories, development of ferroelectric memories utilizing the above-described polarization reversal of ferroelectric materials for storage retention has been advanced.

In the case where the capacitor insulating film of the capacitor is made of the above-mentioned ferroelectric material, or in the case where the above-mentioned ferroelectric material is used for the polarization inversion film of the non-volatile memory, the above-mentioned literature is used. As described, a conductive film for an electrode sandwiching a ferroelectric material film is formed with a material having a high affinity for these materials, for example, a platinum group element (ruthenium (Ru), rhodium (Rh), palladium (Pd)). , Osmium (O
s), iridium (Ir), platinum (Pt)) as a main constituent material, or an oxide thereof.

However, it is generally difficult to etch these platinum group metals or oxides thereof with good anisotropy, and there is a concern that short-circuit failure may occur due to residual etching. For example, a problem in forming a capacitor using Pt is that when a Pt thin film deposited on a substrate is processed by dry etching, a large amount of reaction products having a low vapor pressure adheres to the side surfaces of the pattern. This may cause a short circuit between the capacitors. The presence of such a reaction product adhering to the side surface of the pattern causes the pattern to have poor anisotropy.

That is, according to the study of the present inventors, 1
When a high-dielectric BST is used as a capacitor insulating film for a G-bit DRAM capacitor, the size of the lower electrode is 0.13.
A minimum width of μm and a height of 0.45 μm are required. Further, a space of 0.13 μm is required for the space between the lower electrodes. In order to manufacture such a fine pattern with reliability sufficient for practical use, a taper angle of 80 degrees or more, preferably 85 degrees or more is required. Here, the taper angle refers to an angle between the side wall of the lower electrode and the surface of the base material.

FIG. 27 is a cross-sectional view schematically showing the relationship between the taper angle and the fine pattern shape. Ideally, the taper angle is 90 degrees as shown in FIG.
The pattern bottom width is 0.13 μm and the pattern height is 0.45
If the taper angle is 80 degrees assuming that the diameter is μm (FIG. 27)
In (f)), the pattern height cannot be realized, and the pattern height can be secured only when the taper angle becomes 82 degrees (FIG. 27E). However, in this case, the area of the upper surface of the pattern cannot be secured, and when the taper angle is 85 degrees (FIG. 27D), the area of the upper surface of the pattern can be secured to some extent, and the taper angle is 87 degrees.
In the case of the degree (FIG. 27C), the area of the pattern upper surface can be sufficiently ensured. When the taper angle is 89 degrees (FIG. 27)
In (b)), the state becomes almost ideal.

On the other hand, the present inventors have studied a technique for etching a platinum group metal such as ruthenium or an oxide thereof in an oxygen plasma containing chlorine using a titanium nitride film or the like as a mask, and have studied to increase the flow rate of an etching gas. By over-etching, the taper angle becomes 8
We have developed a technique that has not yet been known to achieve an almost ideal etched cross-sectional shape of 9 degrees.

However, immediately after etching, even if the etching cross-sectional shape is almost ideal, after the process of removing the titanium nitride film or the like as a mask, the etching shape becomes dull due to the mask removing process, that is, the taper angle becomes blunt or There is a problem that pattern thinning occurs.
Further, there is a problem that the surface of the platinum group metal or the oxide thereof as the lower electrode is roughened by the mask removing treatment, and the adhesiveness of the capacitor insulating film is reduced. Further, the underlying insulating film adjacent to the bottom of the columnar lower electrode is scraped by the etching treatment at the time of removing the titanium nitride film serving as the mask. The occurrence of such abrasion increases the difficulty of step coverage of the capacitor insulating film, and is not preferable from the viewpoint of forming a highly reliable capacitor insulating film.

An object of the present invention is to realize a fine etching process of ruthenium or ruthenium oxide suitable for a ferroelectric film such as BST.

Another object of the present invention is to prevent the thinning of the pattern, the occurrence of roughening of the upper surface of the pattern, and the removal of the underlying insulating film in the step of removing the hard mask such as the titanium nitride film, and the formation of a highly reliable capacitive insulating film. It is to provide a forming process.

It is another object of the present invention to simplify a storage capacitor forming step.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described below by dividing them into sections.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) forming a first conductive film to form a lower electrode of an information storage capacitor of a memory cell on a main surface of an integrated circuit wafer; (b) A) forming a first dielectric film pattern made of a high-dielectric or ferroelectric film on the first conductive film; and (c) forming the first dielectric film pattern with the first dielectric film pattern. Patterning the first conductive film by subjecting the first conductive film to dry etching; and (d) forming the memory on the patterned first conductive film and the surface of the first dielectric film pattern. Forming a second dielectric film made of a high dielectric or ferroelectric film to form a capacitive insulating film of the information storage capacitor of the cell; (e) forming the memory cell on the second dielectric film Of the information storage capacitor Forming a second conductive film should constitute.

2. 2. The method for manufacturing a semiconductor integrated circuit device according to item 1, wherein a photoresist pattern is not used in the step (c).

3. 2. The method for manufacturing a semiconductor integrated circuit device according to item 2, wherein the first dielectric film and the second dielectric film are made of substances having substantially the same molecular structure.

4. 3. The method for manufacturing a semiconductor integrated circuit device according to item 3, wherein the first conductive film is made of a platinum group element or an oxide thereof.

5. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) A first conductive material made of a platinum group or an oxide thereof to constitute a lower electrode of an information storage capacitor element of a memory cell on a main surface of an integrated circuit wafer Forming a film; (b) forming a first inorganic film pattern on the first conductive film; and (c) forming a first inorganic film pattern on the first conductive film. Patterning the first conductive film by performing dry etching; and (d) information storage capacitance of the memory cell on the patterned first conductive film and the first inorganic film pattern surface. Forming a second dielectric film which is to constitute a capacitive insulating film of the device; (e) a second electrode which is to constitute an upper electrode of an information storage capacitor of the memory cell on the second dielectric film. Step of forming conductive film

6. 5. The method for manufacturing a semiconductor integrated circuit device according to the item 5, wherein a photoresist pattern is not used in the step (c).

7. 7. The method for manufacturing a semiconductor integrated circuit device according to item 6, wherein the first inorganic film pattern is formed of a silicon oxide film.

8. 6. The method for manufacturing a semiconductor integrated circuit device according to item 6, wherein the first inorganic film pattern is made of a compound containing metal and nitrogen.

9. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) A first electrode made of ruthenium, iridium, or an oxide thereof to constitute a lower electrode of an information storage capacitor element of a memory cell on a main surface of an integrated circuit wafer (B) forming a first platinum film pattern on the first conductive film; and (c) forming the first conductive film in a state where the first platinum film pattern is present. Patterning the first conductive film by performing dry etching on the film; (d) information of the memory cell on the patterned first conductive film and the first platinum film pattern surface; Forming a first dielectric film made of a high dielectric or ferroelectric film to constitute a capacitance insulating film of the storage capacitor; (e) storing information of the memory cell on the first dielectric film capacity Forming a second conductive film for constituting an upper electrode of the child.

10. 9. The method for manufacturing a semiconductor integrated circuit device according to item 9, wherein a photoresist pattern is not used in the step (c).

11. 13. The method for manufacturing a semiconductor integrated circuit device according to item 10, wherein the first conductive film is made of ruthenium or an oxide thereof.

12. 13. The method for manufacturing a semiconductor integrated circuit device according to item 10, wherein the first conductive film is made of iridium or an oxide thereof.

13. A semiconductor integrated circuit device having the following configuration: (a) an integrated circuit substrate having a first main surface; (b) being disposed on the first main surface at an interval equal to or less than the width thereof. A plurality of columnar lower electrodes each forming an information storage capacitor element of a memory cell; (c) a plurality of columnar lower electrodes provided on the side and upper surfaces of each of the columnar lower electrodes, forming a capacitance insulating film of the information storage capacitor element of the memory cell; A first dielectric film made of a dielectric or ferroelectric film; (d) information storage of a memory cell provided on the first dielectric film provided on the side and top surfaces of each of the columnar lower electrodes; A single or a plurality of upper electrodes constituting a capacitive element, wherein each of the plurality of columnar lower electrodes has an upper surface area of 25% or less of an area of a bottom surface thereof.
The side surface has a taper.

14. 13. The semiconductor integrated circuit device according to item 13, wherein at least a part of the plurality of columnar lower electrodes has a substantially triangular cross section in a direction in which the width is small.

15. 14. The semiconductor integrated circuit device according to item 14, wherein each of the plurality of columnar lower electrodes has an aspect ratio of 2 or more in a cross section in a direction in which the width is narrow.

16. 14. The semiconductor integrated circuit device according to item 14, wherein each of the plurality of columnar lower electrodes has an aspect ratio of 3 or more in a cross section in a direction in which the width is narrow.

17. A semiconductor integrated circuit device having the following configuration: (a) an integrated circuit substrate having a first main surface; (b) being disposed on the first main surface at an interval equal to or less than the width thereof. A plurality of columnar lower electrodes each forming an information storage capacitor element of a memory cell; (c) a plurality of columnar lower electrodes provided on the side and upper surfaces of each of the columnar lower electrodes, forming a capacitance insulating film of the information storage capacitor element of the memory cell; A first dielectric film made of a dielectric or ferroelectric film; (d) information storage of a memory cell provided on the first dielectric film provided on the side and top surfaces of each of the columnar lower electrodes; A single or a plurality of upper electrodes constituting a capacitance element; and a contribution of a capacitance to an information storage capacitance element of a corresponding memory cell in a portion corresponding to an upper surface of each of the plurality of columnar lower electrodes is 3% or less. is there.

18. 17. The semiconductor integrated circuit device according to item 17, wherein at least a part of the plurality of columnar lower electrodes has a substantially triangular cross section in a direction in which the width is small.

19. 18. The semiconductor integrated circuit device according to item 18, wherein each of the plurality of columnar lower electrodes has an aspect ratio of 2 or more in a cross section in a direction in which the width is narrow.

20. 18. The semiconductor integrated circuit device according to the item 18, wherein each of the plurality of columnar lower electrodes has an aspect ratio of 3 or more in a narrow direction.

21. A semiconductor integrated circuit device having the following configuration: (a) an integrated circuit substrate having a first main surface; (b) being disposed on the first main surface at an interval equal to or less than the width thereof. A plurality of columnar lower electrodes each forming an information storage capacitor element of a memory cell; (c) a plurality of columnar lower electrodes provided on the side and upper surfaces of each of the columnar lower electrodes, forming a capacitance insulating film of the information storage capacitor element of the memory cell; A first dielectric film made of a dielectric or ferroelectric film; (d) information storage of a memory cell provided on the first dielectric film provided on the side and top surfaces of each of the columnar lower electrodes; A single or a plurality of upper electrodes constituting a capacitive element, wherein each of the plurality of columnar lower electrodes is formed of a lower electrode main part occupying the largest volume thereof and a lower part of a different material arranged to cover the upper surface thereof Including the upper end of the electrode, Both ends of the head at the upper end of the lower electrode have larger chamfers than the cross-sectional shapes of both ends of the head of the lower electrode main part.

22. 21. The semiconductor integrated circuit device according to item 21, wherein an upper end of the lower electrode of each of the plurality of columnar lower electrodes has a trapezoidal cross section.

23. 21. The semiconductor integrated circuit device according to item 21, wherein the lower electrode upper end of each of the plurality of columnar lower electrodes has a triangular cross section.

24. 21. The semiconductor integrated circuit device according to item 21, wherein the upper end of the lower electrode of each of the plurality of columnar lower electrodes has a rectangular cross section in which the side surface of the head is cut out in the thickness direction by half or more.

25. 21. The semiconductor integrated circuit device according to item 21, wherein the upper end of the lower electrode of each of the plurality of columnar lower electrodes has a cross-sectional shape in which the side surface of the head is rounded over half or more in the thickness direction. .

26. A semiconductor integrated circuit device having the following configuration: (a) an integrated circuit substrate having a first main surface; (b) being disposed on the first main surface at an interval equal to or less than the width thereof. A plurality of columnar lower electrodes each including ruthenium or an oxide thereof as a main component constituting the information storage capacitor element of the memory cell; (c) platinum provided at the upper end of each of the columnar lower electrodes; (D) a first dielectric made of a high dielectric or ferroelectric film constituting a capacitive insulating film of an information storage capacitor element of a memory cell provided on each of the side and top surfaces of the columnar lower electrode; (E) a single or a plurality of upper electrodes constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each of the side and upper surfaces of the columnar lower electrode;

27. 26. The semiconductor integrated circuit device according to the paragraph 26, wherein each of the plurality of columnar lower electrodes is thicker than the conductive film formed thereon.

28. 27. The semiconductor integrated circuit device according to item 27, wherein the thickness of each of the plurality of columnar lower electrodes is at least twice as thick as the conductive film formed thereon.

29. A semiconductor integrated circuit device having the following configuration: (a) an integrated circuit substrate having a first main surface; (b) being disposed on the first main surface at an interval equal to or less than the width thereof. , Each dynamic RA
A plurality of columnar lower electrodes mainly composed of iridium or an oxide thereof constituting the information storage capacitor element of the M memory cell; (c) a platinum lower electrode provided at the upper end of each of the columnar lower electrodes; (D) a first dielectric made of a high dielectric or ferroelectric film constituting a capacitive insulating film of an information storage capacitor element of a memory cell provided on each of the side and top surfaces of the columnar lower electrode; (E) a single or a plurality of upper electrodes constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each of the side and upper surfaces of the columnar lower electrode;

30. 29. The semiconductor integrated circuit device according to item 29, wherein each of the plurality of columnar lower electrodes is thicker than the conductive film formed thereon.

31. 30. The semiconductor integrated circuit device according to item 30, wherein each of the plurality of columnar lower electrodes is twice or more thicker than the conductive film formed thereon.

32. A semiconductor integrated circuit device having the following configuration: (a) an integrated circuit base having a first main surface; (b) a first film pattern provided on the first main surface; (c) the first film pattern A second film pattern made of a platinum group element or an oxide thereof provided on the film pattern of (d); (d) a sidewall adhesion film adhered to a side surface of the second film pattern when patterning the second film pattern by dry etching; (E) An insulating film formed directly or indirectly on the first film pattern so as to cover the side wall adhesion film and the second film pattern.

33. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) a step of forming a first film on a main surface of an integrated circuit wafer; (b) a second film made of an inorganic member on the first film A step of forming a film; (c) a step of forming a photoresist film on the second film; (d) a step of patterning the photoresist film; and (e) a state in which the patterned photoresist film is present. Patterning the second film by performing a dry etching process on the second film, and forming a sidewall adhesion film on the side surface of the patterning; (f) patterning the sidewall adhesion film. Having said second
Patterning the first film by performing a dry etching process on the first film in a state where the film is present.

Further, the outlines of the other inventions of the present application are described separately in sections, and are shown below. That is, 1. (A) forming a first conductive film made of a platinum group or an oxide thereof to constitute a lower electrode of an information storage capacitor element of a memory cell on a main surface of an integrated circuit wafer; (b) the first conductive film Forming a first inorganic film pattern on the conductive film; (c) performing dry etching on the first conductive film in a state where the first inorganic film pattern is present, to thereby form the first inorganic film pattern. Patterning the conductive film of (d); a second dielectric to form a capacitive insulating film of the information storage capacitor element of the memory cell on the patterned first conductive film and the surface of the first inorganic film pattern; Forming a body film; and (e) forming a second conductive film to form an upper electrode of the information storage capacitor element of the memory cell on the second dielectric film. The inorganic film pattern of 1 is silicon nitride Film,
A method for manufacturing a semiconductor integrated circuit device, comprising: a platinum film, a ruthenium film, a BST film, a PZT film, or a stacked film of these and a silicon oxide film.

2. (A) an integrated circuit substrate having a first main surface; (b) an information storage capacitor element of a memory cell which is arranged on the first main surface at an interval equal to or less than the width thereof. (C) a plurality of columnar lower electrodes comprising a high-dielectric or ferroelectric film constituting a capacitive insulating film of an information storage capacitor element of a memory cell provided on each of the side and upper surfaces of the columnar lower electrode; (D) a single or a plurality of components constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on the side and top surfaces of each of the columnar lower electrodes; An upper electrode, wherein each of the plurality of columnar lower electrodes has a second dielectric film formed between an upper surface thereof and the first dielectric film, and is in contact with the first dielectric film. The first area S1 of the columnar lower electrode and the second dielectric The second area S2 of the columnar lower electrode in contact with the body film is S1 / (S1 + S2)
> 85%.

3. 2. The semiconductor integrated circuit device according to item 2, wherein the dielectric constant of the first dielectric film is equal to or higher than the dielectric constant of the second dielectric film.

4. (A) forming a first conductive film made of a platinum group or an oxide thereof to constitute a lower electrode of an information storage capacitor element of a memory cell on a main surface of an integrated circuit wafer; (b) the first conductive film Forming a second conductive film thinner than the first conductive film on the conductive film; (c) forming a first inorganic film pattern on the second conductive film; (d) A step of patterning the first and second conductive films by subjecting the first and second conductive films to dry etching in a state where the first inorganic film pattern is present; (e) patterning Forming a second dielectric film to form a capacitance insulating film of the information storage capacitor element of the memory cell on the surfaces of the first and second conductive films thus formed; (e) the second dielectric film The upper electrode of the information storage capacitor of the memory cell is Forming a second conductive film to be formed, wherein the first inorganic film pattern is etched and disappears at the completion of the step (d) or during the period of over-etching. A method for manufacturing an integrated circuit device.

5. 4. The method for manufacturing a semiconductor integrated circuit device according to item 4, wherein the thickness of the first conductive film is 10 times or more the thickness of the second conductive film.

6. 5. The method for manufacturing a semiconductor integrated circuit device according to item 5, wherein the first conductive film is made of ruthenium, iridium, or an oxide thereof, and the second conductive film is made of platinum.

7. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the first inorganic film pattern is formed of a silicon oxide film.

8. (A) an integrated circuit substrate having a first main surface; (b) an information storage capacitor element of a memory cell which is arranged on the first main surface at an interval equal to or less than the width thereof. A plurality of columnar lower electrodes mainly composed of ruthenium, iridium or an oxide thereof; (c) a conductive film made of platinum provided on the upper end of each of the columnar lower electrodes; (d) A first dielectric film made of a high-dielectric or ferroelectric film constituting a capacitive insulating film of an information storage capacitor element of a memory cell provided on each of the side surface and the upper surface of the columnar lower electrode; A single or a plurality of upper electrodes constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each of the side surface and the upper surface of the lower electrode; Each of the lower electrodes Of the semiconductor integrated circuit device, wherein the thick 10 times or more on the conductive film formed thereon.

9. (A) forming a first conductive film made of a platinum group or an oxide thereof to constitute a lower electrode of an information storage capacitor element of a memory cell on a main surface of an integrated circuit wafer; (b) the first conductive film Forming a second conductive film having a smaller thickness than the first conductive film on the conductive film; (c) forming a dielectric film on the second conductive film; (d) forming the dielectric film Forming a third conductive film made of a platinum group or an oxide thereof to form an upper electrode of the information storage capacitor element of the memory cell on the film; (e) forming a third conductive film on the third conductive film Forming a fourth conductive film having a thickness smaller than that of the conductive film; (f) patterning the fourth conductive film, and forming the fourth conductive film in a state where the pattern of the fourth conductive film exists; Patterning the conductive film of (g); patterning the second conductive film; The method of manufacturing a semiconductor integrated circuit device characterized by having: step of the pattern of the conductive film is patterned conductive film wherein in the presence first conductive film.

10. 9. The manufacturing method of a semiconductor integrated circuit device according to item 9, wherein the first and third conductive films are made of ruthenium, iridium, or an oxide thereof, and the second and fourth conductive films are made of platinum. Method.

11. 13. The method for manufacturing a semiconductor integrated circuit device according to item 10, wherein the second and fourth conductive films remain.

[0061]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

Further, in the following embodiments, when it is necessary for convenience, the description will be made by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless otherwise specified. One has a relationship of some or all of the other, the details, the supplementary explanation, and the like.

The term "semiconductor integrated circuit device" used in the present application means not only a device formed on a silicon wafer but also a device formed on another substrate such as a TFT liquid crystal, unless otherwise specified. Shall be included. Also,
In the present application, the term “main surface of the wafer” or “on the main surface” refers to the main surface of the substrate itself or the upper surface on which a single-layer or multilayer thin film is formed on the substrate depending on the situation.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), the number is particularly limited and is limited to a specific number in principle. Except in some cases, the number is not limited, and may be more or less than a specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified and when it is deemed essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and unless otherwise apparently in principle, it is substantially the same. And those similar or similar to the shape or the like. The same applies to the above numerical values, ranges, and the like.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM of Embodiment 1 is formed.
As shown, a semiconductor chip 1 made of single crystal silicon
X direction (long side direction of semiconductor chip 1A) on the main surface of A
And a large number of memory arrays MARY are arranged in a matrix along the Y direction (the short side direction of the semiconductor chip 1A). Memory arrays M adjacent to each other along the X direction
A sense amplifier SA is arranged between ARY. A word driver W is provided at the center of the main surface of the semiconductor chip 1A.
D, control circuits such as data line selection circuits, input / output circuits,
Bonding pads and the like are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM of the second embodiment. As shown, the memory array (MARY) of the DRAM includes a plurality of word lines WL (WL0, WL1, WLn...) And a plurality of bit lines BL arranged in a matrix and a plurality of bit lines BL arranged at intersections thereof. It is composed of memory cells (MC). One memory cell for storing 1-bit information is composed of one information storage capacitor C and one memory cell selecting M connected in series to this.
ISFET Qs. One of a source and a drain of the memory cell selecting MISFET Qs is electrically connected to the information storage capacitor C, and the other is a bit line BL.
Is electrically connected to One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is
It is connected to the sense amplifier SA.

Next, a method of manufacturing the DRAM of the present embodiment will be described in the order of steps with reference to the drawings. 3 to 12 and FIG. 15 are cross-sectional views showing an example of the manufacturing process of the DRAM of the first embodiment in the order of processes.

First, as shown in FIG. 3, an element isolation region and a well region into which impurities are introduced are formed.

An integrated circuit substrate 1 (integrated circuit wafer) made of p-type single crystal silicon having a specific resistance of about 10 Ωcm is prepared, and a thin silicon oxide film having a thickness of about 10 nm formed by wet oxidation at about 850 ° C. (Not shown) and a silicon nitride film (not shown) having a thickness of about 140 nm formed by, for example, a CVD (Chemical Vapor Deposition) method are deposited on the integrated circuit substrate 1. In the present application, the term “integrated circuit wafer” refers to a wafer for manufacturing a semiconductor integrated circuit device or a semiconductor wafer, such as SOS, SOI,
Including insulating substrates such as single crystal silicon substrates and TFTs. Needless to say, not only an unprocessed wafer but also an insulating film or a conductive film formed during a wafer process is included. Needless to say, the integrated circuit substrate in the present application includes not only an unprocessed wafer and a semiconductor single crystal piece after the dicing process but also a wafer in the middle of the wafer process. In general, a semiconductor chip refers to a pellet, and in some cases is a semiconductor integrated circuit device wafer or a semiconductor wafer, and includes an insulating substrate such as an SOS, an SOI, a single crystal silicon substrate, and a TFT.

Next, using the photoresist film (not shown) as a mask, the silicon nitride film and the silicon oxide film in the region where the groove 5 is to be formed are patterned, and using the silicon nitride film as a mask, Is etched to form a groove 5 having a depth of about 300 to 400 nm in the integrated circuit substrate 1 in the element isolation region.

Next, after removing the photoresist film, in order to remove a damaged layer formed on the inner wall of the groove 5 by the etching, a thin film (about 10 nm thick) is formed by wet oxidation at about 850 to 900 ° C. A silicon oxide film 6) is formed on the inner wall of the groove 5 and is deposited by a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas (not shown). Is deposited in a thickness of about 300 to 400 nm. This silicon oxide film may be sintered (baked) at about 1000 ° C. by dry oxidation.

Next, the silicon oxide film is polished by the CMP method to remove the silicon oxide film in the region other than the groove 5.
An element isolation region is formed with the silicon oxide film 7 left inside the groove 5. Before polishing by the CMP method, grooves 5
By forming a silicon nitride film in the region of the above, dishing in which the silicon oxide film in the region of the groove 5 is polished excessively deep can be prevented.

Next, after the silicon oxide film and the silicon nitride film remaining on the surface of the integrated circuit substrate 1 are removed by wet etching using, for example, hot phosphoric acid, a region (memory array) for forming a memory cell is formed. Integrated circuit substrate 1
An n-type semiconductor region 10 is formed by ion-implanting an n-type impurity, for example, P (phosphorus) into the memory array and a part of a peripheral circuit (a region for forming an n-channel MISFET).
A p-type impurity, for example, B (boron) is ion-implanted into the p-type well 11 to form another part of the peripheral circuit (p-type well).
An n-type impurity, for example, P (phosphorus) is ion-implanted into a region for forming a channel type MISFET to form an n-type well 12. Subsequent to the ion implantation, an impurity for adjusting the threshold voltage of the MISFET, for example, BF ₂ (boron fluoride) is added to the p-type well 11.
Then, ions are implanted into the n-type well 12. The n-type semiconductor region 10 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit through the integrated circuit substrate 1.

Next, the surface of the integrated circuit substrate 1 is
After cleaning using an F (hydrofluoric acid) cleaning solution, the integrated circuit substrate 1 is wet-oxidized at about 850 ° C. to perform p-type well 1 cleaning.
A clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of the 1-type and n-type wells 12. Although not particularly limited, after the gate oxide film 13 is formed, the integrated circuit substrate 1 is subjected to a heat treatment in a NO (nitrogen oxide) atmosphere or an N ₂ O (nitrous oxide) atmosphere to form the gate oxide film 13 with the gate oxide film 13. Nitrogen may be segregated at the interface with the integrated circuit substrate 1 (oxynitridation treatment).

Next, as shown in FIG.
The gate electrodes 14A, 14B, 14C are formed on the top of the gate electrode 3. The gate electrode 14A is a MISFE for selecting a memory cell.
T and a word line W in a region other than the active region.
Used as L. The width of the gate electrode 14A (word line WL), that is, the gate length is the memory cell selection M
The size of the ISFET is set to a size within an allowable range in which the short channel effect can be suppressed and the threshold voltage can be secured to a certain value or more. The distance between adjacent gate electrodes 14A (word lines WL) is determined by the resolution of photolithography. It can be configured with dimensions determined by the limits. Gate electrode 14B and gate electrode 14C
Constitute part of each of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

Gate electrode 14A (word line WL) and gate electrodes 14B and 14C are formed by depositing a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) on integrated circuit substrate 1 by CVD. A WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by sputtering, and a silicon nitride film 15 having a thickness of about 150 nm is further formed thereon. Is deposited by a CVD method, and these films are patterned by using the photoresist film 16 as a mask. The WN film is made of W
The film functions as a barrier layer for preventing a reaction between the film and the polycrystalline silicon film to form a high-resistance silicide layer at an interface between them. As the barrier layer, a TiN (titanium nitride) film or the like can be used in addition to the WN film.

Next, after the photoresist film 16 is removed, as shown in FIG.
For example, B (boron) is ion-implanted into the p ^- type semiconductor region 17 in the n-type well 12 on both sides of the gate electrode 14C.
To form An n-type impurity, for example, P (phosphorus) is ion-implanted into p-type well 11 to form gate electrode 14B.
N on both sides of the p-type well 11 ^- -type semiconductor region 18 is formed, to form an n-type semiconductor region 19 in the p-type well 11 on both sides of the gate electrode 14A. As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, after depositing a silicon nitride film 20 having a thickness of about 50 to 100 nm on the integrated circuit substrate 1 by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film 21 and the silicon of the peripheral circuit is formed. By anisotropically etching the nitride film 20, the gate electrodes 14B and 14
A sidewall spacer 20a is formed on the side wall of C.
In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do. In order to minimize the amount of the silicon nitride film 15 on the gate electrodes 14B and 14C, the amount of over-etching is kept to a minimum.

Next, after removing the photoresist film 21, a p-type impurity, for example, B (boron) is ion-implanted into the n-type well 12 in the peripheral circuit region to form a p-channel type M.
Ap ⁺ -type semiconductor region 22 (source, drain) of the ISFET is formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region, so that the n ⁺ -type semiconductor region of the n-channel MISFET is formed. 23 (source, drain) are formed. Thereby, the p-channel MISFET Qp and the n-channel MISFET having the LDD (Lightly Doped Drain) structure in the peripheral circuit region
Qn is formed.

Next, as shown in FIG.
SOG (Spin On Glass) film 2 with a thickness of about 300 nm on top
4 is spin-coated, the integrated circuit substrate 1 is heated at 800 ° C.,
The heat treatment is performed for about a minute, and the SOG film 24 is sintered (sintered). After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the SOG film 24, the silicon oxide film 25 is polished by a CMP method to planarize the surface.
Further, a silicon oxide film 26 having a thickness of about 100 nm is deposited on the silicon oxide film 25. The silicon oxide film 26 is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. The silicon oxide films 25 and 26 are made of, for example, ozone (O
₃ ) and tetraethoxysilane (TEOS) are deposited by a plasma CVD method using a source gas. A PSG (Phospho Silicate Glass) film or the like may be deposited instead of the silicon oxide film 26.

Next, the silicon oxide films 26 and 25 and the SOG film 24 above the n-type semiconductor region 19 (source and drain) of the MISFET Qs for memory cell selection are removed by dry etching using a photoresist film as a mask.
This etching is performed under such conditions that the etching rates of the silicon oxide films 26 and 25 and the SOG film 24 with respect to the silicon nitride film 20 are increased.
9 and the silicon nitride film 2 covering the upper part of the isolation trench 5
Ensure that 0 is not completely removed. Subsequently, the n-type semiconductor region 19 of the MISFET Qs for memory cell selection is dry-etched using the photoresist film as a mask.
By removing the silicon nitride film 20 and the gate oxide film 13 above the (source, drain), a contact hole 28 is formed in one upper part of the n-type semiconductor region 19 (source, drain) and in the other upper part. Contact hole 2
9 is formed. This etching is performed under such conditions that the etching rate of the silicon nitride film 15 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. Make sure that 5 is not sharpened. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the contact holes 28 and 29 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 1.
4A (word line WL) is formed in a self-aligned manner.
In order to form the contact holes 28 and 29 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 20 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

Next, the photoresist film is removed, and dry etching residues and photoresist residues on the substrate surface exposed at the bottoms of the contact holes 28 and 29 are removed using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. After the removal, plugs 30 are formed inside the contact holes 28 and 29. The plug 30 is formed of the silicon oxide film 2
After a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) is deposited on the upper part of the silicon film 6 by a CVD method, the polycrystalline silicon film is polished by a CMP method and left inside the contact holes 28 and 29. It forms by doing.

Next, as shown in FIG. 7, after a silicon oxide film 31 having a thickness of about 200 nm is deposited on the silicon oxide film 26, the integrated circuit substrate 1 is heat-treated at about 800.degree. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. By this heat treatment, the n-type impurity in the polycrystalline silicon film forming the plug 30 diffuses from the bottoms of the contact holes 28 and 29 into the n-type semiconductor region 19 (source, drain) of the MISFET Qs for selecting a memory cell. The region 19 is reduced in resistance.

Next, the surface of the plug 30 is exposed by removing the silicon oxide film 31 above the contact hole 28 by dry etching using a photoresist film as a mask. After that, the silicon oxide film 3 in the peripheral circuit region is dry-etched using a new photoresist film as a mask.
1, 26, 25, SOG film 24 and gate oxide film 13
Is removed, the n-channel MISFET Qn
Contact holes 34 and 35 are formed above the n ⁺ type semiconductor region 23 (source and drain) of
Contact holes 36 and 37 are formed above the p ⁺ type semiconductor region 22 (source and drain) of the ISFET Qp.

Next, after removing the photoresist film, the bit lines BL and first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. To form the bit lines BL and the first layer wirings 38 and 39, first, a Ti film having a thickness of about 50 nm is deposited on the silicon oxide film 31 by a sputtering method, and the integrated circuit substrate 1 is heat-treated at about 800 ° C. . Next, a T film having a thickness of about 50 nm is formed on the Ti film.
An iN film is deposited by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 40 having a thickness of about 200 nm are further deposited on the iN film by a CVD method. Perform patterning.

After a Ti film is deposited on the silicon oxide film 31, the integrated circuit substrate 1 is heat-treated at about 800 ° C., whereby the Ti film reacts with the underlying Si, and the n ⁺ type semiconductor of the n-channel MISFET Qn The surface of the region 23 (source, drain) and the p ^{+ of the} p-channel type MISFET Qp
A low-resistance TiSi ₂ (titanium silicide) layer 42 is formed on the surface of the type semiconductor region 22 (source, drain) and the surface of the plug 30. Thereby, the contact resistance of the wiring (bit line BL, first layer wirings 38 and 39) connected to n ⁺ type semiconductor region 23, p ⁺ type semiconductor region 22 and plug 30 can be reduced. Further, since the bit line BL is formed of the W film / TiN film / Ti film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the information reading speed and the writing speed can be improved, and the bit speed can be improved. Line BL and the first of the peripheral circuits
Since the layer wirings 38 and 39 can be formed simultaneously in one process, the manufacturing process of the DRAM can be shortened. Further, when the first layer wirings (38, 39) of the peripheral circuit are formed of the same layer as the bit line BL, the peripheral wiring is more peripheral than the case where the first layer wiring is formed of the upper layer Al wiring of the memory cell. MISFET (n-channel type MISFE)
Since the aspect ratio of the contact holes (34 to 37) connecting the TQn, p-channel type MISFET Qp) and the first layer wiring is reduced, the connection reliability of the first layer wiring is improved.

The bit line BL is used to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible to improve the information reading speed and the writing speed.
The gap is formed so as to be longer than the width.

Next, after removing the photoresist film, side wall spacers 43 are formed on the side walls of the bit lines BL and the side walls of the first layer wirings 38 and 39. The side wall spacer 43 includes the bit line BL and the first layer wiring 38,
After depositing a silicon nitride film on top of 39 by CVD,
This silicon nitride film is formed by anisotropic etching.

Next, as shown in FIG. 8, an SOG film 44 having a thickness of about 300 nm is spin-coated on the bit lines BL and the first layer wirings 38 and 39. Next, the integrated circuit substrate 1 is heat-treated at 800 ° C. for about 1 minute to sinter (sinter) the SOG film 44. The SOG film 44 is made of BPSG
Since the reflow property is higher than that of the film and the gap fill property between fine wirings is excellent, it is possible to satisfactorily fill gaps between the bit lines BL miniaturized to the resolution limit of photolithography.

Next, a 600 nm thick film is formed on the SOG film 44.
After the silicon oxide film 45 is deposited to a degree, the silicon oxide film 45 is polished by a CMP method to planarize the surface. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in the present embodiment, the SOG film 44 having good flatness is applied on the bit line BL and the first layer wirings 38 and 39 immediately after the film formation, and further, the silicon The oxide film 45 is planarized by the CMP method. Thereby, the gap fill property of the minute gap between the bit lines BL is improved, and the flattening of the insulating film on the bit lines BL and the first layer wirings 38 and 39 can be realized.

Next, a film thickness of 1
A silicon oxide film 46 of about 00 nm is deposited. The silicon oxide film 46 is deposited to repair fine scratches on the surface of the silicon oxide film 45 generated when the silicon oxide film 45 is polished by the CMP method. The silicon oxide film 46 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, a film thickness of 5 is formed on the silicon oxide film 46.
A titanium nitride film 47 of about 0 nm is deposited. The titanium nitride film 47 can be deposited by a CVD method or a sputtering method. The titanium nitride film 47 functions as a stopper film at the time of etching a ruthenium film described later.

Next, the titanium nitride film 47 above the contact hole 29 is removed by dry etching using a photoresist film as a mask.
5. The through hole 48 reaching the surface of the plug 30 is formed by removing the SOG film 44 and the silicon oxide film 31. This silicon oxide film-based film etching is performed under conditions such that the etching rate of the silicon nitride film with respect to the silicon oxide films 46, 45, 31 and the SOG film 44 becomes small, and misalignment between the through hole 48 and the bit line BL is caused. Even if this occurs, the silicon nitride film 40 and the sidewall spacers 43 above the bit lines BL are prevented from being cut deeply. As a result, the through hole 48 is formed in self alignment with the bit line BL.

Next, after removing the photoresist film, a dry etching residue or a photoresist residue on the surface of the plug 30 exposed at the bottom of the through hole 48 is etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. Is removed. At this time, the SOG film 44 exposed on the side wall of the through hole 48 is also exposed to the etching solution. The SOG film 44 has a reduced etching rate with respect to the hydrofluoric acid-based etching solution by the sintering at about 800 ° C. Therefore, the sidewall of the through hole 48 is not largely undercut by the wet etching process.

Next, the plug 4 is inserted into the through hole 48.
9 is formed. The plug 49 may be a conductive member, and the material is not particularly limited. For example, it is made of polycrystalline silicon or a metal compound such as a titanium nitride film. The plug 49 can be formed, for example, by depositing a polycrystalline silicon film filling the through hole 48 on the entire surface of the integrated circuit substrate 1 and then etching back the polycrystalline silicon film.

The barrier metal 5 is provided on the plug 49.
0 is formed. The barrier metal 50 is formed between the lower electrode of the information storage capacitor element and the plug 49, which will be described later. Has the effect of suppressing the reaction with 49. As the barrier metal 50, for example, an alloy of titanium, aluminum and silicon can be used. The barrier metal 50 can be formed, for example, by depositing the alloy on the entire surface of the integrated circuit substrate 1 and then etching back the alloy except for the through holes 48. Polishing by a CMP method can be used instead of etch back.

Next, as shown in FIG. 9, an information storage capacitor C having a columnar lower electrode 51 made of ruthenium metal, a capacitance insulating film 53 made of BST, and an upper electrode 54 made of ruthenium metal is formed. By using a ruthenium metal having a high affinity for BST as the lower electrode 51 in this manner, a high dielectric or ferroelectric BS
A T film can be used for the capacitance insulating film 53. The upper electrode 54 is also made of ruthenium metal, so that an MIM (Metal Insulater) using a BST film with a high dielectric constant as an insulating film.
Metal) Capacitors can be configured with good affinity. Thus, a DRAM of 1 Gbit or more can be realized. In the present application, the term “high dielectric substance” refers to a substance having a relative dielectric constant of 50 or more, such as BST. In general, there are many ABO ₃ type perovskites or those having a similar structure. Further, in the present application, the ferroelectric refers to a substance having a relative dielectric constant of at least 100, such as PZT. In general, there are many ABO ₃ type perovskites or their similar structures (including a composite structure or a layer structure).

On the upper surface of the columnar lower electrode 51, a silicon oxide film 52, which is a part of a hard mask at the time of etching a ruthenium film described later, remains. The merit in process by leaving such a silicon oxide film 52 will be described later. On the other hand, by leaving the silicon oxide film 52, the lower electrode 51 and the capacitor insulating film 53 are formed.
, A silicon oxide film 52 having a small dielectric constant is interposed therebetween, and the effectiveness when the upper surface of the lower electrode 51 substantially functions as a capacitor is reduced. However, as shown in the plan view of FIG. 10A, the lower electrode 51 is formed in a rectangular plane pattern having a long side in the bit line direction (x direction). As shown, it is formed in an elongated column shape. For example, the dimensions of the lower electrode 51 in the present embodiment are 0.39 μm in the long side direction of the lower electrode 51 and 0.13 μm in the short side direction.
μm, the pattern interval is 0.13 μm, and the height of the columnar lower electrode 51 is 0.45 μm. Assuming such numerical values, the surface area of the lower electrode 51 that should serve as a capacitor is equal to the area of the upper surface portion 51a (0.13 μm × 0.39 μm).
m = 0.0507 μm ² ) + area of side surface portion 51b (0.13
μm × 0.45 μm × 2 + 0.39 μm × 0.45 μm × 2 =
0.468 μm ² ).
Even if 1a does not contribute as a capacitor, the area (0.468 μm ² ) of the side surface portion 51b of the lower electrode 51 occupies about 90% of the total surface area (0.5187 μm ² ), so that the overall capacitance value does not decrease. Only about 10%. That is, the storage performance of the information storage capacitor C does not significantly decrease. Such a decrease in the capacitance value is within an allowable range, and the merits in the process described later contribute to simplification of the manufacturing process, improvement of the reliability, etc. It can be said that the application of the above has a great technical effect.

It is considered that the ratio of the upper surface portion 51a of the lower electrode 51 contributing as a capacitor is 3% or less.

Note that, in the plane pattern of FIG.
Although drawn as a rectangle, the actual shape of the lower electrode 51 is not necessarily formed in a rectangular shape as shown in the figure, but is formed in a shape in which each ridge is rounded or has a taper. That is, it is needless to say that the plane pattern in FIG. 10 is a pattern of a photolithography mask, and the pattern shape is not accurately reproduced due to a diffraction phenomenon of exposure light or the like, and is actually formed in a shape close to an oval or an ellipse. .

The steps of forming the information storage capacitor C will be described below with reference to FIGS. FIG. 11 and FIG.
2 is a cross-sectional view showing one example of a manufacturing process of the information storage capacitor of the DRAM according to the first embodiment in the order of processes; Although the columnar lower electrode 51 has a rectangular columnar shape as described above, the cross-sectional view of the information storage capacitor C shown in FIG.
Shows a cross section taken along line AA in FIG. On the other hand, in FIGS. 11 and 12, a cross section taken along line BB in FIG. 10 will be described. In the microfabrication region to which the present invention is applied, the lower electrode 51 is formed with a pattern width of 0.13 μm, a pattern interval of 0.13 μm, and a pattern height of 0.45 μm in the direction of the cross section taken along the line BB shown in FIG. The Rukoto. The formation of the lower electrode having such a high aspect ratio is performed by the lower electrode 51.
Considering that is formed of a platinum group such as ruthenium which is difficult to anisotropically etch, the technical difficulty becomes extremely high. The present invention is significant in that such etching with high technical difficulty is realized, and the information storage capacitor C is simply and easily formed with high reliability without impairing a precisely formed processed shape. In order to clearly explain the feature of the above, a section taken along line BB which is a direction in which etching is difficult will be described. 11 and 12 show only the information storage capacitor C.

After the step of FIG. 8, the ruthenium film 55 and the silicon oxide film 56 are formed on the titanium nitride film 47, as shown in FIG.
A patterned photoresist film 57 is formed thereon.

The ruthenium film 55 can be formed by, for example, a sputtering method or a CVD method, and has a thickness of 0.45 μm. The ruthenium film 55 is to be the lower electrode 51 later, and has a thickness equal to the height of the lower electrode 51. By adjusting the thickness of the ruthenium film 55, the height of the lower electrode 51 can be adjusted. Note that instead of the ruthenium film 55,
A ruthenium dioxide film can be used.

The silicon oxide film 56 is a ruthenium film 55
The layer functions as a hard mask when etching is performed, and its composition and film thickness are determined in consideration of a decrease in a later etching step. Here, TEOS (tetramethoxysilane) is used as the silicon oxide film 56.
An example in which a silicon oxide film (hereinafter, referred to as a PTEOS film) formed by a plasma CVD method containing a gas as a source gas is used. In the case of the PTEOS film, the thickness is set to 0.3 μm in consideration of the fact that the thickness is reduced by a later etching process.

The photoresist film 57 is used as a mask when patterning the silicon oxide film 56, and is formed by a usual photolithography process. The patterning uses the same pattern as the planar pattern of the lower electrode 51 in FIG. That is, in the cross-sectional view of FIG. 11A, it is formed with a line and space of 0.13 μm. The pattern is formed on the plug 49 (barrier metal 50), and is later formed so that the lower electrode 51 is connected to the plug 49 (barrier metal 50). The thickness of the photoresist film 57 is, for example, 0.3 μm. The photoresist film 57 is made of EB (Electron B) in consideration of improvement in resolution.
eam) It is also possible to use a resist.

Next, as shown in FIG. 11B, the silicon oxide film 56 is patterned using the photoresist film 57 as a mask, and the silicon oxide film 52 serving as a hard mask is formed.
To form Since the silicon oxide film 56 can be etched with good anisotropy, the silicon oxide film 52 reproduces the pattern of the photoresist film 57 with good reproducibility. Therefore, a line and space of 0.13 μm is secured at the bottom of the silicon oxide film 52. For etching the silicon oxide film 56, for example, narrow electrode reactive ion etching can be used. The etching conditions are, for example, a reaction pressure of 50 mTorr and an applied power of 1 k each for the upper and lower electrodes.
W, etching gas is octafluorotetracarbon (C ₄ F ₈ ), argon and oxygen (O ₂ ) are each 12 sccm and 400 sc
sccm and 5 sccm, and the substrate temperature can be 0 ° C. Under such etching conditions, PTEOS
The etching rate of the film is about 300 nm / min, and the selectivity to the photoresist film 57 is about 3. Therefore, when the etching of the silicon oxide film 56 is completed, about 1
A photoresist film 57 having a thickness of 00 nm remains on the silicon oxide film 52.

Next, as shown in FIG. 11C, the photoresist film 57 is removed. The photoresist film 57 can be removed by, for example, ashing using oxygen plasma. Thus, a patterned silicon oxide film 52 is formed, and can be used as an etching mask for etching the ruthenium film 55 in the next step. As will be described later, since an oxygen-based gas is used as an etching gas for the ruthenium film 55, an oxidation-resistant mask is required as a mask, and the mask made of the silicon oxide film 52 satisfies this requirement.

Next, as shown in FIG. 11D, the lower electrode 51 is formed by etching the ruthenium film 55 using the silicon oxide film 52 as a mask. This ruthenium film 55 can be etched using the following etching method.

FIG. 13 is a conceptual sectional view showing an example of an etching apparatus used for etching the ruthenium film 55. This etching apparatus includes a reaction chamber 101 having an inner volume of about 33.3 liters, a vacuum pipe 102 connected to an exhaust port of the reaction chamber 101, a control valve CV disposed in the middle of the vacuum pipe 102, and a vacuum chamber. A turbo-molecular pump TMP connected to the other end of the pipe 102; and a roughing valve RV provided on the exhaust port side of the turbo-molecular pump TMP.
And a mechanical booster pump (displacement type dry pump for roughing) MBP connected through the oil-free exhaust system. The reaction chamber 101 has a mechanical strength enough to maintain a reduced pressure state, and the interior of the reaction chamber 101 can be brought into a high vacuum state by the above-described exhaust system. Further, when the processing gas (etching gas) supplied from the gas supply system described later is exhausted by the exhaust system, the reaction chamber 101 is adjusted by adjusting the conductance by the control valve CV.
The internal pressure can be adjusted to a desired value.

A rough evacuation system for evacuation of the reaction chamber 101 from the atmospheric pressure to a low degree of vacuum may be provided, but is not shown. Further, for the roughing exhaust system, a turbo type dry pump, an oil rotary pump or the like may be used instead of the mechanical booster pump MBP.

The present etching apparatus has a gas supply system in which chlorine gas (Cl ₂ ) is introduced into the reaction chamber 101 through the mass flow controller MFC2, and oxygen gas (O ₂ ) is introduced into the reaction chamber 101 through the mass flow controller MFC2. are doing. An appropriate valve (stop valve) can be inserted on the input / output side of each mass flow controller or immediately before the gas introduction section of the reaction chamber 101, but is not shown. Further, a suitable purge system can be provided in the gas supply system, but this is also not shown. Further, a manifold may be provided at a mixed portion of the chlorine gas and the oxygen gas, but is not shown. Further, another gas system, for example, a supply system of a fluorine-based gas for etching a silicon oxide film or a gas system for resist ashing may be provided.

In the reaction chamber 101, a sample table 103 is provided. As shown in the figure, a semiconductor substrate (wafer for manufacturing a semiconductor integrated circuit device) 1 is placed face-up on a sample table 103. The integrated circuit substrate 1 is, for example, a silicon wafer having a diameter of 6 inches, and is held by, for example, an electrostatic chuck. As shown in the drawing, the present etching apparatus is a single-wafer etching apparatus in which one wafer is introduced into the reaction chamber 101. Further, as shown, a gas is supplied from a gas supply nozzle 110. In addition, the sample table 10
Numeral 3 is electrically isolated from the reaction chamber 101 so that high frequency power RF2 for bias can be applied. This makes it possible to apply a high frequency bias to the integrated circuit substrate 1.

The upper part of the reaction chamber 101 is vacuum-sealed by a quartz tube 104, and an inductive coupling coil 10 is placed around the quartz tube 104.
5 are arranged. The inductive coupling coil 105 is connected to a high frequency power supply RF1 of, for example, 13.56 MHz. The power of the high frequency power supply RF1 is
Tube 104 and reaction chamber 10 by inductive coupling through
A plasma is generated in the device. Thus, high density plasma is generated at a low operating pressure (high vacuum range) using the inductively coupled plasma. However, the present apparatus is not limited to the inductively coupled plasma, but may be applied to any plasma generating mechanism at a low pressure. For example, ECR (Electron Cycrotoron Resonans) plasma, ICP (Inductively Coupled Plasma), magnetron RIE plasma, helicon wave plasma, or the like may be used.

The outline of the present etching apparatus is as described above. The characteristic of the apparatus when etching the ruthenium film 55 with good anisotropy will be described below. That is, in order to etch the ruthenium film 55 with good anisotropy, a large flow rate of the etching gas is supplied and exhausted at a high speed. Also, a larger over-etching than usual is performed. The concept of over-etching will be described later.

In the present etching apparatus, the supply capacity of the total gas flow rate of each gas of oxygen and chlorine enables a large flow rate of 2000 sccm, while the operation pressure (at a sufficiently low operation pressure even when such a large flow rate gas is supplied) is obtained. For example, 15mTo
In order to obtain rr), a turbo molecular pump TMP having a maximum pumping capacity of 2000 l / sec is used. Note that the exhaust pressure of the roughing system (the mechanical booster pump MBP including the roughing valve RV and the conductance of the piping) can be reduced to a sufficiently low back pressure in order to secure the maximum pumping capacity (compression ratio) of the turbo molecular pump TMP. Needless to say, the pumping speed is secured.

As described above, the exhaust system is configured using the turbo molecular pump TMP having an exhaust speed of 2000 liters / second, so that, for example, when the total gas flow rate of oxygen and chlorine is about 800 sccm, the effective exhaust speed becomes About 600 l / s are obtained. The effective exhaust speed of the exhaust system refers to the vacuum pipe 102, the control valve CV
, The turbo molecular pump TMP, and the exhaust speed of the entire exhaust system including the roughing exhaust system (mechanical booster pump MBP, roughing valve RV, and piping).

Next, using the above-described etching apparatus,
A method for etching the ruthenium film 55 will be described.

The mass flow controllers MFC1 and MFC2 were adjusted in the reaction chamber 101 to supply chlorine and oxygen at 80 sc each.
cm and 720 sccm. And
Adjust the control valve CV to a pressure of 15 mTorr. Further, the inductive coupling coil 105 and the substrate are supplied with 500 W
A plasma is generated by applying a high-frequency power of 0 W. Etching is performed mainly by a reaction between oxygen ions or oxygen radicals generated by the plasma and the ruthenium film 55.

Under such conditions, 100% over-etching is performed. Here, the concept of over-etching in this specification will be described with reference to FIG. FIG.
Is a graph plotting plasma emission intensity with respect to processing time when a ruthenium film on a base film containing titanium (for example, a titanium nitride film (TiN film)) is etched. Plasma emission can monitor light having a wavelength of 406 nm, which is the emission peak of titanium, for example. Etching starts at time t = 0. While the Ru film is being etched (time t = 0 to T1), TiN
Since the film is not exposed, the emission intensity of 406 nm light is maintained at a low level. When the time t = T1, the RuO in the portion of the wafer center where the etching rate is relatively fast is increased.
₂ / The etching of the Ru film is completed, and the underlying TiN film starts to be exposed. As a result, the emission intensity of the 406 nm light starts to increase, and as the time elapses, that is, the exposed area of the underlying TiN film increases, the emission intensity of the 406 nm light increases. At time t = T2, the etching of the Ru film is completed even in the portion of the wafer center where the etching rate is relatively slow, and the entire surface of the underlying TiN film is exposed. As a result, 4
The emission intensity of the 06 nm light is kept almost constant at a high level. The time t = T2 is defined as the just etching time, and the time from t = 0 to T2 is defined as the main etching time. The etching is further continued, and the etching ends at time t = T3. The time of t = T2 to T3 is defined as the over-etching time. Therefore, over-etching is (T3−T2) / (T2−0) × 100.
(%). The processing pressure is 15 mTorr.
However, the processing pressure may be a pressure at which the plasma is stably generated, and is from 100 mTorr to 0.1.
It can be selected in the range of mTorr, more preferably in the range of 30 mTorr to 1 mTorr.

Since the ruthenium film 55 is a member having an adhesive property on the side wall and is made of a platinum group or the like, a reaction product adheres to the etching side wall during the etching process, and inhibits the anisotropy of the etching and takes a tapered shape. However, by performing etching under the above conditions, the ruthenium film 55
The cross-sectional shape of the lower electrode 51 obtained by etching is substantially perpendicular (the taper angle is 89 degrees). The side wall-adhering member refers to a member that tends to adhere to the side wall due to the low vapor pressure of the product at the time of dry etching, making fine etching difficult. Oxides or sub-oxides (such as platinum group metals), and ABO ₃ transition metal oxides such as perovskite. Here, when a platinum group element or an oxide thereof is referred to, a platinum group element and an oxide containing the same, an oxide containing a platinum element and a constituent element thereof and an oxide containing a plurality of the constituent elements or another group are included. A complex oxide containing a platinum group element,
It is a concept including those solid solutions and the like.

The reason that the etching characteristics are improved as described above is that the etching gas is supplied at a large flow rate first,
This is because generated reaction products (mainly RuO ₄ and RuO _X ) are exhausted at high speed. In the etching of a platinum group element, a reaction product (especially RuO _x ) having a low vapor pressure is formed, so that it easily adheres to the side wall, and this adhering substance hinders the etched shape. And the etched shape is improved. Even if over-etching is about 20%, the taper angle of the etched shape is improved to about 84 degrees only by high-speed exhaust.

The reason why the etching characteristics are improved is as follows.
Second, 100% over-etching is performed.
That is, since the etching of the ruthenium film 55 ends at a certain taper angle, the titanium nitride film 47 as a base material is exposed under over-etching conditions. Since this titanium nitride film is not etched by oxygen ions or oxygen radicals, no reaction product is generated from the etched bottom surface, and no reaction product is scattered to the side wall. In the side wall portion, competition between etching by oxygen ions or oxygen radicals and reattachment of the reaction product generated in the side wall portion has occurred, but as in the above-described etching situation, the reaction product from the bottom portion may fly. As a result, the amount of the reaction product is reduced, and the etching is superior. For this reason, the amount of deposits on the side wall at the time of over-etching is extremely reduced, which causes the taper angle to increase.

As described above, under the above conditions, that is, at a reaction pressure of 15 mTorr, a plasma source power of 500 W,
FR bias power 200W, oxygen and chlorine flow 72
0 sccm and 80 sccm (total flow rate about 800 sccc
Under the condition of m), by setting the over-etching amount to 100%, the etching anisotropy is expressed by a taper angle of 8%.
It can be improved to 9 degrees.

As described above, the ruthenium film 55 is formed with a taper angle of 8
The fact that etching can be performed at 9 degrees makes it difficult in principle to vertically etch a platinum group metal such as ruthenium or an oxide thereof, that is, the vapor pressure of the reaction product is low and the side wall adhesion is high. Considering that the etching system generates a reactive product, this is a very remarkable effect, and enables fine processing of 1 Gbit DRAM class.

Further, by using such an etching method, a fine pattern having a pattern width and a space of 0.13 μm and a pattern height of 0.45 μm (aspect ratio of about 3.5, ie, aspect ratio of 2) Under an extremely severe condition in the etching process of three or more high aspect regions, an ideal columnar pattern having a taper angle of 89 degrees (including a cylinder-like one as well as a clogged one) can be realized. . In the present application, the term “columnar pattern” is not limited to a cylinder or a regular prism, but also includes a conical shape, a pattern having different vertical and horizontal lengths, and the like.

This also indicates that the fine processing margin of etching is large. If the limit of lithography is extended and a finer mask can be formed, it is possible to sufficiently use this technique. This means that fine processing (processing of a fine pattern with a pattern width and space of 0.13 μm or less) is possible.

Note that, under the above etching conditions, the silicon oxide film 52 (PTEOS
The etching selectivity of the film is about 10. Therefore, 0.4
In etching the 5 μm ruthenium film 55, the thickness of the silicon oxide film 52, which is a hard mask, is reduced by about 45 nm. However, since a large over-etching (100%) is performed, the facet of the silicon oxide film 52 is As a result, the silicon oxide film 52 after the etching has a conical shape as shown in FIG. Its height is about 100 nm as shown.

In the etching of the ruthenium film 55, the silicon oxide film is used as a hard mask without using the photoresist film as a mask. This is because the silicon oxide film can have a higher etching selectivity with ruthenium than the photoresist film, and can prevent the formation of the side wall adhesion due to the detachment of the organic substance from the photoresist film, thereby improving the etching shape. It has the effect of.

Next, as shown in FIG. 11E, using the silicon oxide film 52 as a mask, the titanium nitride film 47 as the base of the ruthenium film 55 is etched. The etching of the titanium nitride film 47 is performed, for example, by ECR (Electron Cycro
tron Resonance) plasma.
The etching conditions are, for example, a processing pressure of 8 mTorr,
Microwave power of 300 W, RF bias power of 800 kHz frequency of 70 W, etching gas of boron trichloride (BC
l ₃ ) and chlorine (Cl ₂ ) can be 30 sccm and 70 sccm, respectively, and the substrate temperature can be 50 ° C.
The silicon oxide film 52 (mask) is partially removed by the etching of the titanium nitride film 47, and its thickness is reduced as shown in the figure. The ridge of the silicon oxide film 52 is rounded because it is cut in the above-described process. Due to such roundness, there is an advantage that the deposition of the BST film 58 in the next step can be performed with good coverage.

Next, as shown in FIG. 11F, a BST film 58 is deposited without removing the silicon oxide film 52. The BST film 58 can be deposited by a CVD method, and its thickness is set to 20 nm. Since the BST film 58 is formed by the CVD method, the film can be uniformly formed on the lower electrode 51 which is finely processed and has a high aspect ratio as in this embodiment. Note that, instead of the BST film 58, another high dielectric film, for example, a tantalum oxide film, PZT, PLZT, or the like may be used.

As described above, since the BST film 58 is deposited without removing the silicon oxide film 52, the shape of the lower electrode 51 changes due to the removal process of the silicon oxide film 52, generally, the pattern of the lower electrode 51 becomes thinner and the lower electrode 51 becomes thinner. It is possible to prevent a change in shape unfavorable for fine processing such as rounding of the ridge portion of 51. The shape change of the pattern that occurs after processing as fine as possible has a large effect because it is processed finely, and even if it can be processed finely, the significance of performing fine processing if the shape changes afterwards It is not preferable because it is reduced by half. Therefore, in the present invention, the removal process of the silicon oxide film 52 that hinders the processed shape is omitted, and the state of the lower electrode 51 that has been most precisely processed is maintained.

Further, by not removing the silicon oxide film 52, it is possible to prevent the surface of the lower electrode 51 from being roughened which may occur in the step of removing the silicon oxide film 52. If the silicon oxide film 52 is removed, the surface of the lower electrode 51 becomes rough due to the etching of the silicon oxide film 52. Such roughness (roughening) lowers the adhesiveness of the BST film 58 and lowers the reliability of the information storage capacitor C. In a severe case, the BST film 58 is peeled off and the yield of the DRAM is increased. May be reduced. Therefore, in the present invention, the silicon oxide film 52 is left in order to prevent the occurrence of such roughness.

Further, omitting the step of removing the silicon oxide film 52 eliminates the step of removing the silicon oxide film 52 itself, which simplifies the manufacturing process of the DRAM and also performs the etching process (the process of removing the silicon oxide film 52). The processing steps accompanying the removal step such as the cleaning step after the removal step) can be omitted, and the DRAM manufacturing step can be simplified.

A silicon oxide film 52 is formed on the lower electrode 51.
Is left on the above process or D
There is an advantage in RAM performance. On the other hand, as described above, there is a demerit caused by leaving the silicon oxide film 52, but the demerit is not so dominant as long as it is applied to the lower electrode 51 which is finely processed with dimensions as in the present embodiment. Is as described above.

Next, as shown in FIG.
The film 58 is heat-treated (annealed) in an oxygen atmosphere. The heat treatment temperature is about 700 ° C. By this heat treatment, BST
Oxygen defects in the film 58 can be eliminated. The temperature condition of 700 ° C. is selected from the requirement that the lower electrode 51 and the residue on the upper surface do not undergo volume changes such as expansion due to heat treatment in an oxygen atmosphere. The silicon oxide film 52 has a thickness of 7
No volume expansion by oxygen atmosphere heat treatment at 00 ° C,
Satisfies the above requirements.

Next, as shown in FIG.
A ruthenium film 59 is deposited on the film 58, and a photoresist film 60 is formed on the ruthenium film 59 as shown in FIG.
To form The photoresist film 60 is formed so as to cover the memory cell region of the DRAM. Next, as shown in FIG. 12 (j), the ruthenium film 59 and the BST film 58 are etched using the photoresist film 60 as a mask to form a capacitance insulating film 53 and an upper electrode 54. afterwards,
The photoresist film 60 is removed by ashing or the like to complete an information storage capacitor C having a lower electrode 51 made of ruthenium, a capacitance insulating film 53 made of BST, and an upper electrode 54 made of ruthenium (FIG. 12 (k)). As a result, a memory cell selecting MISFET Qs and an information storage capacitor C connected in series
The memory cell of the RAM is completed.

For the deposition of the ruthenium film 59, for example, a sputtering method or a CVD method can be used. Further, for etching the ruthenium film 59 and the BST film 58,
The etching apparatus shown in FIG. 13 can be used. The etching condition is, for example, a reaction pressure of 2 mTorr.
r, plasma source power 300 W, FR bias power 600 W, carbon tetrafluoride (CF ₄ ) and argon (Ar) are 10 sccm and 40 sccm, respectively, and the amount of overetching can be 10%. Under such conditions, the etched shape does not exhibit anisotropy,
Although the taper angle is about 60 degrees, there is no inconvenience because fine processing is not required here.

Note that an appropriate barrier metal may be formed on the upper electrode. Further, as a material forming the upper electrode 54, a titanium nitride film, a ruthenium film, or a tungsten film can be used instead of the ruthenium dioxide film.

Next, as shown in FIG. 15, a silicon oxide film 61 made of SOG is formed on the information storage capacitor C. When the SOG film is used for the silicon oxide film 61, the region where the memory cell is formed is flattened,
The step with the peripheral circuit region can be reduced. In addition,
Silicon oxide deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) having a thickness of about 40 nm as a source gas between the upper portion of the information storage capacitor C and the silicon oxide film 61. A film may be formed.

Next, the silicon oxide films 61, 46, 45, the SOG film 44 and the silicon nitride film 40 above the first layer wiring 38 of the peripheral circuit are removed by dry etching using a photoresist film as a mask. A through hole 62 is formed. Similarly, a through hole 63 is formed by removing the silicon oxide film 61 on the upper electrode 54. After that, a plug 64 is formed inside the through holes 62 and 63, and then a second layer wiring 65 is formed above the silicon oxide film 61. The plug 64 has a thickness of 100 over the silicon oxide film 61 by a sputtering method.
A TiN film having a thickness of about 500 nm is deposited, and a W film having a thickness of about 500 nm is further deposited thereon by a CVD method. Then, these films are etched back and left inside the through holes 62 and 63. The second layer wiring 65 is formed on the silicon oxide film 61 by a sputtering method so as to have a thickness of about 50 nm.
an iN film, an Al (aluminum) film having a thickness of about 500 nm,
After a Ti film having a thickness of about 50 nm is deposited, these films are formed by patterning by dry etching using a photoresist film as a mask.

Thereafter, a third layer wiring is formed via an interlayer insulating film, and a passivation film composed of a silicon oxide film and a silicon nitride film is deposited thereon, but is not shown. Through the above steps, the DR of the present embodiment
AM is almost completed.

The third-layer wiring and the plugs connected to it can be formed in the same manner as the second-layer wiring.
The interlayer insulating film includes, for example, a silicon oxide film having a thickness of about 300 nm, an SOG film having a thickness of about 400 nm, and a thickness of 300 nm.
It can be composed of a silicon oxide film of a degree. The silicon oxide film can be deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

According to the present embodiment, as the material of the lower electrode 51, ruthenium having a good affinity for the ferroelectric capacitor insulating film 53 such as BST is used. A certain silicon oxide film 52 is left, and a capacitor insulating film 53 is formed with the silicon oxide film 52 remaining. Thereby, the silicon oxide film 5
Step 2 can be simplified by omitting the removal step 2,
In addition, it is possible to prevent the upper surface of the lower electrode 51 or the underlayer from being roughened which may occur in the removing step, and to form the capacitor insulating film 53 with high reliability. Furthermore, the pattern of the lower electrode 51 which is likely to be generated in the step of removing the silicon oxide film 52 can be prevented from being dull or thinned, and the shape of the finely formed lower electrode 51 can be maintained.

In this embodiment, the case where the lower electrode 51 is made of a ruthenium film has been described.
Alternatively, a laminated film of ruthenium and ruthenium dioxide can be used.

Further, in the present embodiment, the ruthenium film 5
Although the titanium nitride film 47 was used as the etching stopper of No. 5, a silicon nitride film can be used instead of the titanium nitride film 47. That is, the silicon nitride film also has a large etching selectivity to the etching action mainly composed of oxygen radicals like the titanium nitride film 47, and thus can be used as the etching stopper of the present embodiment. In this case, since the silicon nitride film is a non-conductor, it is not necessary to remove the silicon nitride film by etching after etching the ruthenium film 55, that is, after forming the lower electrode 51.
The step (e) becomes unnecessary. In this case, FIG.
The BST film 58 after the step (d) may be formed. Therefore, the steps can be simplified. However, a relatively thick silicon oxide film 52 remains on the lower electrode 51. But,
As described above, the silicon oxide film 52 does not hinder the performance of the information storage capacitor C.

(Embodiment 2) DRA of Embodiment 2
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. Therefore,
A method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 16 is a cross-sectional view showing an example of a manufacturing process of the information storage capacitor of the DRAM according to the second embodiment in the order of processes. FIG. 16 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 of the first embodiment, FIG.
As shown in (a), a ruthenium film 55 and a platinum film 66 are formed on a titanium nitride film 47, and a patterned photoresist film 67 is formed on the platinum film 66.

Since the ruthenium film 55 is the same as that of the first embodiment, a detailed description is omitted. Platinum film 66
Functions as a hard mask when the ruthenium film 55 is etched and also functions as a part of the lower electrode. The thickness is set to 0.1 μm in consideration of a decrease in a later etching step.

The photoresist film 67 is used as a mask when patterning the platinum film 66, and is formed by a usual photolithography process. Photoresist film 67
Unlike the first embodiment, the patterning is formed to have a small width in advance in consideration of an increase in the bottom area due to the side wall attached when the platinum film 66 is etched. That is, as shown in the figure, the pattern width is set to 0.1 μm. The pattern interval is 190 nm. The thickness of the photoresist film 67 is set to 300 nm in consideration of a decrease in the etching of the platinum film 66. As in the first embodiment, an EB (Electron Beam) resist can be used for the photoresist film 67. The photoresist film 67 is formed with a rounded or chamfered upper part (ridge), that is, a round resist. By forming the photoresist film 67 with a round resist as described above, it is possible to reduce the amount of deposits on the side wall during the etching of platinum and to etch platinum with good anisotropy.

Next, as shown in FIG. 16B, the platinum film 66 is patterned using the photoresist film 67 as a mask to form a hard mask 68 made of platinum. For etching the platinum film 66, for example, magnetron reactive ion etching can be used. The etching conditions are, for example, a reaction pressure of 5 mTorr and an RF power of 2
kW, an etching gas of 15 sccm of argon, and a substrate temperature of 30 ° C. That is, the platinum film is etched by sputtering. Under such etching conditions, the etching rate of platinum is about 150 nm / mi.
n, and the selectivity to the photoresist film 67 is about 1. Therefore, when the etching of the platinum film 66 is completed, the photoresist film 67 having a thickness of about 200 nm remains on the hard mask 68. Also, the photoresist film 67
In addition, a side wall deposit 69 is formed on the side wall of the hard mask 68. The side wall deposit 69 is formed by reattachment because the reaction product generated during platinum etching has a low vapor pressure, and can be easily formed. In the present embodiment, this side wall deposit 69 is transferred to the ruthenium film 55 in the next step.
This is positively used for the etching mask. By forming the side wall deposits 69, the hard mask 6
The patterning area of the ruthenium film 55 is set to 0.13 μm as intended as the patterning dimension of the ruthenium film 55 at the bottom surface of the area which acts as a mask together with 8. This gives 0.
A lower electrode pattern having a width of 13 μm is formed.

Next, as shown in FIG. 16C, the photoresist film 67 is removed. The removal of the photoresist film 67 is the same as in the first embodiment.

Next, as shown in FIG. 16D, the lower electrode 51 is formed by etching the ruthenium film 55 using the hard mask 68 and the side wall deposit 69 as a mask. The etching of the ruthenium film 55 is performed in the same manner as in the first embodiment. Therefore, the ruthenium film 55 is formed almost anisotropically with an anisotropic taper angle of 89 degrees. In addition,
When the ruthenium film 55 is etched, the ridges of the hard mask 68 and the protrusions of the side wall deposits 69 are etched and rounded.

Next, as shown in FIG. 16E, the titanium nitride film 47, which is the base of the ruthenium film 55, is etched using the hard mask 68 and the side wall deposits 69 as a mask. The etching of the titanium nitride film 47 is performed in the first embodiment.
Is the same as By the etching treatment of the titanium nitride film 47, a part of the hard mask 68 and the side wall deposit 69 are also cut off,
The film thickness decreases as shown. Note that the ridges of the hard mask 68 and the side wall deposits 69 are further rounded because they are cut in the above-described steps. Due to such roundness, there is an advantage that the deposition of the BST film 58 in the next step can be performed with good coverage.

Next, as shown in FIG. 16F, B is removed without removing the hard mask 68 and the side wall deposits 69.
An ST film 58 is deposited. The BST film 58 can be formed in the same manner as in the first embodiment. The merit of depositing the BST film 58 without removing the hard mask 68 and the side wall deposits 69 is the same as the merit described in the first embodiment. Subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated. Since the hard mask 68 remaining on the surface of the lower electrode 51 is made of platinum, the hard mask 68 has excellent heat resistance, and the heat treatment of the BST film 58 in an oxidizing atmosphere does not cause an increase in volume and does not cause deterioration.

According to the present embodiment, in addition to the effects described in the first embodiment, since hard mask 68 remaining on lower electrode 51 is made of platinum which is a conductor, hard mask 68 is also formed of lower electrode. 51, and the area of the lower electrode can be increased by an area corresponding to the upper part of the hard mask 68. Thereby, the storage capacity of the information storage capacitor C can be increased to improve the performance of the DRAM. It should be noted that the side wall deposit 69 is generally not a conductor, and the portion where the side wall deposit 69 is in contact with the BST film 58 cannot be expected to function as a capacitor. However, even in such a case, the first embodiment will be described. As you can see, the impact of that disadvantage is not very large.

The lower electrode 51 is made of ruthenium dioxide,
Alternatively, as in the first embodiment, a laminated film of ruthenium and ruthenium dioxide can be used, and titanium nitride film 47 can be replaced with a silicon nitride film.

(Embodiment 3) DRA of Embodiment 3
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. Therefore,
A method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 17 is a cross-sectional view showing one example of the manufacturing process of the information storage capacitor of the DRAM according to the third embodiment in the order of processes. FIG. 17 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 of the first embodiment, FIG.
As shown in (a), a ruthenium film 55 and a platinum film 66 are formed on a titanium nitride film 47, and a patterned photoresist film 70 is formed on the platinum film 66.

Since the ruthenium film 55 is the same as that of the first embodiment, a detailed description is omitted. Platinum film 66
Functions as a hard mask when the ruthenium film 55 is etched and also functions as a part of the lower electrode. The thickness is set to 0.1 μm in consideration of a decrease in a later etching step.

The photoresist film 70 is used as a mask when patterning the platinum film 66, and is formed by a usual photolithography process. Photoresist film 70
Unlike the first embodiment, the patterning is formed to have a small width in advance in consideration of an increase in the bottom area due to the formation of the tapered portion when the platinum film 66 is etched.
That is, as shown in the figure, the pattern width is formed to be 0.08 μm. The pattern interval is 260 nm.
The thickness of the photoresist film 70 is set to 300 nm in consideration of a decrease in the etching of the platinum film 66. As in the first embodiment, an EB (Electron Beam) resist can be used for the photoresist film 70. Note that the photoresist film 70 is formed in a rounded or chamfered shape at its upper portion (ridge) as in the second embodiment, that is, a round resist.

Next, as shown in FIG. 17B, the platinum film 66 is patterned using the photoresist film 70 as a mask to form a hard mask 68 made of platinum. For etching the platinum film 66, magnetron reactive ion etching can be used as in the second embodiment, but the etching conditions are different. That is, the etching conditions include, for example, a reaction pressure of 1 mTorr, an RF power of 2 kW, and an etching gas of chlorine (Cl ₂ ) 15 scc.
m, and the substrate temperature is 30 ° C. That is, in the second embodiment, the platinum film is etched by sputtering, but in the third embodiment, the platinum film 66 is etched by a chemical action of chlorine radicals. Under such etching conditions, the etching rate of platinum is about 150 nm / min, and the selectivity to the photoresist film 70 is about 0.5. That is, the photoresist film 70 is shaved in large quantities,
At the end of the etching, the patterned platinum film 66
(Hard mask 68) The film thickness is reduced to such an extent that it remains slightly. However, no side wall deposits are formed on the side walls of the patterned hard mask 68. This is because the side wall deposits were scraped off by chlorine radicals. However, the anisotropy of the platinum film 66 is poor, and the taper angle is about 75 degrees. Therefore, the bottom of the hard mask 68 is thicker than the original pattern width of the photoresist film 70, and the width of the bottom of the hard mask 68 is 0.13 μm at the end of etching.
Becomes As a result, a lower electrode pattern having a width of 0.13 μm is formed.

Next, as shown in FIG. 17C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 17D, the lower electrode 51 is formed by etching the ruthenium film 55 using the hard mask 68 as a mask. The etching of the ruthenium film 55 is performed in the same manner as in the first embodiment. Therefore, the ruthenium film 55 is formed almost anisotropically with an anisotropic taper angle of 89 degrees. During the etching of the ruthenium film 55, the hard mask 68 is also partially etched, and its thickness is reduced to 70 nm.

Next, as shown in FIG. 17E, the titanium nitride film 47 as the base of the ruthenium film 55 is etched using the hard mask 68 as a mask. Titanium nitride film 4
The etching of 7 is the same as that of the first embodiment. The hard mask 68 is partially removed by the etching of the titanium nitride film 47, and its thickness is reduced as shown in the figure. In addition,
The ridge of the hard mask 68 is further rounded because it is cut in the above-described process. Due to such roundness, there is an advantage that the deposition of the BST film 58 in the next step can be performed with good coverage.

Next, as shown in FIG. 17F, a BST film 58 is deposited without removing the hard mask 68. The BST film 58 can be formed in the same manner as in the first embodiment.
Thus, the BST can be performed without removing the hard mask 68.
The merit of depositing the film 58 is the same as the merit described in the first embodiment. Subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated. Since the hard mask 68 remaining on the surface of the lower electrode 51 is made of platinum, the hard mask 68 has excellent heat resistance, and the heat treatment in the oxidizing atmosphere of the BST film 58 does not cause the volume increase but also the deterioration. This is the same as in Embodiment 2.

According to the present embodiment, in addition to the effects described in the first embodiment, since hard mask 68 remaining on lower electrode 51 is made of platinum which is a conductor, hard mask 68 is also formed of lower electrode 51. Function as part of
Since no side wall deposit is formed on the side surface of the hard mask 68, the entire region of the hard mask 68 in contact with the BST film 58 can function as a capacitor. That is,
Not only the upper surface of the hard mask 68 but also the hard mask 68
Can also function as a capacitor. As a result, the entire surface area of the lower electrode 51 and the surface of the hard mask 68 contributes to the capacitor, and the storage capacitance of the information storage capacitor C is further increased as compared with the second embodiment.
The performance of M can be improved. That is, despite the effect obtained by leaving the hard mask 68 as described in the first embodiment, the hard mask 6
There is no penalty for leaving 8.

The lower electrode 51 is made of ruthenium dioxide,
Alternatively, as in the first embodiment, a laminated film of ruthenium and ruthenium dioxide can be used, and titanium nitride film 47 can be replaced with a silicon nitride film.

(Embodiment 4) DRA of Embodiment 4
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. Therefore,
A method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 18 is a cross-sectional view showing an example of a manufacturing process of the information storage capacitor of the DRAM according to the fourth embodiment in the order of processes. FIG. 18 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 of the first embodiment, FIG.
7A, a ruthenium film 55, a platinum film 66, and a silicon oxide film 71 are formed on a titanium nitride film 47, and a patterned photoresist film 70 is formed on the silicon oxide film 71.

Since the ruthenium film 55 and the platinum film 66 are the same as in the third embodiment, detailed description will be omitted. The silicon oxide film 71 is similar to the silicon oxide film 56 of the first embodiment. The platinum film 66 functions as a hard mask when etching the ruthenium film 55, and also functions as a part of the lower electrode. Considering that the film thickness will decrease in the subsequent etching process
0.1 μm. Further, the silicon oxide film 56 is formed of the platinum film 6.
6 functions as a hard mask when etching, and its thickness is set to 0.3 μm in consideration of a decrease in a later etching step.

The photoresist film 70 is used as a mask when patterning the silicon oxide film 71, and is formed by a usual photolithography process. As in the case of the third embodiment, the width of the photoresist film 70 is reduced in advance in consideration of an increase in the bottom area due to the formation of the tapered portion when the platinum film 66 is etched. However, in the present embodiment, since the etching of the platinum film 66 is formed with better anisotropy than in the third embodiment, the pattern width is slightly increased to 0.1 μm. The pattern interval is 190 nm. The thickness of the photoresist film 70 is set to 300 nm in consideration of a decrease in the etching of the silicon oxide film 71. As in the first to third embodiments, an EB (Electron Beam) resist can be used for the photoresist film 70.

Next, as shown in FIG. 18B, the silicon oxide film 71 is etched using the photoresist film 70 as a mask to form a hard mask 72 for patterning the platinum film 66. Since the silicon oxide film is formed with good anisotropy, the pattern of the photoresist film 70 is faithfully reproduced, and the bottom of the hard mask 72 is also formed with a pattern width of 100 nm and a pattern interval of 190 nm.

Next, as shown in FIG. 18C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 18D, the platinum film 66 is patterned using the hard mask 72 made of a silicon oxide film as a mask, and the hard mask 6 made of platinum is formed.
8 is formed. For etching the platinum film 66, magnetron reactive ion etching can be used as in the second and third embodiments, but the etching conditions are different. That is, the etching conditions are, for example, a reaction pressure of 5
mTorr, RF power is 1.2 kW, etching gas is 80 sccm and 20 sccm of oxygen (O ₂ ) and chlorine (Cl ₂ ), over-etching is 100%, and substrate temperature is 160 ° C. That is, in the second embodiment, the platinum film is etched by sputtering, and in the third embodiment, chemical etching is performed by chlorine radicals. However, in the fourth embodiment, the platinum film 66 is heated to a substrate temperature of 160 by chemical action of oxygen radicals. Etching is performed at a high temperature of ℃. Under such etching conditions, the etching rate of platinum is about 150 nm / min, and the selectivity to the hard mask 72 made of a silicon oxide film is about 1. Under such conditions, no side wall deposits are formed on the side walls of the hard mask 68, and the anisotropy of the platinum etching is improved as compared with the third embodiment.
Is about 85 degrees. For this reason, the bottom of the hard mask 68 is thicker than the original pattern width of the hard mask 72, and the width of the bottom of the hard mask 68 becomes smaller at the end of etching.
0.13 μm. As a result, a line and space pattern having a width of 0.13 μm is formed. Since the etching characteristics of the platinum film 66 are improved as described above, the margin of the etching process is increased, and fine processing capable of coping with higher integration can be performed.

Next, as shown in FIG. 18E, the lower electrode 51 is formed by etching the ruthenium film 55 using the hard mask 68 as a mask. At this stage, a part of the hard mask 72 is also shaved, and its film thickness is reduced. The etching of the ruthenium film 55 is performed in the same manner as in the first embodiment. Therefore, the ruthenium film 55 is formed almost anisotropically with an anisotropic taper angle of 89 degrees.

Next, as shown in FIG. 18F, the titanium nitride film 47 which is the base of the ruthenium film 55 is etched using the hard mask 68 as a mask. At this stage, the hard mask 72 is shaved and almost disappears. Titanium nitride film 4
The etching of 7 is the same as that of the first embodiment. The hard mask 68 is partially removed by the etching of the titanium nitride film 47, and its thickness is reduced as shown in the figure.

Next, as shown in FIG. 18G, a BST film 58 is deposited without removing the hard mask 68. The BST film 58 can be formed in the same manner as in the first embodiment.
Thus, the BST can be performed without removing the hard mask 68.
The merit of depositing the film 58 is the same as the merit described in the first embodiment. Subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated. Since the hard mask 68 remaining on the surface of the lower electrode 51 is made of platinum, the hard mask 68 has excellent heat resistance, and the heat treatment in the oxidizing atmosphere of the BST film 58 does not cause the volume increase but also the deterioration. This is the same as in Embodiment 2.

According to the present embodiment, in addition to the effects described in the first embodiment, since hard mask 68 remaining on lower electrode 51 is made of platinum which is a conductor, hard mask 68 is also made of lower electrode 51. Function as part of
Since no side wall deposit is formed on the side surface of the hard mask 68, the entire region of the hard mask 68 in contact with the BST film 58 can function as a capacitor. That is,
Not only the upper surface of the hard mask 68 but also the hard mask 68
Can also function as a capacitor. As a result, the entire surface area of the lower electrode 51 and the surface of the hard mask 68 contributes to the capacitor, and the storage capacitance of the information storage capacitor C is further increased as compared with the second embodiment.
The performance of M can be improved. Further, in this embodiment, the photoresist film 70 for performing the first patterning is used.
Can be formed wider than in Embodiment 3, so that the photolithography margin can be increased. Conversely, the present embodiment is more excellent in fine workability.

The lower electrode 51 is made of ruthenium dioxide,
Alternatively, as in the first embodiment, a laminated film of ruthenium and ruthenium dioxide can be used, and titanium nitride film 47 can be replaced with a silicon nitride film.

(Embodiment 5) DRA of Embodiment 5
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. Therefore,
A method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 19 is a cross-sectional view showing one example of a manufacturing process of the information storage capacitor of the DRAM according to the fifth embodiment in the order of the processes. FIG. 19 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 of the first embodiment, FIG.
As shown in FIG. 3A, a ruthenium film 55 and a BST film 73 are formed on a titanium nitride film 47, and a patterned photoresist film 70 is formed on the BST film 73.

Since the ruthenium film 55 is the same as in the first embodiment, a detailed description is omitted. BST film 7
Numeral 3 functions as a hard mask when the ruthenium film 55 is etched and also functions as a part of the capacitance insulating film. The thickness is set to 0.1 μm in consideration of a decrease in a later etching step.

The photoresist film 70 is used as a mask when patterning the BST film 73, and is formed by a usual photolithography process. Photoresist film 7
0 is patterned in the same manner as in the second embodiment.
The width of the ST film 73 is reduced in advance in consideration of the increase in the bottom area due to the formation of the tapered portion when etching the ST film 73. That is, as shown in the figure, the pattern width is set to 0.1 μm. The pattern interval is 190 nm. The thickness of the photoresist film 70 is set to 300 nm in consideration of a decrease in the etching of the BST film 73. As in the first embodiment, an EB (Electron Beam) resist can be used for the photoresist film 70. Note that the photoresist film 70 is formed in a rounded or chamfered shape at its upper portion (ridge) as in the second embodiment, that is, a round resist.

Next, as shown in FIG. 19B, the BST film 73 is patterned using the photoresist film 70 as a mask to form a hard mask 74 made of BST.
The etching of the BST film 73 is performed in the same manner as in the third embodiment. That is, as the etching conditions, for example, the reaction pressure is 1 mTorr, the RF power is 2 kW, the etching gas is chlorine (Cl ₂ ) 15 sccm, and the substrate temperature is 30 ° C.
Under such etching conditions, the etching rate of the BST film 73 is about 150 nm / min, and the selectivity to the photoresist film 70 is about 1. At the end of etching, the taper angle of the patterned BST film 73 (hard mask 74) changes from 70 degrees to 80 degrees, the bottom of the hard mask 74 becomes wider than the original pattern width of the photoresist film 70, and the bottom of the hard mask 74 at the end of etching. Is 0.13 μm. As a result, a line and space pattern having a width of 0.13 μm is formed.

Next, as shown in FIG. 19C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 19D, the lower electrode 51 is formed by etching the ruthenium film 55 using the hard mask 74 as a mask. The etching of the ruthenium film 55 is performed in the same manner as in the first embodiment. Therefore, the ruthenium film 55 is formed almost anisotropically with an anisotropic taper angle of 89 degrees. Note that when the ruthenium film 55 is etched, the hard mask 74 is also partially etched.

Next, as shown in FIG. 19E, the titanium nitride film 47 is etched using the hard mask 74 as a mask. The etching of the titanium nitride film 47 is the same as in the first embodiment. The hard mask 74 is partially removed by the etching of the titanium nitride film 47, and its thickness is reduced.

Next, as shown in FIG. 19F, a BST film 58 is deposited without removing the hard mask 74. The BST film 58 can be formed in the same manner as in the first embodiment.
Thus, the BST can be performed without removing the hard mask 74.
The merit of depositing the film 58 is the same as the merit described in the first embodiment.

Next, as shown in FIG.
The film 58 is subjected to a heat treatment in an oxygen atmosphere. At this time, the hard mask 74 made of BST is integrated with the BST film 58. Subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated.

According to the present embodiment, in addition to the effect described in the first embodiment, the hard mask 74 left over the lower electrode 51 is made of BST,
4 and the BST film 58 are integrally formed. For this reason, the adhesiveness of the BST film 58 on the lower electrode 51 becomes extremely good. Thereby, the information storage capacitor C can be formed with high reliability. Also, since BST is a ferroelectric material,
The contribution of the upper part of the lower electrode 51 to the capacitance of the capacitor is somewhat larger than that of the first embodiment. Therefore, the storage capacitance of the information storage capacitor C can be increased.

The lower electrode 51 is made of ruthenium dioxide,
Alternatively, as in the first embodiment, a laminated film of ruthenium and ruthenium dioxide can be used, and titanium nitride film 47 can be replaced with a silicon nitride film.

(Embodiment 6) DRA of Embodiment 6
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. However,
In this embodiment, a titanium oxide film 75 is used instead of the titanium nitride film 47 of the first embodiment. Titanium oxide film 75
Can be formed by a CVD method or a sputtering method, and the film thickness is 3
It is set to 0 nm. Therefore, a method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 20 is a cross-sectional view showing an example of the manufacturing process of the information storage capacitor element of the DRAM according to the sixth embodiment in the order of steps. FIG. 20 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 of the first embodiment (however, a titanium oxide film 75 is formed instead of the titanium nitride film 47), as shown in FIG.
A ruthenium film 55 and a titanium oxide film 76 are formed thereon, and a patterned photoresist film 70 is formed on the titanium oxide film 76.

The ruthenium film 55 is the same as in the first embodiment. The titanium oxide film 76 is formed of the ruthenium film 5
5 functions as a hard mask when etching. The thickness of the titanium oxide film 76 is 30 nm.

The photoresist film 70 is made of titanium oxide film 7
6 is used as a mask when patterning, and is formed by a normal photolithography process. The patterning of the photoresist film 70 is performed in the same manner as in the first embodiment.

Next, as shown in FIG. 20B, using the photoresist film 70 as a mask, the titanium oxide film 76 is patterned to form a hard mask 77. The etching of the titanium oxide film 76 can be performed in the same manner as in Embodiment 3. Further, since the titanium oxide film 76 is as thin as 30 nm, the etching anisotropy does not matter, and the hard mask 77 is patterned to have substantially the same dimensions as the photoresist film 70. As a result, a line and space pattern having a width of 0.13 μm is formed.

Next, as shown in FIG. 20C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 20D, the lower electrode 51 is formed by etching the ruthenium film 55 using the hard mask 77 as a mask. The etching of the ruthenium film 55 is performed in the same manner as in the first embodiment.

Next, as shown in FIG. 20E, the hard mask 77 (titanium oxide film) and the titanium oxide film 75 are etched.

Next, as shown in FIG.
A film 58 is deposited. The BST film 58 can be formed in the same manner as in the first embodiment. In this manner, the lower electrode 51 can be formed using titanium oxide as the hard mask 77 in the same manner as in the first to fifth embodiments. Note that tantalum oxide can be used instead of the titanium oxide film.

(Embodiment 7) DRA of Embodiment 7
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. Therefore,
A method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 21 is a sectional view showing an example of a manufacturing process of the information storage capacitor of the DRAM according to the seventh embodiment in the order of processes. FIG. 21 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 in the first embodiment (however,
A silicon nitride film 78 is formed instead of the titanium nitride film 47 of the first embodiment. 21), a ruthenium film 55, a platinum film 79 and a silicon oxide film 71 are formed on a silicon nitride film 78, as shown in FIG.
A patterned photoresist film 70 is formed thereon.

Since the ruthenium film 55 is the same as that of the third embodiment, a detailed description is omitted. Platinum film 79
Is a kind of blocking film when the ruthenium film 55 is etched, and has a function of protecting the surface of the lower electrode 51. Further, the platinum film 79 functions as a part of the lower electrode 51. The thickness of the platinum film 79 is 30 nm.

The silicon oxide film 71 is similar to the silicon oxide film 56 of the first embodiment. The silicon oxide film 56 functions as a hard mask when the platinum film 79 and the ruthenium film 55 are etched, and the thickness thereof is 0.3 μm in consideration of a decrease in a later etching step.
And

The photoresist film 70 is used as a mask when patterning the silicon oxide film 71, and is formed by a usual photolithography process. The patterning of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 21B, the silicon oxide film 71 is etched using the photoresist film 70 as a mask to form a hard mask 72 made of a silicon oxide film.
To form Since the silicon oxide film is formed with good anisotropy, the pattern of the photoresist film 70 is faithfully reproduced.
The pattern width is 130n even at the bottom of the hard mask 72.
m, and a pattern interval of 130 nm.

Next, as shown in FIG. 21C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 21D, the platinum film 79 and the ruthenium film 55 are etched using the hard mask 72 made of a silicon oxide film as a mask. The etching of the ruthenium film 55 is performed in the same manner as in the first embodiment. Therefore, the ruthenium film 55 is formed almost anisotropically with an anisotropic taper angle of 89 degrees. Thereby, the lower electrode 5
Form one. The platinum film 7 is provided on the upper surface of the lower electrode 51.
9 are formed, and the platinum film is hardly scraped in this etching step, so that the ruthenium film can be prevented from being shaved. Also, the hard mask 72 is sharply shaved,
The film thickness is reduced to such an extent that the film slightly remains on the upper portion of the lower electrode 51.

Next, as shown in FIG. 21E, the hard mask 72 is removed. In the step of removing the hard mask 72, the platinum film 79 is hardly scraped. Since the underlayer is formed of the silicon nitride film 78, the underlayer is not excessively etched.

Next, as shown in FIG. 21F, a BST film 58 is deposited without removing the platinum film 79. BS
The T film 58 can be formed in the same manner as in the first embodiment. The merit of depositing the BST film 58 without removing the platinum film 79 is the same as the merit described in the first embodiment. Subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated.

Since the platinum film 79 remains on the surface of the lower electrode 51, the heat resistance is excellent, and the BST film 58 does not undergo any heat treatment in an oxidizing atmosphere, and does not undergo any alteration. Also, the platinum film 79 functions as a part of the lower electrode 51, and the entire surface of the lower electrode 51 in contact with the BST film 58 can function as a capacitor. Thereby, the entire surface area of the lower electrode 51 contributes to the capacitor, the storage capacity of the information storage capacitor C is increased, and the performance of the DRAM can be improved.

Note that the lower electrode 51 is made of ruthenium dioxide,
Alternatively, it can be a laminated film of ruthenium and ruthenium dioxide as in the first embodiment.

(Embodiment 8) DRA of Embodiment 8
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. Therefore,
A method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 22 is a cross-sectional view showing an example of a manufacturing process of the information storage capacitor of the DRAM according to the eighth embodiment in the order of processes. FIG. 22 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 of the first embodiment, FIG.
As shown in (a), a ruthenium film 55 and a silicon nitride film 80 are formed on a titanium nitride film 47, and a patterned photoresist film 70 is formed on the silicon nitride film 80.
To form

Since the ruthenium film 55 is the same as that of the first embodiment, a detailed description is omitted. The silicon nitride film 80 functions as a hard mask when the ruthenium film 55 is etched, and has a thickness of the ruthenium film 55.
The thickness is set to 60 nm in consideration of the decrease in film thickness during the etching.

The photoresist film 70 is used as a mask when patterning the silicon nitride film 80, and is formed by a usual photolithography process. The patterning of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 22B, the silicon nitride film 80 is etched using the photoresist film 70 as a mask to form a hard mask 81 made of a silicon nitride film.
To form Since the silicon nitride film is formed with good anisotropy, the pattern of the photoresist film 70 is faithfully reproduced,
The pattern width is 130n even at the bottom of the hard mask 81.
m, and a pattern interval of 130 nm.

Next, as shown in FIG. 22C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 22D, the ruthenium film 55 is etched using the hard mask 81 made of a silicon oxide film as a mask. The etching of the ruthenium film 55 is performed in the same manner as in the first embodiment. Therefore, the ruthenium film 55 is formed almost anisotropically with an anisotropic taper angle of 89 degrees. Thereby, the lower electrode 51 is formed. In this etching step, the hard mask 81 is slightly etched, and its thickness is reduced to 40 nm.

Next, as shown in FIG. 22E, the titanium nitride film 47 is removed. In the step of removing the titanium nitride film, the hard mask 81 is further shaved, so that the ridge is rounded. As a result, the BST film 58 in the next step
And the reliability of the information storage capacitor C can be improved.

Next, as shown in FIG. 22F, a BST film 58 is deposited without removing the hard mask 81. The BST film 58 can be formed in the same manner as in the first embodiment.
Thus, the BST can be performed without removing the hard mask 81.
The advantage of depositing the film 58 is the same as the advantage described in the first embodiment. Further, in the present embodiment, a silicon nitride film having a higher dielectric constant than the silicon oxide film is used as the hard mask 81, so that the hard mask 81 contributes to the capacitance value of the capacitor above the lower electrode 51 as compared with the first embodiment. The rate of doing it increases. Subsequent steps are described in Embodiment 1.
The description is omitted because it is the same as.

Note that the lower electrode 51 is made of ruthenium dioxide,
Alternatively, it can be a laminated film of ruthenium and ruthenium dioxide as in the first embodiment.

(Embodiment 9) DRA of Embodiment 9
M differs from the DRAM of the first embodiment only in the configuration and the manufacturing method of the information storage capacitor C, and other configurations and the manufacturing method are the same as those of the first embodiment. Therefore,
A method of manufacturing the information storage capacitor C will be described, and other description will be omitted.

FIG. 23 is a cross-sectional view showing one example of the manufacturing process of the information storage capacitor of the DRAM according to the ninth embodiment in the order of processes. FIG. 23 is similar to FIG. 1 and FIG.
0 (a) shows a cross section taken along line BB, and
3 shows only the area of the information storage capacitance element C.

After the step of FIG. 8 of the first embodiment (however,
A silicon nitride film 78 is formed instead of the titanium nitride film 47 of the first embodiment. 23, a ruthenium film 55 and a silicon oxide film 82 are formed on a silicon nitride film 78, and a patterned photoresist film 70 is formed on the silicon oxide film 82, as shown in FIG.

Since the ruthenium film 55 is the same as that of the first embodiment, a detailed description is omitted. The silicon oxide film 82 functions as a hard mask when the ruthenium film 55 is etched.
Is selected so that it just disappears when the etching is completed. For example, it is set to 150 nm.

The photoresist film 70 is used as a mask when patterning the silicon oxide film 82, and is formed by a usual photolithography process. The patterning of the photoresist film 70 is selected in consideration of the film thickness of the silicon oxide film 82 so that the silicon oxide film 82 just disappears when the etching of the ruthenium film 55 is completed. The thickness of the silicon oxide film 82 is 150 nm
In this case, for example, the pattern width is set to 80 nm and the pattern interval is set to 180 nm.

Next, as shown in FIG. 23B, the silicon oxide film 82 is etched using the photoresist film 70 as a mask to form a hard mask 83 made of a silicon nitride film.
To form Since the silicon oxide film is formed with good anisotropy, the pattern of the photoresist film 70 is faithfully reproduced.
Even at the bottom of the hard mask 83, the pattern width is 80n.
m, and a pattern interval of 180 nm is maintained.

Next, as shown in FIG. 23C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 23D, the ruthenium film 55 is etched using the hard mask 83 made of a silicon oxide film as a mask. The etching of the ruthenium film 55 is slightly changed from the etching condition of the first embodiment, and a condition in which the etching shape of the ruthenium film 55 has a slightly tapered shape is selected. For example, in the first embodiment, 100% over-etching is performed.
0%. Other conditions are the same as in the first embodiment. Under such conditions. The ruthenium film 55 is not etched at a taper angle of 89 degrees, but is etched at about 85 degrees. Further, as described above, the film thickness and the pattern width are selected so that the hard mask 83 disappears when the etching of the ruthenium film 55 is completed. As a result, when the etching is completed, the sectional shape of the lower electrode 51 becomes
As shown in the figure, the shape becomes triangular. As described above, in the present embodiment, the hard mask 8 is formed when the formation of the lower electrode 51 is completed.
3 has disappeared and need not be removed by etching. As a result, the process is simplified and the lower electrode 51
Does not degrade the processed shape and does not roughen the base.

Next, as shown in FIG.
A film 58 is deposited. The BST film 58 can be formed in the same manner as in the first embodiment.

As described above, in the present embodiment, it is not necessary to remove the hard mask 83, so that the same effect as that described in the first embodiment can be obtained. Further, in the present embodiment, the lower electrode 51 and the BST film 58 can be obtained. Since no substance that reduces the capacitance value is formed between them, the entire surface area of the lower electrode 51 can be used effectively.

The lower electrode 51 is made of ruthenium dioxide,
Alternatively, it can be a laminated film of ruthenium and ruthenium dioxide as in the first embodiment. Further, the silicon nitride film 78 can be replaced with a titanium nitride film. In this case, it is necessary to etch the titanium nitride film after the step of FIG. Considering an increase in the etching process, it is preferable to use the silicon nitride film 78.

(Embodiment 10) D of Embodiment 10
The RAM differs from the DRAM of the first embodiment in the configuration and manufacturing method of the information storage capacitor C, and the other configurations differ in the dimensions of each member. That is, in the first embodiment, the lower electrode 51 is connected to B-
Although formed at a pitch of 260 μm in the B-line direction, in the present embodiment, they are formed at a pitch of 160 μm. That is, the DRAM of the present embodiment is applied to a device having an integration degree of 4 to 16 Gbit. Therefore, the dimensions of the portion other than the information storage capacitance element C are formed so as to conform to the 160 μm pitch.

FIG. 24 is a cross-sectional view showing an example of a manufacturing process of the information storage capacitor of the DRAM according to the tenth embodiment in the order of processes. FIG. 24 shows a cross section taken along line BB in FIG. 10A, as in FIGS.
Only the area of the M information storage capacitor C is shown.

After the step of FIG. 8 of the first embodiment (however, each member is formed so as to conform to the dimensions described above. In addition, a titanium oxide film 75 is formed instead of the titanium nitride film 47. 24, an iridium film 84, a ruthenium film 85 and a silicon oxide film 86 are formed on a silicon nitride film 75, and a patterned photoresist film 70 is formed on the silicon oxide film 86, as shown in FIG. .

The iridium film 84 is formed by, for example, a CVD method or a sputtering method, and becomes a part of the lower electrode 51. The thickness is, for example, 300 nm. The ruthenium film 85 is used as a part of a hard mask when etching the iridium film 84, and is formed with a thickness of 100 nm. Silicon oxide film 8
6 is the same as the silicon oxide film 56 of the first embodiment, and functions as a hard mask when the ruthenium film 85 is etched. The thickness is set to 100 nm in consideration of a decrease in a later etching step.

The photoresist film 70 is used as a mask when patterning the silicon oxide film 86, and is formed by a usual photolithography process. The patterning of the photoresist film 70 is performed in the same manner as in the first embodiment. However, the pattern size is smaller than in the first embodiment, the pattern width is 80 nm, and the pattern interval is 80
nm. The thickness of the photoresist film 70 is set to 300 in consideration of a decrease in etching the silicon oxide film 86.
nm. EB (Electron B)
eam) As in the first embodiment, a resist can be used.

Next, as shown in FIG. 24B, the silicon oxide film 86 is etched using the photoresist film 70 as a mask to form a hard mask 87 for patterning the ruthenium film 85. Since the silicon oxide film is formed with good anisotropy, the pattern of the photoresist film 70 is faithfully reproduced, and the bottom of the hard mask 87 is also formed with a pattern width of 80 nm and a pattern interval of 80 nm.

Next, as shown in FIG. 24C, the photoresist film 70 is removed. The removal of the photoresist film 70 is the same as in the first embodiment.

Next, as shown in FIG. 24D, the ruthenium film 85 is patterned using the hard mask 87 made of a silicon oxide film as a mask to form a hard mask 88 made of ruthenium. For the etching of the ruthenium film 85, the highly anisotropic etching of ruthenium described in the step of FIG. 11D of the first embodiment is used. Under such etching conditions, the etching rate of the ruthenium film 85 is about 112 nm / min, and the selectivity to the hard mask 87 made of a silicon oxide film is as large as about 10. Under such conditions, the taper angle of the hard mask 88 is formed substantially perpendicular to 89 degrees, and a pattern of the hard mask 88 that faithfully reproduces the pattern of the hard mask 87 is formed. At this stage, a part of the hard mask 87 is also shaved, and its film thickness is reduced.

Next, as shown in FIG. 24E, the lower electrode 51 is formed by etching the iridium film 84 using the hard masks 87 and 88 as masks. At this stage, the hard mask 87 is further removed, and the film thickness is further reduced. The etching of the iridium film 84 is performed in the same manner as the etching of the ruthenium film 85 in the previous step. Accordingly, the iridium film 84 is formed almost anisotropically with a taper angle of 89 degrees with good anisotropy.

Next, as shown in FIG. 24F, a PZT film 89 is deposited without removing the hard masks 87 and 88. The PZT film 89 is formed, for example, by sputtering or CV.
It can be formed by Method D. Thus, the hard mask 87,
The merit of depositing the PZT film 89 without removing the 88 is similar to the merit described in the first embodiment.
Since the hard mask 88 formed on the surface of the lower electrode 51 is made of ruthenium, it has excellent heat resistance,
The affinity with the PZT film 89 is also high. Further, the side portion of the hard mask 88 can contribute to the capacitance value of the capacitor. However, since the hard mask 87 is composed of a silicon oxide film, that portion does not contribute to the capacitance value of the capacitor. As described in the first embodiment, even if there is a portion that does not contribute to the capacitance value of the capacitor, the reduction rate of the entire capacitance value is within an allowable range.

The subsequent steps are substantially the same as those in Embodiment 1 and will not be described. However, annealing of the PZT film 89 is performed at about 500 ° C., and an iridium film is used as the upper electrode.

According to the present embodiment, in addition to the effects described in the first embodiment, a highly integrated information storage capacitor C can be formed. As a result, a DRAM of 4 to 16 Gbit class can be manufactured.

The lower electrode 51 can be made of iridium oxide or a laminated film of iridium and iridium oxide. After the step of FIG. 24E, the hard mask 87 can be removed while the silicon nitride film 75 is etched. In this case, the hard mask 87 does not exist, and the upper surface of the hard mask 88 can also contribute to the capacitance value of the capacitor. Thereby, the storage capacity can be increased.

(Embodiment 11) FIGS. 25 and 26
FIG. 39 is a cross-sectional view showing an example of the manufacturing process of the FeRAM according to the eleventh embodiment with respect to the information storage capacitor C in the order of processes. The FeRAM of the present embodiment has a selection MIS
The parts of the FET and the peripheral circuit are the same as in the first embodiment. Hereinafter, only the information storage capacitor C will be described.

After the step of FIG. 8 of the first embodiment, FIG.
As shown in (a), a titanium film 90 having a thickness of 20 nm, an iridium film 91 having a thickness of 150 nm, a platinum film 92 having a thickness of 20 nm, a PZT film 93 having a thickness of 250 nm, and a film thickness of 150 n
m iridium film 94 and a 20 nm-thick platinum film 9
5 are sequentially deposited. Further, a round resist film 96 similar to that described in the second embodiment is formed on the platinum film 95. The round resist film 96 is formed on the plug 49.

Next, as shown in FIG. 25B, the platinum film 95 is etched using the round resist film 96 as a mask. The etching of the platinum film 95 can be performed by using, for example, a magnetron reactive ion etching method. The etching conditions are, for example, a reaction pressure of 5 mTorr.
r, RF power of 1.2 kW, etching gas of chlorine (Cl
₂ ) and 20 sccm and 10 sc argon respectively
cm and the substrate temperature can be 30 ° C. Under such conditions, the taper angle exhibits anisotropy of about 70 degrees. In this etching, since the round resist film 96 is formed, no deposit is generated on the side wall of the etched platinum film 95.

Next, as shown in FIG. 25C, the round resist film 96 is removed by ashing or the like, and the iridium film 94 is etched using the etched platinum film 95 as a mask (FIG. 25D). . This iridium film 94
Is also performed in the same manner as the etching of the platinum film 95. The taper angle of the etched iridium film 94 is approximately 70 degrees, and no side wall deposits are generated.

Next, a resist film 97 is formed so as to cover the etched iridium film 94 without removing the platinum film 95 used as a hard mask at the time of etching the iridium film 94 (FIG. 25E). ). afterwards,
The PZT film 93 is etched using the resist film 97 as a mask (FIG. 25F). The etching of the PZT film 93 is performed in the same manner as the etching of the platinum film 95. The taper angle of the etched PZT film 93 is about 70 degrees, and no side wall deposits are generated.

Next, the resist film 97 is removed (FIG. 25).
(G)) A resist film 98 is formed so as to cover the etched PZT film 93. Thereafter, the platinum film 92 is etched using the resist film 98 as a mask (FIG. 25).
(H)). Further, using the resist film 98 and the etched platinum film 92 as a mask, the iridium film 91 and the titanium film 90 are etched (FIG. 25 (i)). Finally, the resist film 98 is removed by ashing or the like (FIG. 25).
(J)).

Thus, the upper electrode composed of the patterned platinum film 95 and the iridium film 94, the dielectric film composed of the patterned PZT film 93, and the lower electrode composed of the patterned platinum film 92 and the iridium film 91 A capacitor comprising the electrodes is formed.

According to the present embodiment, the platinum films 95, 92
Can be used to etch the iridium films 94 and 91, and a FeRAM capacitor can be formed accurately.

Incidentally, ruthenium can be used instead of platinum. In this case, the etching method of the ruthenium film described in Embodiment 1 can be used. Further, BST can be used instead of PZT.

As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the second embodiment, platinum is used as a hard mask when etching the ruthenium film 55, but the lower electrode 51 is made of iridium, iridium oxide,
Alternatively, a stacked film of iridium and iridium oxide can be used. In this case, the thickness of the conductive film such as iridium to be the lower electrode 51 is 300 nm, the dimension of the photoresist film 67 is 60 nm in pattern width, and 100 nm in pattern interval.
It can be. Alternatively, a PZT film can be used as the capacitor insulating film, and iridium, iridium oxide, or a stacked film of iridium and iridium oxide can be used as the upper electrode. Embodiment 2 in such a configuration
By applying the manufacturing method described in
A 16 Gbit class DRAM can be manufactured.

Further, the PZT film can be applied to an etching mask (hard mask) of iridium, iridium oxide, or a laminated film of iridium and iridium oxide. The ruthenium film 55 of the fifth embodiment is replaced with iridium, iridium oxide, or a laminated film of iridium and iridium oxide, the BST film 73 is replaced with a PZT film, and the dimensions of the photoresist film 70 are changed to a pattern width of 60 nm and a pattern interval of 100 nm. Embodiment 5
By applying the processing method described above, a lower electrode made of iridium or the like can be formed. In such a configuration, as in the tenth embodiment, a DRAM of 4 to 16 Gbit class is used.
Can be manufactured. In this case, PZ is used as the capacitance insulating film.
The use of a T film and a laminated film of iridium, iridium oxide, or iridium and iridium oxide as the upper electrode is the same as described above.

[0270]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) Fine etching of ruthenium or ruthenium oxide suitable for a ferroelectric film such as BST can be realized.

(2) It is possible to prevent the thinning of the pattern, the occurrence of roughening of the upper surface of the pattern, and the shaving of the underlying insulating film due to the step of removing the hard mask such as the titanium nitride film, thereby forming a highly reliable capacitive insulating film.

(3) The storage capacitor forming step can be simplified.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to a first embodiment is formed.

FIG. 2 is an equivalent circuit diagram of a DRAM according to a second embodiment.

FIG. 3 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 4 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 5 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps.

FIG. 6 is a cross-sectional view showing an example of the manufacturing process of the DRAM according to the first embodiment in the order of steps;

FIG. 7 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 8 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps.

FIG. 9 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 10 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 11 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps.

FIG. 12 is a sectional view illustrating an example of a manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 13 is a conceptual sectional view showing an example of an etching apparatus used for etching a ruthenium film.

FIG. 14 is a graph illustrating the concept of over-etching.

FIG. 15 is a cross-sectional view showing an example of the manufacturing process of the DRAM of the first embodiment in the order of steps;

FIG. 16 is a cross-sectional view showing an example of a manufacturing process of the information storage capacitor of the DRAM according to the second embodiment in order of process;

FIG. 17 is a cross-sectional view showing an example of the manufacturing process of the information storage capacitor of the DRAM according to the third embodiment in the order of steps;

FIG. 18 is a cross-sectional view showing an example of a manufacturing step of the information storage capacitor element of the DRAM according to the fourth embodiment in the order of steps;

FIG. 19 is a cross-sectional view showing an example of a manufacturing step of the information storage capacitor of the DRAM according to the fifth embodiment in the order of steps;

FIG. 20 is a cross-sectional view showing an example of the manufacturing process of the information storage capacitor of the DRAM according to the sixth embodiment in the order of processes;

FIG. 21 is a cross-sectional view showing an example of the manufacturing process of the information storage capacitor of the DRAM according to the seventh embodiment in the order of steps;

FIG. 22 is a cross-sectional view showing an example of the manufacturing process of the information storage capacitor of the DRAM according to the eighth embodiment in the order of processes;

FIG. 23 is a cross-sectional view showing an example of a manufacturing step of the information storage capacitor element of the DRAM according to the ninth embodiment in the order of steps;

FIG. 24 is a cross-sectional view showing an example of a manufacturing step of the information storage capacitor element of the DRAM according to the tenth embodiment in the order of steps;

FIG. 25 is a cross-sectional view showing an example of the manufacturing process of the FeRAM according to the eleventh embodiment with respect to the information storage capacitor element in the order of processes.

FIG. 26 is a cross-sectional view showing an example of the manufacturing process of the FeRAM according to the eleventh embodiment with respect to the information storage capacitor element in the order of manufacturing steps;

FIG. 27 is a cross-sectional view schematically showing a relationship between a taper angle and a fine pattern shape.

[Explanation of symbols]

Reference Signs List 1 integrated circuit substrate 1A semiconductor chip 5 groove 5 element isolation groove 6 silicon oxide film 7 silicon oxide film 10 n-type semiconductor region 11 p-type well 12 n-type well 13 gate oxide film 14A gate electrode 14B gate electrode 14C gate electrode 15 silicon nitride Film 16 photoresist film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20a sidewall spacer 21 photoresist film 22 p ⁺ type semiconductor region 23 n ⁺ type semiconductor region 24 SOG film 25 Silicon oxide film 26 Silicon oxide film 28 Contact hole 29 Contact hole 30 Plug 31 Silicon oxide film 34 Contact hole 36 Contact hole 38 First layer wiring 40 Silicon nitride film 43 Sidewall spacer 44 SOG film 45 Recon oxide film 46 Silicon oxide film 47 Titanium nitride film 48 Through hole 49 Plug 50 Barrier metal 51 Lower electrode 51a Upper surface portion 51b Side surface portion 52 Silicon oxide film 53 Capacitive insulating film 54 Upper electrode 55 Ruthenium film 56 Silicon oxide film 57 Photoresist film 58 BST film 59 Ruthenium film 60 Photoresist film 61 Silicon oxide film 62 Through hole 63 Through hole 64 Plug 65 Second layer wiring 66 Platinum film 67 Photoresist film 68 Hard mask 69 Side wall deposit 70 Photoresist film 71 Silicon oxide film 72 Hard mask 73 BST film 74 Hard mask 75 Silicon nitride film 75 Titanium oxide film 76 Titanium oxide film 77 Hard mask 78 Silicon nitride film 79 Platinum film 80 Silicon nitride film 81 Hard mass 82 silicon oxide film 83 hard mask 84 iridium film 85 ruthenium film 86 silicon oxide film 87 hard mask 88 hard mask 89 PZT film 90 titanium film 91 iridium film 92 platinum film 93 PZT film 94 iridium film 95 platinum film 96 round resist film 97 resist Film 98 Resist film 100 Overetching amount 101 Reaction chamber 102 Vacuum piping 103 Sample table 104 Quartz tube 105 Inductive coupling coil 110 Gas supply nozzle BL Bit line BST Ferroelectric material C Information storage capacitor CV Control valve MARY Memory array MBP Mechanical booster pump MFC1 Mass Flow Controller MFC2 Mass Flow Controller Qn N-channel MISFET Qp P-channel MISFET Qs Memory cell Selecting MISFET RF1 frequency power source RF2 frequency power RV roughing valve S1 first area S2 second area SA the sense amplifier TMP turbomolecular pump WD word driver WL the word line t time

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 16, 1999 (1999.2.1
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0263

[Correction method] Change

[Correction contents]

Next, the resist film 97 is removed (FIG. 26).
(G)) A resist film 98 is formed so as to cover the etched PZT film 93. Thereafter, the platinum film 92 is etched using the resist film 98 as a mask (FIG. 26).
(H)). Further, using the resist film 98 and the etched platinum film 92 as a mask, the iridium film 91 and the titanium film 90 are etched (FIG. 26 (i)). Finally, the resist film 98 is removed by ashing or the like (FIG. 26).
(J)).

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] FIG. 26

[Correction method] Change

[Correction contents]

FIG. 26

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Joe Yuji 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in Hitachi Device Co., Ltd. F-term (reference) 5F083 AD21 AD56 AD60 FR01 GA21 HA02 JA15 JA17 JA19 JA32 JA38 JA39 JA40 JA42 JA43 KA01 KA05 LA03 LA12 LA16 LA29 LA30 NA01 PR03 PR12 PR21 PR33 PR36 PR40

Claims (33)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) forming a first conductive film to form a lower electrode of an information storage capacitor of a memory cell on a main surface of an integrated circuit wafer; (B) forming a first dielectric film pattern made of a high-dielectric or ferroelectric film on the first conductive film; (c) a state in which the first dielectric film pattern is present Patterning the first conductive film by subjecting the first conductive film to dry etching; and (d) patterning the first conductive film and the first dielectric film. Forming a second dielectric film made of a high dielectric or ferroelectric film to form a capacitance insulating film of the information storage capacitor of the memory cell on the pattern surface; (e) the second dielectric film The information storage capacity of the memory cell Forming a second conductive film for constituting an upper electrode of the child. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a photoresist pattern is not used in the step (c). 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein said first dielectric film and said second dielectric film are made of a substance having substantially the same molecular structure. A method for manufacturing a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein said first conductive film is made of a platinum group element or an oxide thereof. 5. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) A platinum group or an oxide thereof to form a lower electrode of an information storage capacitor of a memory cell on a main surface of an integrated circuit wafer Forming a first inorganic film pattern on the first conductive film; and (c) forming a first inorganic film pattern on the first conductive film. Patterning the first conductive film by subjecting the first conductive film to dry etching; and (d) forming the memory on the patterned first conductive film and the first inorganic film pattern surface. Forming a second dielectric film that is to constitute a capacitive insulating film of the information storage capacitor of the cell; (e) forming an upper electrode of the information storage capacitor of the memory cell on the second dielectric film The second conductive film to be The step of forming. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein a photoresist pattern is not used in the step (c). 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein said first inorganic film pattern is made of a silicon oxide film. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said first inorganic film pattern is made of a compound containing metal and nitrogen. 9. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) Ruthenium, iridium, or their oxidation to constitute a lower electrode of an information storage capacitor element of a memory cell on a main surface of an integrated circuit wafer (B) forming a first platinum film pattern on the first conductive film; (c) forming a first platinum film pattern on the first conductive film; Patterning the first conductive film by subjecting the first conductive film to dry etching; (d) forming a pattern on the surface of the patterned first conductive film and the first platinum film pattern; Forming a first dielectric film made of a high dielectric or ferroelectric film to form a capacitance insulating film of the information storage capacitor of the memory cell; (e) forming a first dielectric film on the first dielectric film; Memory cell Forming a second conductor film for constituting an upper electrode of the multi-address storage capacitor element. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein a photoresist pattern is not used in the step (c). 11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein said first conductive film is made of ruthenium or an oxide thereof. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein said first conductive film is made of iridium or its oxide. 13. (a) an integrated circuit substrate having a first main surface; (b) being disposed on the first main surface at an interval equal to or less than the width thereof, and A plurality of columnar lower electrodes constituting an information storage capacitor; (c) a high dielectric or ferroelectric material constituting a capacitance insulating film of an information storage capacitor of a memory cell provided on each side and upper surface of the columnar lower electrode; A first dielectric film made of a body film; (d) constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each of the side and top surfaces of the columnar lower electrode; A single or a plurality of upper electrodes; and each of the plurality of columnar lower electrodes has a tapered side surface such that the area of the upper surface is 25% or less of the area of the bottom surface. A semiconductor integrated circuit device characterized by the above-mentioned. 14. The semiconductor integrated circuit device according to claim 13, wherein at least a part of the plurality of columnar lower electrodes has a substantially triangular cross section in a direction in which the width is small. Integrated circuit device. 15. The semiconductor integrated circuit device according to claim 14, wherein each of said plurality of columnar lower electrodes has an aspect ratio of 2 or more in a direction in which a width of said lower electrode is narrower. Circuit device. 16. The semiconductor integrated circuit device according to claim 14, wherein each of the plurality of columnar lower electrodes has an aspect ratio of 3 or more in a direction in which the width of the lower electrode is narrower. Circuit device. 17. An integrated circuit substrate having a first main surface; and (b) being disposed on the first main surface at an interval equal to or less than the width thereof, and A plurality of columnar lower electrodes constituting an information storage capacitor; (c) a high dielectric or ferroelectric material constituting a capacitance insulating film of an information storage capacitor of a memory cell provided on each side and upper surface of the columnar lower electrode; A first dielectric film made of a body film; (d) constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each of the side and top surfaces of the columnar lower electrode; A single or a plurality of upper electrodes; and a portion corresponding to the upper surface of each of the plurality of columnar lower electrodes has a capacitance contribution to the information storage capacitor element of the corresponding memory cell of 3% or less. Semiconductor integrated circuit device 18. The semiconductor integrated circuit device according to claim 17, wherein at least a part of the plurality of columnar lower electrodes has a substantially triangular cross section in a direction in which the width is smaller. Circuit device. 19. The semiconductor integrated circuit device according to claim 18, wherein each of the plurality of columnar lower electrodes has a cross-sectional shape in a direction in which the width is smaller has an aspect ratio of 2 or more. Circuit device. 20. The semiconductor integrated circuit device according to claim 18, wherein each of the plurality of columnar lower electrodes has an aspect ratio of 3 or more in a direction in which the width is narrow. Circuit device. 21. (a) an integrated circuit substrate having a first main surface; and (b) disposed on the first main surface at an interval equal to or less than the width thereof, and A plurality of columnar lower electrodes constituting an information storage capacitor; (c) a high dielectric or ferroelectric material constituting a capacitance insulating film of an information storage capacitor of a memory cell provided on each side and upper surface of the columnar lower electrode; A first dielectric film made of a body film; (d) constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each of the side and top surfaces of the columnar lower electrode; A single or a plurality of upper electrodes; each of the plurality of columnar lower electrodes includes a lower electrode main portion occupying a maximum volume thereof and a lower electrode upper end portion of a different material arranged to cover the upper surface thereof. The head of the upper end of this lower electrode The semiconductor integrated circuit device, characterized by having a large chamfered shape compared to the cross-sectional shape of the head end portions of the lower electrode main portion at both ends. 22. The semiconductor integrated circuit device according to claim 21, wherein the lower electrode upper end of each of the plurality of columnar lower electrodes has a trapezoidal cross section. 23. The semiconductor integrated circuit device according to claim 21, wherein an upper end portion of each of the plurality of columnar lower electrodes has a triangular cross section. 24. The semiconductor integrated circuit device according to claim 21, wherein the upper end of the lower electrode of each of the plurality of columnar lower electrodes has a rectangular cross section in which the side surface of the head is cut out in the thickness direction by half or more. A semiconductor integrated circuit device comprising: 25. The semiconductor integrated circuit device according to claim 21, wherein the upper end of the lower electrode of each of the plurality of columnar lower electrodes is rounded so that the side surface of the head is more than half in the thickness direction. A semiconductor integrated circuit device having a cross-sectional shape. 26. (a) an integrated circuit substrate having a first main surface; and (b) being disposed on the first main surface at an interval equal to or less than the width thereof, and (C) a plurality of pillar-shaped lower electrodes mainly composed of ruthenium or an oxide thereof constituting the information storage capacitor; (c) a conductive film made of platinum provided on the upper end of each of the plurality of pillar-shaped lower electrodes; d) a first dielectric film made of a high dielectric or ferroelectric film constituting a capacitance insulating film of an information storage capacitor element of a memory cell provided on each of the side and top surfaces of the columnar lower electrode; A single or a plurality of upper electrodes constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each side and upper surface of the columnar lower electrode; Semiconductor integrated circuit device . 27. The semiconductor integrated circuit device according to claim 26, wherein each of said plurality of columnar lower electrodes is thicker than said conductive film formed thereon. apparatus. 28. The semiconductor integrated circuit device according to claim 27, wherein the thickness of each of the plurality of columnar lower electrodes is at least twice as thick as the conductive film formed thereon. Semiconductor integrated circuit device. 29. (a) an integrated circuit substrate having a first main surface; and (b) a dynamic RA which is arranged on the first main surface at an interval equal to or less than the width thereof.
A plurality of columnar lower electrodes mainly composed of iridium or an oxide thereof constituting the information storage capacitor element of the M memory cell; (c) a platinum lower electrode provided at the upper end of each of the columnar lower electrodes; (D) a first dielectric made of a high dielectric or ferroelectric film constituting a capacitive insulating film of an information storage capacitor element of a memory cell provided on each of the side and top surfaces of the columnar lower electrode; (E) a single or a plurality of upper electrodes constituting an information storage capacitor element of a memory cell provided on the first dielectric film provided on each of the side and upper surfaces of the columnar lower electrode; A semiconductor integrated circuit device comprising: 30. The semiconductor integrated circuit according to claim 29, wherein each of said plurality of columnar lower electrodes is thicker than said conductive film formed thereon. apparatus. 31. The semiconductor integrated circuit device according to claim 30, wherein the thickness of each of the plurality of columnar lower electrodes is at least twice as large as the thickness of the conductive film formed thereon. Semiconductor integrated circuit device. 32. (a) an integrated circuit substrate having a first main surface; (b) a first film pattern provided on the first main surface; and (c) a first film pattern on the first film pattern. A second film pattern made of a platinum group element or an oxide thereof provided; (d) a side wall adhered film adhered to a side surface when the second film pattern is patterned by dry etching; An insulating film formed directly or indirectly on the first film pattern so as to cover the adhesion film and the second film pattern. 33. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) forming a first film on a main surface of an integrated circuit wafer; (b) an inorganic member on the first film (C) forming a photoresist film on the second film; (d) patterning the photoresist film; and (e) patterning the photoresist. Performing a dry etching process on the second film in a state where the film is present, thereby patterning the second film and forming a sidewall adhesion film on a side surface of the patterning; The second having a sidewall adhesion film
Patterning the first film by performing a dry etching process on the first film in a state where the film is present.