JP2000183270A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise that is generated by an integrated circuit by reducing the inductance of the lead frame of the integrated circuit. SOLUTION: An inductance-reducing plate 1001 is arranged at the lower portion of a lead frame 1010 for feeding power and a lead frame 1020 for grounding with a proper distance. A ground potential is supplied to the inductance-reducing plate 1001. The effective inductance of the lead frame 1010 for feeding power can be drastically reduced by the mutual inductance between the lead frame 1010 for feeding power and the inductance-reducing plate 1001, thus suppressing noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power supply noise and radiation noise generated by an integrated circuit device.

[0002]

2. Description of the Related Art Generally, integrated circuits (ICs) such as LSIs
Is supplied in the form of an integrated circuit device in which a semiconductor chip on which an integrated circuit is formed is sealed in a package. In such an integrated circuit device, a lead frame for performing input / output of signals, power, and ground between a semiconductor chip and the outside is partially sealed in a package and partially exposed to the outside of the package. You. In the package, the semiconductor chip and the lead frame are connected by a thin wire, and signals, power, and ground can be input and output to and from the semiconductor chip from outside using a portion of the lead frame exposed outside the package.

[0003] As a technique for suppressing power supply noise (power supply bounce) and radiation noise generated in such an integrated circuit device, a conventional technique called "transistor technology SPECIAL" has been proposed.
No. 22 Special Issue: All about Digital Circuit Noise Suppression Technology, "Miyazaki et al., CQ Publishing Company (July 1990), p.
As described on pages 11 to 20, a bypass capacitor is mounted on a printed circuit board on which the integrated circuit device is mounted, such that the bypass capacitor is inserted between a power supply lead frame and a ground lead frame of the integrated circuit device. There is known a technology for mounting the device near a lead frame.

According to such a bypass capacitor,
Power supply noise and radiation noise generated in the integrated circuit device can be reduced to some extent.

[0005]

However, when the operating frequency of the integrated circuit increases, the influence of the inductance of the lead frame increases, and the power supply noise and radiation noise cannot be sufficiently reduced only by the technique using the bypass capacitor. There is.

For example, width w = 0.5 mm, thickness h = 0.25
mm and a length l = 10 mm, the inductance L of the lead frame is approximately 7.6 nH from Equation 1.
Inductance.

L = 0.0002l [ln (2l / (w + h) +0.2235 (w + h / l) +0.5) * 1000 [nH] (Equation 1) Therefore, for example, the operating frequency of the integrated circuit is 100
When the fifth harmonic of 500 MHz is considered, the impedance Z of the lead frame at the fifth harmonic of 500 MHz is expressed as f = operating frequency, ω (angular velocity) = 2πf, and Z = From ωL, 24
It is as large as Ω.

For this reason, when the fluctuation of the current consumption per unit time inside the integrated circuit (di / dt) is large, the potential of the power supply or ground in the integrated circuit is compared with the potential of the power supply or ground in the printed circuit board. Fluctuates, which may cause radiation noise and power supply noise.

[0009] The integrated circuit itself and an electronic device on which the integrated circuit is mounted may malfunction due to such radiation noise and power supply noise.

Accordingly, an object of the present invention is to reduce the noise generated in an integrated circuit by reducing the inductance of a lead frame of the integrated circuit.

[0011]

In order to achieve the above object,
The present invention relates to an integrated circuit device having a chip on which an integrated circuit is formed, a package for encapsulating the chip, and a lead frame partially connected to the package for connecting the chip to the outside. And a member to which a constant DC voltage is supplied and a member that forms mutual inductance with the lead frame. More specifically, a conductive member to which a constant DC voltage is supplied, which is disposed at a position facing the lead frame, is provided as the member.

According to such an integrated circuit device, the effective impedance of the lead frame can be reduced by the mutual inductance between the member and the lead frame, thereby suppressing generation of power supply noise and radiation noise. be able to.

[0013]

Embodiments of the present invention will be described below.

First, a first embodiment will be described.

FIG. 1 shows the structure of an integrated circuit device according to this embodiment. However, this drawing does not show the package of the integrated device for easy understanding.

FIG. 1 shows an integrated circuit device having a pin (lead frame) arrangement called a TTL. As shown, a semiconductor chip 1030 sealed in a package and a semiconductor chip 1030 sealed partially in a package are used. Power supply lead frame 1010, ground lead frame 1020, and signal lead frames 1015a and 1015
b is connected.

As shown in the figure, the inductance reducing plate 1001 is composed of a semiconductor chip 1030, a power supply lead frame 1010, and a ground lead frame 102.
0, disposed at an appropriate distance below the signal lead frames 1015a and 1015b. The inductance reducing plate 1001 is a conductive member and is sealed in a package (not shown). The ground potential is supplied to the inductance reducing plate 1001. As a structure for supplying the ground potential to the inductance reducing plate 1001, for example, the inductance reducing plate 1001 is connected to the ground lead frame 1020.
And the inductance reduction plate 1001
Is connected to the ground potential of the semiconductor chip 1030, or a lead frame that is connected only to the inductance reducing plate 1001 and a ground potential is supplied to the lead frame from the outside is used.

By adopting such a structure, the power supply lead frame 1010 has a ground plane formed by the inductance reducing plate 1001 at the lower part thereof.
A microstrip structure is formed by the power supply lead frame 1010 and the inductance reducing plate 1001. The effect of the mutual inductance due to the microstrip structure in this manner can significantly reduce the effective inductance of the power supply lead frame 1010, thereby suppressing the generation of noise.

FIG. 2 shows a model of an integrated circuit device. Inductance L1 (1110)
Is the inductance of the power supply lead frame 1010, and the inductance L2 (1120) is the inductance of the ground lead frame 1020. The resistance R (1115) is the resistance of the lead frame. The capacitor C (1130) is for imitating the load of the semiconductor chip, and the conductance G (1135) is for imitating the power consumption of the semiconductor chip. From FIG. 2, when an equation is set as L = L1 + L2 from Kirchoff's law regarding the current i1 flowing through the capacitor C (1130), the current i2 flowing through the conductance G (1135), and the current i1 + i2 flowing through the lead frame, the following equations are obtained. It becomes as follows.

[0020]

(Equation 1)

If i2 is expressed by the following equation 4,

[0022]

(Equation 2)

I1 is obtained as shown in Expression 5.

[0024]

(Equation 3)

## EQU1 ## From this, as L is smaller, the current i1 + i2 flowing through the lead frame with respect to the initial current A is more rapidly attenuated. Therefore, by reducing L by the structure shown in FIG. 1, noise can be reduced, and power supply noise and radiation noise can be reduced.

By changing the value of L, the resonance frequency f = 1 / (2π * √LC) of the system shown in FIG. 2 can also be changed. Therefore, when the frequency at which the problem occurs in the electronic device equipped with the integrated circuit device and the resonance frequency of the integrated circuit are the same, the resonance frequency can be shifted by changing L, whereby the electronic device can be moved. Thus, it is possible to prevent generation of large noise in a frequency band that is a problem.

As described above, according to the first embodiment, noise can be reduced by reducing the effective inductance of the power supply lead frame. Also, since the inductance reducing plate 1001 is arranged so as to provide a microstrip structure also to the signal lead frames 1015a and 1015b, similarly, the effective impedance of the signal lead frames 1015a and 1015b is reduced, and noise generation is reduced. It also has the effect of reducing.

In the first embodiment, a microstrip line structure may be provided to the ground lead frame 1020 by supplying a power supply potential to the inductance reducing plate 1001. The effective impedance of the ground lead frame 1020 can be reduced, and noise generation can be reduced. Also in this case, the microstrip line structure can be provided to the signal lead frames 1015a and 1015b by the inductance reducing plate 1001, and the effective impedance of the signal lead frames 1015a and 1015b is reduced, and the effect of reducing noise generation is also achieved. is there.

The inductance reducing plate 1001 has:
The same effect can be obtained by supplying a DC low voltage other than the power and the ground.

Hereinafter, a second embodiment of the present invention will be described.

FIG. 3 shows the configuration of an integrated circuit device according to the second embodiment. However, this figure also excludes the package of the integrated device for easy understanding.

This figure shows an integrated circuit device having a pin (lead frame) arrangement called TTL. As shown in the figure, a semiconductor chip 2030 sealed in a package is partially sealed in a package. Power supply lead frame 2010, ground lead frame 2020, and signal lead frames 2015a, 2015
b is connected.

Further, there are provided two inductance reduction plates 2001 and 2002 sealed in a package, which are a semiconductor chip 2030 and a power supply lead frame 201.
0, are disposed at a proper distance below the ground lead frame 2020 and the signal lead frames 2015a and 2015b.

Here, the first inductance reducing plate 20
01 includes the lower part of the power supply lead frame 2010;
It is arranged at a position not including the lower part of the ground lead frame 2020, and a ground potential is supplied as the potential. In addition, the second inductance reduction plate 2002
Includes a lower portion of the ground lead frame 2020,
The power supply lead frame 2010 is disposed at a position that does not include the lower portion, and a power supply potential is supplied as the potential. A structure similar to that of the first embodiment can be used as a structure for supplying each potential to the inductance reducing plates 2001 and 2002.

With such a structure, a microstrip line structure can be simultaneously provided to both the power supply lead frame 2010 and the ground lead frame 2020 to reduce the effective impedance and suppress the generation of noise. . Also in the second embodiment, the microstrip line structure can be given to the signal lead frames 2015a and 2015b by the inductance reduction plates 2001 and 2002, and the effective impedance of the signal lead frames 2015a and 2015 can be reduced. In addition, there is an effect of reducing noise generation.

Hereinafter, a third embodiment of the present invention will be described.

In the third embodiment, an effective impedance of a lead frame of an integrated circuit is reduced by providing a ground plate outside the integrated circuit device, and noise is suppressed.

That is, in this embodiment, as shown in FIG. 4A, the power supply lead frame 3010, the ground lead frame 3020, and the signal lead frame 301
Integrated circuit device 3050 having 5a, 3015b
And an integrated circuit device 3050 as shown in FIG.
The conductive ground plate 3000 shown in FIG. 4A is arranged between the substrates 3110 on which the
000 is connected to the ground lead frame 3020 of the integrated circuit device. The power supply potential and the ground potential are supplied to the integrated circuit device 3050 by connecting the power supply lead frame 3010 and the ground lead frame 3020 to the power supply and ground patterns on the substrate 3110.

By adopting such a structure, a microstrip structure can be provided for the power supply lead frame 3010, and its effective inductance can be reduced.
Generation of noise can be suppressed. In addition, since the ground plate 3000 is arranged so as to provide the signal lead frame 3015a with a microstrip structure, the effective impedance of the signal lead frame 3015a is similarly reduced, and the noise generation is also reduced.

In the third embodiment, the ground plate 3000 is connected to the power supply lead frame 3010,
A microstrip line structure may be provided to the ground lead frame 3020 by supplying a power supply potential. In this case as well, the effective impedance of the ground lead frame 3020 can be reduced and noise generation can be reduced. . Also in this case, since the ground plate 3000 is arranged so as to provide the signal lead frame 3015a with a microstrip structure, the effect of similarly reducing the effective impedance of the signal lead frame 3015a and reducing noise generation is obtained. is there.

The same effect can be obtained by supplying a low DC voltage other than the power and the ground to the ground plate 3000.

In this embodiment, the integrated circuit device 3
Ground plate 30 for impedance reduction outside
Since the structure is provided with 00, the present invention can also be applied to an integrated circuit device having no impedance reducing member inside such as the above-described impedance reducing plate.
In addition, when noise becomes a problem in the electronic device, the electronic device can be applied with flexibility, for example, by selecting a structure for attaching the ground plate 3000.

Hereinafter, a fourth embodiment of the present invention will be described.

FIG. 5A shows a semiconductor chip 4030 of an integrated circuit device according to this embodiment, a ground lead frame 4010 and a power supply lead frame 4020.
Of the semiconductor chip 4030 is shown. In this figure, the illustration of the package is omitted.

As shown in the figure, in this embodiment,
The power supply lead frame 4010 and the ground lead frame 4020 are arranged adjacent to each other. Then, the power supply lead frame 4010 and the ground lead frame 4020 are the same as shown in the AA ′ cross section in FIG. 5B so that both surfaces are opposed to each other and electromagnetic coupling between them is increased. At the same torsion angle θ.

With such a structure, the power supply lead frame 4010 and the ground lead frame 4
The electromagnetic coupling of 020 is greater than simply horizontal without twisting. Thus, the effective inductance of the power supply lead frame 4010 and the ground lead frame 4020 can be reduced, and noise can be suppressed. Further, the resonance frequency of the lead frame at this time can be changed only by adjusting the torsional angle θ without changing the configuration or arrangement of the components, so that several types of integrated devices having different resonance frequencies can be produced. Become like

Hereinafter, a fifth embodiment of the present invention will be described.

FIG. 6A shows a semiconductor chip 5030 of an integrated circuit device according to the present embodiment, a ground lead frame 5010 and a power supply lead frame 5020.
Of the semiconductor chip 4030 is shown. In this figure, the illustration of the package is omitted.

Now, as shown, in the present embodiment,
The power supply lead frame 5010 and the ground lead frame 5020 partially overlap in a direction perpendicular to the plane as shown in the AA ′ cross section in FIG. 6B, and at the outer end of the lead frame, It has a structure that is adjacent to the surface in the horizontal direction. With such a structure, the electromagnetic coupling between the power supply lead frame 5010 and the ground lead frame 5020 can be further increased, the effective inductance between the power supply lead frame 5010 and the ground lead frame 5020 can be reduced, and noise can be reduced. Can be suppressed.

[0050]

As described above, according to the present invention, by reducing the inductance of the lead frame of the integrated circuit,
Noise generated in the integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit that models the integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a structure of an integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a structure of an integrated circuit device according to a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a structure of an integrated circuit device according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating a structure of an integrated circuit device according to a fifth embodiment of the present invention.

[Explanation of symbols]

 1001 ... Inductance reduction plate, 1010 ... Power supply lead frame, 1015a, b ... Signal lead frame, 1020 ... Ground lead frame, 1030 ... Semiconductor chip, 2001 ... Inductance reduction plate, 2002 ... Inductance Reduction plate, 2010 ... Lead frame for power supply, 2015a, b ... Lead frame for signal, 2020 ... Lead frame for ground, 2030 ... Semiconductor chip, 3000 ... Ground plate, 3010 ... Lead frame for power supply, 3015a , B ... signal lead frame, 3020 ... ground lead frame, 3050 ... integrated circuit device, 3110 ... board, 4010 ... power supply lead frame, 4020 ... ground lead frame, 4030 ... semiconductor chip , 5010 ... Lead frame for power supply, 5020 ... Lead frame for ground, 5030 ... Semiconductor chip.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yokota, etc. 810 Shimoimaizumi, Ebina-shi, Kanagawa PC Division, Hitachi, Ltd. F-term (reference) 5F067 CD00 CD03 in Semiconductor Division, Hitachi, Ltd.

Claims (10)

[Claims] An integrated circuit comprising a chip on which an integrated circuit is formed, a package for sealing the chip, and a lead frame partially connected to the package for connecting the chip to the outside. An integrated circuit device, comprising: a member to which a constant DC voltage is supplied; and a member that forms mutual inductance with the lead frame. 2. An integrated circuit comprising a chip on which an integrated circuit is formed, a package for sealing the chip, and a lead frame partially connected to the package for connecting the chip to the outside. An integrated circuit device, comprising: a conductive member provided at a position facing the lead frame and supplied with a constant DC voltage. 3. The integrated circuit device according to claim 2, wherein the conductive member is a flat conductive member sealed in a package and supplied with a power supply voltage or a ground voltage supplied to the chip. An integrated circuit device, characterized in that: 4. The integrated circuit device according to claim 2, wherein said conductive member is a flat conductive member disposed outside said package and supplied with a power supply voltage or a ground voltage supplied to said chip. An integrated circuit device, characterized in that: 5. The integrated circuit device according to claim 2, wherein the conductive member is provided at a position facing a lead frame for supplying a power supply voltage to the chip. A conductive member to which the supplied ground voltage is supplied,
Alternatively, the integrated circuit device is a conductive member, which is provided at a position facing a lead frame for supplying a ground voltage to the chip and supplied with a power supply voltage supplied to the chip. 6. The integrated circuit device according to claim 2, wherein the conductive member is disposed at a position facing a lead frame to which a power supply voltage is supplied, and a ground voltage supplied to the chip. And a second conductive member disposed at a position facing a lead frame to which ground voltage is supplied and a power supply voltage to be supplied to the chip.
An integrated circuit device, comprising: a conductive member; 7. An integrated circuit comprising a chip on which an integrated circuit is formed, a package for sealing the chip, and a lead frame partially connected to the package for connecting the chip to the outside. A lead frame for supplying a power supply voltage to the chip and a lead frame for supplying a ground voltage to the chip are plate-like members arranged adjacent to each other; An integrated circuit, wherein a plate surface of a lead frame for supplying a voltage to the chip and a plate surface of a lead frame for supplying a ground voltage to the chip are arranged so as to partially face each other. Circuit device. 8. The integrated circuit device according to claim 7, wherein the lead frame for supplying a power supply voltage to the chip and the lead frame for supplying a ground voltage to the chip are both intermediate between the lead frame. In part,
The other portion has a torsion portion where the direction of the plate surface is changing, and in the torsion portion, the plate surface of the lead frame for supplying power supply voltage to the chip and the ground voltage are applied to the chip. An integrated circuit device, wherein a plate surface of a lead frame to be supplied is opposed. 9. The integrated circuit device according to claim 7, wherein a lead frame for supplying a power supply voltage to the chip and a lead frame for supplying a ground voltage to the chip are exposed outside the package. At the end on the side where the power supply voltage is supplied to the chip, the surface of the lead frame for supplying the ground voltage to the chip and the surface of the lead frame for supplying the ground voltage to the chip are adjacent on the same plane, and are sealed in the package. At the end on the side of the part, the plate surface of the lead frame for supplying the power supply voltage to the chip and the plate surface of the lead frame for supplying the ground voltage to the chip have a shape and arrangement facing each other. Integrated circuit device. 10. An electronic device comprising: an electronic substrate; and an integrated circuit device mounted on the electronic substrate.
An electronic circuit having a chip on which an integrated circuit is formed, a package for sealing the chip, and a lead frame for connecting the chip to the outside, partially sealed in the package, A lead frame for supplying a power supply voltage to the chip from the electronic substrate or a ground voltage for supplying the chip to the chip, disposed between the integrated circuit device and the electronic substrate so as to face the lead frame; An electronic circuit comprising a conductive member connected to a lead frame.