JPH11298096A - Low emi feeding-wiring structure, circuit board using the same and low emi electronic device - Google Patents

Low emi feeding-wiring structure, circuit board using the same and low emi electronic device

Info

Publication number
JPH11298096A
JPH11298096A JP10602798A JP10602798A JPH11298096A JP H11298096 A JPH11298096 A JP H11298096A JP 10602798 A JP10602798 A JP 10602798A JP 10602798 A JP10602798 A JP 10602798A JP H11298096 A JPH11298096 A JP H11298096A
Authority
JP
Japan
Prior art keywords
wiring
power supply
wirings
circuit board
low emi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10602798A
Other languages
Japanese (ja)
Inventor
Kenichi Shinpo
健一 新保
Taku Suga
卓 須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10602798A priority Critical patent/JPH11298096A/en
Publication of JPH11298096A publication Critical patent/JPH11298096A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To lessen unwanted electromagnetic radiations from feeding and high speed signal wirings by forming a parallel coupling structure of signal or power feed wiring and ground wiring, having the same width with a dielectric layer inserted therebetween to dispose the wirings near to each other face to face. SOLUTION: Wirings 1, 3 having the same width are disposed on the opposite faces of a dielectric layer 2. Self inductances L1, L2 and mutual inductance M exist on each of two parallel wiring boards. The current flows in the reverse direction on a signal or power feed wiring to a ground wiring, so that the effective inductance Le is represented by L3=L1+L2-2M. A relation M=k(L1L2)<1/2> holds between the self inductances L1, L2 and a mutual inductance M, and k is called the coupling factor. The parallel coupling structure has a strong coupling between both wirings, hence the mutual inductance is high and effective inductance L3 is low. Thus unwanted electromagnetic radiations from the feed and high speed signal wirings can be lessened.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子装置に用いる
高速信号回路基板に関し、特に不要電磁輻射を抑制する
給電・配線構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed signal circuit board used for an electronic device, and more particularly to a power supply / wiring structure for suppressing unnecessary electromagnetic radiation.

【0002】[0002]

【従来の技術】近年、電子装置の高速化により不要電磁
輻射は増大し、装置の製品化においてEMI規制に適用
することが必須になってきている。不要電磁輻射は、電
子回路装置内の各部分から発生するが、多層プリント基
板内の給電および高速信号配線が支配的要因であり、こ
の配線に流れる電流の大きさ、または配線が持つインダ
クタンスの大きさに比例して、不要電磁輻射が増えるこ
とが、Introduction toElectromagnetic Compatibility
/Paul,Clayton R.(1992)のP731-P737にも指摘されてい
る。
2. Description of the Related Art Unnecessary electromagnetic radiation has increased in recent years due to the speeding-up of electronic devices, and it has become essential to apply EMI regulations in commercializing devices. Unwanted electromagnetic radiation is generated from each part in the electronic circuit device. Power supply and high-speed signal wiring in the multilayer printed circuit board are the dominant factors, and the magnitude of the current flowing through these wirings or the inductance of the wirings The increase in unwanted electromagnetic radiation increases with the introduction to Electromagnetic Compatibility.
/ Paul, Clayton R. (1992) P731-P737.

【0003】近年の電子回路装置は、高速動作で、かつ
電源電流の変動も高速であるため、多層プリント基板内
の給電および高速信号配線からの不要電磁輻射が重要な
問題となる。現在、この不要電磁輻射に対し、より一層
効果的な対策が必要とされている。
[0003] Since recent electronic circuit devices operate at high speed and change in power supply current at high speed, power supply in a multilayer printed circuit board and unnecessary electromagnetic radiation from high-speed signal wiring become important problems. At present, more effective countermeasures against this unnecessary electromagnetic radiation are required.

【0004】[0004]

【発明が解決しようとする課題】現在の高速電子回路装
置において、不要電磁輻射の支配的要因として多層プリ
ント基板内の給電および高速信号配線が挙げられる。こ
れらの配線には物理的寸法で定まる実効インダクタンス
Leが存在する。ここで、この実効インダクタンスLe
に流れる電流が変動すると、雑音電圧Vnが発生する。
雑音電圧Vnは、実効インダクタンスLeと駆動素子の
動作速度などによって決まる電源電流の変動速度di/
dtを用いて、Vn=Le×di/dtで表される。こ
の雑音電圧は電源電圧に変動を与えるため、雑音電圧が
大きくなると不要電磁輻射も大きくなる。
In the current high-speed electronic circuit device, power supply and high-speed signal wiring in a multilayer printed circuit board can be cited as dominant factors of unnecessary electromagnetic radiation. These wirings have an effective inductance Le determined by physical dimensions. Here, this effective inductance Le
Fluctuates the current flowing through the device, a noise voltage Vn is generated.
The noise voltage Vn is determined by the fluctuation speed di / of the power supply current determined by the effective inductance Le and the operating speed of the driving element.
Using dt, Vn = Le × di / dt. Since the noise voltage fluctuates the power supply voltage, the unnecessary electromagnetic radiation increases as the noise voltage increases.

【0005】また、従来の多層プリント基板では図4の
ようにグランドにベタ層を用いる給電・配線構造が一般
的である。しかし、多層基板では、異なる層間の信号を
接続するスルーホールが必要であり、図5に示すように
上記ベタ層には、スルーホールとの短絡を避けるための
クリアランスホールを設ける場合がある。このクリアラ
ンスホールは、ベタ層を流れるリターン電流の理想的な
経路を阻害し、電流経路のインダクタンスを増幅させ、
しかもベタ層を流れるリターン電流は大きく迂回するよ
うに流れるため、電流ループの面積が大きくなり、不要
電磁輻射も増大してしまう。
A conventional multilayer printed circuit board generally has a power supply / wiring structure using a solid layer for the ground as shown in FIG. However, a multi-layer substrate requires through holes for connecting signals between different layers, and as shown in FIG. 5, a clearance hole may be provided in the solid layer to avoid a short circuit with the through hole. This clearance hole hinders the ideal path of the return current flowing through the solid layer, amplifies the inductance of the current path,
In addition, since the return current flowing through the solid layer flows so as to largely detour, the area of the current loop increases, and the unnecessary electromagnetic radiation also increases.

【0006】そこで、これら配線からの不要電磁輻射を
低減するために、電流の広がりを抑えて電流ループの面
積をできるだけ小さく、かつ、配線の実効インダクタン
スLeを小さくする必要がある。
Therefore, in order to reduce the unnecessary electromagnetic radiation from these wirings, it is necessary to suppress the spread of the current, to make the area of the current loop as small as possible, and to reduce the effective inductance Le of the wirings.

【0007】本発明の課題は、多層プリント基板内にお
ける給電および高速信号配線からの不要電磁輻射を低減
することであり、具体的には配線の実効インダクタンス
Leを小さくすることにある。
An object of the present invention is to reduce unnecessary electromagnetic radiation from power supply and high-speed signal wiring in a multilayer printed circuit board, and specifically to reduce the effective inductance Le of the wiring.

【0008】[0008]

【課題を解決するための手段】多層プリント基板内に形
成する給電および高速信号配線には、信号または電源供
給配線と、そのリターン電流が流れるグランド配線が存
在する。本発明は、信号または電源供給配線と、それと
同じ幅を持つグランド配線とを、誘電体層を挟んで対面
に近接配置した並列結合構造を提供することにより、配
線の低インダクタンス化を図り、また基板内での電流広
がりを抑制することによって、給電および高速信号配線
からの不要電磁輻射低減を実現させる。
The power supply and high-speed signal wiring formed in the multilayer printed circuit board include a signal or power supply wiring and a ground wiring through which a return current flows. The present invention provides a parallel-coupling structure in which a signal or power supply wiring and a ground wiring having the same width are arranged close to each other with a dielectric layer interposed therebetween, thereby reducing the wiring inductance. By suppressing the spread of current in the substrate, it is possible to reduce unnecessary electromagnetic radiation from power supply and high-speed signal wiring.

【0009】[0009]

【発明の実施の形態】以下、実施例を用いて、本発明を
説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

【0010】(実施例1)以下、本発明の第1の実施例
を説明する。図1に本発明の基本となる配線構造のプリ
ント基板を示す。この配線は、誘電体層2を挟んで、対
面に近接配置した配線1と、1と同じ配線幅を持つグラ
ンド配線3で構成される。
(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described. FIG. 1 shows a printed circuit board having a wiring structure which is the basis of the present invention. This wiring is composed of a wiring 1 disposed close to the opposing surface with a dielectric layer 2 interposed therebetween, and a ground wiring 3 having the same wiring width as 1.

【0011】図2に、図1の配線構造の断面部を示す。
本配線構造では、誘電体厚さd(=配線間距離)が配線
幅Wに比べ非常に薄いため、信号または電源配線1とグ
ランド配線3は近接しており、両配線板は配線幅Wの方
向で常に平行に配線される。
FIG. 2 shows a cross section of the wiring structure of FIG.
In the present wiring structure, since the dielectric thickness d (= distance between the wirings) is much smaller than the wiring width W, the signal or power supply wiring 1 and the ground wiring 3 are close to each other. Always wired in parallel in the direction.

【0012】図3に配線が持つインダクタンスの概念図
を示す。本配線構造のように平行した2枚の配線板に
は、それぞれの自己インダクタンスL1,L2と、相互イ
ンダクタンスMが存在する。また、信号または電源配線
とグランド配線とでは電流が互いに逆向きに流れるの
で、実効インダクタンスLeは、Le=L1+L2−2M
で表される。自己インダクタンスL1,L2と相互インダ
クタンスMとの間には、M=k√L1・L2の関係が成り
立つ。ここで、係数kは結合係数と呼ばれ、L1とL2す
なわち、信号または給電配線とグランド配線が磁気的に
どれだけ結合しているかを表している。本配線構造のよ
うな並列結合構造は両配線間で強い結合を持つため、相
互インダクタンスが大きく、実効インダクタンスLeは
小さくなる。したがって、給電および高速信号配線から
の不要電磁輻射を低減できる。
FIG. 3 shows a conceptual diagram of the inductance of the wiring. Two parallel wiring boards like this wiring structure have their own inductances L1 and L2 and mutual inductance M. In addition, since currents flow in opposite directions in the signal or power supply wiring and the ground wiring, the effective inductance Le is Le = L1 + L2-2−M.
It is represented by The relationship of M = k√L1 · L2 is established between the self inductances L1 and L2 and the mutual inductance M. Here, the coefficient k is called a coupling coefficient, and indicates L1 and L2, that is, how much the signal or power supply wiring and the ground wiring are magnetically coupled. Since the parallel coupling structure like the present wiring structure has strong coupling between the two wirings, the mutual inductance is large and the effective inductance Le is small. Therefore, unnecessary electromagnetic radiation from power supply and high-speed signal wiring can be reduced.

【0013】(実施例2)以下、本発明の第2の実施例
を説明する。図6に実施例1の並列結合構造で配線した
プリント基板を示す。プリント基板5は両面プリント基
板で、半導体素子4、半導体素子4を結ぶ信号または電
源配線1とグランド配線3から構成される。
(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described. FIG. 6 shows a printed circuit board wired by the parallel connection structure of the first embodiment. The printed circuit board 5 is a double-sided printed circuit board and includes a semiconductor element 4, a signal or power supply wiring 1 connecting the semiconductor element 4, and a ground wiring 3.

【0014】図7に本実施例の基板電流分布の概念を示
す。給電および高速信号配線を並列結合構造で配線する
ことにより、電流の経路が限定され、電流の広がりが抑
えられるため、電流ループは最小となり、よって給電お
よび高速信号配線からの不要電磁輻射を低減できる。ま
た給電および高速信号配線およびグランド配線には互い
に逆向きの電流が流れているため、配線間の磁界は常に
相殺しあい、不要電磁輻射が低減できる。これは2層以
上の多層基板で配線するのと同等またはそれ以上の性能
を有する。
FIG. 7 shows the concept of the substrate current distribution in this embodiment. By laying the power supply and high-speed signal wiring in a parallel-coupling structure, the current path is limited and the spread of the current is suppressed, so that the current loop is minimized, and thus unnecessary electromagnetic radiation from the power supply and high-speed signal wiring can be reduced. . Further, currents flowing in opposite directions flow through the power supply, the high-speed signal wiring, and the ground wiring, so that the magnetic fields between the wirings always cancel each other, and unnecessary electromagnetic radiation can be reduced. This has performance equal to or better than wiring with a multi-layer substrate of two or more layers.

【0015】(実施例3)以下、本発明の第3の実施例
を説明する。図8に実施例1の並列結合構造で配線した
プリント基板を示す。プリント基板6は2層以上の多層
プリント基板で、半導体素子4、半導体素子4を結ぶ給
電および高速信号配線配線1とグランド配線3、スルー
ホール7等から構成される。図8では基板6のグランド
層に設けられたスルーホール7およびクリアランス8に
よって、給電および高速信号配線1と平行なグランド配
線3を配線できなくなってしまうため、図9の基板拡大
図に示すように、スルーホール7を迂回するように配線
している。これは、全体の配線長は長くなるが、並列結
合構造を保持することで、電流ループを最小にし、不要
電磁輻射の増大を抑制している。
(Embodiment 3) Hereinafter, a third embodiment of the present invention will be described. FIG. 8 shows a printed circuit board wired by the parallel connection structure of the first embodiment. The printed board 6 is a multilayer printed board having two or more layers, and includes the semiconductor element 4, the power supply and high-speed signal wiring 1 connecting the semiconductor elements 4, the ground wiring 3, the through hole 7, and the like. In FIG. 8, the through hole 7 and the clearance 8 provided in the ground layer of the substrate 6 make it impossible to route the ground wiring 3 parallel to the power supply and high-speed signal wiring 1, so that as shown in the enlarged view of the substrate in FIG. , So as to bypass the through hole 7. Although the overall wiring length is long, the current loop is minimized by holding the parallel coupling structure, and the increase of unnecessary electromagnetic radiation is suppressed.

【0016】[0016]

【発明の効果】図10は並列結合構造とシングルストリ
ップ構造の実効インダクタンスLeを電磁界解析により
求めた結果である。ここでは配線幅Wをパラメータとし
た。強い結合を持つ並列結合構造の実効インダクタンス
Leは、結合のないシングルストリップ構造に比べ、非
常に小さい値となり、図10によれば、配線幅を1[mm]
以上にすれば、実効インダクタンスLeを1/10以下
にできる。よって高周波電流が流れることによって発生
する雑音電圧も1/10となり、不要電磁輻射を1/1
0以下に低減できる。
FIG. 10 shows the results obtained by analyzing the effective inductance Le of the parallel coupling structure and the single strip structure by electromagnetic field analysis. Here, the wiring width W was used as a parameter. The effective inductance Le of the parallel coupling structure having strong coupling is much smaller than that of the single strip structure having no coupling. According to FIG. 10, the wiring width is 1 [mm].
By doing so, the effective inductance Le can be reduced to 1/10 or less. Therefore, the noise voltage generated by the flow of the high-frequency current is also reduced to 1/10, and unnecessary electromagnetic radiation is reduced to
It can be reduced to 0 or less.

【0017】また、常に給電および高速信号配線とグラ
ンド配線を平行に配線するので、リターン電流の広がり
がなく、電流ループ面積が最小になるため、不要電磁輻
射が低減できる。また、2層両面基板でも、給電および
高速信号配線の対面には常にグランド配線が設けられて
いるため、グランドのベタ層を用意する2層以上の多層
基板と同等の性能が得られ、基板コストの低減につなが
る。
Further, since the power supply and high-speed signal wiring and the ground wiring are always wired in parallel, the return current does not spread and the current loop area is minimized, so that unnecessary electromagnetic radiation can be reduced. Even with a two-layer double-sided board, ground wiring is always provided on the opposite side of the power supply and high-speed signal wiring. Leads to a reduction in

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1の給電・信号配線構造を示す
斜視図である。
FIG. 1 is a perspective view illustrating a power supply / signal wiring structure according to a first embodiment of the present invention.

【図2】本発明の実施例1の給電・信号配線構造断面図
である。
FIG. 2 is a sectional view of a power supply / signal wiring structure according to the first embodiment of the present invention.

【図3】給電・信号配線のインダクタンスを示した概念
図である。
FIG. 3 is a conceptual diagram illustrating inductance of a power supply / signal wiring.

【図4】従来の給電・信号配線構造を示す斜視図であ
る。
FIG. 4 is a perspective view showing a conventional power supply / signal wiring structure.

【図5】従来の基板における問題点を示した図である。FIG. 5 is a diagram showing a problem in a conventional substrate.

【図6】本発明の実施例2の基板を示す斜視図である。FIG. 6 is a perspective view showing a substrate according to a second embodiment of the present invention.

【図7】本発明の実施例2の電流分布概念図である。FIG. 7 is a conceptual diagram of a current distribution according to a second embodiment of the present invention.

【図8】本発明の実施例3の基板を示す斜視図である。FIG. 8 is a perspective view showing a substrate according to a third embodiment of the present invention.

【図9】本発明の実施例3の基板を示す拡大図である。FIG. 9 is an enlarged view showing a substrate according to a third embodiment of the present invention.

【図10】本発明の効果の配線配線幅とインダクタンス
の関係を示した特性図である。
FIG. 10 is a characteristic diagram showing the relationship between the wiring width and the inductance according to the effect of the present invention.

【符号の説明】[Explanation of symbols]

1…給電・信号配線、2…誘電体、3…グランド配線、
4…半導体素子、5…プリント基板(両面基板)、6…
プリント基板(2層以上の多層基板)、7…スルーホー
ル、8…クリアランス。
DESCRIPTION OF SYMBOLS 1 ... Power supply / signal wiring, 2 ... Dielectric, 3 ... Ground wiring,
4 ... Semiconductor element, 5 ... Printed board (double-sided board), 6 ...
Printed circuit board (multilayer board of two or more layers), 7: through hole, 8: clearance.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】2層以上の多層プリント基板において、信
号または電源供給配線とグランド配線によって、誘電体
を挟みこむ構造とし、さらに誘電体の厚さ以上の幅で対
向させることにより、配線のインダクタンスを低減し、
雑音電圧を抑制したことを特徴とする低EMI給電・配
線構造。
In a multilayer printed circuit board having two or more layers, a dielectric is sandwiched between a signal or power supply wiring and a ground wiring, and furthermore, the wiring is opposed by a width equal to or greater than the thickness of the dielectric, thereby increasing the inductance of the wiring. To reduce
A low EMI power supply / wiring structure characterized by suppressing noise voltage.
【請求項2】請求項1の配線構造を適用して、半導体素
子間を配線したことを特徴とする低EMI給電・配線構
造を用いた回路基板。
2. A circuit board using a low EMI power supply and wiring structure, wherein the wiring structure according to claim 1 is applied and wiring is performed between semiconductor elements.
【請求項3】請求項2の回路基板を用いたことを特徴と
する低EMI電子装置。
3. A low EMI electronic device using the circuit board according to claim 2.
JP10602798A 1998-04-16 1998-04-16 Low emi feeding-wiring structure, circuit board using the same and low emi electronic device Pending JPH11298096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10602798A JPH11298096A (en) 1998-04-16 1998-04-16 Low emi feeding-wiring structure, circuit board using the same and low emi electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10602798A JPH11298096A (en) 1998-04-16 1998-04-16 Low emi feeding-wiring structure, circuit board using the same and low emi electronic device

Publications (1)

Publication Number Publication Date
JPH11298096A true JPH11298096A (en) 1999-10-29

Family

ID=14423169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10602798A Pending JPH11298096A (en) 1998-04-16 1998-04-16 Low emi feeding-wiring structure, circuit board using the same and low emi electronic device

Country Status (1)

Country Link
JP (1) JPH11298096A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081364A (en) * 2005-08-15 2007-03-29 Canon Inc Printed board and semiconductor integrated circuit
US8063480B2 (en) 2006-02-28 2011-11-22 Canon Kabushiki Kaisha Printed board and semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081364A (en) * 2005-08-15 2007-03-29 Canon Inc Printed board and semiconductor integrated circuit
US8063480B2 (en) 2006-02-28 2011-11-22 Canon Kabushiki Kaisha Printed board and semiconductor integrated circuit
US8575743B2 (en) 2006-02-28 2013-11-05 Canon Kabushiki Kaisha Printed board and semiconductor integrated circuit

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